diff options
Diffstat (limited to 'board')
89 files changed, 5312 insertions, 2501 deletions
diff --git a/board/BuS/EB+MCF-EV123/config.mk b/board/BuS/EB+MCF-EV123/config.mk index 50185ae..18fb84e 100644 --- a/board/BuS/EB+MCF-EV123/config.mk +++ b/board/BuS/EB+MCF-EV123/config.mk @@ -22,7 +22,6 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk ifndef CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE = 0xFE000000 endif diff --git a/board/BuS/EB+MCF-EV123/textbase.mk b/board/BuS/EB+MCF-EV123/textbase.mk deleted file mode 100644 index b97c034..0000000 --- a/board/BuS/EB+MCF-EV123/textbase.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0xFFE00000 diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile new file mode 100644 index 0000000..f5ad494 --- /dev/null +++ b/board/CarMediaLab/flea3/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := flea3.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c new file mode 100644 index 0000000..64f4b57 --- /dev/null +++ b/board/CarMediaLab/flea3/flea3.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011, Stefano Babic <sbabic@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> +#include <linux/types.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <netdev.h> + +#ifndef CONFIG_BOARD_EARLY_INIT_F +#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +#endif + +#define CCM_CCMR_CONFIG 0x003F4208 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_PRECHARGE 0x00000400 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 +#define ESDCTL_DELAY_LINE5 0x00F49F00 + +static inline void dram_wait(unsigned int count) +{ + volatile unsigned int wait = count; + + while (wait--) + ; +} + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return 0; +} + +static void board_setup_sdram_bank(u32 start_address) + +{ + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + u32 *cfg_reg, *ctl_reg; + u32 val; + + switch (start_address) { + case CSD0_BASE_ADDR: + cfg_reg = &esdc->esdcfg0; + ctl_reg = &esdc->esdctl0; + break; + case CSD1_BASE_ADDR: + cfg_reg = &esdc->esdcfg1; + ctl_reg = &esdc->esdctl1; + break; + default: + return; + } + + /* Initialize MISC register for DDR2 */ + val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST | + ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN; + writel(val, &esdc->esdmisc); + val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST); + writel(val, &esdc->esdmisc); + + /* + * according to DDR2 specs, wait a while before + * the PRECHARGE_ALL command + */ + dram_wait(0x20000); + + /* Load DDR2 config and timing */ + writel(ESDCTL_DDR2_CONFIG, cfg_reg); + + /* Precharge ALL */ + writel(ESDCTL_0x92220000, + ctl_reg); + writel(0xda, start_address + ESDCTL_PRECHARGE); + + /* Load mode */ + writel(ESDCTL_0xB2220000, + ctl_reg); + writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ + writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ + writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ + + /* Precharge ALL */ + writel(ESDCTL_0x92220000, + ctl_reg); + writel(0xda, start_address + ESDCTL_PRECHARGE); + + /* Set mode auto refresh : at least two refresh are required */ + writel(ESDCTL_0xA2220000, + ctl_reg); + writel(0xda, start_address); + writel(0xda, start_address); + + writel(ESDCTL_0xB2220000, + ctl_reg); + writeb(0xda, start_address + ESDCTL_DDR2_MR); + writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); + + /* OCD mode exit */ + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ + + /* Set normal mode */ + writel(ESDCTL_0x82228080, + ctl_reg); + + dram_wait(0x20000); + + /* Do not set delay lines, only for MDDR */ +} + +static void board_setup_sdram(void) +{ + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* Initialize with default values both CSD0/1 */ + writel(0x2000, &esdc->esdctl0); + writel(0x2000, &esdc->esdctl1); + + board_setup_sdram_bank(CSD1_BASE_ADDR); +} + +static void setup_iomux_uart3(void) +{ + mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7); + mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7); +} + +static void setup_iomux_i2c(void) +{ + int pad; + + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad); +} + + +static void setup_iomux_spi(void) +{ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); +} + +static void setup_iomux_fec(void) +{ + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + +} + +int board_early_init_f(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + /* setup GPIO3_1 to set HighVCore signal */ + mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + gpio_direction_output(65, 1); + + /* initialize PLL and clock configuration */ + writel(CCM_CCMR_CONFIG, &ccm->ccmr); + + writel(CCM_MPLL_532_HZ, &ccm->mpctl); + writel(CCM_PPLL_300_HZ, &ccm->ppctl); + + /* Set the core to run at 532 Mhz */ + writel(0x00001000, &ccm->pdr0); + + /* Set-up RAM */ + board_setup_sdram(); + + /* enable clocks */ + writel(readl(&ccm->cgr0) | + MXC_CCM_CGR0_EMI_MASK | + MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EPIT1_MASK, + &ccm->cgr0); + + writel(readl(&ccm->cgr1) | + MXC_CCM_CGR1_FEC_MASK | + MXC_CCM_CGR1_GPIO1_MASK | + MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | + MXC_CCM_CGR1_I2C1_MASK | + MXC_CCM_CGR1_I2C2_MASK | + MXC_CCM_CGR1_I2C3_MASK, + &ccm->cgr1); + + /* Set-up NAND */ + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); + + /* Set pinmux for the required peripherals */ + setup_iomux_uart3(); + setup_iomux_i2c(); + setup_iomux_fec(); + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +u32 get_board_rev(void) +{ + int rev = 0; + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S new file mode 100644 index 0000000..2f42fc9 --- /dev/null +++ b/board/CarMediaLab/flea3/lowlevel_init.S @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011, Stefano Babic <sbabic@denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> + +/* + * Configuration for the flea3 board. + * These defines are used by the included macros and must + * be defined first + */ +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 + +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 + +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define CCM_PDR0_CONFIG 0x00801000 + +/* + * includes MX35 utility macros + */ +#include <asm/arch/lowlevel_macro.S> + +.globl lowlevel_init +lowlevel_init: + + core_init + + init_aips + + init_max + + init_m3if + + mov pc, lr diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg new file mode 100644 index 0000000..590720a --- /dev/null +++ b/board/LaCie/netspace_v2/kwbimage-is2.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000008 # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg index 361feeb..7e53649 100644 --- a/board/LaCie/netspace_v2/kwbimage.cfg +++ b/board/LaCie/netspace_v2/kwbimage.cfg @@ -69,8 +69,8 @@ DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) # bit12-11: TW2W # bit31-13: zero required -DATA 0xFFD01410 0x0000CCCC # DDR Address Control -# bit1-0: 01, Cs0width=x16 +DATA 0xFFD01410 0x0000000C # DDR Address Control +# bit1-0: 00, Cs0width=x8 # bit3-2: 11, Cs0size=1Gb # bit5-4: 00, Cs2width=nonexistent # bit7-6: 00, Cs1size =nonexistent diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3bb83f3..7c4b15e 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -24,6 +24,7 @@ #include <miiphy.h> #include <netdev.h> #include <command.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 13b4013..31b73c9 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include "dreamplug.h" diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index cab3a83..a1de0dc 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -29,6 +29,8 @@ #include <miiphy.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> #include "dockstar.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile new file mode 100644 index 0000000..2b22124 --- /dev/null +++ b/board/ait/cam_enc_4xx/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c new file mode 100644 index 0000000..1351358 --- /dev/null +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -0,0 +1,446 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <linux/mtd/nand.h> +#include <nand.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/nand_defs.h> +#include <asm/arch/davinci_misc.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +static struct davinci_timer *timer = + (struct davinci_timer *)DAVINCI_TIMER3_BASE; + +static unsigned long get_timer_val(void) +{ + unsigned long now = readl(&timer->tim34); + + return now; +} + +static void stop_timer(void) +{ + writel(0x0, &timer->tcr); + return; +} + +int checkboard(void) +{ + printf("Board: AIT CAM ENC 4XX\n"); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +int board_eth_init(bd_t *bis) +{ + davinci_emac_initialize(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_DAVINCI +static int +davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + struct nand_chip *this = mtd->priv; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + + chip->read_buf(mtd, oob, mtd->oobsize); + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask); + + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.hwctl(mtd, NAND_ECC_READSYN); + + if (chip->ecc.prepad) + oob += chip->ecc.prepad; + + stat = chip->ecc.correct(mtd, p, oob, NULL); + + if (stat == -1) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + oob += eccbytes; + + if (chip->ecc.postpad) + oob += chip->ecc.postpad; + } + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->read_buf(mtd, oob, i); + + return 0; +} + +static void davinci_std_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE]; + struct nand_chip *this = mtd->priv; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + int offset = 0; + const uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + chip->write_buf(mtd, p, eccsize); + + /* Calculate ECC without prepad */ + chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad); + + if (chip->ecc.prepad) { + offset = (chip->ecc.steps - eccsteps) * chunk; + memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + offset = ((chip->ecc.steps - eccsteps) * chunk) + + chip->ecc.prepad; + memcpy(&davinci_ecc_buf[offset], oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + offset = ((chip->ecc.steps - eccsteps) * chunk) + + chip->ecc.prepad + eccbytes; + memcpy(&davinci_ecc_buf[offset], oob, + chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* + * Write the sparebytes into the page once + * all eccsteps have been covered + */ + for (i = 0; i < mtd->oobsize; i++) + writeb(davinci_ecc_buf[i], this->IO_ADDR_W); + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->write_buf(mtd, oob, i); +} + +static int davinci_std_write_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + int pos, status = 0; + const uint8_t *bufpoi = chip->oob_poi; + + pos = mtd->writesize; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); + + chip->write_buf(mtd, bufpoi, mtd->oobsize); + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -1 : 0; +} + +static int davinci_std_read_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page, int sndcmd) +{ + struct nand_chip *this = mtd->priv; + uint8_t *buf = chip->oob_poi; + uint8_t *bufpoi = buf; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + + chip->read_buf(mtd, bufpoi, mtd->oobsize); + + return 1; +} + +static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + unsigned long wbase = (unsigned long) this->IO_ADDR_W; + unsigned long rbase = (unsigned long) this->IO_ADDR_R; + + if (chip == 1) { + __set_bit(14, &wbase); + __set_bit(14, &rbase); + } else { + __clear_bit(14, &wbase); + __clear_bit(14, &rbase); + } + this->IO_ADDR_W = (void *)wbase; + this->IO_ADDR_R = (void *)rbase; +} + +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + nand->select_chip = nand_dm365evm_select_chip; + + return 0; +} + +struct nand_ecc_ctrl org_ecc; +static int notsaved = 1; + +static int nand_switch_hw_func(int mode) +{ + struct nand_chip *nand; + struct mtd_info *mtd; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + printf("Error: Can't switch hw functions," \ + " no devices available\n"); + return -1; + } + + mtd = &nand_info[nand_curr_device]; + nand = mtd->priv; + + if (mode == 0) { + printf("switching to uboot hw functions.\n"); + memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl)); + } else { + /* RBL */ + printf("switching to RBL hw functions.\n"); + if (notsaved == 1) { + memcpy(&org_ecc, &nand->ecc, + sizeof(struct nand_ecc_ctrl)); + notsaved = 0; + } + nand->ecc.mode = NAND_ECC_HW_SYNDROME; + nand->ecc.prepad = 6; + nand->ecc.read_page = davinci_std_read_page_syndrome; + nand->ecc.write_page = davinci_std_write_page_syndrome; + nand->ecc.read_oob = davinci_std_read_oob_syndrome; + nand->ecc.write_oob = davinci_std_write_oob_syndrome; + } + return mode; +} + +static int hwmode; + +static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + goto usage; + if (strncmp(argv[1], "rbl", 2) == 0) + hwmode = nand_switch_hw_func(1); + else if (strncmp(argv[1], "uboot", 2) == 0) + hwmode = nand_switch_hw_func(0); + else + goto usage; + + return 0; + +usage: + printf("Usage: nandrbl %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandrbl, 2, 1, do_switch_ecc, + "switch between rbl/uboot NAND ECC calculation algorithm", + "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm" +); + + +#endif /* #ifdef CONFIG_NAND_DAVINCI */ + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .input_clk = 121500000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + int err; + + /* Add slot-0 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd0); + + return err; +} +#endif + +int board_late_init(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank45; + + /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */ + while (get_timer_val() < 0x186a00) + ; + + /* 1 sec reached -> stop timer, clear all LED */ + stop_timer(); + clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); + return 0; +} + +void reset_phy(void) +{ + char *name = "GENERIC @ 0x00"; + + /* reset the phy */ + miiphy_reset(name, 0x0); +} + +#else /* #ifndef CONFIG_SPL_BUILD */ +static void cam_enc_4xx_set_all_led(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank45; + + setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); +} + +/* + * TIMER 0 is used for tick + */ +static struct davinci_timer *timer = + (struct davinci_timer *)DAVINCI_TIMER3_BASE; + +#define TIMER_LOAD_VAL 0xffffffff +#define TIM_CLK_DIV 16 + +static int cam_enc_4xx_timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + writel(0x0, &timer->tcr); + writel(0x0, &timer->tgcr); + writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); + writel(0x0, &timer->tim34); + writel(TIMER_LOAD_VAL, &timer->prd34); + writel(2 << 22, &timer->tcr); + return 0; +} + +void board_gpio_init(void) +{ + struct davinci_gpio *gpio; + + cam_enc_4xx_set_all_led(); + cam_enc_4xx_timer_init(); + gpio = davinci_gpio_bank01; + clrbits_le32(&gpio->dir, ~0xfdfffffe); + /* clear LED D14 = GPIO25 */ + clrbits_le32(&gpio->out_data, 0x02000000); + gpio = davinci_gpio_bank23; + clrbits_le32(&gpio->dir, ~0x5ff0afef); + /* set GPIO61 to 1 -> intern UART0 as Console */ + setbits_le32(&gpio->out_data, 0x20000000); + /* + * PHY out of reset GIO 50 = 1 + * NAND WP off GIO 51 = 1 + */ + setbits_le32(&gpio->out_data, 0x000c0004); + gpio = davinci_gpio_bank45; + clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK); + /* + * clear LED: + * D17 = GPIO86 + * D11 = GPIO87 + * GPIO88 + * GPIO89 + * D13 = GPIO90 + * GPIO91 + */ + clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); + gpio = davinci_gpio_bank67; + clrbits_le32(&gpio->dir, ~0x000007ff); +} + +/* + * functions for the post memory test. + */ +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + *vstart = CONFIG_SYS_SDRAM_BASE; + *size = PHYS_SDRAM_1_SIZE; + *phys_offset = 0; + return 0; +} + +void arch_memory_failure_handle(void) +{ + cam_enc_4xx_set_all_led(); + puts("mem failure\n"); + while (1) + ; +} +#endif diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk new file mode 100644 index 0000000..b1f9b6c --- /dev/null +++ b/board/ait/cam_enc_4xx/config.mk @@ -0,0 +1,15 @@ +# +# AIT cam_enc_4xx board +# cam_enc_4xx board has 1 bank of 256 MB DDR RAM +# Physical Address: 8000'0000 to 9000'0000 +# +# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +PAD_TO := 12320 +UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.ubl +endif diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds new file mode 100644 index 0000000..6f6e065 --- /dev/null +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + arch/arm/cpu/arm926ejs/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + __image_copy_end = .; + _end = .; +} diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg new file mode 100644 index 0000000..95182ca --- /dev/null +++ b/board/ait/cam_enc_4xx/ublimage.cfg @@ -0,0 +1,48 @@ +# +# (C Copyright 2011 +# Heiko Schocher DENX Software Engineering hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer doc/README.ublimage for more details about how-to configure +# and create ublimage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# UBL special mode : one of +# safe (the board has no nand neither onenand) +MODE safe + +# Entry point address for the user bootloader (absolute address) +# nand spl TEXT_BASE = 0x20 !! +ENTRY 0x00000020 + +# Number of pages (size of user bootloader in number of pages) +# @ nand spl 6 pages +PAGES 6 + +# Block number where user bootloader is present +# RBL starts always with block 1 +START_BLOCK 5 + +# Page number where user bootloader is present +# Page 0 is always UBL header +START_PAGE 0 + +LD_ADDR 0x20 diff --git a/board/alaska/flash.c b/board/alaska/flash.c index aed3b6f..977822a 100644 --- a/board/alaska/flash.c +++ b/board/alaska/flash.c @@ -406,7 +406,7 @@ static unsigned char same_chip_banks (int bank1, int bank2) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0, intel = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -444,7 +444,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } start = get_timer (0); - last = start; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -501,6 +500,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf (" done\n"); } } + if (flag) + enable_interrupts(); + return rcode; } @@ -666,7 +668,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) { FPWV *addr = (FPWV *) dest; ulong start; - int flag; + int flag, rc = 0; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -685,14 +687,18 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + rc = 1; + goto OUT; } } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ +OUT: + *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (0); + if (flag) + enable_interrupts(); + + return rc; } /*----------------------------------------------------------------------- @@ -706,7 +712,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) FPWV *srcaddr = (FPWV *) src; FPWV *dstaddr = (FPWV *) dest; ulong start; - int flag, i; + int flag, i, rc = 0; /* Check if Flash is (sufficiently) erased */ for (i = 0; i < WR_BLOCK; i++) @@ -727,10 +733,10 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) start = get_timer (0); /* wait while polling the status register */ - while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + rc = 1; + goto OUT; } } @@ -752,9 +758,12 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) } } - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ +OUT: + *dstaddr = (FPW)0x00FF00FF; /* restore read mode */ + if (flag) + enable_interrupts(); - return (0); + return rc; } /*----------------------------------------------------------------------- diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c index c833b20..2267829 100644 --- a/board/c2mon/pcmcia.c +++ b/board/c2mon/pcmcia.c @@ -199,7 +199,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; ushort sreg; @@ -210,12 +209,11 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ diff --git a/board/cogent/flash.c b/board/cogent/flash.c index e6c85b6..ec3f94d 100644 --- a/board/cogent/flash.c +++ b/board/cogent/flash.c @@ -23,6 +23,7 @@ #include <common.h> #include <board/cogent/flash.h> +#include <linux/compiler.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -292,7 +293,7 @@ flash_init(void) { unsigned long total; int i; - flash_info_t *fip; + __maybe_unused flash_info_t *fip; /* Init: no FLASHes known */ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index c81ce58..6548281 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -91,8 +91,6 @@ static const u32 gpmc_lan_config[] = { int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 5b2830c..665aedf 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -120,12 +120,6 @@ int board_early_init_f(void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -143,7 +137,7 @@ int board_early_init_f(void) mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8); + mx31_set_gpr(MUX_PGP_UH2, 1); return 0; diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 89ae111..5aa7605 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 9d0f71b..720a360 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -35,11 +35,28 @@ #include <asm/arch/emac_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/da8xx-fb.h> DECLARE_GLOBAL_DATA_PTR; #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) +static const struct da8xx_panel lcd_panel = { + /* Casio COM57H531x */ + .name = "Casio_COM57H531x", + .width = 640, + .height = 480, + .hfp = 12, + .hbp = 144, + .hsw = 30, + .vfp = 10, + .vbp = 35, + .vsw = 3, + .pxl_clk = 25000000, + .invert_pxl_clk = 0, +}; + /* SPI0 pin muxer settings */ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 1 }, @@ -48,12 +65,18 @@ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 5 } }; -/* UART pin muxer settings */ +/* I2C pin muxer settings */ +static const struct pinmux_config i2c_pins[] = { + { pinmux(4), 2, 2 }, + { pinmux(4), 2, 3 } +}; + +/* UART0 pin muxer settings */ static const struct pinmux_config uart_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } + { pinmux(3), 2, 7 }, + { pinmux(3), 2, 6 }, + { pinmux(3), 2, 4 }, + { pinmux(3), 2, 5 } }; #ifdef CONFIG_DRIVER_TI_EMAC @@ -73,70 +96,136 @@ static const struct pinmux_config emac_pins[] = { #ifdef CONFIG_NAND_DAVINCI const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } + { pinmux(7), 1, 0}, /* CS2 */ + { pinmux(7), 0, 1}, /* CS3 in three state*/ + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ + { pinmux(6), 1, 0 } /* EMA_CLK */ }; #endif +const struct pinmux_config gpio_pins[] = { + { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ + { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ + { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/ + { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */ + { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/ +}; + +const struct pinmux_config lcd_pins[] = { + { pinmux(17), 2, 1 }, /* LCD_D_0 */ + { pinmux(17), 2, 0 }, /* LCD_D_1 */ + { pinmux(16), 2, 7 }, /* LCD_D_2 */ + { pinmux(16), 2, 6 }, /* LCD_D_3 */ + { pinmux(16), 2, 5 }, /* LCD_D_4 */ + { pinmux(16), 2, 4 }, /* LCD_D_5 */ + { pinmux(16), 2, 3 }, /* LCD_D_6 */ + { pinmux(16), 2, 2 }, /* LCD_D_7 */ + { pinmux(18), 2, 1 }, /* LCD_D_8 */ + { pinmux(18), 2, 0 }, /* LCD_D_9 */ + { pinmux(17), 2, 7 }, /* LCD_D_10 */ + { pinmux(17), 2, 6 }, /* LCD_D_11 */ + { pinmux(17), 2, 5 }, /* LCD_D_12 */ + { pinmux(17), 2, 4 }, /* LCD_D_13 */ + { pinmux(17), 2, 3 }, /* LCD_D_14 */ + { pinmux(17), 2, 2 }, /* LCD_D_15 */ + { pinmux(18), 2, 6 }, /* LCD_PCLK */ + { pinmux(19), 2, 0 }, /* LCD_HSYNC */ + { pinmux(19), 2, 1 }, /* LCD_VSYNC */ + { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */ +}; + +const struct pinmux_config halten_pin[] = { + { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */ +}; + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), #endif PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(nand_pins), #endif +#ifdef CONFIG_VIDEO + PINMUX_ITEM(lcd_pins), +#endif }; static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_UART0 }, /* console */ { DAVINCI_LPSC_GPIO }, + { DAVINCI_LPSC_LCDC }, /* LCD */ }; -int board_init(void) +int board_early_init_f(void) { + struct davinci_gpio *gpio6_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK67; + + /* PinMux for GPIO */ + if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) + return 1; + + /* Set the RESETOUTn low */ + writel((readl(&gpio6_base->set_data) & ~(1 << 15)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); + + /* Set U0_SW0 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 10)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); + + /* Set U0_SW1 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 12)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); + + /* Set LCD_B_PWR low to power down LCD Backlight*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 6)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir); + + /* Set DISP_ON low to disable LCD output*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 1)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir); + #ifndef CONFIG_USE_IRQ irq_init(); #endif - -#ifdef CONFIG_NAND_DAVINCI /* * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ +#ifdef CONFIG_NAND_DAVINCI writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(0) | + DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(0) | DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab2cr); /* CS3 */ + &davinci_emif_regs->ab1cr); /* CS2 */ #endif - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_EA20; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* * Power on required peripherals * ARM does not have access by default to PSC0 and PSC1 @@ -150,7 +239,7 @@ int board_init(void) writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2), + DAVINCI_SYSCFG_SUSPSRC_UART0), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ @@ -167,10 +256,60 @@ int board_init(void) /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart2_ctrl_regs->pwremu_mgmt); + &davinci_uart0_ctrl_regs->pwremu_mgmt); + + /* + * Reconfigure the LCDC priority to the highest to ensure that + * the throughput/latency requirements for the LCDC are met. + */ + writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, + &davinci_syscfg_regs->mstpri[2]); + + /* Set LCD_B_PWR low to power up LCD Backlight*/ + writel((readl(&gpio6_base->set_data) | (1 << 6)), + &gpio6_base->set_data); + + /* Set DISP_ON low to disable LCD output*/ + writel((readl(&gpio6_base->set_data) | (1 << 1)), + &gpio6_base->set_data); + + return 0; +} + +int board_init(void) +{ + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_EA20; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + da8xx_video_init(&lcd_panel, 16); + + return 0; +} + +#ifdef BOARD_LATE_INIT + +int board_late_init(void) +{ + struct davinci_gpio *gpio8_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK8; + + /* PinMux for HALTEN */ + if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) + return 1; + + /* Set HALTEN to high */ + writel((readl(&gpio8_base->set_data) | (1 << 6)), + &gpio8_base->set_data); + writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir); + + setenv("stdout", "serial"); return 0; } +#endif /* BOARD_LATE_INIT */ #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c index 2fbdb27..8831328 100644 --- a/board/eltec/mhpc/flash.c +++ b/board/eltec/mhpc/flash.c @@ -311,7 +311,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp; FPW data; - int count, i, l, rc, port_width; + int i, l, rc, port_width; if (info->flash_id == FLASH_UNKNOWN) { return 4; @@ -330,9 +330,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ if ((l = addr - wp) != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i=0, cp=wp; i<l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } + for (; i<port_width && cnt>0; ++i) { data = (data << 8) | *src++; --cnt; @@ -351,7 +351,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle word aligned part */ - count = 0; while (cnt >= port_width) { data = 0; for (i=0; i<port_width; ++i) { diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index c1d6e91..182cabc 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c @@ -31,6 +31,7 @@ #include <pci.h> #endif #include <miiphy.h> +#include <linux/compiler.h> /* * I/O Port configuration table @@ -230,8 +231,8 @@ phys_size_t initdram(int board_type) uint psdmr = CONFIG_SYS_PSDMR; int i; - unsigned char ramtmp; unsigned char *ramptr1 = (unsigned char *)0x00000110; + __maybe_unused unsigned char ramtmp; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c index 9b578b5..9de51f3 100644 --- a/board/esd/cpci5200/strataflash.c +++ b/board/esd/cpci5200/strataflash.c @@ -678,12 +678,10 @@ static ulong flash_get_size(ulong base, int banknum) static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *) dest; + cptr.cp = (uchar *)dest; /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 83dbfcb..2e07ac1 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -327,13 +327,11 @@ int phypower(int flag) int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - int status; + if (argv[1][0] == '0') + (void)phypower(0); + else + (void)phypower(1); - if (argv[1][0] == '0') { - status = phypower(0); - } else { - status = phypower(1); - } return (0); } diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c index eb89581..93ad57a 100644 --- a/board/etin/kvme080/multiverse.c +++ b/board/etin/kvme080/multiverse.c @@ -17,6 +17,7 @@ #include <common.h> #include <asm/io.h> #include <pci.h> +#include <linux/compiler.h> #include "multiverse.h" @@ -103,7 +104,7 @@ int multiv_reset(unsigned long base) void multiv_auto_slot_id(unsigned long base) { - unsigned int vector; + __maybe_unused unsigned int vector; int slot_id = 1; if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) { *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe; diff --git a/board/etx094/flash.c b/board/etx094/flash.c index fa51c90..0958e73 100644 --- a/board/etx094/flash.c +++ b/board/etx094/flash.c @@ -24,68 +24,53 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } /* Static FLASH Bank configuration here - FIXME XXX */ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0<<20); } - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - /* Remap FLASH according to real size */ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); #ifdef CONFIG_FLASH_16BIT - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ #else - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V; #endif /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ @@ -95,56 +80,26 @@ unsigned long flash_init (void) &flash_info[0]); #endif - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#ifdef CONFIG_FLASH_16BIT - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V | BR_PS_16; -#else - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } + memctl->memc_br1 = 0; /* invalidate bank 1 */ flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) { + if (info->flash_id == FLASH_UNKNOWN) return; - } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { + for (i = 0; i < info->sector_count; i++) info->start[i] = base + (i * 0x00002000); - } + return; } @@ -156,106 +111,119 @@ static void flash_get_offsets (ulong base, flash_info_t *info) info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { + for (i = 4; i < info->sector_count; i++) info->start[i] = base + (i * 0x00010000) - 0x00030000; #else info->start[0] = base + 0x00000000; info->start[1] = base + 0x00008000; info->start[2] = base + 0x0000C000; info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { + for (i = 4; i < info->sector_count; i++) info->start[i] = base + (i * 0x00020000) - 0x00060000; #endif - } } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { + for (; i >= 0; i--) info->start[i] = base + i * 0x00020000; - } } - } /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); + printf("missing or unknown FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - default: printf ("Unknown Vendor "); break; + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + default: + printf("Unknown Vendor "); + break; } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST200A: + printf("39xF200A (2M = 128K x 16)\n"); + break; + case FLASH_SST400A: + printf("39xF400A (4M = 256K x 16)\n"); + break; + case FLASH_SST800A: + printf("39xF800A (8M = 512K x 16)\n"); + break; + case FLASH_STM800AB: + printf("M29W800AB (8M = 512K x 16)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } - printf (" Size: %ld MB in %d Sectors\n", + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " " ); } - printf ("\n"); + printf("\n"); return; } -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - /* * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; ulong value; @@ -263,7 +231,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ #ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; s_addr[0x5555] = 0x00AA; s_addr[0x2AAA] = 0x0055; s_addr[0x5555] = 0x0090; @@ -293,7 +261,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - return (0); /* no or unknown flash */ + return 0; /* no or unknown flash */ } #ifdef CONFIG_FLASH_16BIT value = s_addr[1]; @@ -349,32 +317,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif break; -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif case SST_ID_xF200A: info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ + info->sector_count = 64; /* 39xF200A (2M = 128K x 16) */ info->size = 0x00080000; break; case SST_ID_xF400A: info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ + info->sector_count = 128; /* 39xF400A (4M = 256K x 16) */ info->size = 0x00100000; break; case SST_ID_xF800A: info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ + info->sector_count = 256; /* 39xF800A (8M = 512K x 16) */ info->size = 0x00200000; break; /* => 2 MB */ case STM_ID_x800AB: @@ -384,55 +339,55 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) break; /* => 2 MB */ default: info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + return 0; /* => no or unknown flash */ } if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", + printf("** ERROR: sector count %d > max (%d) **\n", info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { + for (i = 0; i < info->sector_count; i++) info->start[i] = base + (i * 0x00002000); - } } else { /* AMD and Fujitsu types */ /* set up sector start address table */ if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ #ifdef CONFIG_FLASH_16BIT info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + + (i * 0x00010000) - 0x00030000; #else info->start[0] = base + 0x00000000; info->start[1] = base + 0x00008000; info->start[2] = base + 0x0000C000; info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + + (i * 0x00020000) - 0x00060000; #endif - } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { + for (; i >= 0; i--) info->start[i] = base + i * 0x00020000; - } } /* check for protected sectors */ for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address: + /* + * read sector protection at sector address: * (A7 .. A0) = 0x02 * D0 = 1 if protected */ @@ -459,28 +414,23 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif } - return (info->size); + return info->size; } - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - vu_long *addr = (vu_long*)(info->start[0]); + vu_long *addr = (vu_long *)(info->start[0]); int flag, prot, sect; ulong start, now, last; #ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; #endif if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); return 1; } /*#ifndef CONFIG_FLASH_16BIT @@ -493,30 +443,29 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } #endif*/ prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } - start = get_timer (0); + start = get_timer(0); last = start; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ #ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short*)(info->start[sect]); + vu_short *s_sect_addr = (vu_short *)(info->start[sect]); #else - vu_long *sect_addr = (vu_long*)(info->start[sect]); + vu_long *sect_addr = (vu_long *)(info->start[sect]); #endif - /* Disable interrupts which might cause a timeout here */ + /* Disable interrupts which might cause a timeout */ flag = disable_interrupts(); #ifdef CONFIG_FLASH_16BIT @@ -541,20 +490,21 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); #ifdef CONFIG_FLASH_16BIT while ((s_sect_addr[0] & 0x0080) != 0x0080) { #else while ((sect_addr[0] & 0x00800080) != 0x00800080) { #endif - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); + /* show every second that we're waiting */ + if ((now - last) > 1000) { + putc('.'); last = now; } } @@ -569,7 +519,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0] = 0x00F000F0; /* reset bank */ #endif - printf (" done\n"); + printf(" done\n"); return 0; } @@ -581,37 +531,39 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) * 4 - Flash not identified */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; - if (info->flash_id == FLASH_UNKNOWN) { + if (info->flash_id == FLASH_UNKNOWN) return 4; - } wp = (addr & ~3); /* get lower word aligned address */ /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -620,33 +572,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } /*----------------------------------------------------------------------- @@ -655,22 +606,21 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - vu_long *addr = (vu_long*)(info->start[0]); + vu_long *addr = (vu_long *)(info->start[0]); #ifdef CONFIG_FLASH_16BIT vu_short high_data; vu_short low_data; - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; #endif ulong start; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest) & data) != data) + return 2; #ifdef CONFIG_FLASH_16BIT /* Write the 16 higher-bits */ @@ -685,20 +635,17 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *((vu_short *)dest) = high_data; - /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - /* Write the 16 lower-bits */ #endif @@ -725,7 +672,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); #ifdef CONFIG_FLASH_16BIT while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { @@ -733,12 +680,8 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { #endif - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/fads/fads.c b/board/fads/fads.c index 9f7faaf..317d279 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -603,15 +603,17 @@ static int initsdram(uint base, uint *noMbytes) phys_size_t initdram (int board_type) { uint sdramsz = 0; /* size of sdram in Mbytes */ - uint base = 0; /* base of dram in bytes */ uint m = 0; /* size of dram in Mbytes */ #ifndef CONFIG_MPC885ADS + uint base = 0; /* base of dram in bytes */ uint k, s; #endif #ifdef CONFIG_FADS if (!initsdram (0x00000000, &sdramsz)) { +#ifndef CONFIG_MPC885ADS base = sdramsz << 20; +#endif printf ("(%u MB SDRAM) ", sdramsz); } #endif diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index e7b22e3..3e9f4c3 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -32,9 +32,6 @@ SECTIONS arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*) arch/m68k/lib/libm68k.o (.text*) - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text*) - *(.text*) } _etext = .; diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 2caf4aa..5d48968 100644 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Modified during 2001 by @@ -61,8 +61,8 @@ const iop_conf_t iop_conf_tab[4][32] = { - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ @@ -95,10 +95,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, + }, - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ @@ -131,10 +131,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, + }, - /* Port C */ - { /* conf ppar psor pdir podr pdat */ + /* Port C */ + { /* conf ppar psor pdir podr pdat */ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ @@ -167,10 +167,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, + }, - /* Port D */ - { /* conf ppar psor pdir podr pdat */ + /* Port D */ + { /* conf ppar psor pdir podr pdat */ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ @@ -203,7 +203,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } + } }; typedef struct bscr_ { @@ -224,317 +224,329 @@ typedef struct pci_ic_s { void reset_phy(void) { - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - /* reset the FEC port */ - bcsr->bcsr1 &= ~FETH_RST; - bcsr->bcsr1 |= FETH_RST; + /* reset the FEC port */ + bcsr->bcsr1 &= ~FETH_RST; + bcsr->bcsr1 |= FETH_RST; } -int board_early_init_f (void) +int board_early_init_f(void) { - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; + volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT; - bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; + bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; - /* mask all PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; + /* mask all PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; - return 0; + return 0; } int checkboard(void) { - puts ("Board: Motorola MPC8266ADS\n"); - return 0; + puts("Board: Motorola MPC8266ADS\n"); + return 0; } phys_size_t initdram(int board_type) { /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - uint psrt = 0x21; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; - - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = rows = banks = cols = caslatency = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) - { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0xff; + volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; + int i; + + uint psrt = 0x21; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char data; + u_char cksum; + int j; + + /* + * Keep the compiler from complaining about + * potentially uninitialized vars + */ + data_width = rows = banks = cols = caslatency = 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + cksum = data; + for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - /*printf("addr %d = 0x%02x\n", j, data);*/ - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) - { + /*printf("addr %d = 0x%02x\n", j, data); */ + if (j == 5) + chipselects = data & 0x0F; + else if (j == 6) + data_width = data; + else if (j == 7) + data_width |= data << 8; + else if (j == 3) + rows = data & 0x0F; + else if (j == 4) + cols = data & 0x0F; + else if (j == 12) { /* - * Refresh rate: this assumes the prescaler is set to - * approximately 0.39uSec per tick and the target refresh period - * is about 85% of maximum. + * Refresh rate: this assumes the prescaler is set to + * approximately 0.39uSec per tick and the target + * refresh period is about 85% of maximum. */ - switch(data & 0x7F) - { - default: - case 0: psrt = 0x21; /* 15.625uS */ break; - case 1: psrt = 0x07; /* 3.9uS */ break; - case 2: psrt = 0x0F; /* 7.8uS */ break; - case 3: psrt = 0x43; /* 31.3uS */ break; - case 4: psrt = 0x87; /* 62.5uS */ break; - case 5: psrt = 0xFF; /* 125uS */ break; + switch (data & 0x7F) { + default: + case 0: + psrt = 0x21; /* 15.625uS */ + break; + case 1: + psrt = 0x07; /* 3.9uS */ + break; + case 2: + psrt = 0x0F; /* 7.8uS */ + break; + case 3: + psrt = 0x43; /* 31.3uS */ + break; + case 4: + psrt = 0x87; /* 62.5uS */ + break; + case 5: + psrt = 0xFF; /* 125uS */ + break; } - } - else if(j == 17) banks = data; - else if(j == 18) - { - caslatency = 3; /* default CL */ -# if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; -# else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; -# endif - else - { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", + } else if (j == 17) + banks = data; + else if (j == 18) { + caslatency = 3; /* default CL */ +#if (PESSIMISTIC_SDRAM) + if ((data & 0x04) != 0) + caslatency = 3; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x01) != 0) + caslatency = 1; +#else + if ((data & 0x01) != 0) + caslatency = 1; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x04) != 0) + caslatency = 3; +#endif + else { + printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); } - } - else if(j == 63) - { - if(data != cksum) - { - printf ("WARNING: Configuration data checksum failure:" + } else if (j == 63) { + if (data != cksum) { + printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", - data, cksum); + data, cksum); } } cksum += data; - } + } - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if (caslatency < 2) { printf("CL was %d, forcing to 2\n", caslatency); caslatency = 2; - } - if(rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", rows); + } + if (rows > 14) { + printf("This doesn't look good, rows = %d, should be <= 14\n", + rows); rows = 14; - } - if(cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", cols); + } + if (cols > 11) { + printf("This doesn't look good, columns = %d, should be <= 11\n", + cols); cols = 11; - } + } - if((data_width != 64) && (data_width != 72)) - { + if ((data_width != 64) && (data_width != 72)) { printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - - sdram_size = 1 << (rows + cols + banks + width); - /* hack for high density memory (512MB per CS) */ - /* !!!!! Will ONLY work with Page Based Interleave !!!!! - ( PSDMR[PBI] = 1 ) - */ - /* mamory actually has 11 column addresses, but the memory controller - doesn't really care. - the calculations that follow will however move the rows so that - they are muxed one bit off if you use 11 bit columns. - The solution is to tell the memory controller the correct size of the memory - but change the number of columns to 10 afterwards. - The 11th column addre will still be mucxed correctly onto the bus. - - Also be aware that the MPC8266ADS board Rev B has not connected - Row address 13 to anything. - - The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) - */ - if (cols > 10) - cols = 10; - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; + } + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) + banks = 1; + else if (banks == 4) + banks = 2; + else if (banks == 8) + banks = 3; + + + sdram_size = 1 << (rows + cols + banks + width); + /* hack for high density memory (512MB per CS) */ + /* !!!!! Will ONLY work with Page Based Interleave !!!!! + ( PSDMR[PBI] = 1 ) + */ + /* + * memory actually has 11 column addresses, but the memory + * controller doesn't really care. + * + * the calculations that follow will however move the rows so + * that they are muxed one bit off if you use 11 bit columns. + * + * The solution is to tell the memory controller the correct + * size of the memory but change the number of columns to 10 + * afterwards. + * + * The 11th column addre will still be mucxed correctly onto + * the bus. + * + * Also be aware that the MPC8266ADS board Rev B has not + * connected Row address 13 to anything. + * + * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) + */ + if (cols > 10) + cols = 10; + +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; #else - rowst = 32 - (rows + banks + cols + width); + rowst = 32 - (rows + banks + cols + width); #endif - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - - /*printf("memctl->memc_or2 = 0x%08x\n", or);*/ - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks - 1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + + /*printf("memctl->memc_or2 = 0x%08x\n", or); */ + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; #else - sdam = cols + banks - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; + sdam = cols + banks - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; #endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); +#if (PESSIMISTIC_SDRAM) + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | + PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | + PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX | BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #endif - /*printf("psdmr = 0x%08x\n", psdmr);*/ - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or2 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) + /*printf("psdmr = 0x%08x\n", psdmr); */ + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set + * when we get here. The SDRAM can be accessed at the address + * CONFIG_SYS_SDRAM_BASE. + */ + + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = psrt; + + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; + memctl->memc_or2 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) - { - ramaddr += sdram_size; + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if (chipselects > 1) { + ramaddr += sdram_size; memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; memctl->memc_or3 = or; @@ -551,28 +563,28 @@ phys_size_t initdram(int board_type) memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; - } + } /* print info */ printf("SDRAM configuration read from SPD\n"); printf("\tSize per side = %dMB\n", sdram_size >> 20); - printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); + printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", + chipselects, 1 << (banks), cols, rows, data_width); printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - printf(", Using Bank Based Interleave\n"); +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + printf(", Using Bank Based Interleave\n"); #else - printf(", Using Page Based Interleave\n"); + printf(", Using Page Based Interleave\n"); #endif printf("\tTotal size: "); - /* this delay only needed for original 16MB DIMM... - * Not needed for any other memory configuration */ - if ((sdram_size * chipselects) == (16 *1024 *1024)) - udelay (250000); - return (sdram_size * chipselects); - /*return (16 * 1024 * 1024);*/ -} + /* this delay only needed for original 16MB DIMM... + * Not needed for any other memory configuration */ + if ((sdram_size * chipselects) == (16 * 1024 * 1024)) + udelay(250000); + return sdram_size * chipselects; +} #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 0e7e0ce..1d7b4f6 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -30,6 +30,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <watchdog.h> +#include <pmic.h> +#include <fsl_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -69,16 +71,34 @@ int board_early_init_f(void) return 0; } +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + enable_caches(); + return 0; } int board_late_init(void) { + u32 val; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Enable RTC battery */ + pmic_reg_read(p, REG_POWER_CTL0, &val); + pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); + pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); #ifdef CONFIG_HW_WATCHDOG mxc_hw_watchdog_enable(); #endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h index 409aeb2..6aeb218 100644 --- a/board/freescale/mx35pdk/mx35pdk.h +++ b/board/freescale/mx35pdk/mx35pdk.h @@ -59,24 +59,6 @@ #define CCM_CCMR_CONFIG 0x003F4208 #define CCM_PDR0_CONFIG 0x00801000 -#define PLL_BRM_OFFSET 31 -#define PLL_PD_OFFSET 26 -#define PLL_MFD_OFFSET 16 -#define PLL_MFI_OFFSET 10 - -#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) -#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) -#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) -#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - /* MEMORY SETTING */ #define ESDCTL_0x92220000 0x92220000 #define ESDCTL_0xA2220000 0xA2220000 diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 2a0dad0..37e6e4d 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -38,8 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -static u32 system_rev; - #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, @@ -47,11 +45,6 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { }; #endif -u32 get_board_rev(void) -{ - return system_rev; -} - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -254,16 +247,14 @@ static void power_init(void) pmic_reg_write(p, REG_MODE_1, val); udelay(200); - gpio_direction_output(46, 0); - - /* Reset the ethernet controller over GPIO */ - writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); + mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1); + gpio_direction_output(46, 0); + udelay(500); gpio_set_value(46, 1); @@ -406,8 +397,6 @@ int board_early_init_f(void) int board_init(void) { - system_rev = get_cpu_rev(); - /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index c89da13..be32aee 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -37,11 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index eab9c5f..335661f 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -39,11 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 156f8b5..b4c7f33 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -38,11 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 776784f..87fa7fa 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -35,11 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index a4bfbc9..57bd21f 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -25,6 +25,7 @@ #include <mpc8260.h> #include <asm/m8260_pci.h> #include <miiphy.h> +#include <linux/compiler.h> #include "m88e6060.h" @@ -263,7 +264,7 @@ int board_early_init_f (void) int misc_init_r (void) { volatile ioport_t *iop; - unsigned char temp; + __maybe_unused unsigned char temp; #if 0 /* DUMP UPMA RAM */ volatile immap_t *immap; diff --git a/board/genietv/flash.c b/board/genietv/flash.c index 5313ad8..19a428a 100644 --- a/board/genietv/flash.c +++ b/board/genietv/flash.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -24,32 +24,33 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ @@ -59,21 +60,15 @@ unsigned long flash_init (void) &flash_info[0]); #endif - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- * Fix this to support variable sector sizes */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; @@ -87,73 +82,85 @@ static void flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); return; } - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_BM: + printf("BRIGHT MICRO "); + break; + default: + printf("Unknown Vendor "); + break; } - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); } - puts (" Sector Start Addresses:"); + puts(" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) - { + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - { - puts ("\n "); - } + puts("\n "); - printf (" %08lX%s", + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } - putc ('\n'); + putc('\n'); return; } /*----------------------------------------------------------------------- @@ -163,7 +170,7 @@ void flash_print_info (flash_info_t *info) * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; volatile unsigned char *caddr; @@ -173,9 +180,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#if 0 - printf("Base address is: %08x\n", caddr); -#endif + debug("Base address is: %8p\n", caddr); caddr[0x0555] = 0xAA; caddr[0x02AA] = 0x55; @@ -183,51 +188,47 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = caddr[0]; -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; + debug("Manufact ID: %02x\n", value); - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; + switch (value) { + case 0x1: /* AMD_MANUFACT */ + info->flash_id = FLASH_MAN_AMD; + break; + case 0x4: /* FUJ_MANUFACT */ + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; } value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + debug("Device ID: %02x\n", value); + + switch (value) { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ } - flash_get_offsets ((ulong)addr, &flash_info[0]); + flash_get_offsets((ulong)addr, &flash_info[0]); /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ + for (i = 0; i < info->sector_count; i++) { + /* + * read sector protection at sector address, + * (A7 .. A0) = 0x02 + * D0 = 1 if protected + */ caddr = (volatile unsigned char *)(info->start[i]); info->protect[i] = caddr[2] & 1; } @@ -235,52 +236,47 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* * Prevent writes to uninitialized FLASH. */ - if (info->flash_id != FLASH_UNKNOWN) - { + if (info->flash_id != FLASH_UNKNOWN) { caddr = (volatile unsigned char *)info->start[0]; *caddr = 0xF0; /* reset bank */ } - return (info->size); + return info->size; } - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); int flag, prot, sect, l_sect; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); + printf("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; @@ -295,7 +291,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0x02AA] = 0x55; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr = (volatile unsigned char *)(info->start[sect]); addr[0] = 0x30; @@ -308,7 +304,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -316,19 +312,21 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); + start = get_timer(0); last = start; addr = (volatile unsigned char *)(info->start[l_sect]); - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + while ((addr[0] & 0xFF) != 0xFF) { + + now = get_timer(start); + + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } @@ -339,7 +337,7 @@ DONE: addr[0] = 0xF0; /* reset bank */ - printf (" done\n"); + printf(" done\n"); return 0; } @@ -350,7 +348,7 @@ DONE: * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -360,23 +358,26 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -385,33 +386,33 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } /*----------------------------------------------------------------------- @@ -420,10 +421,11 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; + volatile unsigned char *cdest, *cdata; + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); ulong start; int flag, count = 4 ; @@ -431,39 +433,33 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) cdata = (volatile unsigned char *)&data ; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest) & data) != data) + return 2; - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); + while (count--) { - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - *cdest = *cdata; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); + *cdest = *cdata; - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*cdest ^ *cdata) & 0x80) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - } - cdata++ ; - cdest++ ; + cdata++ ; + cdest++ ; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c index 6035f69..fb29659 100644 --- a/board/gw8260/flash.c +++ b/board/gw8260/flash.c @@ -63,54 +63,50 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); /* functions */ /*********************************************************************/ -/*********************************************************************/ -/* NAME: flash_init() - initializes flash banks */ -/* */ -/* DESCRIPTION: */ -/* This function initializes the flash bank(s). */ -/* */ -/* RETURNS: */ -/* The size in bytes of the flash */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -unsigned long flash_init (void) +/* + * NAME: flash_init() - initializes flash banks + * + * DESCRIPTION: + * This function initializes the flash bank(s). + * + * RETURNS: + * The size in bytes of the flash + * + * RESTRICTIONS/LIMITATIONS: + * + * + */ +unsigned long flash_init(void) { - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + /* for now, only support the 4 MB Flash SIMM */ + (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, + &flash_info[0]); + /* + * protect monitor and environment sectors + */ #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); +#ifndef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); /*size*/ + return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */ } /*********************************************************************/ diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile new file mode 100644 index 0000000..f6b2854 --- /dev/null +++ b/board/hale/tt01/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o +COBJS := tt01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S new file mode 100644 index 0000000..6e9dc80 --- /dev/null +++ b/board/hale/tt01/lowlevel_init.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/macro.h> + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + mov pc, lr diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c new file mode 100644 index 0000000..2995c8f --- /dev/null +++ b/board/hale/tt01/tt01.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <command.h> +#include <pmic.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOARD_STRING "Board: HALE TT-01" + +/* Clock configuration */ +#define CCM_CCMR_SETUP 0x074B0BF5 + +static void board_setup_clocks(void) +{ + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; + volatile int wait = 0x10000; + + writel(CCM_CCMR_SETUP, &ccm->ccmr); + while (wait--) + ; + + writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr); + writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); + + /* Set up clock to 532MHz */ + writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | + PDR0_MCU_PODF(0), &ccm->pdr0); + writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12), + &ccm->mpctl); + writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1), + &ccm->spctl); +} + +/* DRAM configuration */ + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +/* + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + * note: all but tWTR (1), tRC (111) are reset defaults, + * the same values work in the jtag configuration + * + * Bluetechnix setup has 0x75e73a (for 128MB) = + * 0b 0111 0101 1110 0111 0011 1010 + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + */ +#define ESDCFG0_MDDR_SETUP 0x006ac73a +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +static void board_setup_sdram(void) +{ + u32 *pad; + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* + * setup pad control for the controller pins + * no loopback, no pull, no keeper, no open drain, + * standard input, standard drive, slow slew rate + */ + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) + *pad = 0; + + /* set up MX31 DDR Memory Controller */ + writel(ESDMISC_MDDR_SETUP, &esdc->misc); + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); + + /* perform DDR init sequence for CSD0 */ + writel(ESDCTL_PRECHARGE, &esdc->ctl0); + writel(0x12344321, CSD0_BASE+0x0f00); + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); + writel(0x12344321, CSD0_BASE); + writel(0x12344321, CSD0_BASE); + writel(ESDCTL_LOADMODEREG, &esdc->ctl0); + writeb(0xda, CSD0_BASE+0x33); + writeb(0xff, CSD0_BASE+0x1000000); + writel(ESDCTL_RW, &esdc->ctl0); + writel(0xDEADBEEF, CSD0_BASE); + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); +} + +static void tt01_spi3_hw_init(void) +{ + /* CSPI3 */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); + /* CSPI3, SS0 = Atlas */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); + + /* start CSPI3 clock (3 = always on except if PLL off) */ + setbits_le32(CCM_CGR0, 3 << 16); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_early_init_f(void) +{ + /* CS4: FPGA incl. network controller */ + struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + /* this seems essential, won't start without, but why? */ + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); + + board_setup_clocks(); + board_setup_sdram(); + mxc_setup_weimcs(4, &cs4); + + /* Setup UART2 and SPI3 pins */ + mx31_uart2_hw_init(); + tt01_spi3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int board_late_init(void) +{ + pmic_init(); + +#ifdef CONFIG_HW_WATCHDOG + mxc_hw_watchdog_enable(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts(BOARD_STRING "\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/hymod/input.c b/board/hymod/input.c index 998132d..1a2b8d2 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -76,7 +76,6 @@ hymod_get_ethaddr (void) if (n == 17) { int i; char *p, *q; - uchar ea[6]; /* see if it looks like an ethernet address */ @@ -85,7 +84,7 @@ hymod_get_ethaddr (void) for (i = 0; i < 6; i++) { char term = (i == 5 ? '\0' : ':'); - ea[i] = simple_strtol (p, &q, 16); + (void)simple_strtol (p, &q, 16); if ((q - p) != 2 || *q++ != term) break; diff --git a/board/icu862/flash.c b/board/icu862/flash.c index 2afeff4..7f72258 100644 --- a/board/icu862/flash.c +++ b/board/icu862/flash.c @@ -52,13 +52,12 @@ unsigned long flash_init (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } /* Static FLASH Bank configuration here - FIXME XXX */ @@ -70,27 +69,6 @@ unsigned long flash_init (void) size_b0 >> 20); } - if (FLASH_BASE1_PRELIM != 0x0) { - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)" - " > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 >> 20, - size_b0, size_b0 >> 20); - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - } else { - size_b1 = 0; - } - /* Remap FLASH according to real size */ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; @@ -117,13 +95,9 @@ unsigned long flash_init (void) #endif /* ICU862 Board has only one Flash Bank */ - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c index a4c0b54..dbe3c3c 100644 --- a/board/icu862/pcmcia.c +++ b/board/icu862/pcmcia.c @@ -18,18 +18,16 @@ static void cfg_port_B (void) { - volatile immap_t *immap; volatile cpm8xx_t *cp; uint reg; - immap = (immap_t *)CONFIG_SYS_IMMR; cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ + * Configure Port B for TPS2205 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ reg = cp->cp_pbdat; reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ @@ -47,7 +45,6 @@ static void cfg_port_B (void) int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; @@ -58,7 +55,6 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); @@ -188,7 +184,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; @@ -198,7 +193,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index d621833..02db07f 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -281,10 +281,9 @@ phys_size_t initdram (int board_type) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index d3d8ea5..2a29943 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -140,7 +140,6 @@ int board_init() mx25_uart1_init_pins(); #endif /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_TX25; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 6ef5e5d..ca33aae 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -207,8 +207,14 @@ int misc_init_r(void) if (wait_for_ne != NULL) { if (strcmp(wait_for_ne, "true") == 0) { int cnt = 0; + int abort = 0; puts("NE go: "); while (startup_allowed() == 0) { + if (tstc()) { + (void) getc(); /* consume input */ + abort = 1; + break; + } udelay(200000); cnt++; if (cnt == 5) @@ -218,7 +224,10 @@ int misc_init_r(void) puts(" \b\b\b\b"); } } - puts("OK\n"); + if (abort == 1) + printf("\nAbort waiting for ne\n"); + else + puts("OK\n"); } } #endif @@ -258,17 +267,17 @@ int board_early_init_f(void) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif - +#if defined(CONFIG_KM_RECONFIG_XLX) + /* trigger the reconfiguration of the xilinx fpga */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); +#endif return 0; } int board_init(void) { - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; - /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; @@ -396,6 +405,15 @@ int hush_init_var(void) #endif #if defined(CONFIG_BOOTCOUNT_LIMIT) +const ulong patterns[] = { 0x00000000, + 0xFFFFFFFF, + 0xFF00FF00, + 0x0F0F0F0F, + 0xF0F0F0F0}; +const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); +const ulong OFFS_PATTERN = 3; +const ulong REPEAT_PATTERN = 1000; + void bootcount_store(ulong a) { volatile ulong *save_addr; @@ -407,21 +425,34 @@ void bootcount_store(ulong a) save_addr = (ulong*)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(BOOTCOUNT_MAGIC, &save_addr[1]); + + for (i = 0; i < REPEAT_PATTERN; i++) + writel(patterns[i % NBR_OF_PATTERNS], + &save_addr[i+OFFS_PATTERN]); + } ulong bootcount_load(void) { volatile ulong *save_addr; volatile ulong size = 0; - int i; + ulong counter = 0; + int i, tmp; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size += gd->bd->bi_dram[i].size; } save_addr = (ulong*)(size - BOOTCOUNT_ADDR); - if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) - return 0; - else - return readl(save_addr); + + counter = readl(&save_addr[0]); + + /* Is the counter reliable, check in the big pattern for bit errors */ + for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { + tmp = readl(&save_addr[i+OFFS_PATTERN]); + if (tmp != patterns[i % NBR_OF_PATTERNS]) + counter = 0; + } + return counter; } #endif diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c index ce6b186..61ba586 100644 --- a/board/kup/common/pcmcia.c +++ b/board/kup/common/pcmcia.c @@ -20,7 +20,6 @@ int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; @@ -30,15 +29,14 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ /* clear interrupt state, and disable interrupts */ @@ -46,9 +44,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(slot); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -57,9 +55,9 @@ int pcmcia_hardware_enable(int slot) udelay(2500); /* - * Configure Port B pins for - * 3 Volts enable - */ + * Configure Port B pins for + * 3 Volts enable + */ if (slot) { /* Slot A is built-in */ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; @@ -67,8 +65,8 @@ int pcmcia_hardware_enable(int slot) cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ } /* - * Make sure there is a card in the slot, then configure the interface. - */ + * Make sure there is a card in the slot, then configure the interface. + */ udelay(10000); debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, @@ -79,8 +77,8 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On. - */ + * Power On. + */ printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); reg = pcmp->pcmc_pipr; @@ -149,7 +147,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; @@ -162,14 +159,13 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) if (!slot) /* Slot A is not configurable */ return 0; - immap = (immap_t *)CONFIG_SYS_IMMR; pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(slot); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -179,9 +175,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) debug ("PCMCIA power OFF\n"); /* - * Configure Port B pins for - * 3 Volts enable - */ + * Configure Port B pins for + * 3 Volts enable + */ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; /* remove all power */ diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 267821c..e1dc8f7 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -152,7 +152,7 @@ phys_size_t initdram(int board_type) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size = 0; - uchar *latch,rev,mod,tmp; + uchar *latch, rev, tmp; /* * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision @@ -164,7 +164,6 @@ phys_size_t initdram(int board_type) latch = (uchar *)0x90000200; tmp = swapbyte(*latch); rev = (tmp & 0xF8) >> 3; - mod = (tmp & 0x07); upmconfig(UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index 568fdf5..f3e3fce 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -62,14 +62,16 @@ int ide_preinit (void) &ide_bus_offset32); ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe; ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[0] & 0xfffffffe, - PCI_REGION_IO); - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) &ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[1] & 0xfffffffe, - PCI_REGION_IO); + ide_bus_offset[0] & 0xfffffffe, + PCI_REGION_IO); + if (CONFIG_SYS_IDE_MAXBUS > 1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffffe; + ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, + ide_bus_offset[1] & 0xfffffffe, + PCI_REGION_IO); + } } if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) { diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c index ad2e60d..acbb9d5 100644 --- a/board/lwmon/pcmcia.c +++ b/board/lwmon/pcmcia.c @@ -29,8 +29,6 @@ int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -51,10 +49,8 @@ int pcmcia_hardware_enable(int slot) #endif udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -171,7 +167,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile pcmconf8xx_t *pcmp; u_long reg; uchar val; @@ -181,7 +176,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) diff --git a/board/manroland/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c index ad25678..db3821a 100644 --- a/board/manroland/uc100/pcmcia.c +++ b/board/manroland/uc100/pcmcia.c @@ -27,8 +27,8 @@ static void cfg_ports (void) immap = (immap_t *)CONFIG_SYS_IMMR; /* - * Configure Port A for MAX1602 PC-Card Power-Interface Switch - */ + * Configure Port A for MAX1602 PC-Card Power-Interface Switch + */ immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ @@ -40,7 +40,6 @@ static void cfg_ports (void) int pcmcia_hardware_enable(int slot) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -52,15 +51,14 @@ int pcmcia_hardware_enable(int slot) immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ /* clear interrupt state, and disable interrupts */ @@ -68,9 +66,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -78,8 +76,8 @@ int pcmcia_hardware_enable(int slot) udelay(500); /* - * Make sure there is a card in the slot, then configure the interface. - */ + * Make sure there is a card in the slot, then configure the interface. + */ udelay(10000); debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, @@ -90,19 +88,19 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On. - */ + * Power On. + */ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); reg = pcmp->pcmc_pipr; debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, (reg&PCMCIA_VS1(slot))?"n":"ff", (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { + + if ((reg & mask) == mask) puts (" 5.0V card found: "); - } else { + else puts (" 3.3V card found: "); - } /* switch VCC on */ immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ @@ -154,8 +152,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("voltage_set: " @@ -163,12 +159,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -176,10 +170,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) udelay(500); /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ debug ("PCMCIA power OFF\n"); cfg_ports (); /* Enables switch, but all in Hi-Z */ diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile new file mode 100644 index 0000000..01cb517 --- /dev/null +++ b/board/matrix_vision/mvblx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += mvblx.o fpga.o +COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +COBJS := $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +CFLAGS += -Werror + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk new file mode 100644 index 0000000..cf055db --- /dev/null +++ b/board/matrix_vision/mvblx/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c new file mode 100644 index 0000000..dacc138 --- /dev/null +++ b/board/matrix_vision/mvblx/fpga.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2011 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include <asm/gpio.h> +#include "fpga.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, /* Altera_pre_fn */ + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + fast_passive_parallel, + Altera_EP3C5_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +#define GPIO_RESET 43 +#define GPIO_DCLK 65 +#define GPIO_nSTATUS 157 +#define GPIO_CONF_DONE 158 +#define GPIO_nCONFIG 159 +#define GPIO_DATA0 54 +#define GPIO_DATA1 55 +#define GPIO_DATA2 56 +#define GPIO_DATA3 57 +#define GPIO_DATA4 58 +#define GPIO_DATA5 60 +#define GPIO_DATA6 61 +#define GPIO_DATA7 62 + +DECLARE_GLOBAL_DATA_PTR; + +/* return FPGA_SUCCESS on success, else FPGA_FAIL + */ +int mvblx_init_fpga(void) +{ + fpga_debug("Initializing FPGA interface\n"); + fpga_init(); + fpga_add(fpga_altera, &cyclone2); + + if (gpio_request(GPIO_DCLK, "dclk") || + gpio_request(GPIO_nSTATUS, "nStatus") || +#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + gpio_request(GPIO_CONF_DONE, "conf_done") || +#endif + gpio_request(GPIO_nCONFIG, "nConfig") || + gpio_request(GPIO_DATA0, "data0") || + gpio_request(GPIO_DATA1, "data1") || + gpio_request(GPIO_DATA2, "data2") || + gpio_request(GPIO_DATA3, "data3") || + gpio_request(GPIO_DATA4, "data4") || + gpio_request(GPIO_DATA5, "data5") || + gpio_request(GPIO_DATA6, "data6") || + gpio_request(GPIO_DATA7, "data7")) { + printf("%s: error requesting GPIOs.", __func__); + return FPGA_FAIL; + } + + /* set up outputs */ + gpio_direction_output(GPIO_DCLK, 0); + gpio_direction_output(GPIO_nCONFIG, 0); + gpio_direction_output(GPIO_DATA0, 0); + gpio_direction_output(GPIO_DATA1, 0); + gpio_direction_output(GPIO_DATA2, 0); + gpio_direction_output(GPIO_DATA3, 0); + gpio_direction_output(GPIO_DATA4, 0); + gpio_direction_output(GPIO_DATA5, 0); + gpio_direction_output(GPIO_DATA6, 0); + gpio_direction_output(GPIO_DATA7, 0); + + /* NB omap_free_gpio() resets to an input, so we can't + * free ie. nCONFIG, or else the FPGA would reset + * Q: presumably gpio_free() has the same effect? + */ + + /* set up inputs */ + gpio_direction_input(GPIO_nSTATUS); +#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + gpio_direction_input(GPIO_CONF_DONE); +#endif + + fpga_config_fn(0, 1, 0); + udelay(60); + + return FPGA_SUCCESS; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert); + if (flush) { + gpio_set_value(GPIO_nCONFIG, !assert); + udelay(1); + gpio_set_value(GPIO_nCONFIG, assert); + } + + return assert; +} + +int fpga_done_fn(int cookie) +{ + int result = 0; + + /* since revA of BLX, we will not get this signal. */ + udelay(10); +#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + fpga_debug("not waiting for CONF_DONE."); + result = 1; +#else + fpga_debug("CONF_DONE check ... "); + if (gpio_get_value(GPIO_CONF_DONE)) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + gpio_free(GPIO_CONF_DONE); +#endif + + return result; +} + +int fpga_status_fn(int cookie) +{ + int result = 0; + fpga_debug("STATUS check ... "); + + result = gpio_get_value(GPIO_nSTATUS); + + if (result < 0) + fpga_debug("error\n"); + else if (result > 0) + fpga_debug("high\n"); + else + fpga_debug("low\n"); + + return result; +} + +static inline int _write_fpga(u8 byte) +{ + gpio_set_value(GPIO_DATA0, byte & 0x01); + gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01); + gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01); + gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01); + gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01); + gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01); + gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01); + gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01); + + /* clock */ + gpio_set_value(GPIO_DCLK, 1); + udelay(1); + gpio_set_value(GPIO_DCLK, 0); + udelay(1); + + return 0; +} + +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i]); + fpga_debug("-%s\n", __func__); + + return FPGA_SUCCESS; +} diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h new file mode 100644 index 0000000..3d427bf --- /dev/null +++ b/board/matrix_vision/mvblx/fpga.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvblx_init_fpga(void); + +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c new file mode 100644 index 0000000..74b5b19 --- /dev/null +++ b/board/matrix_vision/mvblx/mvblx.c @@ -0,0 +1,169 @@ +/* + * MATRIX VISION GmbH mvBlueLYNX-X + * + * Derived from Beagle and Overo + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "mvblx.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) +static void setup_net_chip(void); +#endif /* CONFIG_CMD_NET */ + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + printf("mvBlueLYNX-X\n"); + if (get_cpu_family() == CPU_OMAP36XX) + setenv("mpurate", "1000"); + else + setenv("mpurate", "600"); + + twl4030_power_init(); + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif /* CONFIG_CMD_NET */ + + mvblx_init_fpga(); + + mac_read_from_eeprom(); + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MVBLX(); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + omap_mmc_init(1); + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 139 as output pin */ + writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe); + + /* Now send a pulse on the GPIO pin */ + writel(GPIO11, &gpio5_base->setdataout); + udelay(1); + writel(GPIO11, &gpio5_base->cleardataout); + udelay(1); + writel(GPIO11, &gpio5_base->setdataout); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +int overwrite_console(void) +{ + /* return TRUE if console should be overwritten */ + return 0; +} + +#endif /* CONFIG_CMD_NET */ diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h new file mode 100644 index 0000000..cda5b0b --- /dev/null +++ b/board/matrix_vision/mvblx/mvblx.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2008 + * Dirk Behme <dirk.behme@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MVBLX_H_ +#define _MVBLX_H_ + +#include <asm/arch/sys_proto.h> + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 mvBlueLYNX-X camera", + "no NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MVBLX() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card 1*/\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\ + /*Expansion card 2 */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\ + MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\ + /* USB EHCI (port 2) not used */\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\ + /* USB EHCI (port 1) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\ + /*Die to Die */\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + +#endif diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c new file mode 100644 index 0000000..945a36d --- /dev/null +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -0,0 +1,395 @@ +/* + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * Timur Tabi (timur@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> + +/* #define DEBUG */ + +/* + * static eeprom: EEPROM layout + */ +static struct __attribute__ ((__packed__)) eeprom { + u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */ + u8 sn[10]; /* 0x10 - 0x19 Serial Number */ + u8 date[6]; /* 0x1A - 0x1F Build Date */ + u8 mac[6]; /* 0x20 - 0x25 MAC address */ + u8 reserved[10];/* 0x26 - 0x2f reserved */ + u32 crc; /* x+1 CRC32 checksum */ +} e; + +/* Set to 1 if we've read EEPROM into memory */ +static int has_been_read; + +/** + * show_eeprom - display the contents of the EEPROM + */ +static void show_eeprom(void) +{ + unsigned int crc; + char safe_string[16]; + +#ifdef DEBUG + int i; +#endif + u8 *p; + + /* ID */ + strncpy(safe_string, (char *)e.id, sizeof(e.id)); + safe_string[sizeof(e.id)-1] = 0; + printf("ID: mvBlueLYNX-X%s\n", safe_string); + + /* Serial number */ + strncpy(safe_string, (char *)e.sn, sizeof(e.sn)); + safe_string[sizeof(e.sn)-1] = 0; + printf("SN: %s\n", safe_string); + + /* Build date, BCD date values, as YYMMDDhhmmss */ + printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", + e.date[0], e.date[1], e.date[2], + e.date[3] & 0x7F, e.date[4], e.date[5], + e.date[3] & 0x80 ? "PM" : ""); + + /* Show MAC address */ + p = e.mac; + printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n", + p[0], p[1], p[2], p[3], p[4], p[5]); + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + + if (crc == be32_to_cpu(e.crc)) + printf("CRC: %08x\n", be32_to_cpu(e.crc)); + else + printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc); + +#ifdef DEBUG + printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); + for (i = 0; i < sizeof(e); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&e)[i]); + if (((i % 16) == 15) || (i == sizeof(e) - 1)) + printf("\n"); + } +#endif +} + +/** + * read_eeprom - read the EEPROM into memory + */ +static int read_eeprom(void) +{ + int ret; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + if (has_been_read) + return 0; + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e, sizeof(e)); + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + +#ifdef DEBUG + show_eeprom(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + + return ret; +} + +/** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc; + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + e.crc = cpu_to_be32(crc); +} + +/** + * prog_eeprom - write the EEPROM from memory + */ +static int prog_eeprom(void) +{ + int ret = 0; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + update_crc(); + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e, sizeof(e)); + + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; +#ifdef DEBUG + printf("%s verifying...\n", __func__); +#endif + ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e2, sizeof(e2)); + + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + + if (ret) { + printf("Programming failed.\n"); + has_been_read = 0; + return -1; + } + + printf("Programming passed.\n"); + return 0; +} + +/** + * h2i - converts hex character into a number + * + * This function takes a hexadecimal character (e.g. '7' or 'C') and returns + * the integer equivalent. + */ +static inline u8 h2i(char p) +{ + if ((p >= '0') && (p <= '9')) + return p - '0'; + + if ((p >= 'A') && (p <= 'F')) + return (p - 'A') + 10; + + if ((p >= 'a') && (p <= 'f')) + return (p - 'a') + 10; + + return 0; +} + +/** + * set_date - stores the build date into the EEPROM + * + * This function takes a pointer to a string in the format "YYMMDDhhmmss" + * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, + * and stores it in the build date field of the EEPROM local copy. + */ +static void set_date(const char *string) +{ + unsigned int i; + + if (strlen(string) != 12) { + printf("Usage: mac date YYMMDDhhmmss\n"); + return; + } + + for (i = 0; i < 6; i++) + e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); +} + +/** + * set_mac_address - stores a MAC address into the EEPROM + * + * This function takes a pointer to MAC address string + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and + * stores it in the MAC address field in the EEPROM local copy. + */ +static void set_mac_address(const char *string) +{ + char *p = (char *) string; + unsigned int i; + + for (i = 0; *p && (i < 6); i++) { + e.mac[i] = simple_strtoul(p, &p, 16); + if (*p == ':') + p++; + } + + update_crc(); +} + +int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char cmd; + + if (argc == 1) { + show_eeprom(); + return 0; + } + + cmd = argv[1][0]; + + if (cmd == 'r') { +#ifdef DEBUG + printf("%s read\n", __func__); +#endif + read_eeprom(); + return 0; + } + + if (argc == 2) { + switch (cmd) { + case 's': /* save */ +#ifdef DEBUG + printf("%s save\n", __func__); +#endif + prog_eeprom(); + break; + default: + return cmd_usage(cmdtp); + } + + return 0; + } + + /* We know we have at least one parameter */ + + switch (cmd) { + case 'n': /* serial number */ +#ifdef DEBUG + printf("%s serial number\n", __func__); +#endif + memset(e.sn, 0, sizeof(e.sn)); + strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); + break; + case 'd': /* date BCD format YYMMDDhhmmss */ + set_date(argv[2]); + break; + case 'e': /* errata */ + printf("mac errata not implemented\n"); + break; + case 'i': /* id */ + memset(e.id, 0, sizeof(e.id)); + strncpy((char *)e.id, argv[2], sizeof(e.id) - 1); + update_crc(); + break; + case 'p': /* ports */ + printf("mac ports not implemented (always 1 port)\n"); + break; + case '0' ... '9': + /* we only have "mac 0" but any digit can be used here */ + set_mac_address(argv[2]); + break; + case 'h': /* help */ + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +int mac_read_from_eeprom(void) +{ + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ + + if (read_eeprom()) { + printf("EEPROM Read failed.\n"); + return -1; + } + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { + printf("EEPROM CRC mismatch (%08x != %08x)\n", crc, + be32_to_cpu(e.crc)); + return -1; + } + + if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && + memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { + char ethaddr[9]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + e.mac[0], + e.mac[1], + e.mac[2], + e.mac[3], + e.mac[4], + e.mac[5]); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!getenv("ethaddr")) + setenv("ethaddr", ethaddr); + } + + if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) && + memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) { + char serial_num[12]; + + strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!getenv("serial#")) + setenv("serial#", serial_num); + } + + /* TODO should I calculate CRC here? */ + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial && (strlen(serial) > 3)) { + /* use the numerical part of the serial number LXnnnnnn */ + serialnr->high = 0; + serialnr->low = simple_strtoul(serial + 2, NULL, 10); + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c index 255796b..0f014e1 100644 --- a/board/mbx8xx/mbx8xx.c +++ b/board/mbx8xx/mbx8xx.c @@ -117,14 +117,16 @@ static const uint sdram_table_50[] = { /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_SYS_USE_OSCCLK static unsigned int get_reffreq(void); +#endif static unsigned int board_get_cpufreq(void); void mbx_init (void) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, refclock, plprcr, sccr; + ulong speed, plprcr, sccr; ulong br0_32 = memctl->memc_br0 & 0x400; /* real-time clock status and control register */ @@ -152,7 +154,6 @@ void mbx_init (void) immr->im_clkrst.car_sccr = sccr; speed = board_get_cpufreq (); - refclock = get_reffreq (); #if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) plprcr = CONFIG_SYS_PLPRCR; @@ -163,7 +164,7 @@ void mbx_init (void) #endif #ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; + plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; #endif immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; @@ -226,21 +227,27 @@ static unsigned int board_get_cpufreq (void) { #ifndef CONFIG_8xx_GCLK_FREQ vpd_packet_t *packet; + ulong *p; packet = vpd_find_packet (VPD_PID_ICS); - return *((ulong *) packet->data); + p = (ulong *)packet->data; + return *p; #else return((unsigned int)CONFIG_8xx_GCLK_FREQ ); #endif /* CONFIG_8xx_GCLK_FREQ */ } +#ifdef CONFIG_SYS_USE_OSCCLK static unsigned int get_reffreq (void) { vpd_packet_t *packet; + ulong *p; packet = vpd_find_packet (VPD_PID_RCS); - return *((ulong *) packet->data); + p = (ulong *)packet->data; + return *p; } +#endif static void board_get_enetaddr(uchar *addr) { diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c index e672d8c..497e260 100644 --- a/board/mbx8xx/pcmcia.c +++ b/board/mbx8xx/pcmcia.c @@ -77,10 +77,7 @@ int pcmcia_voltage_set (int slot, int vcc, int vpp) int pcmcia_hardware_enable (int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; uint reg, mask; debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", @@ -88,10 +85,7 @@ int pcmcia_hardware_enable (int slot) udelay (10000); - immap = (immap_t *) CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm)); /* clear interrupt state, and disable interrupts */ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 49213d0..4152873 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -341,7 +341,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; - int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; + int i, res = 0, cnt, old_ctrlc; char *env; long start, end; @@ -450,8 +450,6 @@ int do_auto_update(void) /* make sure that we see CTRL-C and save the old state */ old_ctrlc = disable_ctrlc(0); - bitmap_first = 0; - /* validate the images first */ for (i = 0; i < AU_MAXFILES; i++) { ulong imsize; @@ -506,14 +504,11 @@ int do_auto_update(void) /* this is really not a good idea, but it's what the */ /* customer wants. */ cnt = 0; - got_ctrlc = 0; do { res = au_do_update(i, sz); /* let the user break out of the loop */ if (ctrlc() || had_ctrlc()) { clear_ctrlc(); - if (res < 0) - got_ctrlc = 1; break; } cnt++; diff --git a/board/mousse/flash.c b/board/mousse/flash.c index d729f33..cc40535 100644 --- a/board/mousse/flash.c +++ b/board/mousse/flash.c @@ -776,8 +776,7 @@ void flash_print_info (flash_info_t * info) */ int flash_erase (flash_info_t * info, int s_first, int s_last) { - vu_long *addr = (vu_long *) (info->start[0]); - int prot, sect, l_sect; + int prot, sect; flash_dev_t *dev = NULL; if ((s_first < 0) || (s_first > s_last)) { @@ -803,17 +802,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Start erase on unprotected sectors */ dev = getFlashDevFromInfo (info); if (dev) { printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (dev->base); - /* printf("erase_sector: sector=%d, addr=0x%x\n", - sect, addr); */ printf ("."); if (ERROR == flashEraseSector (dev, sect)) { printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 61f031a..81d7271 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -600,7 +600,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i, rcode = 0; @@ -632,8 +632,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -672,7 +670,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) rcode |= wait_for_DQ7(info, sect); } } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -691,16 +688,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* wait at least 80us - let's wait 1 ms */ udelay (1000); -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - -DONE: -#endif /* reset to read mode */ addr = (FLASH_WORD_SIZE *)info->start[0]; addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ diff --git a/board/netta/codec.c b/board/netta/codec.c index c8d31d7..e303aa4 100644 --- a/board/netta/codec.c +++ b/board/netta/codec.c @@ -1386,34 +1386,31 @@ static inline unsigned int s_transfer_internal(int s_id, unsigned int address, u static void s_write_BR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = 0x70 | (regno & 15); val &= 0xff; - v = s_transfer_internal(s_id, address, val); + (void)s_transfer_internal(s_id, address, val); } static void s_write_OR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = 0x70 | (regno & 15); val &= 0xff; - v = s_transfer_internal(s_id, address, val); + (void)s_transfer_internal(s_id, address, val); } static void s_write_NR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = (regno & 7) << 4; val &= 0xf; - v = s_transfer_internal(s_id, address | val, 0x00); + (void)s_transfer_internal(s_id, address | val, 0x00); } #define BR7_IFR 0x08 /* IDL2 free run */ diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c index ed58f2c..3fa1925 100644 --- a/board/netta/pcmcia.c +++ b/board/netta/pcmcia.c @@ -147,23 +147,16 @@ static void set_shdn(int what) static void cfg_ports (void) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ cfg_shdn(); cfg_oc(); /* - * Configure Port A for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ + * Configure Port A for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ set_vppd(0, 1); set_vppd(1, 1); set_vccd(0, 0); set_vccd(1, 0); set_shdn(1); @@ -173,10 +166,7 @@ static void cfg_ports (void) int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; uint reg, pipr, mask; int i; @@ -184,10 +174,7 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); @@ -197,9 +184,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -221,8 +208,8 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); pipr = pcmp->pcmc_pipr; debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", @@ -267,15 +254,10 @@ int pcmcia_hardware_enable(int slot) #if defined(CONFIG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* Configure PCMCIA General Control Register */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; @@ -296,24 +278,19 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; - ushort sreg; debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -322,30 +299,29 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) udelay(500); /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ debug ("PCMCIA power OFF\n"); cfg_ports (); /* Enables switch, but all in Hi-Z */ - sreg = immap->im_ioport.iop_pcdat; set_vppd(0, 1); set_vppd(1, 1); switch(vcc) { - case 0: - break; /* Switch off */ + case 0: + break; /* Switch off */ - case 33: - set_vccd(0, 1); set_vccd(1, 0); - break; + case 33: + set_vccd(0, 1); set_vccd(1, 0); + break; - case 50: - set_vccd(0, 0); set_vccd(1, 1); - break; + case 50: + set_vccd(0, 0); set_vccd(1, 1); + break; - default: - goto done; + default: + goto done; } /* Checking supported voltages */ diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 64c8624..01dcd56 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -370,7 +370,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -404,7 +404,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } start = get_timer (0); - last = start; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -440,6 +439,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf (" done\n"); } } + + if (flag) + enable_interrupts(); + return rcode; } @@ -543,6 +546,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) ulong status; ulong start; int flag; + int rcode = 0; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -561,14 +565,17 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + rcode = 1; + break; } } *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); + if (flag) + enable_interrupts(); + + return rcode; } void inline spin_wheel (void) diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c index 85da41b..a939b31 100644 --- a/board/r360mpi/pcmcia.c +++ b/board/r360mpi/pcmcia.c @@ -19,7 +19,6 @@ int pcmcia_hardware_enable(int slot) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -31,7 +30,6 @@ int pcmcia_hardware_enable(int slot) immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -127,13 +125,11 @@ int pcmcia_hardware_enable(int slot) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* remove all power */ immap->im_ioport.iop_pcdat |= 0x0400; diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c index cb1e089..6be2bc9 100644 --- a/board/rbc823/flash.c +++ b/board/rbc823/flash.c @@ -24,32 +24,30 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -/*----------------------------------------------------------------------- +/* * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ @@ -59,21 +57,15 @@ unsigned long flash_init (void) &flash_info[0]); #endif - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- * Fix this to support variable sector sizes */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; @@ -87,83 +79,93 @@ static void flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); return; } - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_BM: + printf("BRIGHT MICRO "); + break; + default: + printf("Unknown Vendor "); + break; } - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); } - puts (" Sector Start Addresses:"); + puts(" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) - { + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - { - puts ("\n "); - } + puts("\n "); - printf (" %08lX%s", + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } - putc ('\n'); + putc('\n'); return; } -/*----------------------------------------------------------------------- - */ /* * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; volatile unsigned char *caddr; @@ -173,9 +175,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#if 0 - printf("Base address is: %08x\n", caddr); -#endif + debug("Base address is: %8p\n", caddr); caddr[0x0555] = 0xAA; caddr[0x02AA] = 0x55; @@ -183,51 +183,49 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = caddr[0]; -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; + debug("Manufact ID: %02x\n", value); + + switch (value) { + case 0x01: /*AMD_MANUFACT*/ + info->flash_id = FLASH_MAN_AMD; break; - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; + case 0x04: /*FUJ_MANUFACT*/ + info->flash_id = FLASH_MAN_FUJ; break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; } value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + debug("Device ID: %02x\n", value); + + switch (value) { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ } - flash_get_offsets ((ulong)addr, &flash_info[0]); + flash_get_offsets((ulong)addr, &flash_info[0]); /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ + for (i = 0; i < info->sector_count; i++) { + /* + * read sector protection at sector address, + * (A7 .. A0) = 0x02 + * D0 = 1 if protected + */ caddr = (volatile unsigned char *)(info->start[i]); info->protect[i] = caddr[2] & 1; } @@ -235,52 +233,48 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* * Prevent writes to uninitialized FLASH. */ - if (info->flash_id != FLASH_UNKNOWN) - { + if (info->flash_id != FLASH_UNKNOWN) { caddr = (volatile unsigned char *)info->start[0]; *caddr = 0xF0; /* reset bank */ } - return (info->size); + return info->size; } -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); int flag, prot, sect, l_sect; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); + printf("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; @@ -295,7 +289,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0x02AA] = 0x55; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr = (volatile unsigned char *)(info->start[sect]); addr[0] = 0x30; @@ -308,7 +302,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -316,19 +310,19 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); + start = get_timer(0); last = start; addr = (volatile unsigned char *)(info->start[l_sect]); - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + while ((addr[0] & 0xFF) != 0xFF) { + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } @@ -339,18 +333,18 @@ DONE: addr[0] = 0xF0; /* reset bank */ - printf (" done\n"); + printf(" done\n"); return 0; } -/*----------------------------------------------------------------------- +/* * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -360,23 +354,27 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -385,45 +383,46 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } -/*----------------------------------------------------------------------- +/* * Write a word to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; + volatile unsigned char *cdest, *cdata; + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); ulong start; int flag, count = 4 ; @@ -431,39 +430,32 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) cdata = (volatile unsigned char *)&data ; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest)&data) != data) + return 2; - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); + while (count--) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; - *cdest = *cdata; + *cdest = *cdata; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); + /* data polling for D7 */ + start = get_timer(0); + while ((*cdest ^ *cdata) & 0x80) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - } - cdata++ ; - cdest++ ; + cdata++ ; + cdest++ ; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c index be29b65..70ae1d2 100644 --- a/board/rpxsuper/flash.c +++ b/board/rpxsuper/flash.c @@ -47,41 +47,39 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size; - int i; + int i; - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } + /* Init: no FLASHes known */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; - /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); + /* for now, only support the 4 MB Flash SIMM */ + (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, + &flash_info[0]); - /* - * protect monitor and environment sectors - */ + /* + * protect monitor and environment sectors + */ #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); +#ifndef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); + return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; } /*----------------------------------------------------------------------- diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index 61cab87..536d7de 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -39,7 +39,7 @@ extern void eth_loopback_test(void); #endif /* CONFIG_ETHER_LOOPBACK_TEST */ #include "clkinit.h" -#include "ioconfig.h" /* I/O configuration table */ +#include "ioconfig.h" /* I/O configuration table */ /* * PBI Page Based Interleaving @@ -61,88 +61,86 @@ extern void eth_loopback_test(void); /* * ADC/DAC Defines: */ -#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ -#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ -#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ -#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ -#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ +#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ +#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ +#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ +#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ +#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ /* * ADC Defines: */ -#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ -#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ +#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ +#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ -#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ -#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ +#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ +#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ -#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ -#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ -#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ +#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ +#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ +#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ #define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) - /* Wait at least 4100 LRCLK's */ - -#define ADC_REG1_FRAME_START 0x80 /* Frame start */ -#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ -#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ -#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ - -#define ADC_REG2_128x 0x80 /* Oversample at 128x */ -#define ADC_REG2_CAL 0x40 /* System calibration enable */ -#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ -#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ -#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ -#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ -#define ADC_REG2_DFS 0x02 /* Digital format select */ -#define ADC_REG2_MUTE 0x01 /* Mute */ - -#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ -#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ -#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ -#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ -#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ -#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ -#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ + /* Wait at least 4100 LRCLK's */ + +#define ADC_REG1_FRAME_START 0x80 /* Frame start */ +#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ +#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ +#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ + +#define ADC_REG2_128x 0x80 /* Oversample at 128x */ +#define ADC_REG2_CAL 0x40 /* System calibration enable */ +#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ +#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ +#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ +#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ +#define ADC_REG2_DFS 0x02 /* Digital format select */ +#define ADC_REG2_MUTE 0x01 /* Mute */ + +#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ +#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ +#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ +#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ +#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ +#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ +#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ /* * DAC Defines: */ -#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ +#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ -#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ -#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ -#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ +#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ +#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ +#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ -#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ +#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ -#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ -#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ -#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ -#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ -#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ -#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ +#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ +#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ +#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ +#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ +#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ +#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ -#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ -#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ -#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ -#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ +#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ +#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ +#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ +#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ -#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ -#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ -#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ -#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ +#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ +#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ +#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ +#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ -#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ -#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ -#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ -#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ -#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ -#define DAC_REG5_FREEZE 0x04 /* Freeze */ -#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ -#define DAC_REG5_RESERVED 0x01 /* Reserved */ - -/* ------------------------------------------------------------------------- */ +#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ +#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ +#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ +#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ +#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ +#define DAC_REG5_FREEZE 0x04 /* Freeze */ +#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ +#define DAC_REG5_RESERVED 0x01 /* Reserved */ /* * Check Board Identity: @@ -150,290 +148,297 @@ extern void eth_loopback_test(void); int checkboard(void) { - printf ("SACSng\n"); + printf("SACSng\n"); - return 0; + return 0; } -/* ------------------------------------------------------------------------- */ - phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - uint psrt = 14; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0; + volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; + int i; + uint psrt = 14; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + #ifdef SDRAM_SPD_ADDR - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char data; + u_char cksum; + int j; #endif #ifdef SDRAM_SPD_ADDR - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = chipselects = rows = banks = cols = caslatency = psrt = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 1uSec per tick. - */ - switch(data & 0x7F) { - default: - case 0: psrt = 14 ; /* 15.625uS */ break; - case 1: psrt = 2; /* 3.9uS */ break; - case 2: psrt = 6; /* 7.8uS */ break; - case 3: psrt = 29; /* 31.3uS */ break; - case 4: psrt = 60; /* 62.5uS */ break; - case 5: psrt = 120; /* 125uS */ break; - } - } - else if(j == 17) banks = data; - else if(j == 18) { - caslatency = 3; /* default CL */ + /* Keep the compiler from complaining about potentially uninitialized vars */ + data_width = chipselects = rows = banks = cols = caslatency = psrt = + 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + cksum = data; + for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ + i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); + if (j == 5) + chipselects = data & 0x0F; + else if (j == 6) + data_width = data; + else if (j == 7) + data_width |= data << 8; + else if (j == 3) + rows = data & 0x0F; + else if (j == 4) + cols = data & 0x0F; + else if (j == 12) { + /* + * Refresh rate: this assumes the prescaler is set to + * approximately 1uSec per tick. + */ + switch (data & 0x7F) { + default: + case 0: + psrt = 14; /* 15.625uS */ + break; + case 1: + psrt = 2; /* 3.9uS */ + break; + case 2: + psrt = 6; /* 7.8uS */ + break; + case 3: + psrt = 29; /* 31.3uS */ + break; + case 4: + psrt = 60; /* 62.5uS */ + break; + case 5: + psrt = 120; /* 125uS */ + break; + } + } else if (j == 17) + banks = data; + else if (j == 18) { + caslatency = 3; /* default CL */ #if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; + if ((data & 0x04) != 0) + caslatency = 3; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x01) != 0) + caslatency = 1; #else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; + if ((data & 0x01) != 0) + caslatency = 1; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x04) != 0) + caslatency = 3; #endif - else { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } + else { + printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); + } + } else if (j == 63) { + if (data != cksum) { + printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum); + } + } + cksum += data; } - else if(j == 63) { - if(data != cksum) { - printf ("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } + + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if (caslatency < 2) { + printf("WARNING: CL was %d, forcing to 2\n", caslatency); + caslatency = 2; + } + if (rows > 14) { + printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", + rows); + rows = 14; + } + if (cols > 11) { + printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", + cols); + cols = 11; + } + + if ((data_width != 64) && (data_width != 72)) { + printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", + data_width); } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { - printf("WARNING: CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if(rows > 14) { - printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows); - rows = 14; - } - if(cols > 11) { - printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols); - cols = 11; - } - - if((data_width != 64) && (data_width != 72)) - { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - sdram_size = 1 << (rows + cols + banks + width); - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) + banks = 1; + else if (banks == 4) + banks = 2; + else if (banks == 8) + banks = 3; + + sdram_size = 1 << (rows + cols + banks + width); + +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; #else - rowst = 32 - (rows + banks + cols + width); + rowst = 32 - (rows + banks + cols + width); #endif - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - memctl->memc_or2 = or; - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks - 1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + memctl->memc_or2 = or; + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; #else - sdam = cols - 6; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; + sdam = cols - 6; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; #endif #if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | + PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | + PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX | BUFCMD) | + caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #endif #endif - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) { - ramaddr += sdram_size; + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. + */ - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = psrt; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) - *ramaddr = c; + *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; - } - /* return total ram size */ - return (sdram_size * chipselects); + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if (chipselects > 1) { + ramaddr += sdram_size; + + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; + memctl->memc_or3 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + } + + /* return total ram size */ + return (sdram_size * chipselects); } /*----------------------------------------------------------------------- * Board Control Functions */ -void board_poweroff (void) +void board_poweroff(void) { - while (1); /* hang forever */ + while (1); /* hang forever */ } @@ -441,301 +446,288 @@ void board_poweroff (void) /* ------------------------------------------------------------------------- */ int misc_init_r(void) { - /* - * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. - */ - volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); - volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); - - int reg; /* I2C register value */ - char *ep; /* Environment pointer */ - char str_buf[12] ; /* sprintf output buffer */ - int sample_rate; /* ADC/DAC sample rate */ - int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ - int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ - int right_just; /* Is the data to the DAC right justified? */ - int mclk_divide; /* MCLK Divide */ - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - if ((ep = getenv("quiet")) != NULL) { - quiet = simple_strtol(ep, NULL, 10); - } - else { - setenv("quiet", "0"); - } - - /* - * SACSng custom initialization: - * Start the ADC and DAC clocks, since the Crystal parts do not - * work on the I2C bus until the clocks are running. - */ - - sample_rate = INITIAL_SAMPLE_RATE; - if ((ep = getenv("DaqSampleRate")) != NULL) { - sample_rate = simple_strtol(ep, NULL, 10); - } - - sample_64x = INITIAL_SAMPLE_64X; - sample_128x = INITIAL_SAMPLE_128X; - if ((ep = getenv("Daq64xSampling")) != NULL) { - sample_64x = simple_strtol(ep, NULL, 10); + /* + * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. + */ + volatile ioport_t *iopa = + ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ ); + volatile ioport_t *iop = + ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); + + int reg; /* I2C register value */ + char *ep; /* Environment pointer */ + char str_buf[12]; /* sprintf output buffer */ + int sample_rate; /* ADC/DAC sample rate */ + int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ + int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ + int right_just; /* Is the data to the DAC right justified? */ + int mclk_divide; /* MCLK Divide */ + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + + if ((ep = getenv("quiet")) != NULL) + quiet = simple_strtol(ep, NULL, 10); + else + setenv("quiet", "0"); + + /* + * SACSng custom initialization: + * Start the ADC and DAC clocks, since the Crystal parts do not + * work on the I2C bus until the clocks are running. + */ + + sample_rate = INITIAL_SAMPLE_RATE; + if ((ep = getenv("DaqSampleRate")) != NULL) + sample_rate = simple_strtol(ep, NULL, 10); + + sample_64x = INITIAL_SAMPLE_64X; + sample_128x = INITIAL_SAMPLE_128X; + if ((ep = getenv("Daq64xSampling")) != NULL) { + sample_64x = simple_strtol(ep, NULL, 10); + if (sample_64x) + sample_128x = 0; + else + sample_128x = 1; + } else { + if ((ep = getenv("Daq128xSampling")) != NULL) { + sample_128x = simple_strtol(ep, NULL, 10); + if (sample_128x) + sample_64x = 0; + else + sample_64x = 1; + } + } + + /* + * Stop the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has really stopped. + */ + Daq_Stop_Clocks(); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + /* + * Initialize the clocks with the new rates + */ + Daq_Init_Clocks(sample_rate, sample_64x); + sample_rate = Daq_Get_SampleRate(); + + /* + * Start the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has become stable. + */ + Daq_Start_Clocks(sample_rate); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + sprintf(str_buf, "%d", sample_rate); + setenv("DaqSampleRate", str_buf); + if (sample_64x) { - sample_128x = 0; + setenv("Daq64xSampling", "1"); + setenv("Daq128xSampling", NULL); + } else { + setenv("Daq64xSampling", NULL); + setenv("Daq128xSampling", "1"); } - else { - sample_128x = 1; + + /* + * Display the ADC/DAC clocking information + */ + if (!quiet) + Daq_Display_Clocks(); + + /* + * Determine the DAC data justification + */ + + right_just = INITIAL_RIGHT_JUST; + if ((ep = getenv("DaqDACRightJustified")) != NULL) + right_just = simple_strtol(ep, NULL, 10); + + sprintf(str_buf, "%d", right_just); + setenv("DaqDACRightJustified", str_buf); + + /* + * Determine the DAC MCLK Divide + */ + + mclk_divide = INITIAL_MCLK_DIVIDE; + if ((ep = getenv("DaqDACMClockDivide")) != NULL) + mclk_divide = simple_strtol(ep, NULL, 10); + + sprintf(str_buf, "%d", mclk_divide); + setenv("DaqDACMClockDivide", str_buf); + + /* + * Initializing the I2C address in the Crystal A/Ds: + * + * 1) Wait for VREF cap to settle (10uSec per uF) + * 2) Release pullup on SDATA + * 3) Write the I2C address to register 6 + * 4) Enable address matching by setting the MSB in register 7 + */ + + if (!quiet) + printf("Initializing the ADC...\n"); + + udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ + + iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ + ADC_REG7_ADDR_ENABLE); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; + if (reg != I2C_ADC_1_ADDR) { + printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_1_ADDR); } - } - else { - if ((ep = getenv("Daq128xSampling")) != NULL) { - sample_128x = simple_strtol(ep, NULL, 10); - if (sample_128x) { - sample_64x = 0; - } - else { - sample_64x = 1; - } + + iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + /* set address (do not set ADDREN yet) */ + i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); + + i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; + if (reg != I2C_ADC_2_ADDR) { + printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_2_ADDR); } - } - - /* - * Stop the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has really stopped. - */ - Daq_Stop_Clocks(); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - /* - * Initialize the clocks with the new rates - */ - Daq_Init_Clocks(sample_rate, sample_64x); - sample_rate = Daq_Get_SampleRate(); - - /* - * Start the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has become stable. - */ - Daq_Start_Clocks(sample_rate); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - sprintf(str_buf, "%d", sample_rate); - setenv("DaqSampleRate", str_buf); - - if (sample_64x) { - setenv("Daq64xSampling", "1"); - setenv("Daq128xSampling", NULL); - } - else { - setenv("Daq64xSampling", NULL); - setenv("Daq128xSampling", "1"); - } - - /* - * Display the ADC/DAC clocking information - */ - if (!quiet) { - Daq_Display_Clocks(); - } - - /* - * Determine the DAC data justification - */ - - right_just = INITIAL_RIGHT_JUST; - if ((ep = getenv("DaqDACRightJustified")) != NULL) { - right_just = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", right_just); - setenv("DaqDACRightJustified", str_buf); - - /* - * Determine the DAC MCLK Divide - */ - - mclk_divide = INITIAL_MCLK_DIVIDE; - if ((ep = getenv("DaqDACMClockDivide")) != NULL) { - mclk_divide = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", mclk_divide); - setenv("DaqDACMClockDivide", str_buf); - - /* - * Initializing the I2C address in the Crystal A/Ds: - * - * 1) Wait for VREF cap to settle (10uSec per uF) - * 2) Release pullup on SDATA - * 3) Write the I2C address to register 6 - * 4) Enable address matching by setting the MSB in register 7 - */ - - if (!quiet) { - printf("Initializing the ADC...\n"); - } - udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ - - iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ - ADC_REG7_ADDR_ENABLE); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_1_ADDR) - printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_1_ADDR); - - iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */ - - i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_2_ADDR) - printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_2_ADDR); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ - ADC_REG1_FRAME_START | - ADC_REG1_GROUND_CAL); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_CAL | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ - - /* - * Now that we have synchronized the ADC's, enable address - * selection on the second ADC as well as the first. - */ - i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); - - /* - * Initialize the Crystal DAC - * - * Two of the config lines are used for I2C so we have to set them - * to the proper initialization state without inadvertantly - * sending an I2C "start" sequence. When we bring the I2C back to - * the normal state, we send an I2C "stop" sequence. - */ - if (!quiet) { - printf("Initializing the DAC...\n"); - } - - /* - * Bring the I2C clock and data lines low for initialization - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - - /* Reset the DAC */ - iopa->pdat &= ~DAC_RST_MASK; - udelay(DAC_RESET_DELAY); - - /* Release the DAC reset */ - iopa->pdat |= DAC_RST_MASK; - udelay(DAC_INITIAL_DELAY); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Cause the DAC to: - * Auto-mute disabled - * . Format 0, left justified 24 bits - * . Format 3, right justified 24 bits - * No de-emphasis - * . Single speed mode - * . Double speed mode - */ - i2c_reg_write(I2C_DAC_ADDR, 0x01, - (right_just ? DAC_REG1_RIGHT_JUST_24BIT : - DAC_REG1_LEFT_JUST_24_BIT) | - DAC_REG1_DEM_NO | - (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); - - sprintf(str_buf, "%d", - sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); - setenv("DaqDACFunctionalMode", str_buf); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Remove power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Create a I2C stop condition: - * low->high on data while clock is high. - */ - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; - - if (!quiet) { - printf("\n"); - } + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ + ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_CAL | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ + + /* + * Now that we have synchronized the ADC's, enable address + * selection on the second ADC as well as the first. + */ + i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); + + /* + * Initialize the Crystal DAC + * + * Two of the config lines are used for I2C so we have to set them + * to the proper initialization state without inadvertantly + * sending an I2C "start" sequence. When we bring the I2C back to + * the normal state, we send an I2C "stop" sequence. + */ + if (!quiet) + printf("Initializing the DAC...\n"); + + /* + * Bring the I2C clock and data lines low for initialization + */ + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(0); + I2C_ACTIVE; + I2C_DELAY; + + /* Reset the DAC */ + iopa->pdat &= ~DAC_RST_MASK; + udelay(DAC_RESET_DELAY); + + /* Release the DAC reset */ + iopa->pdat |= DAC_RST_MASK; + udelay(DAC_INITIAL_DELAY); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + DAC_REG5_POWER_DOWN | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Cause the DAC to: + * Auto-mute disabled + * . Format 0, left justified 24 bits + * . Format 3, right justified 24 bits + * No de-emphasis + * . Single speed mode + * . Double speed mode + */ + i2c_reg_write(I2C_DAC_ADDR, 0x01, + (right_just ? DAC_REG1_RIGHT_JUST_24BIT : + DAC_REG1_LEFT_JUST_24_BIT) | + DAC_REG1_DEM_NO | + (sample_rate >= + 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); + + sprintf(str_buf, "%d", + sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); + setenv("DaqDACFunctionalMode", str_buf); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Remove power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Create a I2C stop condition: + * low->high on data while clock is high. + */ + I2C_SCL(1); + I2C_DELAY; + I2C_SDA(1); + I2C_DELAY; + I2C_TRISTATE; + + if (!quiet) + printf("\n"); #ifdef CONFIG_ETHER_LOOPBACK_TEST - /* - * Run the Ethernet loopback test - */ - eth_loopback_test (); + /* + * Run the Ethernet loopback test + */ + eth_loopback_test(); #endif /* CONFIG_ETHER_LOOPBACK_TEST */ #ifdef CONFIG_SHOW_BOOT_PROGRESS - /* - * Turn off the RED fail LED now that we are up and running. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); + /* + * Turn off the RED fail LED now that we are up and running. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_OFF); #endif - return 0; + return 0; } #ifdef CONFIG_SHOW_BOOT_PROGRESS @@ -749,85 +741,86 @@ int misc_init_r(void) */ static void flash_code(uchar number, uchar modulo, uchar digits) { - int j; - - /* - * Recursively do upper digits. - */ - if(digits > 1) { - flash_code(number / modulo, modulo, digits - 1); - } - - number = number % modulo; - - /* - * Zero is indicated by one long flash (dash). - */ - if(number == 0) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(1000000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } else { - /* - * Non-zero is indicated by short flashes, one per count. - */ - for(j = 0; j < number; j++) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(100000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } - } - /* - * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total - */ - udelay(700000); -} - -static int last_boot_progress; + int j; -void show_boot_progress (int status) -{ - int i,j; - if(status > 0) { - last_boot_progress = status; - } else { /* - * If a specific failure code is given, flash this code - * else just use the last success code we've seen + * Recursively do upper digits. */ - if(status < -1) - last_boot_progress = -status; + if (digits > 1) + flash_code(number / modulo, modulo, digits - 1); + + number = number % modulo; /* - * Flash this code 5 times + * Zero is indicated by one long flash (dash). */ - for(j=0; j<5; j++) { - /* - * Houston, we have a problem. - * Blink the last OK status which indicates where things failed. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - - /* - * Delay 5 seconds between repetitions, - * with the fault LED blinking - */ - for(i=0; i<5; i++) { - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); - udelay(500000); - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - udelay(500000); - } + if (number == 0) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(1000000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } else { + /* + * Non-zero is indicated by short flashes, one per count. + */ + for (j = 0; j < number; j++) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(100000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } } - /* - * Reset the board to retry initialization. + * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total */ - do_reset (NULL, 0, 0, NULL); - } + udelay(700000); +} + +static int last_boot_progress; + +void show_boot_progress(int status) +{ + int i, j; + + if (status > 0) { + last_boot_progress = status; + } else { + /* + * If a specific failure code is given, flash this code + * else just use the last success code we've seen + */ + if (status < -1) + last_boot_progress = -status; + + /* + * Flash this code 5 times + */ + for (j = 0; j < 5; j++) { + /* + * Houston, we have a problem. + * Blink the last OK status which indicates where things failed. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + flash_code(last_boot_progress, 5, 3); + + /* + * Delay 5 seconds between repetitions, + * with the fault LED blinking + */ + for (i = 0; i < 5; i++) { + status_led_set(STATUS_LED_RED, + STATUS_LED_OFF); + udelay(500000); + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + udelay(500000); + } + } + + /* + * Reset the board to retry initialization. + */ + do_reset(NULL, 0, 0, NULL); + } } #endif /* CONFIG_SHOW_BOOT_PROGRESS */ @@ -841,27 +834,29 @@ void show_boot_progress (int status) #define SPI_DAC_CS_MASK 0x00001000 static const u32 cs_mask[] = { - SPI_ADC_CS_MASK, - SPI_DAC_CS_MASK, + SPI_ADC_CS_MASK, + SPI_DAC_CS_MASK, }; int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); + return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); } void spi_cs_activate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); + volatile ioport_t *iopd = + ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - iopd->pdat &= ~cs_mask[slave->cs]; + iopd->pdat &= ~cs_mask[slave->cs]; } void spi_cs_deactivate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); + volatile ioport_t *iopd = + ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - iopd->pdat |= cs_mask[slave->cs]; + iopd->pdat |= cs_mask[slave->cs]; } #endif diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index bb6eaf6..3a885a5 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -41,7 +41,7 @@ OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) ALL +=$(obj).depend $(LIB) ifdef CONFIG_SPL_BUILD -ALL += tools/mk$(BOARD)spl.exe +ALL += $(OBJTREE)/tools/mk$(BOARD)spl endif all: $(ALL) @@ -50,8 +50,8 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) ifdef CONFIG_SPL_BUILD -tools/mk$(BOARD)spl.exe: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe +$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl endif ######################################################################### diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index d168abd..56e0c16 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -26,16 +26,33 @@ LIB = $(obj)lib$(BOARD).o SOBJS := mem_setup.o SOBJS += lowlevel_init.o +ifndef CONFIG_SPL_BUILD COBJS += smdkv310.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS += mmc_boot.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -all: $(obj).depend $(LIB) +ALL := $(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL += $(OBJTREE)/tools/mk$(BOARD)spl +endif + +all: $(ALL) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +ifdef CONFIG_SPL_BUILD +$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/samsung/smdkv310/mmc_boot.c b/board/samsung/smdkv310/mmc_boot.c new file mode 100644 index 0000000..d3fc18d --- /dev/null +++ b/board/samsung/smdkv310/mmc_boot.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<config.h> + +/* +* Copy U-boot from mmc to RAM: +* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains +* API (Data transfer from mmc to ram) +*/ +void copy_uboot_to_ram(void) +{ + u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR; + + copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + copy_uboot_to_ram(); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /*Function attribute is no-return*/ + /*This Function never executes*/ + while (1) + ; +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index e0b89dd..d9caca7 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,7 +57,6 @@ int board_init(void) smc9115_pre_init(); - gd->bd->bi_arch_number = MACH_TYPE_SMDKV310; gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } @@ -75,13 +74,17 @@ int dram_init(void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ + PHYS_SDRAM_1_SIZE); gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ + PHYS_SDRAM_2_SIZE); gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ + PHYS_SDRAM_3_SIZE); gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ + PHYS_SDRAM_4_SIZE); } int board_eth_init(bd_t *bis) diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mkv310_image.c new file mode 100644 index 0000000..1a51913 --- /dev/null +++ b/board/samsung/smdkv310/tools/mkv310_image.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <fcntl.h> +#include <errno.h> +#include <string.h> +#include <sys/stat.h> + +#define CHECKSUM_OFFSET (14*1024-4) +#define BUFSIZE (16*1024) +#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ + | S_IWGRP | S_IROTH | S_IWOTH) +/* +* Requirement: +* IROM code reads first 14K bytes from boot device. +* It then calculates the checksum of 14K-4 bytes and compare with data at +* 14K-4 offset. +* +* This function takes two filenames: +* IN "u-boot-spl.bin" and +* OUT "u-boot-mmc-spl.bin" as filenames. +* It reads the "u-boot-spl.bin" in 16K buffer. +* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. +* It writes the buffer to "u-boot-mmc-spl.bin" file. +*/ + +int main(int argc, char **argv) +{ + int i, len; + unsigned char buffer[BUFSIZE] = {0}; + int ifd, ofd; + unsigned int checksum = 0, count; + + if (argc != 3) { + printf(" %d Wrong number of arguments\n", argc); + exit(EXIT_FAILURE); + } + + ifd = open(argv[1], O_RDONLY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[1], strerror(errno)); + exit(EXIT_FAILURE); + } + + ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[2], strerror(errno)); + if (ifd) + close(ifd); + exit(EXIT_FAILURE); + } + + len = lseek(ifd, 0, SEEK_END); + lseek(ifd, 0, SEEK_SET); + + count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; + + if (read(ifd, buffer, count) != count) { + fprintf(stderr, "%s: Can't read %s: %s\n", + argv[0], argv[1], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) + checksum += buffer[i]; + + memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); + + if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { + fprintf(stderr, "%s: Can't write %s: %s\n", + argv[0], argv[2], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + return EXIT_SUCCESS; +} diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 1b27e8b..d767eaa 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,6 +27,7 @@ #include <asm/arch/adc.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -57,6 +58,10 @@ int board_init(void) check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); +#if defined(CONFIG_PMIC) + pmic_init(); +#endif + return 0; } diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 926e491..461b56e 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -24,6 +24,7 @@ #include <common.h> #include <ioports.h> #include <mpc8260.h> +#include <linux/compiler.h> #include "scm.h" @@ -397,7 +398,7 @@ static void config_scoh_cs (void) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE; - volatile uint tmp, i; + __maybe_unused volatile uint tmp, i; /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ memctl->memc_or3 = CONFIG_SYS_CAN0_OR3; diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c index db1f21a..af329b9 100644 --- a/board/svm_sc8xx/flash.c +++ b/board/svm_sc8xx/flash.c @@ -27,155 +27,163 @@ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif -#ifdef CONFIG_BOOT_8B -static int my_in_8( unsigned char *addr); -static void my_out_8( unsigned char *addr, int val); +static int write_word(flash_info_t *info, ulong dest, ulong data); + +#ifdef CONFIG_BOOT_8B +static int my_in_8(unsigned char *addr); +static void my_out_8(unsigned char *addr, int val); #endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr); -static void my_out_be16( unsigned short *addr, int val); +#ifdef CONFIG_BOOT_16B +static int my_in_be16(unsigned short *addr); +static void my_out_be16(unsigned short *addr, int val); #endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr); -static void my_out_be32( unsigned *addr, int val); +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32(unsigned *addr); +static void my_out_be32(unsigned *addr, int val); #endif /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; - size_b0=0; - size_b1=0; + size_b0 = 0; + size_b1 = 0; /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } + #ifdef CONFIG_SYS_DOC_BASE #ifndef CONFIG_FEL8xx_AT - memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + /* 32k bytes */ + memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; #else - memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + /* 32k bytes */ + memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; #endif #endif -#if defined( CONFIG_BOOT_8B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x80000; /* 512 K */ +#if defined(CONFIG_BOOT_8B) + size_b0 = 0x80000; /* 512 K */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; flash_info[0].sector_count = 8; flash_info[0].size = 0x00080000; + /* set up sector start address table */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); + flash_info[0].start[i] = 0x40000000 + (i * 0x10000); + /* protect all sectors */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#elif defined (CONFIG_BOOT_16B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ + flash_info[0].protect[i] = 0x1; + +#elif defined(CONFIG_BOOT_16B) + size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; flash_info[0].sector_count = 67; flash_info[0].size = 0x00400000; + /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000 ; + flash_info[0].start[0] = 0x40000000; flash_info[0].start[1] = 0x40000000 + 0x4000; flash_info[0].start[2] = 0x40000000 + 0x6000; flash_info[0].start[3] = 0x40000000 + 0x8000; - for (i = 4; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000); + + for (i = 4; i < flash_info[0].sector_count; i++) { + flash_info[0].start[i] = + 0x40000000 + 0x10000 + ((i - 4) * 0x10000); + } + /* protect all sectors */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; + flash_info[0].protect[i] = 0x1; #endif - #ifdef CONFIG_BOOT_32B /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); } - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); if (size_b1 > size_b0) { - printf ("## ERROR: " + printf("## ERROR: " "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); + size_b1, size_b1 << 20, size_b0, size_b0 << 20); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + + return 0; } /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | + (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, + &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | + (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + + size_b0), &flash_info[1]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0, + &flash_info[1]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #endif @@ -183,11 +191,11 @@ unsigned long flash_init (void) /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #endif } else { - memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_br1 = 0; /* invalidate bank */ flash_info[1].flash_id = FLASH_UNKNOWN; flash_info[1].sector_count = -1; @@ -197,350 +205,209 @@ unsigned long flash_init (void) flash_info[1].size = size_b1; -#endif /* CONFIG_BOOT_32B */ +#endif /* CONFIG_BOOT_32B */ - return (size_b0 + size_b1); + return size_b0 + size_b1; } -#if 0 -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} -#endif -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) + +void flash_print_info(flash_info_t *info) { int i; if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); + printf("missing or unknown FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + default: + printf("Unknown Vendor "); + break; } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } - printf (" Size: %ld MB in %d Sectors\n", + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); } - printf ("\n"); + printf("\n"); return; } -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - /* * The following code cannot be run from FLASH! */ -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect,in_mid,in_did; + vu_long *addr = (vu_long *) (info->start[0]); + int flag, prot, sect, l_sect, in_mid, in_did; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); -#if defined (CONFIG_BOOT_8B ) - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); + +#if defined(CONFIG_BOOT_8B) + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90); + + in_mid = my_in_8((unsigned char *)addr); + in_did = my_in_8((unsigned char *)((ulong)addr + 1)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_8((unsigned char *)addr, 0xf0); udelay(1); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); + + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); + addr = (vu_long *) (info->start[sect]); /*addr[0] = 0x00300030; */ - my_out_8( (unsigned char *) ((ulong)addr),0x30 ); + my_out_8((unsigned char *)((ulong)addr), 0x30); l_sect = sect; } } -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 ); - in_mid=my_in_be16( (unsigned short * ) addr ); - in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be16( (unsigned short *)addr, 0xf0); +#elif defined(CONFIG_BOOT_16B) + my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55); + my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90); + in_mid = my_in_be16((unsigned short *)addr); + in_did = my_in_be16((unsigned short *)((ulong)addr + 2)); + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + my_out_be16((unsigned short *)addr, 0xf0); udelay(1); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be16( (unsigned short *) ((ulong)addr),0x30 ); + addr = (vu_long *) (info->start[sect]); + my_out_be16((unsigned short *)((ulong)addr), 0x30); l_sect = sect; } } #elif defined(CONFIG_BOOT_32B) - my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa ); - my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 ); - in_mid=my_in_be32( (unsigned * ) addr ); - in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be32( (unsigned *)addr, 0xf0); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90); + + in_mid = my_in_be32((unsigned *)addr); + in_did = my_in_be32((unsigned *)((ulong)addr + 4)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_be32((unsigned *) addr, 0xf0); udelay(1); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); + + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be32( (unsigned *) ((ulong)addr),0x00300030 ); + addr = (vu_long *) (info->start[sect]); + my_out_be32((unsigned *)((ulong)addr), 0x00300030); l_sect = sect; } } #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -548,53 +415,55 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if defined (CONFIG_BOOT_8B) - while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 ) -#elif defined(CONFIG_BOOT_16B ) - while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 ) + start = get_timer(0); + last = start; + addr = (vu_long *) (info->start[l_sect]); +#if defined(CONFIG_BOOT_8B) + while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80) +#elif defined(CONFIG_BOOT_16B) + while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080) #elif defined(CONFIG_BOOT_32B) - while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 ) + while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080) #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } DONE: /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if defined (CONFIG_BOOT_8B) - my_out_8( (unsigned char *)addr, 0xf0); -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) addr , 0x00f0 ); + addr = (volatile unsigned long *) info->start[0]; + +#if defined(CONFIG_BOOT_8B) + my_out_8((unsigned char *) addr, 0xf0); +#elif defined(CONFIG_BOOT_16B) + my_out_be16((unsigned short *) addr, 0x00f0); #elif defined(CONFIG_BOOT_32B) - my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */ + my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */ #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif - printf (" done\n"); + printf(" done\n"); return 0; } -/*----------------------------------------------------------------------- +/* * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -604,23 +473,26 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } + for (; cnt == 0 && i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } wp += 4; } @@ -629,113 +501,123 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } + for (; i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); - return (write_word(info, wp, data)); + return write_word(info, wp, data); } -/*----------------------------------------------------------------------- +/* * Write a word to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - ulong addr = (ulong)(info->start[0]); - ulong start,last; + ulong addr = (ulong) (info->start[0]); + ulong start; int flag; ulong i; - int data_short[2]; + int data_short[2]; /* Check if Flash is (sufficiently) erased */ - if ( ((ulong) *(ulong *)dest & data) != data ) { - return (2); - } + if (((ulong)*(ulong *)dest & data) != data) + return 2; + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); #if defined(CONFIG_BOOT_8B) #ifdef DEBUG { - int in_mid,in_did; - my_out_8( (unsigned char * ) (addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) (addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); - udelay(1); + int in_mid, in_did; + + my_out_8((unsigned char *) (addr + 0x555), 0xaa); + my_out_8((unsigned char *) (addr + 0x2aa), 0x55); + my_out_8((unsigned char *) (addr + 0x555), 0x90); + + in_mid = my_in_8((unsigned char *) addr); + in_did = my_in_8((unsigned char *) (addr + 1)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_8((unsigned char *) addr, 0xf0); + udelay(1); } #endif - { - int data_ch[4]; - data_ch[0]=(int ) ((data>>24) & 0xff); - data_ch[1]=(int ) ((data>>16) &0xff ); - data_ch[2]=(int ) ((data >>8) & 0xff); - data_ch[3]=(int ) (data & 0xff); - for (i=0;i<4;i++ ){ - my_out_8( (unsigned char *) (addr+0x555),0xaa); - my_out_8((unsigned char *) (addr+0x2aa),0x55); - my_out_8( (unsigned char *) (addr+0x555),0xa0); - my_out_8((unsigned char *) (dest+i) ,data_ch[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - last = start; - while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { - return 1; - } - } - }/* for */ - } -#elif defined( CONFIG_BOOT_16B) - data_short[0]=(int) (data>>16) & 0xffff; - data_short[1]=(int ) data & 0xffff ; - for (i=0;i<2;i++ ){ - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 ); - my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - start = get_timer (0); - last = start; - while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { - return 1; - } - } + { + int data_ch[4]; + + data_ch[0] = (int) ((data >> 24) & 0xff); + data_ch[1] = (int) ((data >> 16) & 0xff); + data_ch[2] = (int) ((data >> 8) & 0xff); + data_ch[3] = (int) (data & 0xff); + + for (i = 0; i < 4; i++) { + my_out_8((unsigned char *) (addr + 0x555), 0xaa); + my_out_8((unsigned char *) (addr + 0x2aa), 0x55); + my_out_8((unsigned char *) (addr + 0x555), 0xa0); + my_out_8((unsigned char *) (dest + i), data_ch[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + while ((my_in_8((unsigned char *)(dest + i))) != + (data_ch[i])) { + if (get_timer(start) > + CONFIG_SYS_FLASH_WRITE_TOUT) { + return 1; + } + } + } /* for */ + } +#elif defined(CONFIG_BOOT_16B) + data_short[0] = (int) (data >> 16) & 0xffff; + data_short[1] = (int) data & 0xffff; + for (i = 0; i < 2; i++) { + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0); + my_out_be16((unsigned short *)(dest + (i * 2)), + data_short[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + while ((my_in_be16((unsigned short *)(dest + (i * 2)))) != + (data_short[i])) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; + } } -#elif defined( CONFIG_BOOT_32B) +#elif defined(CONFIG_BOOT_32B) addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00A000A0; @@ -747,51 +629,54 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } #endif - - - return (0); + return 0; } -#ifdef CONFIG_BOOT_8B -static int my_in_8 ( unsigned char *addr) + +#ifdef CONFIG_BOOT_8B +static int my_in_8(unsigned char *addr) { - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + int ret; + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_8 ( unsigned char *addr, int val) +static void my_out_8(unsigned char *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr) +#ifdef CONFIG_BOOT_16B +static int my_in_be16(unsigned short *addr) { - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + int ret; + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_be16( unsigned short *addr, int val) + +static void my_out_be16(unsigned short *addr, int val) { - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr) +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32(unsigned *addr) { unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_be32( unsigned *addr, int val) + +static void my_out_be32(unsigned *addr, int val) { - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index f34b835..771bb4a 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -80,15 +80,12 @@ int checkboard(void) char buf[64]; int i; int l = getenv_f("serial#", buf, sizeof(buf)); - int board_type; if (l < 0 || strncmp(buf, "SVM8", 4)) { printf("### No HW ID - assuming SVM SC8xx\n"); return (0); } - board_type = 1; - for (i = 0; i < l; ++i) { if (buf[i] == ' ') break; @@ -97,7 +94,7 @@ int checkboard(void) putc('\n'); - return (0); + return 0; } /* ------------------------------------------------------------------------- */ diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c index 63a0d33..72288fe 100644 --- a/board/syteco/jadecpu/jadecpu.c +++ b/board/syteco/jadecpu/jadecpu.c @@ -40,7 +40,6 @@ int board_init(void) writel(0x00000010, &ccnt->cmux_md); gd->flags = 0; - gd->bd->bi_arch_number = MACH_TYPE_JADECPU; gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; icache_enable(); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index b17c0fb..8c43463 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -217,7 +217,22 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_SMC911X +#define STR_ENV_ETHADDR "ethaddr" + + struct eth_device *dev; + uchar eth_addr[6]; + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("omap3evm: Couldn't get eth device\n"); + rc = -1; + } + } #endif return rc; } diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index 4c8922f..5329c2a 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -279,7 +279,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) @@ -305,8 +305,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -322,7 +320,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -609,7 +606,7 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) @@ -635,8 +632,6 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -652,7 +647,6 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 0789c58..c40f7f0 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -82,18 +82,17 @@ static void spi_init(void) static int spi_transmit(unsigned char data) { - int dummy; struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; spi->dr = data; /* wait for SPI transmission completed */ - while(!(spi->sr & 0x80)) - { - if (spi->sr & 0x40) /* if write collision occured */ - { + while (!(spi->sr & 0x80)) { + if (spi->sr & 0x40) { /* if write collision occured */ + int dummy; + /* do dummy read to clear status register */ dummy = spi->dr; - printf ("SPI write collision\n"); + printf("SPI write collision: dr=0x%x\n", dummy); return -1; } } @@ -172,10 +171,8 @@ static void i2s_init(void) psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ psc->ctur = 0x0F; /* 16 bit frame width */ - for(i=0;i<128;i++) - { + for (i = 0; i < 128; i++) psc->psc_buffer_32 = 0; /* clear tx fifo */ - } } static int i2s_play_wave(unsigned long addr, unsigned long len) @@ -183,7 +180,6 @@ static int i2s_play_wave(unsigned long addr, unsigned long len) unsigned long i; unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip * wav header*/ - unsigned char swapped[4]; struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; /* @@ -192,11 +188,16 @@ static int i2s_play_wave(unsigned long addr, unsigned long len) psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); for(i = 0;i < (len / 4); i++) { + unsigned char swapped[4]; + unsigned long *p = (unsigned long*)swapped; + swapped[3] = *wave_file++; swapped[2] = *wave_file++; swapped[1] = *wave_file++; swapped[0] = *wave_file++; - psc->psc_buffer_32 = *((unsigned long*)swapped); + + psc->psc_buffer_32 = *p; + while (psc->tfnum > 400) { if(ctrlc()) return 0; diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 9efb541..5aca227 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -459,10 +459,9 @@ phys_size_t initdram (int board_type) #ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index d3815b2..f556d30 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -31,7 +31,6 @@ #include <asm/arch/iomux.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> -#include <asm/errno.h> #include <i2c.h> #include <mmc.h> #include <pmic.h> @@ -44,8 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; -static u32 system_rev; - static struct fb_videomode nec_nl6448bc26_09c = { "NEC_NL6448BC26-09C", 60, /* Refresh */ @@ -151,13 +148,6 @@ static void init_drive_strength(void) PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); } -u32 get_board_rev(void) -{ - system_rev = get_cpu_rev(); - - return system_rev; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, |