diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6q_sabresd/flash_header.S | 178 |
1 files changed, 71 insertions, 107 deletions
diff --git a/board/freescale/mx6q_sabresd/flash_header.S b/board/freescale/mx6q_sabresd/flash_header.S index 30aec4d..063a5e1 100644 --- a/board/freescale/mx6q_sabresd/flash_header.S +++ b/board/freescale/mx6q_sabresd/flash_header.S @@ -63,127 +63,91 @@ plugin: .word 0x0 #if defined CONFIG_MX6DL_DDR3 #if defined CONFIG_DDR_32BIT -dcd_hdr: .word 0x406802D2 /* Tag=0xD2, Len=76*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x046402CC /* Tag=0xCC, Len=76*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x40E001D2 /* Tag=0xD2, Len=59*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04DC01CC /* Tag=0xCC, Len=59*8 + 4, Param=0x04 */ -# IOMUXC_BASE_ADDR = 0x20e0000 -# DDR IO TYPE -MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000) +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000C0000) MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000) -# Clock + MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030) MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030) -# Address + MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030) MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030) MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030) -# Control + MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030) -MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000) -MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000) -MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000) -MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030) -MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030) -MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030) -# Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS, -# CMOS mode saves power, but have less timing margin in case of DDR -# timing issue on your board you can try DDR_MODE: [= 0x00020000] -MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00000000) - -MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030) -MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030) -MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030) -MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030) -MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000000) -MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000000) -MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000000) -MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000000) -# DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS, -# CMOS mode saves power, but have less timing margin in case of DDR -# timing issue on your board you can try DDR_MODE: [= 0x00020000] - -MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00000000) - -MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030) -MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030) -MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030) -MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030) -MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000000) -MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000000) -MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000000) -MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000000) - -MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030) -MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030) -MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030) -MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030) -MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000000) -MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000000) -MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000000) -MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x00000000) -# MMDC_P0_BASE_ADDR = 0x021b0000 -# MMDC_P1_BASE_ADDR = 0x021b4000 -# Calibrations -# ZQ -MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003) -MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003) -# write leveling -MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x00450049) -MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x00390043) -# DQS gating, read delay, write delay calibration values -# based on calibration compare of 0x00ffff00 -MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42240229) -MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0219) -MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4e4f5150) -MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x35363136) -# read data bit delay -MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) -MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) -MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) -MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) -# Complete calibration by forced measurment -MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) -MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) -# MMDC init: -# in DDR3, 32-bit mode, only MMDC0 is initiated: -MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d) -MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x00333030) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000) -MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323) -MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030) -MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db) -MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x018, 0x00001740) -MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) -MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2) -MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21) -/* CS0_END - 0x2fffffff, 512M */ -MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x040, 0x00000017) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000) + +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030) -/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */ -MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x400, 0x11420000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x760, 0x00020000) -/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */ -MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x000, 0x83190000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x764, 0x00000030) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x770, 0x00000030) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x778, 0x00000030) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x77c, 0x00000030) -# Initialize 2GB DDR3 - Micron MT41J128M -# MR2 -MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032) -# MR3 -MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) -# MR1 -MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031) -# MR0 -MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030) -# ZQ calibration -MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) -# final DDR setup -MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) -MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) -MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) -MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x470, 0x00000030) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x474, 0x00000030) +MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x478, 0x00000030) +MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x47c, 0x00000030) + +MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003) + +MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F) +MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F) + +MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x83c, 0x42190219) +MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x840, 0x017B0177) +MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x848, 0x4B4D4E4D) +MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x850, 0x3F3E2D36) + +MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) +MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) +MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) +MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) + +MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) + +MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x004, 0x0002002D) +MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x008, 0x00333030) +MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x00c, 0x3F435313) +MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8B63) +MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB) +MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x018, 0x00001740) + +MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) +MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2) + +MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x030, 0x00431023) +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x040, 0x00000017) + +MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x000, 0x83190000) + +MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032) +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031) +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030) +MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) + +MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) + +MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) +MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) + +MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) #else /* i.MX6DL 64BIT-DDR */ dcd_hdr: .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */ |