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-rw-r--r--board/freescale/mx35_3stack/lowlevel_init.S36
-rw-r--r--board/freescale/mx35_3stack/mx35_3stack.c108
2 files changed, 121 insertions, 23 deletions
diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S
index 40792f1..0b47ef1 100644
--- a/board/freescale/mx35_3stack/lowlevel_init.S
+++ b/board/freescale/mx35_3stack/lowlevel_init.S
@@ -24,6 +24,22 @@
#include "board-mx35_3stack.h"
/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+ ldr \tmp, =IIM_BASE_ADDR
+ ldr \ret, [\tmp, #IIM_SREV]
+ cmp \ret, #0x00
+ moveq \tmp, #ROMPATCH_BASE_ADDR
+ ldreq \ret, [\tmp, #ROMPATCH_REV]
+ moveq \ret, \ret, lsl #4
+ addne \ret, \ret, #0x10
+.endm
+
+/*
* L2CC Cache setup/invalidation/disable
*/
.macro init_l2cc
@@ -46,11 +62,6 @@
orr r1, r1, r2
str r1, [r0, #L2_CACHE_AUX_CTL_REG]
-/* Workaournd for DDR issue:WT*/
- ldr r1, [r0, #L2_CACHE_DBG_CTL_REG]
- orr r1, r1, #2
- str r1, [r0, #L2_CACHE_DBG_CTL_REG]
-
/* Invalidate L2 */
mov r1, #0x000000FF
str r1, [r0, #L2_CACHE_INV_WAY_REG]
@@ -184,11 +195,15 @@
ldr r2, =CCM_CCMR_CONFIG
str r2, [r0, #CLKCTL_CCMR]
+ check_soc_version r1, r2
+ cmp r1, #0x20
+ ldrhs r3, =CCM_MPLL_399_HZ
+ bhs 1f
ldr r2, [r0, #CLKCTL_PDR0]
tst r2, #CLKMODE_CONSUMER
ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-
+1:
str r3, [r0, #CLKCTL_MPCTL]
ldr r1, =CCM_PPLL_300_HZ
@@ -231,12 +246,15 @@
mov lr, fp
+ check_soc_version r3, r4
+ cmp r1, #0x20
+ bhs 1f
cmp r5, #0
movne r3, #L2CC_BASE_ADDR
ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
orrne r4, r4, #0x1000
strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
-
+1:
ldr r3, =ESDCTL_DELAY_LINE5
str r3, [r0, #0x30]
.endm /* setup_sdram */
@@ -280,8 +298,6 @@ lowlevel_init:
#endif
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
- init_l2cc
-
/* initializes very early AIPS, what for?
* Then it also initializes Multi-Layer AHB Crossbar Switch,
* M3IF */
@@ -289,6 +305,8 @@ lowlevel_init:
ldr r0, =0x40000015 /* start from AIPS 2GB region */
mcr p15, 0, r0, c15, c2, 4
+ init_l2cc
+
init_aips
init_max
diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
index f6d5641..7854f86 100644
--- a/board/freescale/mx35_3stack/mx35_3stack.c
+++ b/board/freescale/mx35_3stack/mx35_3stack.c
@@ -31,6 +31,35 @@
DECLARE_GLOBAL_DATA_PTR;
+static u32 system_rev;
+
+u32 get_board_rev(void)
+{
+ return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+ int reg;
+ reg = __REG(IIM_BASE_ADDR + IIM_SREV);
+ if (!reg) {
+ reg = __REG(ROMPATCH_BASE_ADDR + ROMPATCH_REV);
+ reg <<= 4;
+ } else
+ reg += 0x10;
+ system_rev = 0x35000 + (reg & 0xFF);
+}
+
+static inline void set_board_rev(int rev)
+{
+ system_rev |= (rev & 0xF) << 8;
+}
+
+static inline int is_soc_rev(int rev)
+{
+ return (system_rev & 0xFF) - rev;
+}
+
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
@@ -43,6 +72,8 @@ int board_init(void)
{
int pad;
+ setup_soc_rev();
+
/* enable clocks */
__REG(CCM_BASE_ADDR + CLKCTL_CGR0) |= 0x003F0000;
__REG(CCM_BASE_ADDR + CLKCTL_CGR1) |= 0x00030FFF;
@@ -124,40 +155,89 @@ int board_init(void)
}
#ifdef BOARD_LATE_INIT
+static inline int board_detect(void)
+{
+ u8 buf[4];
+ int id;
+
+ if (i2c_read(0x08, 0x7, 1, buf, 3) < 0) {
+ printf("board_late_init: read PMIC@0x08:0x7 fail\n");
+ return 0;
+ }
+ id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
+ printf("PMIC@0x08:0x7 is %x\n", id);
+ id = (id >> 6) & 0x7;
+ if (id == 0x7) {
+ set_board_rev(1);
+ return 1;
+ }
+ return 0;
+}
+
int board_late_init(void)
{
- u8 reg;
+ u8 reg[3];
int i;
- if (i2c_read(0x69, 0x20, 1, &reg, 1) < 0) {
- printf("board_late_init: read PMIC@0x20 fail\n");
+
+ if (board_detect()) {
+ mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
+ MUX_CONFIG_ALT1);
+ printf("i.MX35 CPU board version 2.0\n");
+ if (i2c_read(0x08, 0x1E, 1, reg, 3)) {
+ printf("board_late_init: read PMIC@0x08:0x1E fail\n");
+ return 0;
+ }
+ reg[2] |= 0x3;
+ if (i2c_write(0x08, 0x1E, 1, reg, 3)) {
+ printf("board_late_init: write PMIC@0x08:0x1E fail\n");
+ return 0;
+ }
+ if (i2c_read(0x08, 0x20, 1, reg, 3)) {
+ printf("board_late_init: read PMIC@0x08:0x20 fail\n");
+ return 0;
+ }
+ reg[2] |= 0x1;
+ if (i2c_write(0x08, 0x20, 1, reg, 3)) {
+ printf("board_late_init: write PMIC@0x08:0x20 fail\n");
+ return 0;
+ }
+ mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+ __REG(GPIO1_BASE_ADDR + 0x04) |= 1 << 5;
+ __REG(GPIO1_BASE_ADDR) |= 1 << 5;
+ } else
+ printf("i.MX35 CPU board version 1.0\n");
+
+ if (i2c_read(0x69, 0x20, 1, reg, 1) < 0) {
+ printf("board_late_init: read PMIC@0x69:0x20 fail\n");
return 0;
}
- reg |= 0x4;
- if (i2c_write(0x69, 0x20, 1, &reg, 1) < 0) {
- printf("board_late_init: write back PMIC@0x20 fail\n");
+ reg[0] |= 0x4;
+ if (i2c_write(0x69, 0x20, 1, reg, 1) < 0) {
+ printf("board_late_init: write back PMIC@0x69:0x20 fail\n");
return 0;
}
for (i = 0; i < 1000; i++)
udelay(200);
- if (i2c_read(0x69, 0x1A, 1, &reg, 1) < 0) {
- printf("board_late_init: read PMIC@0x1A fail\n");
+ if (i2c_read(0x69, 0x1A, 1, reg, 1) < 0) {
+ printf("board_late_init: read PMIC@0x69:0x1A fail\n");
return 0;
}
- reg &= 0x7F;
- if (i2c_write(0x69, 0x1A, 1, &reg, 1) < 0) {
- printf("board_late_init: write back PMIC@0x1A fail\n");
+ reg[0] &= 0x7F;
+ if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
+ printf("board_late_init: write back PMIC@0x69:0x1A fail\n");
return 0;
}
for (i = 0; i < 1000; i++)
udelay(200);
- reg |= 0x80;
- if (i2c_write(0x69, 0x1A, 1, &reg, 1) < 0) {
- printf("board_late_init: 2st write back PMIC@0x1A fail\n");
+ reg[0] |= 0x80;
+ if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
+ printf("board_late_init: 2st write back PMIC@0x69:0x1A fail\n");
return 0;
}
generated by cgit v1.1 at 2024-11-22 19:14:40 +0000