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-rw-r--r--board/freescale/mpc8360erdk/nand.c4
-rw-r--r--board/tqc/tqm85xx/nand.c5
2 files changed, 6 insertions, 3 deletions
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
index 8e22e13..9ffffb4 100644
--- a/board/freescale/mpc8360erdk/nand.c
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -57,7 +57,7 @@ static void upm_setup(struct fsl_upm *upm)
eieio();
}
-static int dev_ready(void)
+static int dev_ready(int chip_nr)
{
if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
debug("nand ready\n");
@@ -76,7 +76,7 @@ static struct fsl_upm_nand fun = {
.upm_cmd_offset = 8,
.upm_addr_offset = 16,
.dev_ready = dev_ready,
- .wait_pattern = 1,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
.chip_delay = 50,
};
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 8133fdc..3da689a 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -385,7 +385,7 @@ static void upmb_write (u_char addr, ulong val)
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
/* dummy access to perform write */
- out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
+ out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
}
@@ -446,7 +446,10 @@ static struct fsl_upm_nand fun = {
.width = 8,
.upm_cmd_offset = 0x08,
.upm_addr_offset = 0x10,
+ .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
+ .chip_offset = CONFIG_SYS_NAND_CS_DIST,
.chip_delay = NAND_BIG_DELAY_US,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
};
void board_nand_select_device (struct nand_chip *nand, int chip)