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-rw-r--r--board/BuS/EB+MCF-EV123/EB+MCF-EV123.c4
-rw-r--r--board/MAI/AmigaOneG3SE/cmd_boota.c2
-rw-r--r--board/MAI/menu/cmd_menu.c2
-rw-r--r--board/ads5121/ads5121_diu.c4
-rw-r--r--board/amcc/acadia/cmd_acadia.c4
-rw-r--r--board/amcc/canyonlands/bootstrap.c4
-rw-r--r--board/amcc/katmai/cmd_katmai.c4
-rw-r--r--board/amcc/kilauea/cmd_pll.c8
-rw-r--r--board/amcc/luan/luan.c4
-rw-r--r--board/amcc/makalu/cmd_pll.c8
-rw-r--r--board/amcc/sequoia/cmd_sequoia.c4
-rw-r--r--board/amcc/taihu/lcd.c14
-rw-r--r--board/amcc/taihu/taihu.c10
-rw-r--r--board/amcc/taihu/update.c2
-rw-r--r--board/amcc/taishan/lcd.c20
-rw-r--r--board/amcc/taishan/showinfo.c6
-rw-r--r--board/amcc/taishan/update.c2
-rw-r--r--board/amcc/yucca/cmd_yucca.c4
-rw-r--r--board/amirix/ap1000/ap1000.c10
-rw-r--r--board/amirix/ap1000/powerspan.c2
-rw-r--r--board/barco/barco.c8
-rw-r--r--board/bc3450/cmd_bc3450.c10
-rw-r--r--board/bf533-ezkit/Makefile8
-rw-r--r--board/bf533-ezkit/bf533-ezkit.c23
-rw-r--r--board/bf533-ezkit/flash-defines.h4
-rw-r--r--board/bf533-ezkit/flash.c10
-rw-r--r--board/bf533-stamp/Makefile12
-rw-r--r--board/bf533-stamp/bf533-stamp.c50
-rw-r--r--board/bf533-stamp/bf533-stamp.h3
-rw-r--r--board/bf533-stamp/video.c167
-rw-r--r--board/bf533-stamp/video.h25
-rw-r--r--board/bf537-stamp/Makefile10
-rw-r--r--board/bf537-stamp/bf537-stamp.c14
-rw-r--r--board/bf537-stamp/cmd_bf537led.c2
-rw-r--r--board/bf537-stamp/nand.c9
-rw-r--r--board/bf537-stamp/post-memory.c23
-rw-r--r--board/bf537-stamp/spi_flash.c8
-rw-r--r--board/bf561-ezkit/Makefile8
-rw-r--r--board/bf561-ezkit/bf561-ezkit.c14
-rw-r--r--board/cm5200/cmd_cm5200.c2
-rw-r--r--board/davinci/dvevm/dvevm.c24
-rw-r--r--board/delta/delta.c2
-rw-r--r--board/delta/lowlevel_init.S2
-rw-r--r--board/esd/ar405/ar405.c6
-rw-r--r--board/esd/cms700/cms700.c2
-rw-r--r--board/esd/common/auto_update.c2
-rw-r--r--board/esd/common/cmd_loadpci.c2
-rw-r--r--board/esd/common/lcd.c4
-rw-r--r--board/esd/common/xilinx_jtag/micro.c2
-rw-r--r--board/esd/cpci2dp/cpci2dp.c2
-rw-r--r--board/esd/cpci405/cpci405.c6
-rw-r--r--board/esd/cpci5200/cpci5200.c2
-rw-r--r--board/esd/cpci750/cpci750.c2
-rw-r--r--board/esd/dasa_sim/cmd_dasa_sim.c4
-rw-r--r--board/esd/du440/du440.c16
-rw-r--r--board/esd/hh405/hh405.c2
-rw-r--r--board/esd/ocrtc/cmd_ocrtc.c4
-rw-r--r--board/esd/pci405/cmd_pci405.c2
-rw-r--r--board/esd/pci405/pci405.c2
-rw-r--r--board/esd/pf5200/pf5200.c6
-rw-r--r--board/esd/plu405/plu405.c2
-rw-r--r--board/esd/pmc405/pmc405.c2
-rw-r--r--board/esd/pmc440/cmd_pmc440.c18
-rw-r--r--board/esd/tasreg/tasreg.c12
-rw-r--r--board/esd/voh405/voh405.c2
-rw-r--r--board/evb64260/zuma_pbb.c6
-rw-r--r--board/freescale/common/pixis.c4
-rw-r--r--board/freescale/common/sys_eeprom.c4
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c7
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c4
-rw-r--r--board/g2000/g2000.c6
-rw-r--r--board/gdsys/gdppc440etx/Makefile51
-rw-r--r--board/gdsys/gdppc440etx/config.mk44
-rw-r--r--board/gdsys/gdppc440etx/gdppc440etx.c323
-rw-r--r--board/gdsys/gdppc440etx/init.S75
-rw-r--r--board/gdsys/gdppc440etx/u-boot.lds144
-rw-r--r--board/hymod/bsp.c8
-rw-r--r--board/keymile/common/keymile_hdlc_enet.c4
-rw-r--r--board/korat/korat.c23
-rw-r--r--board/lwmon/lwmon.c10
-rw-r--r--board/lwmon5/kbd.c2
-rw-r--r--board/lwmon5/lwmon5.c6
-rw-r--r--board/micronas/vct/Makefile57
-rw-r--r--board/micronas/vct/bcu.h170
-rw-r--r--board/micronas/vct/config.mk31
-rw-r--r--board/micronas/vct/dcgu.c258
-rw-r--r--board/micronas/vct/dcgu.h179
-rw-r--r--board/micronas/vct/ebi.c48
-rw-r--r--board/micronas/vct/ebi.h95
-rw-r--r--board/micronas/vct/ebi_nor_flash.c131
-rw-r--r--board/micronas/vct/ebi_onenand.c198
-rw-r--r--board/micronas/vct/ebi_smc911x.c94
-rw-r--r--board/micronas/vct/ehci.c110
-rw-r--r--board/micronas/vct/gpio.c88
-rw-r--r--board/micronas/vct/scc.c669
-rw-r--r--board/micronas/vct/scc.h205
-rw-r--r--board/micronas/vct/smc_eeprom.c394
-rw-r--r--board/micronas/vct/top.c289
-rw-r--r--board/micronas/vct/u-boot.lds71
-rw-r--r--board/micronas/vct/vct.c117
-rw-r--r--board/micronas/vct/vct.h104
-rw-r--r--board/micronas/vct/vcth/reg_dcgu.h36
-rw-r--r--board/micronas/vct/vcth/reg_ebi.h242
-rw-r--r--board/micronas/vct/vcth/reg_fwsram.h73
-rw-r--r--board/micronas/vct/vcth/reg_gpio.h32
-rw-r--r--board/micronas/vct/vcth/reg_scc.h102
-rw-r--r--board/micronas/vct/vcth/reg_usbh.h33
-rw-r--r--board/micronas/vct/vcth/reg_wdt.h24
-rw-r--r--board/micronas/vct/vcth2/reg_ebi.h290
-rw-r--r--board/micronas/vct/vctv/reg_dcgu.h25
-rw-r--r--board/micronas/vct/vctv/reg_ebi.h290
-rw-r--r--board/micronas/vct/vctv/reg_gpio.h32
-rw-r--r--board/micronas/vct/vctv/reg_wdt.h24
-rw-r--r--board/mpc8540eval/mpc8540eval.c2
-rw-r--r--board/mpl/common/common_util.c2
-rw-r--r--board/mpl/mip405/cmd_mip405.c2
-rw-r--r--board/mpl/pati/cmd_pati.c2
-rw-r--r--board/mpl/pip405/cmd_pip405.c2
-rw-r--r--board/mpl/vcma9/cmd_vcma9.c2
-rw-r--r--board/pcippc2/pcippc2.c4
-rw-r--r--board/pcs440ep/pcs440ep.c6
-rw-r--r--board/pn62/cmd_pn62.c8
-rw-r--r--board/prodrive/pdnb3/pdnb3.c4
-rw-r--r--board/pxa255_idp/pxa_idp.c2
-rw-r--r--board/r360mpi/r360mpi.c2
-rw-r--r--board/renesas/sh7785lcr/rtl8169_mac.c8
-rw-r--r--board/renesas/sh7785lcr/selfcheck.c6
-rw-r--r--board/sandburst/common/ppc440gx_i2c.c2
-rw-r--r--board/sandburst/karef/karef.c4
-rw-r--r--board/sandburst/metrobox/metrobox.c4
-rw-r--r--board/sbc8560/sbc8560.c2
-rw-r--r--board/siemens/common/fpga.c4
-rw-r--r--board/siemens/pcu_e/pcu_e.c4
-rw-r--r--board/ssv/common/cmd_sled.c4
-rw-r--r--board/ssv/common/wd_pio.c4
-rw-r--r--board/tqc/tqm5200/cmd_stk52xx.c22
-rw-r--r--board/tqc/tqm5200/cmd_tb5200.c4
-rw-r--r--board/tqc/tqm8272/tqm8272.c2
-rw-r--r--board/trab/cmd_trab.c24
-rw-r--r--board/trab/trab.c2
-rw-r--r--board/trizepsiv/eeprom.c10
-rw-r--r--board/w7o/cmd_vpd.c4
-rw-r--r--board/zeus/update.c2
-rw-r--r--board/zeus/zeus.c4
-rw-r--r--board/zylonite/lowlevel_init.S2
145 files changed, 5687 insertions, 359 deletions
diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
index d509a8f..02a095e 100644
--- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
+++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
@@ -144,7 +144,7 @@ int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
rcode = 0;
break;
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
rcode = 1;
break;
}
@@ -155,7 +155,7 @@ int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
vcimage, 2, 0, do_vcimage,
- "vcimage - loads an image to Display\n",
+ "loads an image to Display",
"vcimage addr\n"
);
diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c
index 949af18..6b955d8 100644
--- a/board/MAI/AmigaOneG3SE/cmd_boota.c
+++ b/board/MAI/AmigaOneG3SE/cmd_boota.c
@@ -122,7 +122,7 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if defined(CONFIG_AMIGAONEG3SE) && defined(CONFIG_CMD_BSP)
U_BOOT_CMD(
boota, 3, 1, do_boota,
- "boota - boot an Amiga kernel\n",
+ "boot an Amiga kernel",
"address disk"
);
#endif /* _CMD_BOOTA_H */
diff --git a/board/MAI/menu/cmd_menu.c b/board/MAI/menu/cmd_menu.c
index 079f1ff..2b97d23 100644
--- a/board/MAI/menu/cmd_menu.c
+++ b/board/MAI/menu/cmd_menu.c
@@ -10,7 +10,7 @@ int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
#if defined(CONFIG_AMIGAONEG3SE) && defined(CONFIG_CMD_BSP)
U_BOOT_CMD(
menu, 1, 1, do_menu,
- "menu - display BIOS setup menu\n",
+ "display BIOS setup menu",
""
);
#endif
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
index 11450aa..4f7dda0 100644
--- a/board/ads5121/ads5121_diu.c
+++ b/board/ads5121/ads5121_diu.c
@@ -79,7 +79,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
unsigned int addr;
if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -101,7 +101,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
U_BOOT_CMD(
diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp,
- "diufb init | addr - Init or Display BMP file\n",
+ "Init or Display BMP file",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
);
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
index 052cf61..d47cf1a 100644
--- a/board/amcc/acadia/cmd_acadia.c
+++ b/board/amcc/acadia/cmd_acadia.c
@@ -45,7 +45,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int cpu_freq;
if (argc < 3) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -96,6 +96,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bootstrap, 3, 0, do_bootstrap,
- "bootstrap - program the I2C bootstrap EEPROM\n",
+ "program the I2C bootstrap EEPROM",
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
);
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index b1f4a21..30046fe 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -99,7 +99,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
extern char console_buffer[];
if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -190,6 +190,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
- "bootstrap - program the I2C bootstrap EEPROM\n",
+ "program the I2C bootstrap EEPROM",
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);
diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
index ba71bd5..2c2849b 100644
--- a/board/amcc/katmai/cmd_katmai.c
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -43,7 +43,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char pcixClock[4];
if (argc < 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -213,6 +213,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bootstrap, 3, 1, do_bootstrap,
- "bootstrap - program the serial device strap\n",
+ "program the serial device strap",
"wrclk [prom0|prom1] - program the serial device strap\n"
);
diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c
index 0f571fe..6b38493 100644
--- a/board/amcc/kilauea/cmd_pll.c
+++ b/board/amcc/kilauea/cmd_pll.c
@@ -183,7 +183,7 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char c = '\0';
pll_freq_t pll_freq;
if (argc < 2) {
- printf("Usage: \n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
goto ret;
}
@@ -222,8 +222,8 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
goto ret;
default:
- printf("Invalid options"
- "\n\nUsage: \n%s\n", cmdtp->usage);
+ printf("Invalid options\n\n");
+ cmd_usage(cmdtp);
goto ret;
}
@@ -237,7 +237,7 @@ ret:
U_BOOT_CMD(
pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
- "pllalter- change pll frequence \n",
+ "change pll frequence",
"pllalter <selection> - change pll frequence \n\n\
** New freq take effect after reset. ** \n\
----------------------------------------------\n\
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index de3e3d8..d2a3b9e 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -319,7 +319,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
l2cache_status() ? "ON" : "OFF");
return 0;
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -329,7 +329,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
U_BOOT_CMD(
l2cache, 2, 1, do_l2cache,
- "l2cache - enable or disable L2 cache\n",
+ "enable or disable L2 cache",
"[on, off]\n"
" - enable or disable L2 cache\n"
);
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
index 0f571fe..6b38493 100644
--- a/board/amcc/makalu/cmd_pll.c
+++ b/board/amcc/makalu/cmd_pll.c
@@ -183,7 +183,7 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char c = '\0';
pll_freq_t pll_freq;
if (argc < 2) {
- printf("Usage: \n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
goto ret;
}
@@ -222,8 +222,8 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
goto ret;
default:
- printf("Invalid options"
- "\n\nUsage: \n%s\n", cmdtp->usage);
+ printf("Invalid options\n\n");
+ cmd_usage(cmdtp);
goto ret;
}
@@ -237,7 +237,7 @@ ret:
U_BOOT_CMD(
pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
- "pllalter- change pll frequence \n",
+ "change pll frequence",
"pllalter <selection> - change pll frequence \n\n\
** New freq take effect after reset. ** \n\
----------------------------------------------\n\
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index 3402f84..6dfd8ba 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -128,7 +128,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
extern char console_buffer[];
if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -226,6 +226,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
- "bootstrap - program the I2C bootstrap EEPROM\n",
+ "program the I2C bootstrap EEPROM",
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);
diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c
index 3d042df..6b68f33 100644
--- a/board/amcc/taihu/lcd.c
+++ b/board/amcc/taihu/lcd.c
@@ -140,7 +140,7 @@ static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
lcd_puts(argv[1]);
@@ -151,7 +151,7 @@ static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
lcd_putc((char)argv[1][0]);
@@ -166,7 +166,7 @@ static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
char cur_addr;
if (argc < 3) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -232,25 +232,25 @@ static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
lcd_cls, 1, 1, do_lcd_clear,
- "lcd_cls - lcd clear display\n",
+ "lcd clear display",
NULL
);
U_BOOT_CMD(
lcd_puts, 2, 1, do_lcd_puts,
- "lcd_puts - display string on lcd\n",
+ "display string on lcd",
"<string> - <string> to be displayed\n"
);
U_BOOT_CMD(
lcd_putc, 2, 1, do_lcd_putc,
- "lcd_putc - display char on lcd\n",
+ "display char on lcd",
"<char> - <char> to be displayed\n"
);
U_BOOT_CMD(
lcd_cur, 3, 1, do_lcd_cur,
- "lcd_cur - shift cursor on lcd\n",
+ "shift cursor on lcd",
"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
" <count> - 0..31\n"
" <dir> - 0=backward 1=forward\n"
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 6e9330f..5224378 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -93,7 +93,7 @@ static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
U_BOOT_CMD (
sw2_stat, 1, 1, do_sw_stat,
- "sw2_stat - show status of switch 2\n",
+ "show status of switch 2",
NULL
);
@@ -102,13 +102,13 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
int led_no;
if (argc != 3) {
- printf("%s", cmd_tp->usage);
+ cmd_usage(cmd_tp);
return -1;
}
led_no = simple_strtoul(argv[1], NULL, 16);
if (led_no != 1 && led_no != 2) {
- printf("%s", cmd_tp->usage);
+ cmd_usage(cmd_tp);
return -1;
}
@@ -123,7 +123,7 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
else
gpio_write_bit(31, 0);
} else {
- printf("%s", cmd_tp->usage);
+ cmd_usage(cmd_tp);
return -1;
}
@@ -132,7 +132,7 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
U_BOOT_CMD (
led_ctl, 3, 1, do_led_ctl,
- "led_ctl - make led 1 or 2 on or off\n",
+ "make led 1 or 2 on or off",
"<led_no> <on/off> - make led <led_no> on/off,\n"
"\tled_no is 1 or 2\t"
);
diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c
index 52bad56..8e96905 100644
--- a/board/amcc/taihu/update.c
+++ b/board/amcc/taihu/update.c
@@ -127,6 +127,6 @@ static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[]
U_BOOT_CMD (
update_boot_eeprom, 1, 1, update_boot_eeprom,
- "update_boot_eeprom - update boot eeprom content\n",
+ "update boot eeprom content",
NULL
);
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
index 624ae40..e4d0705 100644
--- a/board/amcc/taishan/lcd.c
+++ b/board/amcc/taishan/lcd.c
@@ -167,7 +167,7 @@ static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
lcd_puts(argv[1]);
@@ -176,7 +176,7 @@ static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
lcd_putc((char)argv[1][0]);
@@ -189,7 +189,7 @@ static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
char cur_addr;
if (argc < 3) {
- printf("%s", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -254,16 +254,16 @@ static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return 0;
}
-U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL);
-U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL);
+U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", NULL);
+U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", NULL);
U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
- "lcd_puts - display string on lcd\n",
+ "display string on lcd",
"<string> - <string> to be displayed\n");
U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
- "lcd_putc - display char on lcd\n",
+ "display char on lcd",
"<char> - <char> to be displayed\n");
U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
- "lcd_cur - shift cursor on lcd\n",
+ "shift cursor on lcd",
"<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
" <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n");
@@ -373,8 +373,8 @@ static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
- "ledon - led test light on\n", NULL);
+ "led test light on", NULL);
U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
- "ledoff - led test light off\n", NULL);
+ "led test light off", NULL);
#endif
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index 5b8b88e..b471c95 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -168,7 +168,7 @@ int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
- "xbriinfo - Show PCIX bridge info\n", NULL);
+ "Show PCIX bridge info", NULL);
#define TAISHAN_PCI_DEV_ID0 0x800
#define TAISHAN_PCI_DEV_ID1 0x1000
@@ -222,7 +222,7 @@ int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
}
U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
- "xdevinfo - Show PCIX Device info\n", NULL);
+ "Show PCIX Device info", NULL);
extern void show_reset_reg(void);
@@ -233,4 +233,4 @@ int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
- "resetinfo - Show Reset REG info\n", NULL);
+ "Show Reset REG info", NULL);
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
index 96b918b..63f8744 100644
--- a/board/amcc/taishan/update.c
+++ b/board/amcc/taishan/update.c
@@ -74,5 +74,5 @@ int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
- "update_boot_eeprom - update bootstrap eeprom content\n", NULL);
+ "update bootstrap eeprom content", NULL);
#endif
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index d969860..d2ca257 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -59,7 +59,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
char pcixClock[4];
if (argc < 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -281,6 +281,6 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
U_BOOT_CMD(
evb440spe, 3, 1, do_evb440spe,
- "evb440spe - program the serial device strap\n",
+ "program the serial device strap",
"wrclk [prom0|prom1] - program the serial device strap\n"
);
diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c
index e9f80ff..fcf2698 100644
--- a/board/amirix/ap1000/ap1000.c
+++ b/board/amirix/ap1000/ap1000.c
@@ -659,7 +659,7 @@ done:
}
U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
- "temp - interact with the temperature sensor\n",
+ "interact with the temperature sensor",
"temp [s]\n"
" - Show status.\n"
"temp l LOW [HIGH] [THERM]\n"
@@ -674,28 +674,28 @@ U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
#if 0
U_BOOT_CMD (loadace, 2, 0, do_loadace,
- "loadace - load fpga configuration from System ACE compact flash\n",
+ "load fpga configuration from System ACE compact flash",
"N\n"
" - Load configuration N (0-7) from System ACE compact flash\n"
"loadace\n" " - loads default configuration\n");
#endif
U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
- "swconfig- display or modify the software configuration byte\n",
+ "display or modify the software configuration byte",
"N [ADDRESS]\n"
" - set software configuration byte to N, optionally use ADDRESS as\n"
" location of buffer for flash copy\n"
"swconfig\n" " - display software configuration byte\n");
U_BOOT_CMD (pause, 2, 0, do_pause,
- "pause - sleep processor until any key is pressed with poll time of N seconds\n",
+ "sleep processor until any key is pressed with poll time of N seconds",
"N\n"
" - sleep processor until any key is pressed with poll time of N seconds\n"
"pause\n"
" - sleep processor until any key is pressed with poll time of 1 second\n");
U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
- "swrecon - trigger a board reconfigure to the software selected configuration\n",
+ "trigger a board reconfigure to the software selected configuration",
"\n"
" - trigger a board reconfigure to the software selected configuration\n");
diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c
index f048155..f727061 100644
--- a/board/amirix/ap1000/powerspan.c
+++ b/board/amirix/ap1000/powerspan.c
@@ -478,7 +478,7 @@ int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
- "eeprom - read/write/copy to/from the PowerSpan II eeprom\n",
+ "read/write/copy to/from the PowerSpan II eeprom",
"eeprom r OFF [NUM]\n"
" - read NUM words starting at OFF\n"
"eeprom w OFF VAL\n"
diff --git a/board/barco/barco.c b/board/barco/barco.c
index ed35572..a19e1ed 100644
--- a/board/barco/barco.c
+++ b/board/barco/barco.c
@@ -292,7 +292,7 @@ int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if 0
if (argc > 1) {
- printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
#endif
@@ -306,19 +306,19 @@ int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD (
try_working, 1, 1, barcobcd_boot_image,
- " try_working - check flash value and boot the appropriate image\n",
+ "check flash value and boot the appropriate image",
"\n"
);
U_BOOT_CMD (
boot_working, 1, 1, barcobcd_boot_image,
- " boot_working - check flash value and boot the appropriate image\n",
+ "check flash value and boot the appropriate image",
"\n"
);
U_BOOT_CMD (
boot_default, 1, 1, barcobcd_boot_image,
- " boot_default - check flash value and boot the appropriate image\n",
+ "check flash value and boot the appropriate image",
"\n"
);
/*
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
index ae5061f..aa46e58 100644
--- a/board/bc3450/cmd_bc3450.c
+++ b/board/bc3450/cmd_bc3450.c
@@ -194,7 +194,7 @@ int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD (dip, 1, 1, cmd_dip,
- "dip - read dip switch and config inputs\n",
+ "read dip switch and config inputs",
"\n"
" - prints the state of the dip switch and/or\n"
" external configuration inputs as hex value.\n"
@@ -228,7 +228,7 @@ static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD (buz, 2, 1, cmd_buz,
- "buz - turns buzzer on/off\n",
+ "turns buzzer on/off",
"\n" "buz <on/off>\n" " - turns the buzzer on or off\n");
#endif /* CONFIG_BC3450_BUZZER */
@@ -322,7 +322,7 @@ static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD (fp, 3, 1, cmd_fp,
- "fp - front panes access functions\n",
+ "front panes access functions",
"\n"
"fp bl <on/off>\n"
" - turns the CCFL backlight of the display on/off\n"
@@ -523,7 +523,7 @@ static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD (temp, 3, 1, cmd_temp,
- "temp - print current temperature\n",
+ "print current temperature",
"\n" "temp\n" " - print current temperature\n");
#ifdef CONFIG_BC3450_CAN
@@ -816,7 +816,7 @@ int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return 1;
}
-U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n"
+U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
#ifdef CONFIG_BC3450_CAN
"test can\n"
" - connect CAN1 (X8) with CAN2 (X9) for this test\n"
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
index 6a45b7c..1260277 100644
--- a/board/bf533-ezkit/Makefile
+++ b/board/bf533-ezkit/Makefile
@@ -29,11 +29,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o
+COBJS-y := $(BOARD).o flash.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
index 42c4b50..d5f0b7c 100644
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -1,7 +1,7 @@
/*
- * U-boot - ezkit533.c
+ * U-boot - main board file
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -26,9 +26,8 @@
*/
#include <common.h>
-#if defined(CONFIG_MISC_INIT_R)
#include "psd4256.h"
-#endif
+#include "flash-defines.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -41,24 +40,11 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
-#ifdef DEBUG
- int brate;
- char *tmp = getenv("baudrate");
- brate = simple_strtoul(tmp, NULL, 16);
- printf("Serial Port initialized with Baud rate = %x\n", brate);
- printf("SDRAM attributes:\n");
- printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
- "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
- 3, 3, 6, 2, 3);
- printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
- printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
-#endif
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
- return CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
}
-#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
@@ -71,4 +57,3 @@ int misc_init_r(void)
return 0;
}
-#endif
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
index 1a4aa5f..eb0af94 100644
--- a/board/bf533-ezkit/flash-defines.h
+++ b/board/bf533-ezkit/flash-defines.h
@@ -50,6 +50,7 @@
#define FLASH_SIZE 0x220000
#define FLASH_MAN_ST 2
#define CONFIG_SYS_FLASH0_BASE 0x20000000
+#define CONFIG_SYS_FLASH1_BASE 0x20200000
#define RESET_VAL 0xF0
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
@@ -68,9 +69,6 @@ int write_flash(long nOffset, int nValue);
void get_sector_number(long lOffset, int *pnSector);
int GetSectorProtectionStatus(flash_info_t * info, int nSector);
int GetOffset(int nBlock);
-int AFP_NumSectors = 40;
-long AFP_SectorSize1 = 0x10000;
-int AFP_SectorSize2 = 0x4000;
#define WRITESEQ1 0x0AAA
#define WRITESEQ2 0x0554
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
index a861e16..ab808d8 100644
--- a/board/bf533-ezkit/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -29,6 +29,10 @@
#include <asm/io.h>
#include "flash-defines.h"
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
void flash_reset(void)
{
reset_flash();
@@ -123,7 +127,7 @@ void flash_print_info(flash_info_t * info)
printf("ST Microelectronics ");
break;
default:
- printf("Unknown Vendor: (0x%08X) ", info->flash_id);
+ printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
@@ -211,7 +215,7 @@ int write_data(long lStart, long lCount, uchar * pnData)
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
- ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+ ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
ulOffset);
return FLASH_FAIL;
}
@@ -230,7 +234,7 @@ int write_data(long lStart, long lCount, uchar * pnData)
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
- ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+ ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
ulOffset);
return FLASH_FAIL;
}
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
index 5ae0228..a03fe89 100644
--- a/board/bf533-stamp/Makefile
+++ b/board/bf533-stamp/Makefile
@@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Device Inc.
+# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -29,11 +29,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o spi_flash.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_VIDEO) += video.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 0c6324b..44ebc93 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -49,43 +49,28 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
-#ifdef DEBUG
- printf("SDRAM attributes:\n");
- printf
- (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
- "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
- (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
- printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
- printf("Bank size = %d MB\n", 128);
-#endif
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
- return (gd->bd->bi_memsize);
+ return gd->bd->bi_memsize;
}
+/* PF0 and PF1 are used to switch between the ethernet and flash:
+ * PF0 PF1
+ * flash: 0 0
+ * ether: 1 0
+ */
void swap_to(int device_id)
{
-
- if (device_id == ETHERNET) {
- *pFIO_DIR = PF0;
- SSYNC();
- *pFIO_FLAG_S = PF0;
- SSYNC();
- } else if (device_id == FLASH) {
- *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
- *pFIO_FLAG_S = (PF4 | PF3 | PF2);
- *pFIO_MASKA_D = (PF8 | PF6 | PF5);
- *pFIO_MASKB_D = (PF7);
- *pFIO_POLAR = (PF8 | PF6 | PF5);
- *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
- *pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
- *pFIO_FLAG_D = (PF4 | PF3 | PF2);
- SSYNC();
- } else {
- printf("Unknown bank to switch\n");
- }
-
- return;
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
+ SSYNC();
+ bfin_write_FIO_FLAG_C(PF1);
+ if (device_id == ETHERNET)
+ bfin_write_FIO_FLAG_S(PF0);
+ else if (device_id == FLASH)
+ bfin_write_FIO_FLAG_C(PF0);
+ else
+ printf("Unknown device to switch\n");
+ SSYNC();
}
#if defined(CONFIG_MISC_INIT_R)
@@ -113,9 +98,6 @@ int misc_init_r(void)
if (cf_stat) {
printf("Booting from COMPACT flash\n");
- /* Set cycle time for CF */
- *(volatile unsigned long *)ambctl1 = CF_AMBCTL1VAL;
-
for (i = 0; i < 0x1000; i++)
asm("nop;");
for (i = 0; i < 0x1000; i++)
diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h
index 3b0d620..ebd39c7 100644
--- a/board/bf533-stamp/bf533-stamp.h
+++ b/board/bf533-stamp/bf533-stamp.h
@@ -34,9 +34,6 @@ extern volatile unsigned long *ambctl0;
extern volatile unsigned long *ambctl1;
extern volatile unsigned long *amgctl;
-extern unsigned long pll_div_fact;
-extern void serial_setbrg(void);
-
/* Definitions used in Compact Flash Boot support */
#define FIO_EDGE_CF_BITS 0x0000
#define FIO_POLAR_CF_BITS 0x0000
diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c
new file mode 100644
index 0000000..3c15eaa
--- /dev/null
+++ b/board/bf533-stamp/video.c
@@ -0,0 +1,167 @@
+/*
+ * BF533-STAMP splash driver
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/ppi.h>
+
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE 720 * 240 */
+#define VERTICAL 2
+#define HORIZONTAL 4
+
+int is_vblank_line(const int line)
+{
+ /*
+ * This array contains a single bit for each line in
+ * an NTSC frame.
+ */
+ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+ return true;
+
+ return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+ const int NTSC_frames = 1;
+ const int NTSC_lines = 525;
+ char *dest = base_address;
+ int frame_num, line_num;
+
+ for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+ for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+ unsigned int code;
+ int offset = 0;
+ int i;
+
+ if (is_vblank_line(line_num))
+ offset++;
+
+ if (line_num > 266 || line_num < 3)
+ offset += 2;
+
+ /* Output EAV code */
+ code = system_code_map[offset].eav;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output horizontal blanking */
+ for (i = 0; i < 67 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+
+ /* Output SAV */
+ code = system_code_map[offset].sav;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output empty horizontal data */
+ for (i = 0; i < 360 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+ }
+ }
+
+ return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+ int *OddPtr32;
+ int OddLine;
+ int *EvenPtr32;
+ int EvenLine;
+ int i;
+ int *data;
+ int m, n;
+
+ /* fill odd and even frames */
+ for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+ OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+ EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+ for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+ *OddPtr32 = Value;
+ *EvenPtr32 = Value;
+ }
+ }
+
+ for (m = 0; m < VERTICAL; m++) {
+ data = (int *)u_boot_logo.data;
+ for (OddLine = (22 + m), EvenLine = (285 + m);
+ OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+ OddLine += VERTICAL, EvenLine += VERTICAL) {
+ OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+ EvenPtr32 =
+ (int *)((Frame + ((EvenLine) * 1716)) + 276);
+ for (i = 0; i < u_boot_logo.width / 2; i++) {
+ /* enlarge one pixel to m x n */
+ for (n = 0; n < HORIZONTAL; n++) {
+ *OddPtr32++ = *data;
+ *EvenPtr32++ = *data;
+ }
+ data++;
+ }
+ }
+ }
+}
+
+static void video_init(char *NTSCFrame)
+{
+ NTSC_framebuffer_init(NTSCFrame);
+ fill_frame(NTSCFrame, BLUE);
+
+ bfin_write_PPI_CONTROL(0x0082);
+ bfin_write_PPI_FRAME(0x020D);
+
+ bfin_write_DMA0_START_ADDR(NTSCFrame);
+ bfin_write_DMA0_X_COUNT(0x035A);
+ bfin_write_DMA0_X_MODIFY(0x0002);
+ bfin_write_DMA0_Y_COUNT(0x020D);
+ bfin_write_DMA0_Y_MODIFY(0x0002);
+ bfin_write_DMA0_CONFIG(0x1015);
+ bfin_write_PPI_CONTROL(0x0083);
+}
+
+int drv_video_init(void)
+{
+ device_t videodev;
+
+ video_init((void *)NTSC_FRAME_ADDR);
+
+ memset(&videodev, 0, sizeof(videodev));
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO;
+ videodev.flags = DEV_FLAGS_SYSTEM;
+
+ return device_register(&videodev);
+}
diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h
new file mode 100644
index 0000000..80837e2
--- /dev/null
+++ b/board/bf533-stamp/video.h
@@ -0,0 +1,25 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK (0x01800180) /* black pixel pattern */
+#define BLUE (0x296E29F0) /* blue pixel pattern */
+#define RED (0x51F0515A) /* red pixel pattern */
+#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
+#define GREEN (0x91229136) /* green pixel pattern */
+#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
+#define YELLOW (0xD292D210) /* yellow pixel pattern */
+#define WHITE (0xFE80FE80) /* white pixel pattern */
+
+#define true 1
+#define false 0
+
+typedef struct {
+ unsigned int sav;
+ unsigned int eav;
+} system_code_type;
+
+const system_code_type system_code_map[] = {
+ { 0xFF000080, 0xFF00009D },
+ { 0xFF0000AB, 0xFF0000B6 },
+ { 0xFF0000C7, 0xFF0000DA },
+ { 0xFF0000EC, 0xFF0000F1 },
+};
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index e5ef9af..cb38b96 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -29,11 +29,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
+COBJS-y := $(BOARD).o post-memory.o cmd_bf537led.o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
index cec2b26..5b619be 100644
--- a/board/bf537-stamp/bf537-stamp.c
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -84,21 +84,9 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
phys_size_t initdram(int board_type)
{
-#ifdef DEBUG
- int brate;
- char *tmp = getenv("baudrate");
- brate = simple_strtoul(tmp, NULL, 16);
- printf("Serial Port initialized with Baud rate = %x\n", brate);
- printf("SDRAM attributes:\n");
- printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
- "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
- 3, 3, 6, 2, 3);
- printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
- printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
-#endif
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
- return CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
}
#if defined(CONFIG_MISC_INIT_R)
diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c
index fa650f2..e77bb0c 100644
--- a/board/bf537-stamp/cmd_bf537led.c
+++ b/board/bf537-stamp/cmd_bf537led.c
@@ -196,6 +196,6 @@ void show_cmd_usage()
/* Register information for u-boot to find this command */
U_BOOT_CMD(led, 3, 1, do_bf537led,
- "led- Control BF537 stamp LEDs\n", USAGE_LONG);
+ "Control BF537 stamp LEDs", USAGE_LONG);
#endif
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
index 20a7d0e..181e83d 100644
--- a/board/bf537-stamp/nand.c
+++ b/board/bf537-stamp/nand.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
+ * Copyright (c) 2006-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,8 +23,6 @@
#include <common.h>
#include <asm/io.h>
-#if defined(CONFIG_CMD_NAND)
-
#include <nand.h>
#define CONCAT(a,b,c,d) a ## b ## c ## d
@@ -43,11 +41,11 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
- if( ctrl & NAND_CLE )
+ if (ctrl & NAND_CLE)
IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
else
IO_ADDR_W = CONFIG_SYS_NAND_BASE;
- if( ctrl & NAND_ALE )
+ if (ctrl & NAND_ALE)
IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
else
IO_ADDR_W = CONFIG_SYS_NAND_BASE;
@@ -100,4 +98,3 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
-#endif
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index 889aa5c..9626f4c 100644
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -21,10 +21,10 @@ int post_init_sdram(int sclk);
void post_init_uart(int sclk);
const int pll[CCLK_NUM][SCLK_NUM][2] = {
- {{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
- {{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
- {{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
- {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
+ { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
+ { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */
+ { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */
+ { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */
};
const char *const log[CCLK_NUM][SCLK_NUM] = {
{"CCLK-500MHz SCLK-125MHz: Writing...\0",
@@ -119,7 +119,8 @@ void post_out_buff(char *buff)
{
int i = 0;
- for (i = 0; i < 0x80000; i++) ;
+ for (i = 0; i < 0x80000; i++)
+ ;
i = 0;
while ((buff[i] != '\0') && (i != 100)) {
while (!(*pUART_LSR & 0x20)) ;
@@ -127,7 +128,8 @@ void post_out_buff(char *buff)
SSYNC();
i++;
}
- for (i = 0; i < 0x80000; i++) ;
+ for (i = 0; i < 0x80000; i++)
+ ;
}
/* Using sw10-PF5 as the hotkey */
@@ -150,9 +152,8 @@ int post_key_pressed(void)
value = 0;
goto key_pressed;
}
- if (value != 0) {
+ if (value != 0)
goto key_pressed;
- }
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
@@ -164,9 +165,8 @@ int post_key_pressed(void)
value = 0;
goto key_pressed;
}
- if (value != 0) {
+ if (value != 0)
goto key_pressed;
- }
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
@@ -178,9 +178,8 @@ int post_key_pressed(void)
value = 0;
goto key_pressed;
}
- if (value != 0) {
+ if (value != 0)
goto key_pressed;
- }
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index 11a2803..99caa96 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -182,8 +182,8 @@ static struct manufacturer_info flash_manufacturers[] = {
* BF533, BF561: SSEL2
*/
#ifndef CONFIG_SPI_FLASH_SSEL
-# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
- defined(__ADSPBF533__) || defined(__ADSPBF561__)
+# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+ defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__)
# define CONFIG_SPI_FLASH_SSEL 2
# else
# define CONFIG_SPI_FLASH_SSEL 1
@@ -797,8 +797,8 @@ int eeprom_info(void)
ret = 1;
else
printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
- "Parameters: num sectors = %i, sector size = %i, write size = %i\n"
- "Flash Size: %i mbit (%i mbyte)\n"
+ "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n"
+ "Flash Size: %lu mbit (%lu mbyte)\n"
"Status: 0x%02X\n",
flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
flash.device_id1, flash.device_id2, flash.num_sectors,
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
index e7ee243..daebb74 100644
--- a/board/bf561-ezkit/Makefile
+++ b/board/bf561-ezkit/Makefile
@@ -29,11 +29,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS-y := $(BOARD).o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
index 7f8598c..5aede17 100644
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -39,19 +39,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
-#ifdef DEBUG
- int brate;
- char *tmp = getenv("baudrate");
- brate = simple_strtoul(tmp, NULL, 16);
- printf("Serial Port initialized with Baud rate = %x\n", brate);
- printf("SDRAM attributes:\n");
- printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
- "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
- 3, 3, 6, 2, 3);
- printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
- printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
-#endif
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
- return CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
}
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
index 00f0671..52f031c 100644
--- a/board/cm5200/cmd_cm5200.c
+++ b/board/cm5200/cmd_cm5200.c
@@ -435,7 +435,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
fkt, 4, 1, cmd_fkt,
- "fkt - Function test routines\n",
+ "Function test routines",
"i2c\n"
" - Test I2C communication\n"
"fkt led\n"
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index abf60b3..bf36f73 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -52,6 +52,7 @@ int board_init(void)
lpsc_on(DAVINCI_LPSC_UART0);
lpsc_on(DAVINCI_LPSC_TIMER1);
lpsc_on(DAVINCI_LPSC_GPIO);
+ lpsc_on(DAVINCI_LPSC_USB);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
@@ -101,3 +102,26 @@ int misc_init_r(void)
return(0);
}
+
+#ifdef CONFIG_USB_DAVINCI
+
+/* IO Expander I2C address and USB VBUS enable mask */
+#define IOEXP_I2C_ADDR 0x3A
+#define IOEXP_VBUSEN_MASK 1
+
+/*
+ * This function enables USB VBUS by writting to IO expander using I2C.
+ * Note that the I2C is already initialized at this stage. This
+ * function is used by davinci specific USB wrapper code.
+ */
+void enable_vbus(void)
+{
+ uchar data; /* IO Expander data to enable VBUS */
+
+ /* Write to IO expander to enable VBUS */
+ i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+ data &= ~IOEXP_VBUSEN_MASK;
+ i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+}
+#endif
+
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 878416f..73e6c3e 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -259,7 +259,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
- "kbd - read keyboard status\n",
+ "read keyboard status",
NULL
);
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
index eef6318..1664f3b 100644
--- a/board/delta/lowlevel_init.S
+++ b/board/delta/lowlevel_init.S
@@ -74,7 +74,7 @@ mem_init:
/* 3. wait nop power up waiting period (200ms)
* optimization: Steps 4+6 can be done during this
*/
- wait #300
+ wait #0x300
/* 4. Perform an initial Rcomp-calibration cycle */
ldr r0, =RCOMP
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index 3abcfe6..c4b4b67 100644
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -247,7 +247,7 @@ int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
digtest, 3, 1, do_digtest,
- "digtest - Test digital in-/output\n",
+ "Test digital in-/output",
NULL
);
@@ -341,7 +341,7 @@ int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
anatest, 2, 1, do_anatest,
- "anatest - Test analog in-/output\n",
+ "Test analog in-/output",
NULL
);
@@ -408,7 +408,7 @@ int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
inctest, 3, 1, do_inctest,
- "inctest - Test incremental encoder inputs\n",
+ "Test incremental encoder inputs",
NULL
);
#endif
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 5709d45..d0ee193 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -198,7 +198,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 633f641..4ea373a 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -550,7 +550,7 @@ int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
autoupd, 1, 1, auto_update,
- "autoupd - Automatically update images\n",
+ "Automatically update images",
NULL
);
#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index ad490c3..0a6626e 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -123,7 +123,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
loadpci, 1, 1, do_loadpci,
- "loadpci - Wait for pci bootcmd and boot it\n",
+ "Wait for pci bootcmd and boot it",
NULL
);
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 1eea59e..066df74 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -346,7 +346,7 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *str;
#endif
if (argc != 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -372,6 +372,6 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
esdbmp, 2, 1, do_esdbmp,
- "esdbmp - display BMP image\n",
+ "display BMP image",
"<imageAddr> - display image\n"
);
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
index 318f229..9b2cf90 100644
--- a/board/esd/common/xilinx_jtag/micro.c
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -1859,6 +1859,6 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
cpld, 1, 1, do_cpld,
- "cpld - Program onboard CPLD\n",
+ "Program onboard CPLD",
NULL
);
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index dcab906..517b174 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -176,7 +176,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index bd569a6..0aca825 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -689,7 +689,7 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
onewire, 1, 1, do_onewire,
- "onewire - Read 1-write ID\n",
+ "Read 1-write ID",
NULL
);
@@ -750,7 +750,7 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
getbpip, 1, 1, do_get_bpip,
- "getbpip - Update IP-Address with Backplane IP-Address\n",
+ "Update IP-Address with Backplane IP-Address",
NULL
);
@@ -786,7 +786,7 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
setbpip, 2, 1, do_set_bpip,
- "setbpip - Write Backplane IP-Address\n",
+ "Write Backplane IP-Address",
NULL
);
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
index 6eedb83..b6b50fb 100644
--- a/board/esd/cpci5200/cpci5200.c
+++ b/board/esd/cpci5200/cpci5200.c
@@ -294,5 +294,5 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "writepci- Write some data to pcibus\n",
+ "Write some data to pcibus",
"<addr> <size>\n" " - Write some data to pcibus.\n");
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 70bae60..4826633 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -993,6 +993,6 @@ int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
show_config, 1, 1, do_show_config,
- "show_config - Show Marvell strapping register\n",
+ "Show Marvell strapping register",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index 36dd58c..f405be9 100644
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -220,14 +220,14 @@ int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
return 0;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
pci9054, 3, 1, do_pci9054,
- "pci9054 - PLX PCI9054 EEPROM access\n",
+ "PLX PCI9054 EEPROM access",
"pci9054 info - print EEPROM values\n"
"pci9054 update - updates EEPROM with default values\n"
);
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 2f97a12..f9b91b5 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -606,7 +606,7 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
dcf77, 1, 1, do_dcf77,
- "dcf77 - Check DCF77 receiver\n",
+ "Check DCF77 receiver",
NULL
);
@@ -656,7 +656,7 @@ int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
hubinit, 1, 1, do_hubinit,
- "hubinit - Initialize USB hub\n",
+ "Initialize USB hub",
NULL
);
#endif /* CONFIG_I2C_MULTI_BUS */
@@ -789,7 +789,7 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
sbe, 2, 0, do_setup_boot_eeprom,
- "sbe - setup boot eeprom\n",
+ "setup boot eeprom",
NULL
);
@@ -863,7 +863,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
@@ -914,7 +914,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
wpi, 1, 1, do_waitpwrirq,
- "wpi - Wait for power change interrupt\n",
+ "Wait for power change interrupt",
NULL
);
@@ -959,7 +959,7 @@ int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
dviinit, 1, 1, do_dviinit,
- "dviinit - Initialize DVI Panellink transmitter\n",
+ "Initialize DVI Panellink transmitter",
NULL
);
@@ -999,7 +999,7 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
time, CONFIG_SYS_MAXARGS, 1, do_time,
- "time - run command and output execution time\n",
+ "run command and output execution time",
NULL
);
@@ -1049,6 +1049,6 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
- "gfxdemo - demo\n",
+ "demo",
NULL
);
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index efadf16..ae3bc80 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -733,7 +733,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c
index f83dfe8..db2c548 100644
--- a/board/esd/ocrtc/cmd_ocrtc.c
+++ b/board/esd/ocrtc/cmd_ocrtc.c
@@ -54,7 +54,7 @@ int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
setdevice, 1, 1, do_setdevice,
- "setdevice - Set device number on pci adapter boards\n",
+ "Set device number on pci adapter boards",
NULL
);
@@ -77,7 +77,7 @@ int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
getdevice, 1, 1, do_getdevice,
- "getdevice - Get device number and set slot env variable\n",
+ "Get device number and set slot env variable",
NULL
);
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
index f558a2b..a0d1f3f 100644
--- a/board/esd/pci405/cmd_pci405.c
+++ b/board/esd/pci405/cmd_pci405.c
@@ -108,7 +108,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
loadpci, 1, 1, do_loadpci,
- "loadpci - Wait for pci-image and boot it\n",
+ "Wait for pci-image and boot it",
NULL
);
#endif
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 42774ad..0602abf 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -375,7 +375,7 @@ int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
wpeeprom, 2, 1, do_wpeeprom,
- "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
+ "Check/Enable/Disable I2C EEPROM write protection",
"wpeeprom\n"
" - check I2C EEPROM write protection state\n"
"wpeeprom 1\n"
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
index f7962af..f225f0e 100644
--- a/board/esd/pf5200/pf5200.c
+++ b/board/esd/pf5200/pf5200.c
@@ -294,7 +294,7 @@ int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return (0);
}
-U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", NULL);
int phypower(int flag)
{
@@ -338,7 +338,7 @@ int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(phypower, 2, 2, do_phypower,
- "phypower- Switch power of ethernet phy\n", NULL);
+ "Switch power of ethernet phy", NULL);
int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
@@ -369,5 +369,5 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "writepci- Write some data to pcibus\n",
+ "Write some data to pcibus",
"<addr> <size>\n" " - Write some data to pcibus.\n");
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 85057a2..7c0aaa2 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -333,6 +333,6 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index c0781dc..975b6d6 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -203,6 +203,6 @@ int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
cantest, 3, 1, do_cantest,
- "cantest - Test CAN controller",
+ "Test CAN controller",
NULL
);
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 16c9c7e..7808d4d 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -98,7 +98,7 @@ int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
waithci, 1, 1, do_waithci,
- "waithci - Wait for host control interrupt\n",
+ "Wait for host control interrupt",
NULL
);
@@ -258,7 +258,7 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
fifo, 5, 1, do_fifo,
- "fifo - Fifo module operations\n",
+ "Fifo module operations",
"wait\nfifo read\n"
"fifo write fifo(0..3) data [cnt=1]\n"
"fifo write address(>=4) data [cnt=1]\n"
@@ -336,7 +336,7 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
}
U_BOOT_CMD(
sbe, 4, 0, do_setup_bootstrap_eeprom,
- "sbe - setup bootstrap eeprom\n",
+ "setup bootstrap eeprom",
"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
);
@@ -399,7 +399,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
painit, 1, 1, do_painit,
- "painit - prepare PciAccess system\n",
+ "prepare PciAccess system",
NULL
);
#endif /* CONFIG_PRAM */
@@ -411,7 +411,7 @@ int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
selfreset, 1, 1, do_selfreset,
- "selfreset- assert self-reset# signal\n",
+ "assert self-reset# signal",
NULL
);
@@ -448,7 +448,7 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
resetout, 2, 1, do_resetout,
- "resetout - assert PMC-RESETOUT# signal\n",
+ "assert PMC-RESETOUT# signal",
NULL
);
@@ -480,7 +480,7 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
inta, 2, 1, do_inta,
- "inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
+ "Assert/Deassert or query INTA# state in non-monarch mode",
NULL
);
@@ -513,7 +513,7 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
pmm, 2, 1, do_pmm,
- "pmm - Setup pmm[1] registers\n",
+ "Setup pmm[1] registers",
"<pciaddr> (pciaddr will be aligned to 256MB)\n"
);
@@ -549,7 +549,7 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
index 64e6d63..80ff237 100644
--- a/board/esd/tasreg/tasreg.c
+++ b/board/esd/tasreg/tasreg.c
@@ -248,7 +248,7 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
iploop, 2, 1, do_iploop,
- "iploop - iprobe loop <addr>\n",
+ "iprobe loop <addr>",
NULL
);
@@ -301,7 +301,7 @@ int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
codec, 1, 1, do_codec,
- "codec - Enable codec\n",
+ "Enable codec",
NULL
);
@@ -334,7 +334,7 @@ int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
saa, 5, 1, do_saa,
- "saa - Write to SAA1064 <addr> <instr> <cntrl> <data>\n",
+ "Write to SAA1064 <addr> <instr> <cntrl> <data>",
NULL
);
@@ -373,7 +373,7 @@ int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
iwrite, 6, 1, do_iwrite,
- "iwrite - Write n bytes to I2C-device\n",
+ "Write n bytes to I2C-device",
"addr cnt data0 ... datan\n"
);
@@ -405,7 +405,7 @@ int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
iread, 3, 1, do_iread,
- "iread - Read from I2C <addr> <cnt>\n",
+ "Read from I2C <addr> <cnt>",
NULL
);
@@ -443,7 +443,7 @@ int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
ireadl, 2, 1, do_ireadl,
- "ireadl - Read-loop from I2C <addr>\n",
+ "Read-loop from I2C <addr>",
NULL
);
#endif
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index ec65ffd..5480105 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -392,6 +392,6 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
+ "Enable / disable / query EEPROM write access",
NULL);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c
index 1d03570..aef9c27 100644
--- a/board/evb64260/zuma_pbb.c
+++ b/board/evb64260/zuma_pbb.c
@@ -202,19 +202,19 @@ do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
zinit, 1, 0, do_zuma_init_pbb,
- "zinit - init zuma pbb\n",
+ "init zuma pbb",
"\n"
" - init zuma pbb\n"
);
U_BOOT_CMD(
zdtest, 3, 1, do_zuma_test_dma,
- "zdtest - run dma test\n",
+ "run dma test",
"[cmd [count]]\n"
" - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n"
);
U_BOOT_CMD(
zminit, 1, 0, do_zuma_init_mbox,
- "zminit - init zuma mbox\n",
+ "init zuma mbox",
"\n"
" - init zuma mbox\n"
);
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 96820ac..eb76d93 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -280,7 +280,7 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
U_BOOT_CMD(
diswd, 1, 0, pixis_disable_watchdog_cmd,
- "diswd - Disable watchdog timer \n",
+ "Disable watchdog timer",
NULL);
#ifdef CONFIG_PIXIS_SGMII_CMD
@@ -539,7 +539,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
- "pixis_reset - Reset the board using the FPGA sequencer\n",
+ "Reset the board using the FPGA sequencer",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index eb58c7f..988cb94 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -328,7 +328,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
prog_eeprom();
break;
default:
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
break;
}
@@ -362,7 +362,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
break;
case 'h': /* help */
default:
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
break;
}
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 1e2e2dc..eb80500 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -37,6 +37,7 @@
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>
+#include <sata.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
@@ -582,15 +583,15 @@ get_board_ddr_clk(ulong dummy)
}
#endif
-int is_sata_supported(void)
+int sata_initialize(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint sdrs2_io_sel =
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
if (sdrs2_io_sel & 0x04)
- return 0;
+ return 1;
- return 1;
+ return __sata_initialize();
}
int board_eth_init(bd_t *bis)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index cd25d4a..2b2d5d7 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -116,7 +116,7 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
unsigned int addr;
if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -138,7 +138,7 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
U_BOOT_CMD(
diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp,
- "diufb init | addr - Init or Display BMP file\n",
+ "Init or Display BMP file",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
);
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 48fc643..b35038d 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -185,7 +185,7 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
dumpebc, 1, 1, do_dumpebc,
- "dumpebc - Dump all EBC registers\n",
+ "Dump all EBC registers",
NULL
);
@@ -207,7 +207,7 @@ int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
dumpdcr, 1, 1, do_dumpdcr,
- "dumpdcr - Dump all DCR registers\n",
+ "Dump all DCR registers",
NULL
);
@@ -271,7 +271,7 @@ int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
dumpspr, 1, 1, do_dumpspr,
- "dumpspr - Dump all SPR registers\n",
+ "Dump all SPR registers",
NULL
);
#endif
diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile
new file mode 100644
index 0000000..b93f2c3
--- /dev/null
+++ b/board/gdsys/gdppc440etx/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk
new file mode 100644
index 0000000..045f3e9
--- /dev/null
+++ b/board/gdsys/gdppc440etx/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# G&D 440EP/GR ETX-Module
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
new file mode 100644
index 0000000..a661057
--- /dev/null
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -0,0 +1,323 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/yosemite/yosemite.c
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*
+ * Setup the external bus controller/chip selects
+ */
+ mfebc(xbcfg, reg);
+ mtebc(xbcfg, reg | 0x04000000); /* Set ATC */
+
+ /*
+ * Setup the GPIO pins
+ */
+
+ /* setup Address lines for flash size 64Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
+
+ /* setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /* UART0 and UART1*/
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
+
+ /* disable boot-eeprom WP */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
+
+ /* external interrupts IRQ0...3 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*
+ * Setup other serial configuration
+ */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
+ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val;
+ uint sz;
+
+ /* Re-do sizing to get full correct info */
+ mfebc(pb0cr, pbcr);
+
+ if (gd->bd->bi_flashsize > 0x08000000)
+ panic("Max. flash banksize is 128 MB!\n");
+
+ for (sz = gd->bd->bi_flashsize, size_val = 7;
+ ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
+ sz <<= 1;
+
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(pb0cr, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ /* enable 66 MHz ext. Clock */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
+ out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Set up Direct MMIO registers
+ */
+
+ /*
+ * PowerPC440 EP PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF
+ * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIX0_PMM0PCIHA, 0x00000000);
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIX0_PMM1PCIHA, 0x00000000);
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001);
+ out32r(PCIX0_PTM1LA, 0);
+ out32r(PCIX0_PTM2MS, 0);
+ out32r(PCIX0_PTM2LA, 0);
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+/*
+ * pci_master_init
+ *
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
+
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
new file mode 100644
index 0000000..0bbd45a
--- /dev/null
+++ b/board/gdsys/gdppc440etx/init.S
@@ -0,0 +1,75 @@
+/*
+* (C) Copyright 2008
+* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+*
+* based on board/amcc/yosemite/init.S
+* original Copyright not specified there
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
+ * the speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
+ 0, AC_R|AC_W|AC_X|SA_G )
+
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
+ 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
+ 0, AC_R|AC_W|SA_G|SA_I )
+
+ /* PCI */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
+ 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
+ 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
+ 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
+ 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds
new file mode 100644
index 0000000..1df817b
--- /dev/null
+++ b/board/gdsys/gdppc440etx/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/gdsys/gdppc440etx/init.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
index 1848bb3..092d368 100644
--- a/board/hymod/bsp.c
+++ b/board/hymod/bsp.c
@@ -272,12 +272,12 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
fpga, 6, 1, do_fpga,
- "fpga - FPGA sub-system\n",
+ "FPGA sub-system",
"load [type] addr size\n"
" - write the configuration data at memory address `addr',\n"
" size `size' bytes, into the FPGA of type `type' (either\n"
@@ -324,7 +324,7 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
/* fall through ... */
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -336,7 +336,7 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
eeclear, 1, 0, do_eecl,
- "eeclear - Clear the eeprom on a Hymod board \n",
+ "Clear the eeprom on a Hymod board",
"[type]\n"
" - write zeroes into the EEPROM on the board of type `type'\n"
" (`type' is either `main' or `mezz' - default `main')\n"
diff --git a/board/keymile/common/keymile_hdlc_enet.c b/board/keymile/common/keymile_hdlc_enet.c
index 141371b..5797880 100644
--- a/board/keymile/common/keymile_hdlc_enet.c
+++ b/board/keymile/common/keymile_hdlc_enet.c
@@ -590,7 +590,7 @@ int hdlc_enet_stest(struct cmd_tbl_s *a, int b, int c, char **d)
}
U_BOOT_CMD(
stest, 1, 1, hdlc_enet_stest,
- "stest - simple send test for hdlc_enet\n",
+ "simple send test for hdlc_enet",
"no arguments\n"
);
/* simple receive test routine */
@@ -612,7 +612,7 @@ int hdlc_enet_rtest(struct cmd_tbl_s *a, int b, int c, char **d)
}
U_BOOT_CMD(
rtest, 1, 1, hdlc_enet_rtest,
- "rtest - simple receive test for hdlc_enet\n",
+ "simple receive test for hdlc_enet",
"no arguments\n"
);
#endif
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 5ad75f7..8328ba3 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
* Larry Johnson, lrj@acm.org
*
* (C) Copyright 2006-2007
@@ -351,6 +351,7 @@ int misc_init_r(void)
unsigned long sdr0_pfc1;
uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
char const *const act = getenv("usbact");
+ char const *const usbcf = getenv("korat_usbcf");
/*
* Re-do FLASH1 sizing and adjust flash start and offset.
@@ -405,6 +406,26 @@ int misc_init_r(void)
/*
* USB suff...
*/
+ /*
+ * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
+ * ("pci") for the CompactFlash.
+ */
+ if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
+ /*
+ * If environment variable "usbcf" is defined and set to "ppc",
+ * then connect the CompactFlash controller to the PowerPC USB
+ * port.
+ */
+ printf("Attaching CompactFalsh controller to PPC USB\n");
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
+ } else {
+ if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
+ printf("Warning: \"korat_usbcf\" is not set to a legal "
+ "value (\"ppc\" or \"pci\")\n");
+
+ printf("Attaching CompactFalsh controller to PCI USB\n");
+ }
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 878752c..1b665a9 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -846,12 +846,12 @@ int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
pic, 4, 1, do_pic,
- "pic - read and write PIC registers\n",
+ "read and write PIC registers",
"read reg - read PIC register `reg'\n"
"pic write reg val - write value `val' to PIC register `reg'\n"
);
@@ -910,7 +910,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
- "kbd - read keyboard status\n",
+ "read keyboard status",
NULL
);
@@ -976,13 +976,13 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
lsb, 2, 1, do_lsb,
- "lsb - check and set LSB switch\n",
+ "check and set LSB switch",
"on - switch LSB on\n"
"lsb off - switch LSB off\n"
"lsb - print current setting\n"
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 0a8787a..bafd39c 100644
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
@@ -432,7 +432,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
- "kbd - read keyboard status\n",
+ "read keyboard status",
NULL
);
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index aa62f37..4c04b98 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -467,7 +467,7 @@ void hw_watchdog_reset(void)
int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -476,7 +476,7 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} else if ((strcmp(argv[1], "off") == 0)) {
gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
} else {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -486,7 +486,7 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
eepromwp, 2, 0, do_eeprom_wp,
- "eepromwp- eeprom write protect off/on\n",
+ "eeprom write protect off/on",
"<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n"
);
diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile
new file mode 100644
index 0000000..2737ade
--- /dev/null
+++ b/board/micronas/vct/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-y += ebi.o
+COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
+COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
+COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
+COBJS-y += gpio.o
+COBJS-y += top.o
+COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/micronas/vct/bcu.h b/board/micronas/vct/bcu.h
new file mode 100644
index 0000000..cac31f2
--- /dev/null
+++ b/board/micronas/vct/bcu.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BCU_H
+#define _BCU_H
+
+enum bcu_tags {
+ BCU_VBV1 = 0,
+ BCU_VBV2 = 1,
+ BCU_BSS1 = 2,
+ BCU_BSS2 = 3,
+ BCU_TSD_TXT = 4,
+ BCU_TSD_SUBTITLES = 5,
+ BCU_TSD_PES_0 = 6,
+ BCU_TSD_PES_1 = 7,
+ BCU_TSD_PES_2 = 8,
+ BCU_TSD_PES_3 = 9,
+ BCU_TSIO_RECORD_0 = 10,
+ BCU_TSIO_RECORD_1 = 11,
+ BCU_TSIO_PLAYBACK_0 = 12,
+ BCU_TSIO_PLAYBACK_1 = 13,
+ BCU_SECURE_BUFFER = 14,
+ BCU_PCM1 = 15,
+ BCU_PCM2 = 16,
+ BCU_BSS_COPY = 17,
+ BCU_BSS_EXT1 = 18,
+ BCU_BSS_EXT2 = 19,
+ BCU_PCM_JINGLE = 20,
+ BCU_EBI_CPU_BUFFER = 21,
+ BCU_PCM_DELAY = 22,
+ BCU_FH_BUFFER_0 = 23,
+ BCU_FH_BUFFER_1 = 24,
+ BCU_TSD_SECTION_0 = 25,
+ BCU_TSD_SECTION_1 = 26,
+ BCU_TSD_SECTION_2 = 27,
+ BCU_TSD_SECTION_3 = 28,
+ BCU_TSD_SECTION_4 = 29,
+ BCU_TSD_SECTION_5 = 30,
+ BCU_TSD_SECTION_6 = 31,
+ BCU_TSD_SECTION_7 = 32,
+ BCU_TSD_SECTION_8 = 33,
+ BCU_TSD_SECTION_9 = 34,
+ BCU_TSD_SECTION_10 = 35,
+ BCU_TSD_SECTION_11 = 36,
+ BCU_TSD_SECTION_12 = 37,
+ BCU_TSD_SECTION_13 = 38,
+ BCU_TSD_SECTION_14 = 39,
+ BCU_TSD_SECTION_15 = 40,
+ BCU_TSD_SECTION_16 = 41,
+ BCU_TSD_SECTION_17 = 42,
+ BCU_TSD_SECTION_18 = 43,
+ BCU_TSD_SECTION_19 = 44,
+ BCU_TSD_SECTION_20 = 45,
+ BCU_TSD_SECTION_21 = 46,
+ BCU_TSD_SECTION_22 = 47,
+ BCU_TSD_SECTION_23 = 48,
+ BCU_TSD_SECTION_24 = 49,
+ BCU_TSD_SECTION_25 = 50,
+ BCU_TSD_SECTION_26 = 51,
+ BCU_TSD_SECTION_27 = 52,
+ BCU_TSD_SECTION_28 = 53,
+ BCU_TSD_SECTION_29 = 54,
+ BCU_TSD_SECTION_30 = 55,
+ BCU_TSD_SECTION_31 = 56,
+ BCU_TSD_SECTION_32 = 57,
+ BCU_TSD_SECTION_33 = 58,
+ BCU_TSD_SECTION_34 = 59,
+ BCU_TSD_SECTION_35 = 60,
+ BCU_TSD_SECTION_36 = 61,
+ BCU_TSD_SECTION_37 = 62,
+ BCU_TSD_SECTION_38 = 63,
+ BCU_TSD_SECTION_39 = 64,
+ BCU_TSD_SECTION_40 = 65,
+ BCU_TSD_SECTION_41 = 66,
+ BCU_TSD_SECTION_42 = 67,
+ BCU_TSD_SECTION_43 = 68,
+ BCU_TSD_SECTION_44 = 69,
+ BCU_TSD_SECTION_45 = 70,
+ BCU_TSD_SECTION_46 = 71,
+ BCU_TSD_SECTION_47 = 72,
+ BCU_TSD_SECTION_48 = 73,
+ BCU_TSD_SECTION_49 = 74,
+ BCU_TSD_SECTION_50 = 75,
+ BCU_TSD_SECTION_51 = 76,
+ BCU_TSD_SECTION_52 = 77,
+ BCU_TSD_SECTION_53 = 78,
+ BCU_TSIO_RECORD_2 = 79,
+ BCU_TSIO_RECORD_3 = 80,
+ BCU_TSIO_RECORD_4 = 81,
+ BCU_TSIO_RECORD_5 = 82,
+ BCU_TSIO_RECORD_6 = 83,
+ BCU_TSIO_RECORD_7 = 84,
+ BCU_TSIO_RECORD_8 = 85,
+ BCU_TSIO_RECORD_9 = 86,
+ BCU_PCM_DELAY_LINEAR = 87,
+ BCU_VD_MASTER_USER_DATA = 88,
+ BCU_VD_SLAVE_USER_DATA = 89,
+ BCU_VD_MASTER_REF0 = 90,
+ BCU_VD_MASTER_REF1 = 91,
+ BCU_VD_SLAVE_REF0 = 92,
+ BCU_VD_SLAVE_REF1 = 93,
+ BCU_VD_MASTER_DISP0_Y = 94,
+ BCU_VD_MASTER_DISP1_Y = 95,
+ BCU_VD_MASTER_DISP2_Y = 96,
+ BCU_VD_MASTER_DISP0_C = 97,
+ BCU_VD_MASTER_DISP1_C = 98,
+ BCU_VD_MASTER_DISP2_C = 99,
+ BCU_VD_SLAVE_DISP0_Y = 100,
+ BCU_VD_SLAVE_DISP1_Y = 101,
+ BCU_VD_SLAVE_DISP2_Y = 102,
+ BCU_VD_SLAVE_DISP0_C = 103,
+ BCU_VD_SLAVE_DISP1_C = 104,
+ BCU_VD_SLAVE_DISP2_C = 105,
+ BCU_CLUT_BUFFER_0 = 106,
+ BCU_CLUT_BUFFER_1 = 107,
+ BCU_OSD_FRAME_BUFFER_0 = 108,
+ BCU_OSD_FRAME_BUFFER_1 = 109,
+ BCU_GRAPHIC_FRAME_BUFFER0 = 110,
+ BCU_GRAPHIC_FRAME_BUFFER1 = 111,
+ BCU_DVP_VBI_REINSERTION = 112,
+ BCU_DVP_OSD_FRAME_BUFFER0 = 113,
+ BCU_DVP_OSD_FRAME_BUFFER1 = 114,
+ BCU_GAI_BUFFER = 115,
+ BCU_GA_SRC_BUFFER_0 = 116,
+ BCU_GA_SRC_BUFFER_1 = 117,
+ BCU_USB_BUFFER_0 = 118,
+ BCU_USB_BUFFER_1 = 119,
+ BCU_FE_3DCOMB_0 = 120,
+ BCU_FE_3DCOMB_1 = 121,
+ BCU_FE_3DCOMB_2 = 122,
+ BCU_FE_3DCOMB_3 = 123,
+ BCU_TNR_BUFFER_0 = 124,
+ BCU_TNR_BUFFER_1 = 125,
+ BCU_TNR_BUFFER_2 = 126,
+ BCU_MVAL_BUFFER = 127,
+ BCU_RC_BUFFER_0 = 128,
+ BCU_RC_BUFFER_1 = 129,
+ BCU_RC_BUFFER_2 = 130,
+ BCU_RC_BUFFER_3 = 131,
+ BCU_PIP_BUFFER_0 = 132,
+ BCU_PIP_BUFFER_1 = 133,
+ BCU_PIP_BUFFER_2 = 134,
+ BCU_PIP_BUFFER_3 = 135,
+ BCU_EWARP_BUFFER = 136,
+ BCU_OSD_BUFFER_0 = 137,
+ BCU_OSD_BUFFER_1 = 138,
+ BCU_GLOBAL_BUFFER_0 = 139,
+ BCU_GLOBAL_BUFFER_1 = 140,
+ BCU_MAX = 141
+};
+
+#endif /* _BCU_H */
diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk
new file mode 100644
index 0000000..2a71dad
--- /dev/null
+++ b/board/micronas/vct/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# vct_xxx boards with MIPS 4Kc CPU core
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0x87000000
+endif
diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c
new file mode 100644
index 0000000..b2e86b7
--- /dev/null
+++ b/board/micronas/vct/dcgu.c
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+ u32 enable;
+ union dcgu_clk_en1 en1;
+ union dcgu_clk_en2 en2;
+
+ switch (setup) {
+ case DCGU_SWITCH_ON:
+ enable = 1;
+ break;
+ case DCGU_SWITCH_OFF:
+ enable = 0;
+ break;
+ default:
+ printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
+ setup);
+ return -EINVAL;
+ }
+
+ if (module == DCGU_HW_MODULE_CPU)
+ en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+ else
+ en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+
+ switch (module) {
+ case DCGU_HW_MODULE_MSMC:
+ en1.bits.en_clkmsmc = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_S:
+ en1.bits.en_clkssi_s = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_M:
+ en1.bits.en_clkssi_m = enable;
+ break;
+ case DCGU_HW_MODULE_SMC:
+ en1.bits.en_clksmc = enable;
+ break;
+ case DCGU_HW_MODULE_EBI:
+ en1.bits.en_clkebi = enable;
+ break;
+ case DCGU_HW_MODULE_USB_PLL:
+ en1.bits.en_usbpll = enable;
+ break;
+ case DCGU_HW_MODULE_USB_60:
+ en1.bits.en_clkusb60 = enable;
+ break;
+ case DCGU_HW_MODULE_USB_24:
+ en1.bits.en_clkusb24 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_2:
+ en1.bits.en_clkuart2 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_1:
+ en1.bits.en_clkuart1 = enable;
+ break;
+ case DCGU_HW_MODULE_PERI:
+ en1.bits.en_clkperi20 = enable;
+ break;
+ case DCGU_HW_MODULE_CPU:
+ en2.bits.en_clkcpu = enable;
+ break;
+ case DCGU_HW_MODULE_I2S:
+ en1.bits.en_clk_i2s_dly = enable;
+ break;
+ case DCGU_HW_MODULE_ABP_SCC:
+ en1.bits.en_clk_scc_abp = enable;
+ break;
+ case DCGU_HW_MODULE_SPDIF:
+ en1.bits.en_clk_dtv_spdo = enable;
+ break;
+ case DCGU_HW_MODULE_AD:
+ en1.bits.en_clkad = enable;
+ break;
+ case DCGU_HW_MODULE_MVD:
+ en1.bits.en_clkmvd = enable;
+ break;
+ case DCGU_HW_MODULE_TSD:
+ en1.bits.en_clktsd = enable;
+ break;
+ case DCGU_HW_MODULE_GA:
+ en1.bits.en_clkga = enable;
+ break;
+ case DCGU_HW_MODULE_DVP:
+ en1.bits.en_clkdvp = enable;
+ break;
+ case DCGU_HW_MODULE_MR2:
+ en1.bits.en_clkmr2 = enable;
+ break;
+ case DCGU_HW_MODULE_MR1:
+ en1.bits.en_clkmr1 = enable;
+ break;
+ default:
+ printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+ __LINE__, module);
+ return -EINVAL;
+ }
+
+ /*
+ * The reg_read() following the reg_write() below forces the write to
+ * be really done on the bus.
+ * Otherwise the clock may not be switched on when this API function
+ * returns, which may cause an bus error if a registers of the hardware
+ * module connected to the clock is accessed.
+ */
+ if (module == DCGU_HW_MODULE_CPU) {
+ reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
+ en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+ } else {
+ reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
+ en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+ }
+
+ return 0;
+}
+
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+ union dcgu_reset_unit1 val;
+ u32 enable;
+
+ switch (setup) {
+ case DCGU_SWITCH_ON:
+ enable = 1;
+ break;
+ case DCGU_SWITCH_OFF:
+ enable = 0;
+ break;
+ default:
+ printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
+ setup);
+ return -EINVAL;
+ }
+
+ val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
+ switch (module) {
+ case DCGU_HW_MODULE_MSMC:
+ val.bits.swreset_clkmsmc = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_S:
+ val.bits.swreset_clkssi_s = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_M:
+ val.bits.swreset_clkssi_m = enable;
+ break;
+ case DCGU_HW_MODULE_SMC:
+ val.bits.swreset_clksmc = enable;
+ break;
+ case DCGU_HW_MODULE_EBI:
+ val.bits.swreset_clkebi = enable;
+ break;
+ case DCGU_HW_MODULE_USB_60:
+ val.bits.swreset_clkusb60 = enable;
+ break;
+ case DCGU_HW_MODULE_USB_24:
+ val.bits.swreset_clkusb24 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_2:
+ val.bits.swreset_clkuart2 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_1:
+ val.bits.swreset_clkuart1 = enable;
+ break;
+ case DCGU_HW_MODULE_PWM:
+ val.bits.swreset_pwm = enable;
+ break;
+ case DCGU_HW_MODULE_GPT:
+ val.bits.swreset_gpt = enable;
+ break;
+ case DCGU_HW_MODULE_I2C2:
+ val.bits.swreset_i2c2 = enable;
+ break;
+ case DCGU_HW_MODULE_I2C1:
+ val.bits.swreset_i2c1 = enable;
+ break;
+ case DCGU_HW_MODULE_GPIO2:
+ val.bits.swreset_gpio2 = enable;
+ break;
+ case DCGU_HW_MODULE_GPIO1:
+ val.bits.swreset_gpio1 = enable;
+ break;
+ case DCGU_HW_MODULE_CPU:
+ val.bits.swreset_clkcpu = enable;
+ break;
+ case DCGU_HW_MODULE_I2S:
+ val.bits.swreset_clk_i2s_dly = enable;
+ break;
+ case DCGU_HW_MODULE_ABP_SCC:
+ val.bits.swreset_clk_scc_abp = enable;
+ break;
+ case DCGU_HW_MODULE_SPDIF:
+ val.bits.swreset_clk_dtv_spdo = enable;
+ break;
+ case DCGU_HW_MODULE_AD:
+ val.bits.swreset_clkad = enable;
+ break;
+ case DCGU_HW_MODULE_MVD:
+ val.bits.swreset_clkmvd = enable;
+ break;
+ case DCGU_HW_MODULE_TSD:
+ val.bits.swreset_clktsd = enable;
+ break;
+ case DCGU_HW_MODULE_TSIO:
+ val.bits.swreset_clktsio = enable;
+ break;
+ case DCGU_HW_MODULE_GA:
+ val.bits.swreset_clkga = enable;
+ break;
+ case DCGU_HW_MODULE_MPC:
+ val.bits.swreset_clkmpc = enable;
+ break;
+ case DCGU_HW_MODULE_CVE:
+ val.bits.swreset_clkcve = enable;
+ break;
+ case DCGU_HW_MODULE_DVP:
+ val.bits.swreset_clkdvp = enable;
+ break;
+ case DCGU_HW_MODULE_MR2:
+ val.bits.swreset_clkmr2 = enable;
+ break;
+ case DCGU_HW_MODULE_MR1:
+ val.bits.swreset_clkmr1 = enable;
+ break;
+ default:
+ printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+ __LINE__, module);
+ return -EINVAL;
+ }
+ reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
+
+ return 0;
+}
diff --git a/board/micronas/vct/dcgu.h b/board/micronas/vct/dcgu.h
new file mode 100644
index 0000000..ca129c0
--- /dev/null
+++ b/board/micronas/vct/dcgu.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DCGU_H
+#define _DCGU_H
+
+enum dcgu_switch {
+ DCGU_SWITCH_OFF, /* Switch off */
+ DCGU_SWITCH_ON /* Switch on */
+};
+
+enum dcgu_hw_module {
+ DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */
+
+ DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */
+ DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/
+
+ DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */
+ DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */
+ DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */
+ DCGU_HW_MODULE_DVP, /* Selects dig video processing module */
+ DCGU_HW_MODULE_CVE, /* Selects color video encoder module */
+ DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */
+
+ DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */
+ DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */
+
+ DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */
+ DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */
+
+ DCGU_HW_MODULE_UART_1, /* Selects first UART module */
+ DCGU_HW_MODULE_UART_2, /* Selects second UART module */
+
+ DCGU_HW_MODULE_AD, /* Selects audio decoder module */
+ DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */
+ DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
+ DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */
+
+ DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/
+ DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */
+ DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
+
+ DCGU_HW_MODULE_USBH, /* Selects USB hub module */
+ DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
+ DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */
+ DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */
+
+ DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/
+ DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/
+ DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/
+ DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */
+ DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */
+ DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */
+
+ DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/
+ DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/
+
+ DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
+ DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
+
+ DCGU_HW_MODULE_COM, /* Selects COM unit module */
+ DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
+ DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */
+
+ DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/
+ DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */
+ DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */
+ DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */
+
+ DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */
+ DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */
+ DCGU_HW_MODULE_SRAM, /* Selects SRAM module */
+ DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/
+ DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */
+ DCGU_HW_MODULE_SCC, /* Selects SCC module */
+ DCGU_HW_MODULE_MM, /* Selects Memory Manager module */
+ DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */
+ DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */
+ DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */
+ DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */
+ DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/
+};
+
+union dcgu_clk_en1 {
+ u32 reg;
+ struct {
+ u32 res1:8; /* reserved */
+ u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
+ u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
+ u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
+ u32 en_clksmc:1; /* Enable bit for clksmc (#) */
+ u32 en_clkebi:1; /* Enable bit for clkebi (#) */
+ u32 en_usbpll:1; /* Enable bit for the USB PLL */
+ u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */
+ u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */
+ u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */
+ u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */
+ u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */
+ u32 res2:3; /* reserved */
+ u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */
+ u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */
+ u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */
+ u32 en_clkad:1; /* Enable bit for clkad (#) */
+ u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */
+ u32 en_clktsd:1; /* Enable bit for clktsd (#) */
+ u32 en_clkga:1; /* Enable bit for clkga (#) */
+ u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */
+ u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */
+ u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */
+ } bits;
+};
+
+union dcgu_clk_en2 {
+ u32 reg;
+ struct {
+ u32 res1:31; /* reserved */
+ u32 en_clkcpu:1; /* Enable bit for clkcpu */
+ } bits;
+};
+
+union dcgu_reset_unit1 {
+ u32 reg;
+ struct {
+ u32 res1:1;
+ u32 swreset_clkmsmc:1;
+ u32 swreset_clkssi_s:1;
+ u32 swreset_clkssi_m:1;
+ u32 swreset_clksmc:1;
+ u32 swreset_clkebi:1;
+ u32 swreset_clkusb60:1;
+ u32 swreset_clkusb24:1;
+ u32 swreset_clkuart2:1;
+ u32 swreset_clkuart1:1;
+ u32 swreset_pwm:1;
+ u32 swreset_gpt:1;
+ u32 swreset_i2c2:1;
+ u32 swreset_i2c1:1;
+ u32 swreset_gpio2:1;
+ u32 swreset_gpio1:1;
+ u32 swreset_clkcpu:1;
+ u32 res2:2;
+ u32 swreset_clk_i2s_dly:1;
+ u32 swreset_clk_scc_abp:1;
+ u32 swreset_clk_dtv_spdo:1;
+ u32 swreset_clkad:1;
+ u32 swreset_clkmvd:1;
+ u32 swreset_clktsd:1;
+ u32 swreset_clktsio:1;
+ u32 swreset_clkga:1;
+ u32 swreset_clkmpc:1;
+ u32 swreset_clkcve:1;
+ u32 swreset_clkdvp:1;
+ u32 swreset_clkmr2:1;
+ u32 swreset_clkmr1:1;
+ } bits;
+};
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+
+#endif /* _DCGU_H */
diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c
new file mode 100644
index 0000000..8e93f69
--- /dev/null
+++ b/board/micronas/vct/ebi.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+int ebi_initialize(void)
+{
+#if defined(CONFIG_VCT_NOR)
+ if (ebi_init_nor_flash())
+ return -1;
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+ if (ebi_init_onenand())
+ return -1;
+#endif
+
+#if defined(CONFIG_DRIVER_SMC911X)
+ if (ebi_init_smc911x())
+ return -1;
+#endif
+
+ reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100);
+
+ ebi_wait();
+
+ return 0;
+}
diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h
new file mode 100644
index 0000000..69456bd
--- /dev/null
+++ b/board/micronas/vct/ebi.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EBI__
+#define __EBI__
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+#define EXT_DEVICE_CHANNEL_3 (0x30000000)
+#define EXT_DEVICE_CHANNEL_2 (0x20000000)
+#define EXT_DEVICE_CHANNEL_1 (0x10000000)
+#define EXT_CPU_ACCESS_ACTIVE (0x00000001)
+#define EXT_DMA_ACCESS_ACTIVE (1 << 14)
+#define EXT_CPU_IORDY_SL (0x00000001)
+
+#define EBI_CPU_WRITE (1 << 31)
+#define EBI_CPU_ID_SHIFT (28)
+#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
+#define ADDR_LATCH_ENABLE 0
+#define ADDR_ACTIVATION 4
+#define CHIP_SELECT_START 8
+#define OUTPUT_ENABLE_START 12
+#define WAIT_TIME 28
+#define READ_DURATION 20
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
+#define OUTPUT_ENABLE_END 0
+#define CHIP_SELECT_END 4
+#define ADDR_DEACTIVATION 8
+#define RECOVER_TIME 12
+#define ACK_TIME 20
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
+#define EBI_EXTERNAL_DATA_8 (1 << 8)
+#define EBI_EXT_ADDR_SHIFT (1 << 22)
+#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
+#define EBI_CHIP_SELECT_1 0x2
+#define EBI_CHIP_SELECT_2 0x4
+#define EBI_BUSY_EN_RD (1 << 12)
+#define DIR_ACCESS_WRITE (1 << 20)
+#define DIR_ACCESS_MASK (1 << 20)
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
+#define ADDRESS_INCREMENT_ON 0x0
+#define ADDRESS_INCREMENT_OFF 0x100
+#define QUEUE_LENGTH_1 0x40
+#define QUEUE_LENGTH_2 0x80
+#define QUEUE_LENGTH_3 0xC0
+#define QUEUE_LENGTH_4 0
+#define CPU_TRANSFER_SIZE_32 0
+#define CPU_TRANSFER_SIZE_16 0x10
+#define CPU_TRANSFER_SIZE_8 0x20
+#define READ_ENDIANNESS_ABCD 0
+#define READ_ENDIANNESS_DCBA 0x4
+#define READ_ENDIANNESS_BADC 0x8
+#define READ_ENDIANNESS_CDAB 0xC
+#define WRITE_ENDIANNESS_ABCD 0
+#define WRITE_ENDIANNESS_DCBA 0x1
+#define WRITE_ENDIANNESS_BADC 0x2
+#define WRITE_ENDIANNESS_CDAB 0x3
+
+/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
+#define IORDY_ACTIVELEVEL_HIGH (1 << 14)
+#define ALE_ACTIVELEVEL_HIGH (1 << 8)
+
+/* bits in register EBI_SIG_LEVEL */
+#define IORDY_LEVEL_MASK 1
+
+static inline void ebi_wait(void)
+{
+ while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
+ ; /* wait */
+}
+
+#endif
diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c
new file mode 100644
index 0000000..ae87643
--- /dev/null
+++ b/board/micronas/vct/ebi_nor_flash.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+static u32 ebi_read(u32 addr)
+{
+ addr &= ~0xFC000000;
+
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr);
+ ebi_wait();
+
+ return reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+}
+
+static int ebi_write_u16(u32 addr, u32 data, int fetchIO)
+{
+ u32 val = (data << 16);
+
+ addr &= ~0xFC000000;
+
+ ebi_wait();
+
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+
+ if (fetchIO) {
+ u32 counter = 0;
+ while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) {
+ if (counter++ > 0xFFFFFF)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static u16 ebi_read_u16(u32 addr)
+{
+ return ((ebi_read(addr) >> 16) & 0xFFFF);
+}
+
+static u8 ebi_read_u8(u32 addr)
+{
+ u32 val = ebi_read(addr) >> 16;
+
+ if (addr & 0x1)
+ return val & 0xff;
+ else
+ return (val >> 8) & 0xff;
+}
+
+/*
+ * EBI initialization for NOR FLASH access
+ */
+int ebi_init_nor_flash(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+ reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002);
+ reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+ reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113);
+ reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000);
+ reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113);
+ reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011);
+ reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+
+ return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ */
+void flash_write8(u8 value, void *addr)
+{
+ ebi_write_u16((u32)addr, value, 0);
+}
+
+void flash_write16(u16 value, void *addr)
+{
+ ebi_write_u16((u32)addr, value, 0);
+}
+
+u8 flash_read8(void *addr)
+{
+ return ebi_read_u8((u32)addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ return ebi_read_u16((u32)addr);
+}
+
+u32 flash_read32(void *addr)
+{
+ return ((u32)ebi_read_u16((u32)addr) << 16) |
+ ebi_read_u16((u32)addr + 2);
+}
+
+void *board_flash_read_memcpy(void *dest, const void *src, size_t count)
+{
+ u16 *tmp = (u16 *)dest, *s = (u16 *)src;
+ int i;
+
+ for (i = 0; i < count; i += 2)
+ *tmp++ = flash_read16(s++);
+
+ return dest;
+}
diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c
new file mode 100644
index 0000000..522b88f
--- /dev/null
+++ b/board/micronas/vct/ebi_onenand.c
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include "vct.h"
+
+#define BURST_SIZE_WORDS 4
+
+static u16 ebi_nand_read_word(void __iomem *addr)
+{
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
+ ebi_wait();
+
+ return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
+}
+
+static void ebi_nand_write_word(u16 data, void __iomem * addr)
+{
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
+ ebi_wait();
+}
+
+/*
+ * EBI initialization for OneNAND FLASH access
+ */
+int ebi_init_onenand(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+ reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
+ reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+ reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
+ reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
+
+ reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
+ reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
+ reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
+ reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
+ reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
+ reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
+ reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
+ reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
+
+ reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ /* prepare DMA configuration for EBI */
+ reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
+
+ /* READ only no byte order change, TAG 1 used */
+ reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
+
+ reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
+ reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
+ reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
+ reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
+
+ return 0;
+}
+
+static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u16 *d = dst;
+ u16 *s = (u16 *)src;
+
+ len >>= 1;
+ while (len-- > 0)
+ *d++ = ebi_nand_read_word(s++);
+
+ return ret;
+}
+
+static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u32 *d = (u32 *)dst;
+ u32 s = (u32)src;
+ u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
+ u32 n_blocks = len / bytes_per_block;
+ u32 block = 0;
+ u32 burst_word;
+
+ for (block = 0; block < n_blocks; block++) {
+ /* Trigger read channel 3 */
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
+ /* Poll status to see whether read has finished */
+ ebi_wait();
+
+ /* Squirrel the data away in a safe place */
+ for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
+ *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+ }
+
+ return ret;
+}
+
+static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u16 *d = dst;
+ u16 *s = (u16 *)src;
+
+ len >>= 1;
+ while (len-- > 0)
+ ebi_nand_write_word(*s++, d++);
+
+ return ret;
+}
+
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (ONENAND_CURRENT_BUFFERRAM(this)) {
+ if (area == ONENAND_DATARAM)
+ return mtd->writesize;
+ if (area == ONENAND_SPARERAM)
+ return mtd->oobsize;
+ }
+
+ return 0;
+}
+
+static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ if (count < 4)
+ memcpy_16_from_onenand(buffer, bufferram + offset, count);
+ else
+ memcpy_32_from_onenand(buffer, bufferram + offset, count);
+
+ return 0;
+}
+
+static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ const unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy_16_to_onenand(bufferram + offset, buffer, count);
+
+ return 0;
+}
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *chip = mtd->priv;
+
+ /*
+ * Insert board specific OneNAND access functions
+ */
+ chip->read_word = ebi_nand_read_word;
+ chip->write_word = ebi_nand_write_word;
+
+ chip->read_bufferram = ebi_read_bufferram;
+ chip->read_spareram = ebi_read_bufferram;
+ chip->write_bufferram = ebi_write_bufferram;
+}
diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c
new file mode 100644
index 0000000..e1b67a0
--- /dev/null
+++ b/board/micronas/vct/ebi_smc911x.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * EBI initialization for SMC911x access
+ */
+int ebi_init_smc911x(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020);
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+
+ reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100);
+ reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111);
+
+ reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100);
+ reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110);
+
+ return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/net/smc911x.c
+ */
+u32 smc911x_reg_read(u32 addr)
+{
+ volatile u32 data;
+
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+ ebi_wait();
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+ ebi_wait();
+ data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+ return (data);
+}
+
+void smc911x_reg_write(u32 addr, u32 data)
+{
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+}
+
+void pkt_data_push(u32 addr, u32 data)
+{
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+
+ return;
+}
+
+u32 pkt_data_pull(u32 addr)
+{
+ volatile u32 data;
+
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+ ebi_wait();
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+ ebi_wait();
+ data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+ return data;
+}
diff --git a/board/micronas/vct/ehci.c b/board/micronas/vct/ehci.c
new file mode 100644
index 0000000..d04bdce
--- /dev/null
+++ b/board/micronas/vct/ehci.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include "vct.h"
+
+int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
+{
+ int retval;
+ u32 val;
+ u32 addr;
+
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
+
+ /* Wait until (DCGU_USBPHY_STAT == 7) */
+ addr = DCGU_USBPHY_STAT(DCGU_BASE);
+ val = reg_read(addr);
+ while (val != 7)
+ val = reg_read(addr);
+
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
+
+ retval = scc_reset(SCC_USB_RW, 0);
+ if (retval) {
+ printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
+ return retval;
+ } else {
+ retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
+ if (retval) {
+ printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
+ retval);
+ return retval;
+ }
+ }
+
+ if (!retval) {
+ /*
+ * For the AGU bypass, where the SCC client provides full
+ * physical address
+ */
+ scc_set_usb_address_generation_mode(1);
+ scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+ USE_NO_FH, DMA_READ, 0);
+ scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+ USE_NO_FH, DMA_WRITE, 0);
+ scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+ USE_NO_FH, DMA_WRITE, 0);
+ scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+ USE_NO_FH, DMA_READ, 0);
+
+ /* Enable memory interface */
+ scc_enable(SCC_USB_RW, 1);
+
+ /* Start (start_cmd=0) DMAs */
+ scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
+ scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
+ } else {
+ printf("Cannot configure USB memory channel.\n");
+ printf("USB can not access RAM. SCC configuration failed.\n");
+ return retval;
+ }
+
+ /* Wait a short while */
+ udelay(300000);
+
+ reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+ /* Set EHCI structures and DATA in RAM */
+ reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
+ /* Set USBMODE to bigendian and set host mode */
+ reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
+
+ /*
+ * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
+ * 512 byte USB transfers on the bulk pipe to work properly.
+ * Set USBH_BURSTSIZE to 0x00001c1c
+ */
+ reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+ /* Insert access register addresses */
+ *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
+ *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
+
+ return 0;
+}
diff --git a/board/micronas/vct/gpio.c b/board/micronas/vct/gpio.c
new file mode 100644
index 0000000..2c113be
--- /dev/null
+++ b/board/micronas/vct/gpio.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * Find out to which of the 2 gpio modules the pin specified in the
+ * argument belongs:
+ * GPIO_MODULE yields 0 for pins 0 to 31,
+ * 1 for pins 32 to 63
+ */
+#define GPIO_MODULE(pin) ((pin) >> 5)
+
+/*
+ * Bit position within a 32-bit peripheral register (where every
+ * bit is one bitslice)
+ */
+#define MASK(pin) (1 << ((pin) & 0x1F))
+#define BASE_ADDR(mod) module_base[mod]
+
+/*
+ * Lookup table for transforming gpio module number 0 to 2 to
+ * address offsets
+ */
+static u32 module_base[] = {
+ GPIO1_BASE,
+ GPIO2_BASE
+};
+
+static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
+{
+ reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
+}
+
+int vct_gpio_dir(int pin, int dir)
+{
+ u32 gpio_base;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+ if (dir == 0)
+ clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
+ else
+ clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
+
+ return 0;
+}
+
+void vct_gpio_set(int pin, int val)
+{
+ u32 gpio_base;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+ if (val == 0)
+ clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
+ else
+ clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
+}
+
+int vct_gpio_get(int pin)
+{
+ u32 gpio_base;
+ u32 value;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+ value = reg_read(GPIO_EXT_PORTA(gpio_base));
+
+ return ((value & MASK(pin)) ? 1 : 0);
+}
diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
new file mode 100644
index 0000000..0368183
--- /dev/null
+++ b/board/micronas/vct/scc.c
@@ -0,0 +1,669 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+/*
+ * List of statically defined buffers per SCC.
+ * The first entry in the table is the number of fixed buffers
+ * followed by the list of buffer IDs
+ */
+static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_5[] = { 3, 127, 139, 140 };
+static u32 buffer_list_6[] = { 3, 127, 139, 140 };
+static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 };
+static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 };
+
+/** Issue#7674 (new) - DP/DVP buffer assignment */
+static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 };
+static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 };
+static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 };
+static u32 buffer_list_19[] = { 3, 112, 139, 140 };
+static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 79, 80, 81, 82, 83, 84, 85, 86, 139, 140 };
+static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+ 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78, 139, 140 };
+static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 88, 89, 139, 140 };
+static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 };
+static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
+ 100, 101, 102, 103, 104, 105, 139, 140 };
+static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 };
+static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 };
+static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 };
+static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 };
+static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117,
+ 139, 140 };
+static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+ 115, 116, 117, 139, 140 };
+static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+ 115, 116, 117, 139, 140 };
+static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 87, 139, 140 };
+static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 87, 139, 140 };
+static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 118, 119, 139, 140 };
+static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+ 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 118, 119, 139, 140 };
+static u32 buffer_list_40[] = { 0 };
+
+/*
+ * List of statically defined vcid.csize values.
+ * The first entry in the table is the number of possible csize values
+ * followed by the list of data path values in bits.
+ */
+static u32 csize_list_0[] = { 2, 0, 1 };
+static u32 csize_list_1[] = { 2, 0, 1 };
+static u32 csize_list_2[] = { 1, 1 };
+static u32 csize_list_3[] = { 1, 1 };
+static u32 csize_list_4[] = { 1, 1 };
+static u32 csize_list_5[] = { 1, 0 };
+static u32 csize_list_6[] = { 1, 0 };
+static u32 csize_list_7[] = { 1, 1 };
+static u32 csize_list_8[] = { 1, 1 };
+static u32 csize_list_9[] = { 1, 1 };
+static u32 csize_list_10[] = { 1, 1 };
+static u32 csize_list_11[] = { 1, 1 };
+static u32 csize_list_12[] = { 1, 1 };
+static u32 csize_list_13[] = { 1, 1 };
+static u32 csize_list_14[] = { 1, 2 };
+static u32 csize_list_15[] = { 1, 4 };
+static u32 csize_list_16[] = { 3, 0, 1, 2 };
+static u32 csize_list_17[] = { 3, 0, 1, 2 };
+static u32 csize_list_18[] = { 3, 0, 1, 2 };
+static u32 csize_list_19[] = { 1, 2 };
+static u32 csize_list_20[] = { 1, 0 };
+static u32 csize_list_21[] = { 1, 0 };
+static u32 csize_list_22[] = { 1, 2 };
+static u32 csize_list_23[] = { 1, 3 };
+static u32 csize_list_24[] = { 1, 3 };
+static u32 csize_list_25[] = { 1, 3 };
+static u32 csize_list_26[] = { 1, 0 };
+static u32 csize_list_27[] = { 1, 0 };
+static u32 csize_list_28[] = { 1, 0 };
+static u32 csize_list_29[] = { 1, 0 };
+static u32 csize_list_30[] = { 1, 2 };
+static u32 csize_list_31[] = { 1, 2 };
+static u32 csize_list_32[] = { 1, 2 };
+static u32 csize_list_33[] = { 1, 2 };
+static u32 csize_list_34[] = { 1, 2 };
+static u32 csize_list_35[] = { 1, 2 };
+static u32 csize_list_36[] = { 1, 2 };
+static u32 csize_list_37[] = { 2, 0, 1 };
+static u32 csize_list_38[] = { 1, 2 };
+static u32 csize_list_39[] = { 1, 3 };
+static u32 csize_list_40[] = { 1, 3 };
+
+/*
+ * SCC_Configuration table
+ */
+static const struct scc_descriptor scc_descriptor_table[] = {
+/* scn scc_name profile SCC scc_id mci_id rd wr m p fh si cfg sta */
+ {"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1,
+ buffer_list_0, csize_list_0},
+ {"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0,
+ 1, buffer_list_1, csize_list_1},
+ {"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1,
+ buffer_list_2, csize_list_2},
+ {"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3,
+ 0, 1, buffer_list_3, csize_list_3},
+ {"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4,
+ 0, 1, buffer_list_4, csize_list_4},
+ {"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1,
+ buffer_list_5, csize_list_5},
+ {"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1,
+ buffer_list_6, csize_list_6},
+ {"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1,
+ buffer_list_7, csize_list_7},
+ {"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0,
+ 1, buffer_list_8, csize_list_8},
+ {"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0,
+ 1, buffer_list_9, csize_list_9},
+ {"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10,
+ 0, 1, buffer_list_10, csize_list_10},
+ {"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11,
+ 0, 1, buffer_list_11, csize_list_11},
+ {"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0,
+ 1, buffer_list_12, csize_list_12},
+ {"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13,
+ 0, 1, buffer_list_13, csize_list_13},
+ {"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0,
+ 1, buffer_list_14, csize_list_14},
+ {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0,
+ buffer_list_15, csize_list_15},
+ {"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0,
+ 1, buffer_list_16, csize_list_16},
+ {"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16,
+ 0, 1, buffer_list_17, csize_list_17},
+ {"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0,
+ 1, buffer_list_18, csize_list_18},
+ {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0,
+ 0, buffer_list_19, csize_list_19},
+ {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0,
+ buffer_list_20, csize_list_20},
+ {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0,
+ buffer_list_21, csize_list_21},
+ {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0,
+ buffer_list_22, csize_list_22},
+ {"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0,
+ 0, buffer_list_23, csize_list_23},
+ {"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0,
+ buffer_list_24, csize_list_24},
+ {"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1,
+ 0, 0, buffer_list_25, csize_list_25},
+ {"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18,
+ 0, 1, buffer_list_26, csize_list_26},
+ {"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19,
+ 0, 1, buffer_list_27, csize_list_27},
+ {"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20,
+ 0, 1, buffer_list_28, csize_list_28},
+ {"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21,
+ 0, 1, buffer_list_29, csize_list_29},
+ {"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1,
+ buffer_list_30, csize_list_30},
+ {"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1,
+ 1, buffer_list_31, csize_list_31},
+ {"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1,
+ 1, buffer_list_32, csize_list_32},
+ {"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0,
+ buffer_list_33, csize_list_33},
+ {"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0,
+ buffer_list_34, csize_list_34},
+ {"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0,
+ buffer_list_35, csize_list_35},
+ {"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0,
+ buffer_list_36, csize_list_36},
+ {"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0,
+ buffer_list_37, csize_list_37},
+ {"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0,
+ buffer_list_38, csize_list_38},
+ {"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0,
+ 0, buffer_list_39, csize_list_39},
+ {"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1,
+ 0, 0, buffer_list_40, csize_list_40},
+};
+
+/* DMA state structures for read and write channels for each SCC */
+
+static struct scc_dma_state scc_state_rd_0[] = { {-1} };
+static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_1[] = { {-1} };
+static struct scc_dma_state scc_state_rd_2[] = { {-1} };
+static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_3[] = { {-1} };
+static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_4[] = { {-1} };
+static struct scc_dma_state scc_state_rd_5[] = { {-1} };
+static struct scc_dma_state scc_state_wr_5[] = { {0} };
+static struct scc_dma_state scc_state_rd_6[] = { {0} };
+static struct scc_dma_state scc_state_wr_6[] = { {-1} };
+static struct scc_dma_state scc_state_rd_7[] = { {-1} };
+static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_8[] = { {-1} };
+static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, };
+static struct scc_dma_state scc_state_wr_9[] = { {-1} };
+static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_10[] = { {-1} };
+static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_11[] = { {-1} };
+static struct scc_dma_state scc_state_rd_12[] = { {-1} };
+static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_13[] = { {-1} };
+static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_14[] = { {-1} };
+static struct scc_dma_state scc_state_rd_15[] = { {0} };
+static struct scc_dma_state scc_state_wr_15[] = { {0} };
+static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_16[] = { {-1} };
+static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_17[] = { {-1} };
+static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_18[] = { {-1} };
+static struct scc_dma_state scc_state_rd_19[] = { {0} };
+static struct scc_dma_state scc_state_wr_19[] = { {-1} };
+static struct scc_dma_state scc_state_rd_20[] = { {-1} };
+static struct scc_dma_state scc_state_wr_20[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_21[] = { {-1} };
+static struct scc_dma_state scc_state_rd_22[] = { {-1} };
+static struct scc_dma_state scc_state_wr_22[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_24[] = { {-1} };
+static struct scc_dma_state scc_state_rd_25[] = { {-1} };
+static struct scc_dma_state scc_state_wr_25[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0} };
+static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_26[] = { {-1} };
+static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_27[] = { {-1} };
+static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_28[] = { {-1} };
+static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_29[] = { {-1} };
+static struct scc_dma_state scc_state_rd_30[] = { {-1} };
+static struct scc_dma_state scc_state_wr_30[] = { {0} };
+static struct scc_dma_state scc_state_rd_31[] = { {0} };
+static struct scc_dma_state scc_state_wr_31[] = { {-1} };
+static struct scc_dma_state scc_state_rd_32[] = { {0} };
+static struct scc_dma_state scc_state_wr_32[] = { {-1} };
+static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_33[] = { {-1} };
+static struct scc_dma_state scc_state_rd_34[] = { {-1} };
+static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_35[] = { {-1} };
+static struct scc_dma_state scc_state_rd_36[] = { {-1} };
+static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_38[] = { {0} };
+static struct scc_dma_state scc_state_wr_38[] = { {0} };
+static struct scc_dma_state scc_state_rd_39[] = { {0} };
+static struct scc_dma_state scc_state_wr_39[] = { {0} };
+static struct scc_dma_state scc_state_rd_40[] = { {-1} };
+static struct scc_dma_state scc_state_wr_40[] = { {-1} };
+
+/* DMA state references to access from the driver */
+static struct scc_dma_state *scc_state_rd[] = {
+ scc_state_rd_0,
+ scc_state_rd_1,
+ scc_state_rd_2,
+ scc_state_rd_3,
+ scc_state_rd_4,
+ scc_state_rd_5,
+ scc_state_rd_6,
+ scc_state_rd_7,
+ scc_state_rd_8,
+ scc_state_rd_9,
+ scc_state_rd_10,
+ scc_state_rd_11,
+ scc_state_rd_12,
+ scc_state_rd_13,
+ scc_state_rd_14,
+ scc_state_rd_15,
+ scc_state_rd_16,
+ scc_state_rd_17,
+ scc_state_rd_18,
+ scc_state_rd_19,
+ scc_state_rd_20,
+ scc_state_rd_21,
+ scc_state_rd_22,
+ scc_state_rd_23,
+ scc_state_rd_24,
+ scc_state_rd_25,
+ scc_state_rd_26,
+ scc_state_rd_27,
+ scc_state_rd_28,
+ scc_state_rd_29,
+ scc_state_rd_30,
+ scc_state_rd_31,
+ scc_state_rd_32,
+ scc_state_rd_33,
+ scc_state_rd_34,
+ scc_state_rd_35,
+ scc_state_rd_36,
+ scc_state_rd_37,
+ scc_state_rd_38,
+ scc_state_rd_39,
+ scc_state_rd_40,
+};
+
+static struct scc_dma_state *scc_state_wr[] = {
+ scc_state_wr_0,
+ scc_state_wr_1,
+ scc_state_wr_2,
+ scc_state_wr_3,
+ scc_state_wr_4,
+ scc_state_wr_5,
+ scc_state_wr_6,
+ scc_state_wr_7,
+ scc_state_wr_8,
+ scc_state_wr_9,
+ scc_state_wr_10,
+ scc_state_wr_11,
+ scc_state_wr_12,
+ scc_state_wr_13,
+ scc_state_wr_14,
+ scc_state_wr_15,
+ scc_state_wr_16,
+ scc_state_wr_17,
+ scc_state_wr_18,
+ scc_state_wr_19,
+ scc_state_wr_20,
+ scc_state_wr_21,
+ scc_state_wr_22,
+ scc_state_wr_23,
+ scc_state_wr_24,
+ scc_state_wr_25,
+ scc_state_wr_26,
+ scc_state_wr_27,
+ scc_state_wr_28,
+ scc_state_wr_29,
+ scc_state_wr_30,
+ scc_state_wr_31,
+ scc_state_wr_32,
+ scc_state_wr_33,
+ scc_state_wr_34,
+ scc_state_wr_35,
+ scc_state_wr_36,
+ scc_state_wr_37,
+ scc_state_wr_38,
+ scc_state_wr_39,
+ scc_state_wr_40,
+};
+
+static u32 scc_takeover_mode = SCC_TO_IMMEDIATE;
+
+/* Change mode of the SPDMA for given direction */
+static u32 scc_agu_mode_sp = AGU_BYPASS;
+
+/* Change mode of the USB for given direction */
+static u32 scc_agu_mode_usb = AGU_BYPASS;
+
+static union scc_softwareconfiguration scc_software_configuration[SCC_MAX];
+
+static u32 dma_fsm[4][4] = {
+ /* DMA_CMD_RESET DMA_CMD_SETUP DMA_CMD_START DMA_CMD_STOP */
+ /* DMA_STATE_RESET */
+ {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR},
+ /* DMA_STATE_SETUP */
+ {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP},
+ /* DMA_STATE_START */
+ {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP},
+ /* DMA_STATE_ERROR */
+ {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR},
+};
+
+static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd)
+{
+ dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd];
+ dma_state->dma_cmd = cmd;
+}
+
+static void dma_state_process_dma_command(struct scc_dma_state *dma_state,
+ u32 dma_cmd)
+{
+ dma_state->dma_cmd = dma_cmd;
+ switch (dma_cmd) {
+ case DMA_START:
+ case DMA_START_FH_RESET:
+ dma_state_process(dma_state, DMA_CMD_START);
+ break;
+ case DMA_STOP:
+ dma_state_process(dma_state, DMA_CMD_STOP);
+ break;
+ default:
+ break;
+ }
+}
+
+static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs)
+{
+ union scc_cmd dma_cmd;
+
+ dma_cmd.reg = 0;
+
+ /* Prepare the takeover for the DMA channel */
+ dma_cmd.bits.action = DMA_TAKEOVER;
+ dma_cmd.bits.id = dma_id;
+ dma_cmd.bits.rid = TO_DMA_CFG; /* this is DMA_CFG register takeover */
+ if (drs == DMA_WRITE)
+ dma_cmd.bits.drs = DMA_WRITE;
+
+ reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+}
+
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs)
+{
+ union scc_cmd dma_cmd;
+ struct scc_dma_state *dma_state;
+
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ dma_cmd.reg = 0;
+
+ /* Prepare the takeover for the DMA channel */
+ dma_cmd.bits.action = cmd;
+ dma_cmd.bits.id = dma_id;
+ if (drs == DMA_WRITE) {
+ dma_cmd.bits.drs = DMA_WRITE;
+ dma_state = &scc_state_wr[id][dma_id];
+ } else {
+ dma_state = &scc_state_rd[id][dma_id];
+ }
+
+ dma_state->scc_id = id;
+ dma_state->dma_id = dma_id;
+ dma_state_process_dma_command(dma_state, cmd);
+
+ reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+
+ return 0;
+}
+
+int scc_set_usb_address_generation_mode(u32 agu_mode)
+{
+ if (AGU_ACTIVE == agu_mode) {
+ /* Ensure both DMAs are stopped */
+ scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE);
+ scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ);
+ } else {
+ agu_mode = AGU_BYPASS;
+ }
+
+ scc_agu_mode_usb = agu_mode;
+
+ return 0;
+}
+
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+ u32 type, u32 fh_mode, u32 drs, u32 dma_id)
+{
+ struct scc_dma_state *dma_state;
+ int return_value = 0;
+ union scc_dma_cfg dma_cfg;
+ u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+ u32 tag_count, t, t_valid;
+
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ /* if the register is only configured by hw, cannot write! */
+ if (1 == scc_descriptor_table[id].hw_dma_cfg)
+ return -EACCES;
+
+ if (DMA_WRITE == drs) {
+ if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr)
+ return -EINVAL;
+ dma_state = &scc_state_wr[id][dma_id];
+ } else {
+ if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd)
+ return -EINVAL;
+ dma_state = &scc_state_rd[id][dma_id];
+ }
+
+ /* Compose the DMA configuration register */
+ tag_count = buffer_tag_list[0];
+ t_valid = 0;
+ for (t = 1; t <= tag_count; t++) {
+ if (buffer_tag == buffer_tag_list[t]) {
+ /* Tag found - validate */
+ t_valid = 1;
+ break;
+ }
+ }
+
+ if (!t_valid)
+ return -EACCES;
+
+ /*
+ * Read the register first -- two functions write into the register
+ * it does not make sense to read the DMA config back, because there
+ * are two register configuration sets (drs)
+ */
+ dma_cfg.reg = 0;
+ dma_cfg.bits.buffer_id = buffer_tag;
+ dma_state_process(dma_state, DMA_CMD_SETUP);
+
+ /*
+ * This is Packet CFG set select - usable for TSIO, EBI and those SCCs
+ * which habe 2 packet configs
+ */
+ dma_cfg.bits.packet_cfg_id =
+ scc_software_configuration[id].bits.packet_select;
+
+ if (type == DMA_CYCLIC)
+ dma_cfg.bits.buffer_type = 1;
+ else
+ dma_cfg.bits.buffer_type = 0;
+
+ if (fh_mode == USE_FH)
+ dma_cfg.bits.fh_mode = 1;
+ else
+ dma_cfg.bits.fh_mode = 0;
+
+ if (id == SCC_CPU1_SPDMA_RW)
+ dma_cfg.bits.agu_mode = scc_agu_mode_sp;
+
+ if (id == SCC_USB_RW)
+ dma_cfg.bits.agu_mode = scc_agu_mode_usb;
+
+ reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address),
+ dma_cfg.reg);
+
+ /* The DMA_CFG needs a takeover! */
+ if (SCC_TO_IMMEDIATE == scc_takeover_mode)
+ scc_takeover_dma(id, dma_id, drs);
+
+ /* if (buffer_tag is not used) */
+ dma_state->buffer_tag = buffer_tag;
+
+ dma_state->scc_id = id;
+ dma_state->dma_id = dma_id;
+
+ return return_value;
+}
+
+int scc_enable(enum scc_id id, u32 value)
+{
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ if (value == 0) {
+ scc_software_configuration[id].bits.enable_status = 0;
+ } else {
+ value = 1;
+ scc_software_configuration[id].bits.enable_status = 1;
+ }
+ reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value);
+
+ return 0;
+}
+
+static inline void ehb(void)
+{
+ __asm__ __volatile__(
+ " .set mips32r2 \n"
+ " ehb \n"
+ " .set mips0 \n");
+}
+
+int scc_reset(enum scc_id id, u32 value)
+{
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ /* Invert value to the strait logic from the negative hardware logic */
+ if (value == 0)
+ value = 1;
+ else
+ value = 0;
+
+ /* Write the value to the register */
+ reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value);
+
+ /* sync flush */
+ asm("sync"); /* request bus write queue flush */
+ ehb(); /* wait until previous bus commit instr has finished */
+ asm("nop"); /* wait for flush to occur */
+ asm("nop"); /* wait for flush to occur */
+
+ udelay(100);
+
+ return 0;
+}
diff --git a/board/micronas/vct/scc.h b/board/micronas/vct/scc.h
new file mode 100644
index 0000000..8415167
--- /dev/null
+++ b/board/micronas/vct/scc.h
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCC_H
+#define _SCC_H
+
+#define DMA_READ 0 /* SCC read DMA */
+#define DMA_WRITE 1 /* SCC write DMA */
+
+#define DMA_LINEAR 0 /* DMA linear buffer access method */
+#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
+
+#define DMA_START 0 /* DMA command - start DMA */
+#define DMA_STOP 1 /* DMA command - stop DMA */
+#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
+#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
+
+#define AGU_ACTIVE 0 /* enable AGU address calculation */
+#define AGU_BYPASS 1 /* set AGU to bypass mode */
+
+#define USE_NO_FH 0 /* order the DMA to not use FH */
+#define USE_FH 1 /* order the DMA to work with FH*/
+
+#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */
+#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
+
+#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
+#define TO_DMA_CFG 2 /* takeover command for the DMA config*/
+
+#define DMA_CMD_RESET 0
+#define DMA_CMD_SETUP 1
+#define DMA_CMD_START 2
+#define DMA_CMD_STOP 3
+
+#define DMA_STATE_RESET 0
+#define DMA_STATE_SETUP 1
+#define DMA_STATE_START 2
+#define DMA_STATE_ERROR 3
+
+#define SRMD 0
+#define STRM_D 1
+#define STRM_P 2
+
+/*
+ * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
+ */
+#define RESET_TIME 2 /* cycle calc see in SCC_Reset */
+
+struct scc_descriptor {
+ char *pu_name; /* PU identifier */
+ char *scc_instance; /* SCC Name */
+ u32 profile; /* SCC VCI_D profile */
+
+ u32 base_address; /* base address of the SCC unit reg shell*/
+
+ /* SCS Interconnect configuration */
+ u32 p_scc_id; /* instance number of SCC unit */
+ u32 p_mci_id; /* memory channel ID */
+
+ /* DMA Registers configuration */
+ u32 p_dma_channels_rd; /* Number of Read DMA channels */
+ u32 p_dma_channels_wr; /* Number of Write DMA channels */
+
+ u32 p_dma_packet_desc; /* Number of packet descriptors */
+ u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */
+
+ int use_fh; /* the flag tells if SCC uses an FH */
+
+ int p_si2ocp_id; /* instance number of SI2OCP unit */
+ int hw_dma_cfg; /* HW or SW DMA config flag */
+ int hw_dma_start; /* HW or SW DMA start/stop flag */
+
+ u32 *buffer_tag_list; /* list of the buffer tags available */
+ u32 *csize_list; /* list of the valid CSIZE values */
+};
+
+struct scc_dma_state {
+ u32 scc_id:8; /* SCC id */
+ u32 dma_id:8; /* DMA id, used for match with array idx*/
+ u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */
+ u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
+ u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
+ u32 dma_cmd:4; /* last executed command on this DMA */
+};
+
+union scc_cmd {
+ u32 reg;
+ struct {
+ u32 res1:19; /* reserved */
+ u32 drs:1; /* DMA Register Set */
+ u32 rid:2; /* Register Identifier */
+ u32 id:6; /* DMA Identifier */
+ u32 action:4; /* DMA Command encoding */
+ } bits;
+};
+
+union scc_dma_cfg {
+ u32 reg;
+ struct {
+ u32 res1:17; /* reserved */
+ u32 agu_mode:1; /* AGU Mode */
+ u32 res2:1; /* reserved */
+ u32 fh_mode:1; /* Fifo Handler */
+ u32 buffer_type:1; /* Defines type of mem buffers */
+ u32 mci_cfg_id:1; /* MCI_CFG register selector */
+ u32 packet_cfg_id:1; /* PACKET_CFG register selector */
+ u32 buffer_id:8; /* DMA Buffer Identifier */
+ } bits;
+};
+
+union scc_debug {
+ u32 reg;
+ struct {
+ u32 res1:20; /* reserved */
+ u32 arg:8; /* SCC Debug Command Argument (#) */
+ u32 cmd:4; /* SCC Debug Command Register */
+ } bits;
+};
+
+union scc_softwareconfiguration {
+ u32 reg;
+ struct {
+ u32 res1:28; /* reserved */
+ u32 clock_status:1; /* clock on/off */
+ u32 packet_select:1; /* active SCC packet id */
+ u32 enable_status:1; /* enabled [1/0] */
+ u32 active_status:1; /* 1=active 0=reset */
+ } bits;
+};
+
+/*
+ * System on Chip Channel ID
+ */
+enum scc_id {
+ SCC_NULL = -1, /* illegal SCC identifier */
+ SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
+ SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
+ SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
+ SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
+ SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
+ SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
+ SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
+ SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
+ SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
+ SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
+ SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
+ SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
+ SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
+ SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
+ SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
+ SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
+ SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
+ SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
+ SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
+ SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
+ SCC_TSIO_WR, /* SCC_TSIO Write channel */
+ SCC_TSIO_RD, /* SCC_TSIO Read channel */
+ SCC_TSD_WR, /* SCC_TSD Write channel */
+ SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
+ SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
+ SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
+ SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
+ SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
+ SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
+ SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
+ SCC_GA_WR, /* SCC_GA Write channel */
+ SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
+ SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
+ SCC_AD_RD, /* SCC_AD Read channel */
+ SCC_AD_WR, /* SCC_AD Write channel */
+ SCC_ABP_RD, /* SCC_ABP Read channel */
+ SCC_ABP_WR, /* SCC_ABP Write channel */
+ SCC_EBI_RW, /* SCC_EBI Read/Write channel */
+ SCC_USB_RW, /* SCC_USB Read/Write channel */
+ SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
+ SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */
+ SCC_MAX /* maximum limit on the SCC id */
+};
+
+int scc_set_usb_address_generation_mode(u32 agu_mode);
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+ u32 type, u32 fh_mode, u32 drs, u32 dma_id);
+int scc_enable(enum scc_id id, u32 value);
+int scc_reset(enum scc_id id, u32 value);
+
+#endif /* _SCC_H */
diff --git a/board/micronas/vct/smc_eeprom.c b/board/micronas/vct/smc_eeprom.c
new file mode 100644
index 0000000..2bc7ad4
--- /dev/null
+++ b/board/micronas/vct/smc_eeprom.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright 2005, Seagate Technology LLC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+
+#include "vct.h"
+
+#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE
+#define BYTE_TEST (SMSC9118_BASE + 0x64)
+#define GPIO_CFG (SMSC9118_BASE + 0x88)
+#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4)
+#define MAC_CSR_CMD_CSR_BUSY (0x80000000)
+#define MAC_CSR_CMD_RNW (0x40000000)
+#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \
+ (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW))
+#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \
+ (MAC_CSR_CMD_CSR_BUSY))
+#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8)
+#define E2P_CMD (SMSC9118_BASE + 0xB0)
+#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */
+#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */
+#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */
+#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */
+#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */
+#define E2P_DATA (SMSC9118_BASE + 0xB4)
+
+#define MAC_ADDRH (0x2)
+#define MAC_ADDRL (0x3)
+
+#define MAC_TIMEOUT 200
+
+#define HIBYTE(word) ((u8)(((u16)(word)) >> 8))
+#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU))
+#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16))
+#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL))
+
+static int mac_busy(int req_to)
+{
+ int timeout = req_to;
+
+ while (timeout--) {
+ if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
+ goto done;
+ }
+ return 1; /* Timeout */
+
+done:
+ return 0; /* No timeout */
+}
+
+static ulong get_mac_reg(int reg)
+{
+ ulong reg_val = 0xffffffff;
+
+ if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) {
+ printf("get_mac_reg: previous command not complete\n");
+ goto done;
+ }
+
+ smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg));
+ udelay(10000);
+
+ if (mac_busy(MAC_TIMEOUT) == 1) {
+ printf("get_mac_reg: timeout waiting for response from MAC\n");
+ goto done;
+ }
+
+ reg_val = smc911x_reg_read(MAC_CSR_DATA);
+
+done:
+ return (reg_val);
+}
+
+static ulong eeprom_enable_access(void)
+{
+ ulong gpio;
+
+ gpio = smc911x_reg_read(GPIO_CFG);
+ debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio,
+ (gpio & 0xFF0FFFFFUL));
+
+ smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL));
+ return gpio;
+}
+
+static void eeprom_disable_access(ulong gpio)
+{
+ debug("%s: gpio= 0x%08lx\n", __func__, gpio);
+ smc911x_reg_write(GPIO_CFG, gpio);
+}
+
+static int eeprom_is_mac_address_loaded(void)
+{
+ int ret;
+
+ ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_;
+ debug("%s: ret = %x\n", __func__, ret);
+
+ return ret;
+}
+
+static int eeprom_read_location(unchar address, u8 *data)
+{
+ ulong timeout = 100000;
+ ulong temp = 0;
+
+ if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ |
+ ((ulong) address)));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout\n");
+ return 0;
+ }
+ (*data) = (unchar) (smc911x_reg_read(E2P_DATA));
+ debug("%s: ret = %x\n", __func__, (*data));
+
+ return 1;
+}
+
+static int eeprom_enable_erase_and_write(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[1]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_disable_erase_and_write(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[2]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_write_location(unchar address, unchar data)
+{
+ ulong timeout = 100000;
+
+ debug("%s: address: %x data = %x\n", __func__, address, data);
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_DATA, ((ulong) data));
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ |
+ ((ulong) address)));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[3]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_erase_all(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[4]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_reload(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return -1;
+ }
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0)
+ return 0;
+
+ return 1;
+}
+
+static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32)
+{
+ int result = 0;
+
+ debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32);
+
+ if (!eeprom_enable_erase_and_write())
+ goto DONE;
+ if (!eeprom_erase_all())
+ goto DONE;
+ if (!eeprom_write_location(0, 0xA5))
+ goto DONE;
+ if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16))))
+ goto DONE;
+ if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16))))
+ goto DONE;
+ if (!eeprom_disable_erase_and_write())
+ goto DONE;
+
+ result = 1;
+
+DONE:
+ return result;
+}
+
+static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unchar data = 0, index = 0;
+ ulong gpio_old_val;
+
+ gpio_old_val = eeprom_enable_access();
+
+ printf("EEPROM content: \n");
+ for (index = 0; index < 8; index++) {
+ if (eeprom_read_location(index, &data))
+ printf("%02x ", data);
+ else
+ printf("FAILED");
+ }
+
+ eeprom_disable_access(gpio_old_val);
+ printf("\n");
+
+ return 0;
+}
+
+static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ eeprom_erase_all();
+
+ return 0;
+}
+
+static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong hi16, lo32;
+ unchar ethaddr[6], i;
+ ulong gpio;
+ char *tmp, *end;
+
+ tmp = argv[1];
+ for (i = 0; i < 6; i++) {
+ ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
+
+ hi16 = (ethaddr[5] << 8) | (ethaddr[4]);
+ lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) |
+ (ethaddr[1] << 8) | (ethaddr[0]);
+
+ gpio = eeprom_enable_access();
+
+ eeprom_save_mac_address(hi16, lo32);
+
+ eeprom_reload();
+
+ /* Check new values */
+ if (eeprom_is_mac_address_loaded()) {
+ ulong mac_hi16, mac_lo32;
+
+ mac_hi16 = get_mac_reg(MAC_ADDRH);
+ mac_lo32 = get_mac_reg(MAC_ADDRL);
+ printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32);
+ } else {
+ printf("Address is not reloaded \n");
+ }
+ eeprom_disable_access(gpio);
+
+ return 0;
+}
+
+U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all,
+ "smcee - Erase content of SMC EEPROM\n",);
+
+U_BOOT_CMD(smced, 1, 0, do_eeprom_dump,
+ "smced - Dump content of SMC EEPROM\n",);
+
+U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac,
+ "smcew - Write MAC address to SMC EEPROM\n",
+ "aa:bb:cc:dd:ee:ff new mac address\n");
diff --git a/board/micronas/vct/top.c b/board/micronas/vct/top.c
new file mode 100644
index 0000000..0923954
--- /dev/null
+++ b/board/micronas/vct/top.c
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "vct.h"
+
+typedef union _TOP_PINMUX_t
+{
+ u32 reg;
+ struct {
+ u32 res : 24; /* reserved */
+ u32 drive : 2; /* Driver strength */
+ u32 slew : 1; /* Slew rate */
+ u32 strig : 1; /* Schmitt trigger input*/
+ u32 pu_pd : 2; /* Pull up/ pull down */
+ u32 funsel : 2; /* Pin function */
+ } Bits;
+} TOP_PINMUX_t;
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+
+static TOP_PINMUX_t top_read_pin(int pin)
+{
+ TOP_PINMUX_t reg;
+
+ switch (pin) {
+ case 2:
+ case 3:
+ case 6:
+ case 9:
+ reg.reg = 0xdeadbeef;
+ break;
+ case 4:
+ reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
+ break;
+ case 5:
+ reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
+ break;
+ case 7:
+ reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
+ break;
+ case 8:
+ reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+ ((pin - 10) * 4));
+ break;
+ default:
+ reg.reg = reg_read(TOP_BASE + (pin * 4));
+ break;
+ }
+
+ return reg;
+}
+
+static void top_write_pin(int pin, TOP_PINMUX_t reg)
+{
+
+ switch (pin) {
+ case 4:
+ reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 5:
+ reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 7:
+ reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 8:
+ reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+ ((pin - 10) * 4), reg.reg);
+ break;
+ default:
+ reg_write(TOP_BASE + (pin * 4), reg.reg);
+ break;
+ }
+}
+
+int top_set_pin(int pin, int func)
+{
+ TOP_PINMUX_t reg;
+
+ /* check global range */
+ if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
+ return -1; /* pin number or function out of valid range */
+
+ /* check undefined values; */
+ if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
+ return -1; /* pin number out of valid range */
+
+ reg = top_read_pin(pin);
+ reg.Bits.funsel = func;
+ top_write_pin(pin, reg);
+
+ return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+
+int top_set_pin(int pin, int func)
+{
+ TOP_PINMUX_t reg;
+
+ /* check global range */
+ if ((pin < 0) || (pin > 158))
+ return -1; /* pin number or function out of valid range */
+
+ reg.reg = reg_read(TOP_BASE + (pin * 4));
+ reg.Bits.funsel = func;
+ reg_write(TOP_BASE + (pin * 4), reg.reg);
+
+ return 0;
+}
+
+#endif
+
+void vct_pin_mux_initialize(void)
+{
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+ top_set_pin(34, 01); /* EBI_CS0 */
+ top_set_pin(33, 01); /* EBI_CS1 */
+ top_set_pin(32, 01); /* EBI_CS2 */
+ top_set_pin(100, 02); /* EBI_CS3 */
+ top_set_pin(101, 02); /* EBI_CS4 */
+ top_set_pin(102, 02); /* EBI_CS5 */
+ top_set_pin(103, 02); /* EBI_CS6 */
+ top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(35, 01); /* EBI_ALE */
+ top_set_pin(36, 01); /* EBI_ADDR15 */
+ top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
+ top_set_pin(38, 01); /* EBI_ADDR13 */
+ top_set_pin(39, 01); /* EBI_ADDR12 */
+ top_set_pin(40, 01); /* EBI_ADDR11 */
+ top_set_pin(41, 01); /* EBI_ADDR10 */
+ top_set_pin(42, 01); /* EBI_ADDR9 */
+ top_set_pin(43, 01); /* EBI_ADDR8 */
+ top_set_pin(44, 01); /* EBI_ADDR7 */
+ top_set_pin(45, 01); /* EBI_ADDR6 */
+ top_set_pin(46, 01); /* EBI_ADDR5 */
+ top_set_pin(47, 01); /* EBI_ADDR4 */
+ top_set_pin(48, 01); /* EBI_ADDR3 */
+ top_set_pin(49, 01); /* EBI_ADDR2 */
+ top_set_pin(50, 01); /* EBI_ADDR1 */
+ top_set_pin(51, 01); /* EBI_ADDR0 */
+ top_set_pin(52, 01); /* EBI_DIR */
+ top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
+ top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
+ top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
+ top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
+ top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
+ top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
+ top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
+ top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
+ top_set_pin(61, 01); /* EBI_DAT7 */
+ top_set_pin(62, 01); /* EBI_DAT6 */
+ top_set_pin(63, 01); /* EBI_DAT5 */
+ top_set_pin(64, 01); /* EBI_DAT4 */
+ top_set_pin(65, 01); /* EBI_DAT3 */
+ top_set_pin(66, 01); /* EBI_DAT2 */
+ top_set_pin(67, 01); /* EBI_DAT1 */
+ top_set_pin(68, 01); /* EBI_DAT0 */
+ top_set_pin(69, 01); /* EBI_IORD */
+ top_set_pin(70, 01); /* EBI_IOWR */
+ top_set_pin(71, 01); /* EBI_WE */
+ top_set_pin(72, 01); /* EBI_OE */
+ top_set_pin(73, 01); /* EBI_IORDY */
+ top_set_pin(95, 02); /* EBI_EBI_DMACK*/
+ top_set_pin(112, 02); /* EBI_IRQ0 */
+ top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
+ top_set_pin(107, 02); /* EBI_IRQ2 */
+ top_set_pin(108, 02); /* EBI_IRQ3 */
+ top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
+ top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
+ top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
+ top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
+ top_set_pin(110, 02); /* EBI_BURST_CLK */
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+ top_set_pin(19, 01); /* EBI_CS0 */
+ top_set_pin(18, 01); /* EBI_CS1 */
+ top_set_pin(17, 01); /* EBI_CS2 */
+ top_set_pin(92, 02); /* EBI_CS3 */
+ top_set_pin(93, 02); /* EBI_CS4 */
+ top_set_pin(95, 02); /* EBI_CS6 */
+ top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(20, 01); /* EBI_ALE */
+ top_set_pin(21, 01); /* EBI_ADDR15 */
+ top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
+ top_set_pin(23, 01); /* EBI_ADDR13 */
+ top_set_pin(24, 01); /* EBI_ADDR12 */
+ top_set_pin(25, 01); /* EBI_ADDR11 */
+ top_set_pin(26, 01); /* EBI_ADDR10 */
+ top_set_pin(27, 01); /* EBI_ADDR9 */
+ top_set_pin(28, 01); /* EBI_ADDR8 */
+ top_set_pin(29, 01); /* EBI_ADDR7 */
+ top_set_pin(30, 01); /* EBI_ADDR6 */
+ top_set_pin(31, 01); /* EBI_ADDR5 */
+ top_set_pin(32, 01); /* EBI_ADDR4 */
+ top_set_pin(33, 01); /* EBI_ADDR3 */
+ top_set_pin(34, 01); /* EBI_ADDR2 */
+ top_set_pin(35, 01); /* EBI_ADDR1 */
+ top_set_pin(36, 01); /* EBI_ADDR0 */
+ top_set_pin(37, 01); /* EBI_DIR */
+ top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
+ top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
+ top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
+ top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
+ top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
+ top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
+ top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
+ top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
+ top_set_pin(46, 01); /* EBI_DAT7 */
+ top_set_pin(47, 01); /* EBI_DAT6 */
+ top_set_pin(48, 01); /* EBI_DAT5 */
+ top_set_pin(49, 01); /* EBI_DAT4 */
+ top_set_pin(50, 01); /* EBI_DAT3 */
+ top_set_pin(51, 01); /* EBI_DAT2 */
+ top_set_pin(52, 01); /* EBI_DAT1 */
+ top_set_pin(53, 01); /* EBI_DAT0 */
+ top_set_pin(54, 01); /* EBI_IORD */
+ top_set_pin(55, 01); /* EBI_IOWR */
+ top_set_pin(56, 01); /* EBI_WE */
+ top_set_pin(57, 01); /* EBI_OE */
+ top_set_pin(58, 01); /* EBI_IORDY */
+ top_set_pin(87, 02); /* EBI_EBI_DMACK*/
+ top_set_pin(106, 02); /* EBI_IRQ0 */
+ top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
+ top_set_pin(101, 02); /* EBI_IRQ2 */
+ top_set_pin(102, 02); /* EBI_IRQ3 */
+ top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
+ top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
+ top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
+ top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
+ top_set_pin(104, 02); /* EBI_BURST_CLK */
+#endif
+
+ /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
+ top_set_pin(0, 2); /* SCL2 on GPIO 11 */
+ top_set_pin(1, 2); /* SDA2 on GPIO 10 */
+
+ /* UART pins */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+ top_set_pin(141, 1);
+ top_set_pin(143, 1);
+#endif
+#if defined(CONFIG_VCT_PLATINUMAVC)
+ top_set_pin(107, 1);
+ top_set_pin(109, 1);
+#endif
+}
diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds
new file mode 100644
index 0000000..da9e605
--- /dev/null
+++ b/board/micronas/vct/u-boot.lds
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ . = ALIGN(4);
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
+
+ . = ALIGN(4);
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss (NOLOAD) : { *(.sbss) }
+ . = ALIGN(4);
+ .bss (NOLOAD) : { *(.bss) }
+ uboot_end = .;
+}
diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c
new file mode 100644
index 0000000..d320e0b
--- /dev/null
+++ b/board/micronas/vct/vct.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include "vct.h"
+
+#if defined(CONFIG_VCT_PREMIUM)
+#define BOARD_NAME "PremiumD"
+#elif defined(CONFIG_VCT_PLATINUM)
+#define BOARD_NAME "PlatinumD"
+#elif defined(CONFIG_VCT_PLATINUMAVC)
+#define BOARD_NAME "PlatinumAVC"
+#else
+#error "vct: No board variant defined!"
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define BOARD_NAME_ADD " OneNAND"
+#else
+#define BOARD_NAME_ADD " NOR"
+#endif
+
+int board_early_init_f(void)
+{
+ /*
+ * First initialize the PIN mulitplexing
+ */
+ vct_pin_mux_initialize();
+
+ /*
+ * Init the EBI very early so that FLASH can be accessed
+ */
+ ebi_initialize();
+
+ return 0;
+}
+
+void _machine_restart(void)
+{
+ reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
+ reg_write(WDT_TORR(WDT_BASE), 0x00);
+ reg_write(WDT_CR(WDT_BASE), 0x1D);
+
+ /*
+ * Now wait for the watchdog to trigger the reset
+ */
+ udelay(1000000);
+}
+
+/*
+ * SDRAM is already configured by the bootstrap code, only return the
+ * auto-detected size here
+ */
+phys_size_t initdram(int board_type)
+{
+ return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_MBYTES_SDRAM << 20);
+}
+
+int checkboard(void)
+{
+ u32 config0 = read_c0_prid();
+ char *s = getenv("serial#");
+
+ if ((config0 & 0xff0000) == PRID_COMP_LEGACY
+ && (config0 & 0xff00) == PRID_IMP_LX4280) {
+ puts("Board: MDED \n");
+ printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
+ && (config0 & 0xff00) == PRID_IMP_VGC) {
+ u32 jedec_id = *((u32 *) 0xBEBC71A0);
+ if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
+ puts("Board: VGCA \n");
+ } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
+ || (((jedec_id) >> 12) & 0xFF) == 0x49) {
+ puts("Board: VGCB \n");
+ }
+ printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else if (config0 == 0x19378) {
+ printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else {
+ printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
+ config0);
+ }
+
+ printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h
new file mode 100644
index 0000000..f1a4851
--- /dev/null
+++ b/board/micronas/vct/vct.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+
+#include "bcu.h"
+#include "dcgu.h"
+#include "ebi.h"
+#include "scc.h"
+
+#ifdef CONFIG_VCT_PREMIUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth2/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUMAVC
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbdc00000
+#define TOP_BASE 0x00050000
+
+#include "vctv/reg_ebi.h"
+#include "vctv/reg_dcgu.h"
+#include "vctv/reg_wdt.h"
+#include "vctv/reg_gpio.h"
+#endif
+
+#ifndef _VCT_H
+#define _VCT_H
+
+/*
+ * Defines
+ */
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MIPS 0x010000
+#define PRID_IMP_LX4280 0xc200
+#define PRID_IMP_VGC 0x9000
+
+/*
+ * Prototypes
+ */
+int ebi_initialize(void);
+int ebi_init_nor_flash(void);
+int ebi_init_onenand(void);
+int ebi_init_smc911x(void);
+u32 smc911x_reg_read(u32 addr);
+void smc911x_reg_write(u32 addr, u32 data);
+int top_set_pin(int pin, int func);
+void vct_pin_mux_initialize(void);
+
+/*
+ * static inlines
+ */
+static inline void reg_write(u32 addr, u32 data)
+{
+ __raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+ return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+}
+
+#endif /* _VCT_H */
diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h
new file mode 100644
index 0000000..6ac0ddd
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_dcgu.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE 0x00084000
+
+/* Relative offsets of the register adresses */
+
+#define DCGU_CLK_EN1_OFFS 0x00000010
+#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS)
+#define DCGU_CLK_EN2_OFFS 0x00000014
+#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS)
+#define DCGU_RESET_UNIT1_OFFS 0x00000018
+#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS)
+#define DCGU_USBPHY_STAT_OFFS 0x00000054
+#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS)
+#define DCGU_EN_WDT_RESET_OFFS 0x00000064
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h
new file mode 100644
index 0000000..7a1e115
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_ebi.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000008
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000010
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h
new file mode 100644
index 0000000..19afb6b
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_fwsram.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Premium & Platinum register addresses/definitions seem to be
+ * identical, so we only need to use one file for both platforms.
+ */
+
+#ifndef _REG_FWSRAM_H_
+#define _REG_FWSRAM_H_
+
+#define FWSRAM_BASE 0x00030000
+
+/* Relative offsets of the register adresses */
+
+#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
+#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
+#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
+#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
+#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
+#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
+#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
+#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
+#define FWSRAM_TOP_CID1_L_OFFS 0x00002010
+#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
+#define FWSRAM_TOP_CID2_H_OFFS 0x00002014
+#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
+#define FWSRAM_TOP_CID2_L_OFFS 0x00002018
+#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
+#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
+#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
+#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
+#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
+#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
+#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
+#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
+#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
+#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
+#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
+#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
+#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
+#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
+#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
+#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
+#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h
new file mode 100644
index 0000000..7ada9c9
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE 0x00088000
+#define GPIO2_BASE 0x0008c000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vcth/reg_scc.h b/board/micronas/vct/vcth/reg_scc.h
new file mode 100644
index 0000000..5e4bfc5
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_scc.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_SCC_PREMIUM_H_
+#define _REG_SCC_PREMIUM_H_
+
+#define SCC0_BASE 0x00110000
+#define SCC1_BASE 0x00110080
+#define SCC2_BASE 0x00110100
+#define SCC3_BASE 0x00110180
+#define SCC4_BASE 0x00110200
+#define SCC5_BASE 0x00110280
+#define SCC6_BASE 0x00110300
+#define SCC7_BASE 0x00110380
+#define SCC8_BASE 0x00110400
+#define SCC9_BASE 0x00110480
+#define SCC10_BASE 0x00110500
+#define SCC11_BASE 0x00110580
+#define SCC12_BASE 0x00110600
+#define SCC13_BASE 0x00110680
+#define SCC14_BASE 0x00110700
+#define SCC15_BASE 0x00110780
+#define SCC16_BASE 0x00110800
+#define SCC17_BASE 0x00110880
+#define SCC18_BASE 0x00110900
+#define SCC19_BASE 0x00110980
+#define SCC20_BASE 0x00110a00
+#define SCC21_BASE 0x00110a80
+#define SCC22_BASE 0x00110b00
+#define SCC23_BASE 0x00110b80
+#define SCC24_BASE 0x00110c00
+#define SCC25_BASE 0x00110c80
+#define SCC26_BASE 0x00110d00
+#define SCC27_BASE 0x00110d80
+#define SCC28_BASE 0x00110e00
+#define SCC29_BASE 0x00110e80
+#define SCC30_BASE 0x00110f00
+#define SCC31_BASE 0x00110f80
+#define SCC32_BASE 0x00111000
+#define SCC33_BASE 0x00111080
+#define SCC34_BASE 0x00111100
+#define SCC35_BASE 0x00111180
+#define SCC36_BASE 0x00111200
+#define SCC37_BASE 0x00111280
+#define SCC38_BASE 0x00111300
+#define SCC39_BASE 0x00111380
+#define SCC40_BASE 0x00111400
+
+/* Relative offsets of the register adresses */
+
+#define SCC_ENABLE_OFFS 0x00000000
+#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS)
+#define SCC_RESET_OFFS 0x00000004
+#define SCC_RESET(base) ((base) + SCC_RESET_OFFS)
+#define SCC_VCID_OFFS 0x00000008
+#define SCC_VCID(base) ((base) + SCC_VCID_OFFS)
+#define SCC_MCI_CFG_OFFS 0x0000000C
+#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS)
+#define SCC_PACKET_CFG1_OFFS 0x00000010
+#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS)
+#define SCC_PACKET_CFG2_OFFS 0x00000014
+#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS)
+#define SCC_PACKET_CFG3_OFFS 0x00000018
+#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS)
+#define SCC_DMA_CFG_OFFS 0x0000001C
+#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS)
+#define SCC_CMD_OFFS 0x00000020
+#define SCC_CMD(base) ((base) + SCC_CMD_OFFS)
+#define SCC_PRIO_OFFS 0x00000024
+#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS)
+#define SCC_DEBUG_OFFS 0x00000028
+#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS)
+#define SCC_STATUS_OFFS 0x0000002C
+#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS)
+#define SCC_IMR_OFFS 0x00000030
+#define SCC_IMR(base) ((base) + SCC_IMR_OFFS)
+#define SCC_ISR_OFFS 0x00000034
+#define SCC_ISR(base) ((base) + SCC_ISR_OFFS)
+#define SCC_DMA_OFFSET_OFFS 0x00000038
+#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS)
+#define SCC_RS_CTLSTS_OFFS 0x0000003C
+#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_usbh.h b/board/micronas/vct/vcth/reg_usbh.h
new file mode 100644
index 0000000..9187a34
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_usbh.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define USBH_BASE 0x00080000
+
+/* Relative offsets of the register adresses */
+
+#define USBH_CAPLENGTH_OFFS 0x00000100
+#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS)
+#define USBH_USBCMD_OFFS 0x00000140
+#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS)
+#define USBH_BURSTSIZE_OFFS 0x00000160
+#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS)
+#define USBH_USBMODE_OFFS 0x000001A8
+#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS)
+#define USBH_USBHMISC_OFFS 0x00000200
+#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS)
diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h
new file mode 100644
index 0000000..a9b4bf0
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE 0x000b0000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h
new file mode 100644
index 0000000..37f0711
--- /dev/null
+++ b/board/micronas/vct/vcth2/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h
new file mode 100644
index 0000000..6f5c968
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_dcgu.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE 0x0004c000
+#define DCGU_EN_WDT_RESET_OFFS 0x000000FC
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h
new file mode 100644
index 0000000..82f345e
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PLATINUMAVC_H_
+#define _REG_EBI_PLATINUMAVC_H_
+
+#define EBI_BASE 0x00014000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h
new file mode 100644
index 0000000..24eb8e9
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE 0x00044000
+#define GPIO2_BASE 0x00048000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h
new file mode 100644
index 0000000..04842e5
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE 0x00040000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index bf270f4..72a1ad3 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -50,7 +50,7 @@ int checkboard (void)
get_sys_info (&sysinfo);
printf ("Board: Freescale MPC8540EVAL Board\n");
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 877a2d0..d169391 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -559,7 +559,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#endif
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
index 6ad95b5..dc13804 100644
--- a/board/mpl/mip405/cmd_mip405.c
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -55,7 +55,7 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
mip405, 8, 1, do_mip405,
- "mip405 - MIP405 specific Cmds\n",
+ "MIP405 specific Cmds",
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"mip405 flash mps - updates U-Boot with image from MPS\n"
"mip405 info - displays board information\n"
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
index 9d9531b..95bfdcc 100644
--- a/board/mpl/pati/cmd_pati.c
+++ b/board/mpl/pati/cmd_pati.c
@@ -427,7 +427,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
pati, 8, 1, do_pati,
- "pati - PATI specific Cmds\n",
+ "PATI specific Cmds",
"info - displays board information\n"
"pati pci - displays PCI registers\n"
"pati led <nr> <on> \n"
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
index 945e5c9..ad5e0a1 100644
--- a/board/mpl/pip405/cmd_pip405.c
+++ b/board/mpl/pip405/cmd_pip405.c
@@ -60,7 +60,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
pip405, 6, 1, do_pip405,
- "pip405 - PIP405 specific Cmds\n",
+ "PIP405 specific Cmds",
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
"pip405 flash mps - updates U-Boot with image from MPS\n"
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index d3629c5..2748fa9 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -175,6 +175,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
vcma9, 6, 1, do_vcma9,
- "vcma9 - VCMA9 specific commands\n",
+ "VCMA9 specific commands",
"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
);
diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index a3dbdc8..80c2cb5 100644
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -230,13 +230,13 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
wd, 2, 1, do_wd,
- "wd - check and set watchdog\n",
+ "check and set watchdog",
"on - switch watchDog on\n"
"wd off - switch watchdog off\n"
"wd - print current status\n"
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 271005f..5fd3291 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -761,7 +761,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
led, 2, 1, do_led,
- "led [bitmask] - set the DIAG-LED\n",
+ "set the DIAG-LED",
"[bitmask] 0x01 = DIAG 1 on\n"
" 0x02 = DIAG 2 on\n"
" 0x04 = DIAG 3 on\n"
@@ -780,7 +780,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (argc < 2) {
usage:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -823,7 +823,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
sha1, 4, 1, do_sha1,
- "sha1 - calculate the SHA1 Sum\n",
+ "calculate the SHA1 Sum",
"address len [addr] calculate the SHA1 sum [save at addr]\n"
" -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
" -c check the U-Boot image in flash\n"
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
index 3f53e4b..10d0df6 100644
--- a/board/pn62/cmd_pn62.c
+++ b/board/pn62/cmd_pn62.c
@@ -41,7 +41,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
unsigned int number, function;
if (argc != 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
number = simple_strtoul(argv[1], NULL, 10);
@@ -53,7 +53,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
led , 3, 1, do_led,
- "led - set LED 0..11 on the PN62 board\n",
+ "set LED 0..11 on the PN62 board",
"i fun\n"
" - set 'i'th LED to function 'fun'\n"
);
@@ -83,7 +83,7 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
addr = simple_strtoul(argv[1], NULL, 16);
break;
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -174,7 +174,7 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
loadpci, 2, 1, do_loadpci,
- "loadpci - load binary file over PCI\n",
+ "load binary file over PCI",
"[addr]\n"
" - load binary file over PCI to address 'addr'\n"
);
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index 3773ba1..8777284 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -216,7 +216,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong addr;
if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -227,7 +227,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
fpga, 2, 0, do_fpga,
- "fpga - boot FPGA\n",
+ "boot FPGA",
"address size\n - boot FPGA with gzipped image at <address>\n"
);
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index b0aa8dd..aa598aa 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -128,7 +128,7 @@ int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
- "idpcmd - custom IDP command\n",
+ "custom IDP command",
"no args at this time\n"
);
diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c
index b502e4d..1871984 100644
--- a/board/r360mpi/r360mpi.c
+++ b/board/r360mpi/r360mpi.c
@@ -414,6 +414,6 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
- "kbd - read keyboard status\n",
+ "read keyboard status",
NULL
);
diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c
index bf0ba14..6d0bbc0 100644
--- a/board/renesas/sh7785lcr/rtl8169_mac.c
+++ b/board/renesas/sh7785lcr/rtl8169_mac.c
@@ -305,7 +305,7 @@ int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *s, *e;
if (argc != 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -323,7 +323,7 @@ int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
setmac, 2, 1, do_set_mac,
- "setmac - write MAC address for RTL8110SCL\n",
+ "write MAC address for RTL8110SCL",
"\n"
"setmac <mac address> - write MAC address for RTL8110SCL\n"
);
@@ -331,7 +331,7 @@ U_BOOT_CMD(
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc != 1) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -342,7 +342,7 @@ int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
printmac, 1, 1, do_print_mac,
- "printmac - print MAC address for RTL8110\n",
+ "print MAC address for RTL8110",
"\n"
" - print MAC address for RTL8110\n"
);
diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c
index ce0620f..6dbb784 100644
--- a/board/renesas/sh7785lcr/selfcheck.c
+++ b/board/renesas/sh7785lcr/selfcheck.c
@@ -113,7 +113,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *cmd;
if (argc != 2) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -150,7 +150,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
test_net();
break;
default:
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -159,7 +159,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
hwtest, 2, 1, do_hw_test,
- "hwtest - hardware test for R0P7785LC0011RL board\n",
+ "hardware test for R0P7785LC0011RL board",
"\n"
"hwtest all - test all hardware\n"
"hwtest pld - output PLD version\n"
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
index 9af6b8d..c1af70c 100644
--- a/board/sandburst/common/ppc440gx_i2c.c
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -500,7 +500,7 @@ int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
iprobe1, 1, 1, do_i2c1_probe,
- "iprobe1 - probe to discover valid I2C chip addresses\n",
+ "probe to discover valid I2C chip addresses",
"\n -discover valid I2C chip addresses\n"
);
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 8d97a9c..9b94af5 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -578,7 +578,7 @@ int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
- "kasetup - Set environment to factory defaults\n", NULL);
+ "Set environment to factory defaults", NULL);
U_BOOT_CMD(karecover, 1, 1, karefRecover,
- "karecover - Set environment to allow for fs recovery\n", NULL);
+ "Set environment to allow for fs recovery", NULL);
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 19302dc..ec4c451 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -544,7 +544,7 @@ int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
- "mbsetup - Set environment to factory defaults\n", NULL);
+ "Set environment to factory defaults", NULL);
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
- "mbrecover - Set environment to allow for fs recovery\n", NULL);
+ "Set environment to allow for fs recovery", NULL);
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 3d4008b..7f032c8 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -247,7 +247,7 @@ int checkboard (void)
#else
printf ("Board: Wind River SBC8540 Board\n");
#endif
- printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor));
+ printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
index ac0022e..c9a93e1 100644
--- a/board/siemens/common/fpga.c
+++ b/board/siemens/common/fpga.c
@@ -286,13 +286,13 @@ int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
failure:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
fpga, 4, 1, do_fpga,
- "fpga - access FPGA(s)\n",
+ "access FPGA(s)",
"fpga status [name] - print FPGA status\n"
"fpga reset [name] - reset FPGA\n"
"fpga load [name] addr - load FPGA configuration data\n"
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
index a60c825..f87d6bc 100644
--- a/board/siemens/pcu_e/pcu_e.c
+++ b/board/siemens/pcu_e/pcu_e.c
@@ -399,12 +399,12 @@ int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD (puma, 4, 1, do_puma,
- "puma - access PUMA FPGA\n",
+ "access PUMA FPGA",
"status - print PUMA status\n"
"puma load addr len - load PUMA configuration data\n");
diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c
index 2208580..99ff507 100644
--- a/board/ssv/common/cmd_sled.c
+++ b/board/ssv/common/cmd_sled.c
@@ -133,7 +133,7 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -156,7 +156,7 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#endif
U_BOOT_CMD (sled, 3, 0, do_sled,
- "sled - check and set status led\n",
+ "check and set status led",
"sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n");
#endif
#endif /* CONFIG_STATUS_LED */
diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c
index 9945c59..9b38425 100644
--- a/board/ssv/common/wd_pio.c
+++ b/board/ssv/common/wd_pio.c
@@ -145,13 +145,13 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
default:
break;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
wd, 2, 1, do_wd,
- "wd - check and set watchdog\n",
+ "check and set watchdog",
"on - switch watchDog on\n"
"wd off - switch watchdog off\n"
"wd - print current status\n"
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
index 5483fca..20632a7 100644
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -327,7 +327,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
switch (argc) {
case 0:
case 1:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 2:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -342,7 +342,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 3:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -358,7 +358,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
LEFT_RIGHT);
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 4:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -382,7 +382,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcm1772_write_reg((uchar)reg, (uchar)val);
return 0;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 5:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -412,7 +412,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
channel);
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
@@ -513,7 +513,7 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
channel = LEFT_RIGHT;
break;
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -1194,7 +1194,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
sound , 5, 1, cmd_sound,
- "sound - Sound sub-system\n",
+ "Sound sub-system",
"saw [duration] [freq] [channel]\n"
" - generate sawtooth for 'duration' ms with frequency 'freq'\n"
" on left \"l\" or right \"r\" channel\n"
@@ -1206,14 +1206,14 @@ U_BOOT_CMD(
U_BOOT_CMD(
wav , 3, 1, cmd_wav,
- "wav - play wav file\n",
+ "play wav file",
"[addr] [bytes]\n"
" - play wav file at address 'addr' with length 'bytes'\n"
);
U_BOOT_CMD(
beep , 2, 1, cmd_beep,
- "beep - play short beep\n",
+ "play short beep",
"[channel]\n"
" - play short beep on \"l\"eft or \"r\"ight channel\n"
);
@@ -1222,7 +1222,7 @@ U_BOOT_CMD(
#if defined(CONFIG_STK52XX)
U_BOOT_CMD(
fkt , 4, 1, cmd_fkt,
- "fkt - Function test routines\n",
+ "Function test routines",
"led number on/off\n"
" - 'number's like printed on STK52XX board\n"
"fkt can\n"
@@ -1237,7 +1237,7 @@ U_BOOT_CMD(
#elif defined(CONFIG_FO300)
U_BOOT_CMD(
fkt , 3, 1, cmd_fkt,
- "fkt - Function test routines\n",
+ "Function test routines",
"fkt can\n"
" - loopback plug for X16/X29 required\n"
"fkt rs232 number\n"
diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c
index 214dca6..b9c9e7e 100644
--- a/board/tqc/tqm5200/cmd_tb5200.c
+++ b/board/tqc/tqm5200/cmd_tb5200.c
@@ -90,13 +90,13 @@ int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
led , 2, 1, cmd_led,
- "led - switch status LED on or off\n",
+ "switch status LED on or off",
"on/off\n"
);
U_BOOT_CMD(
backlight , 2, 1, cmd_backlight,
- "backlight - switch backlight on or off\n",
+ "switch backlight on or off",
"on/off\n"
);
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index 5d0741d..5bc080f 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -866,7 +866,7 @@ int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
hwib, 1, 1, do_hwib_dump,
- "hwib - dump HWIB'\n",
+ "dump HWIB'",
"\n"
);
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index daa6aee..7e2a672 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -168,7 +168,7 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int cycle_status;
if (argc > 1) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -258,7 +258,7 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
burn_in, 1, 1, do_burn_in,
- "burn_in - start burn-in test application on TRAB\n",
+ "start burn-in test application on TRAB",
"\n"
" - start burn-in test application\n"
" The burn-in test could took a while to finish!\n"
@@ -271,7 +271,7 @@ int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int i, dip;
if (argc > 1) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -292,7 +292,7 @@ int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
dip, 1, 1, do_dip,
- "dip - read dip switch on TRAB\n",
+ "read dip switch on TRAB",
"\n"
" - read state of dip switch (S1) on TRAB board\n"
" read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n"
@@ -304,7 +304,7 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int vcc5v;
if (argc > 1) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -321,7 +321,7 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
vcc5v, 1, 1, do_vcc5v,
- "vcc5v - read VCC5V on TRAB\n",
+ "read VCC5V on TRAB",
"\n"
" - read actual value of voltage VCC5V\n"
);
@@ -332,7 +332,7 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int contact_temp;
if (argc > 1) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -346,7 +346,7 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
c_temp, 1, 1, do_contact_temp,
- "c_temp - read contact temperature on TRAB\n",
+ "read contact temperature on TRAB",
"\n"
" - reads the onboard temperature (=contact temperature)\n"
);
@@ -355,7 +355,7 @@ U_BOOT_CMD(
int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc > 1) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -398,7 +398,7 @@ int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bis, 1, 1, do_burn_in_status,
- "bis - print burn in status on TRAB\n",
+ "print burn in status on TRAB",
"\n"
" - prints the status variables of the last burn in test\n"
" stored in the onboard EEPROM on TRAB board\n"
@@ -851,7 +851,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#endif
if (argc > 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -886,7 +886,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
tlog, 2, 1, do_temp_log,
- "tlog - log contact temperature [1/100 C] to console (endlessly)\n",
+ "log contact temperature [1/100 C] to console (endlessly)",
"delay\n"
" - contact temperature [1/100 C] is printed endlessly to console\n"
" <delay> specifies the seconds to wait between two measurements\n"
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 57ff718..7fcc450 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -322,7 +322,7 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
- "kbd - read keyboard status\n",
+ "read keyboard status",
NULL
);
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
index 7a2b905..63f1c6c 100644
--- a/board/trizepsiv/eeprom.c
+++ b/board/trizepsiv/eeprom.c
@@ -43,7 +43,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *
int offset,value;
if (argc < 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -51,7 +51,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *
value=simple_strtoul(argv[3],NULL,16);
if (offset > 0x40) {
printf("Wrong offset : 0x%x\n",offset);
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
write_srom_word(offset, value);
@@ -60,7 +60,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *
int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -69,14 +69,14 @@ int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
} else if (strcmp (argv[1],"write") == 0) {
return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
} else {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
}
U_BOOT_CMD(
dm9000ee,4,1,do_dm9000_eeprom,
- "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
+ "Read/Write eeprom connected to Ethernet Controller",
"\ndm9000ee write <word offset> <value> \n"
"\tdm9000ee read \n"
"\tword:\t\t00-02 : MAC Address\n"
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
index 310fde0..eaec940 100644
--- a/board/w7o/cmd_vpd.c
+++ b/board/w7o/cmd_vpd.c
@@ -39,7 +39,7 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
/* Validate usage */
if (argc > 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -58,7 +58,7 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
vpd, 2, 1, do_vpd,
- "vpd - Read Vital Product Data\n",
+ "Read Vital Product Data",
"[dev_addr]\n"
" - Read VPD Data from default address, or device address 'dev_addr'.\n"
);
diff --git a/board/zeus/update.c b/board/zeus/update.c
index 2f2a127..ce1f34f 100644
--- a/board/zeus/update.c
+++ b/board/zeus/update.c
@@ -98,7 +98,7 @@ int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
U_BOOT_CMD (
update_boot_eeprom, 1, 1, do_update_boot_eeprom,
- "update_boot_eeprom - update boot eeprom content\n",
+ "update boot eeprom content",
NULL
);
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 974bdf2..3f329c2 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -327,7 +327,7 @@ int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
setdef, 4, 1, do_set_default,
- "setdef - write board-specific values to EEPROM (ethaddr...)\n",
+ "write board-specific values to EEPROM (ethaddr...)",
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
);
@@ -418,7 +418,7 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
U_BOOT_CMD (
chkreset, 1, 1, do_chkreset,
- "chkreset- Check for status of SW-reset button and act accordingly\n",
+ "Check for status of SW-reset button and act accordingly",
NULL
);
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
index ff17c7e..6f2ad23 100644
--- a/board/zylonite/lowlevel_init.S
+++ b/board/zylonite/lowlevel_init.S
@@ -121,7 +121,7 @@ lowlevel_init:
/* ldr r2, [r3] */
/* cmp r4, r2 */
/* bgt 1b */
- wait #300
+ wait #0x300
mem_init: