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-rw-r--r--board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c27
-rw-r--r--board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c32
-rw-r--r--board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c27
3 files changed, 59 insertions, 27 deletions
diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
index 645e8d1..cc76c92 100644
--- a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
+++ b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
@@ -352,6 +352,9 @@ static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
/*
* ALT5 mode is only valid when TAMPER pin is used for GPIO.
* This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
@@ -381,7 +384,9 @@ static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
@@ -390,17 +395,9 @@ static void setup_iomux_fec(int fec_id)
if (fec_id == 0) {
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
- gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
} else {
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
- gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
}
}
#endif
@@ -679,6 +676,13 @@ static int setup_fec(int fec_id)
if (ret)
return ret;
+ imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
+ ARRAY_SIZE(fec1_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
+
} else {
if (check_module_fused(MX6_MODULE_ENET2))
return -1;
@@ -686,6 +690,13 @@ static int setup_fec(int fec_id)
/* clk from phy, set gpr1[14], clear gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+
+ imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
+ ARRAY_SIZE(fec2_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
}
enable_enet_clk(1);
diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c
index ee6d725..cd91106 100644
--- a/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c
+++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c
@@ -316,13 +316,16 @@ static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
/*
* ALT5 mode is only valid when TAMPER pin is used for GPIO.
* This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
*
- * ENET2_RST
+ * ENET1_RST
*/
- MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
/* Conflict with UART1 */
@@ -346,8 +349,10 @@ static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
- MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
+ MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
@@ -355,17 +360,9 @@ static void setup_iomux_fec(int fec_id)
if (fec_id == 0) {
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
- gpio_request(IMX_GPIO_NR(5, 4), "fec1 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
} else {
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
- gpio_request(IMX_GPIO_NR(5, 2), "fec2 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
}
}
#endif
@@ -626,10 +623,23 @@ static int setup_fec(int fec_id)
if (ret)
return ret;
+ imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
+ ARRAY_SIZE(fec1_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
} else {
/* clk from phy, set gpr1[13], clear gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
+
+ imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
+ ARRAY_SIZE(fec2_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
}
enable_enet_clk(1);
diff --git a/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
index 3ba85ec..aeb39ee 100644
--- a/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
+++ b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
@@ -272,6 +272,9 @@ static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
/*
* ALT5 mode is only valid when TAMPER pin is used for GPIO.
* This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
@@ -302,7 +305,9 @@ static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
/*
* ENET2_RST
*
@@ -316,17 +321,9 @@ static void setup_iomux_fec(int fec_id)
if (fec_id == 0) {
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
- gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
} else {
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
- gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
- udelay(50);
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
}
}
#endif
@@ -817,6 +814,13 @@ static int setup_fec(int fec_id)
if (ret)
return ret;
+ imx_iomux_v3_setup_multiple_pads(fec1_phy_rst,
+ ARRAY_SIZE(fec1_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
+
} else {
if (check_module_fused(MX6_MODULE_ENET2))
return -1;
@@ -824,6 +828,13 @@ static int setup_fec(int fec_id)
/* clk from phy, set gpr1[14], clear gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+
+ imx_iomux_v3_setup_multiple_pads(fec2_phy_rst,
+ ARRAY_SIZE(fec2_phy_rst));
+ gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+ udelay(50);
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
}
enable_enet_clk(1);
generated by cgit v1.1 at 2024-07-04 22:50:54 +0000