diff options
Diffstat (limited to 'board')
38 files changed, 146 insertions, 153 deletions
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index b3fb09c..0608a5a 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -123,7 +123,7 @@ void xr3pci_setup_atr(void) base += XR3PCI_ATR_TABLE_SIZE; /* setup IO space translation */ - xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START, + xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0, XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO); base += XR3PCI_ATR_TABLE_SIZE; diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig index c7aab75..01d68e1 100644 --- a/board/freescale/b4860qds/Kconfig +++ b/board/freescale/b4860qds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_B4860QDS +if TARGET_B4860QDS || TARGET_B4420QDS config SYS_BOARD default "b4860qds" diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index 673d2ea..c032242 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -8,7 +8,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += b4860qds.o -obj-$(CONFIG_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index c2ceb80..83a7015 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -437,7 +437,7 @@ int configure_vsc3316_3308(void) } break; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* @@ -496,7 +496,7 @@ int configure_vsc3316_3308(void) /* Configure VSC3308 crossbar switch */ ret = select_i2c_ch_pca(I2C_CH_VSC3308); switch (serdes2_prtcl) { -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x9d: #endif case 0x9E: @@ -929,7 +929,7 @@ int config_serdes2_refclks(void) * For this SerDes2's Refclk1 need to be set to 100MHz */ switch (serdes2_prtcl) { -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x9d: #endif case 0x9E: diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index fcccb8f..901f8b0 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -28,7 +28,7 @@ static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {5, 14}, {4, 15}, {2, 12}, {12, 13} }; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif @@ -54,7 +54,7 @@ static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 11}, {15, 10}, {13, 3}, {12, 12} }; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 164ec0a..89a1883 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -213,7 +213,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index be114ce..e941949 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -45,18 +45,18 @@ endif obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o -obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_MPC8572DS) += ics307_clk.o -obj-$(CONFIG_P1022DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o -obj-$(CONFIG_P3041DS) += ics307_clk.o -obj-$(CONFIG_P4080DS) += ics307_clk.o -obj-$(CONFIG_P5020DS) += ics307_clk.o -obj-$(CONFIG_P5040DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o @@ -65,11 +65,11 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o # deal with common files for P-series corenet based devices -obj-$(CONFIG_P2041RDB) += p_corenet/ -obj-$(CONFIG_P3041DS) += p_corenet/ -obj-$(CONFIG_P4080DS) += p_corenet/ -obj-$(CONFIG_P5020DS) += p_corenet/ -obj-$(CONFIG_P5040DS) += p_corenet/ +obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ +obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ +obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h index 9328404..e6e0f66 100644 --- a/board/freescale/common/pixis.h +++ b/board/freescale/common/pixis.h @@ -7,7 +7,7 @@ #define __PIXIS_H_ 1 /* PIXIS register set. */ -#if defined(CONFIG_MPC8536DS) +#if defined(CONFIG_TARGET_MPC8536DS) typedef struct pixis { u8 id; u8 ver; @@ -46,7 +46,7 @@ typedef struct pixis { u8 res2[4]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8544DS) +#elif defined(CONFIG_TARGET_MPC8544DS) typedef struct pixis { u8 id; u8 ver; @@ -73,7 +73,7 @@ typedef struct pixis { u8 res2[34]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8572DS) +#elif defined(CONFIG_TARGET_MPC8572DS) typedef struct pixis { u8 id; u8 ver; @@ -102,7 +102,7 @@ typedef struct pixis { u8 res4[25]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8610HPCD) +#elif defined(CONFIG_TARGET_MPC8610HPCD) typedef struct pixis { u8 id; u8 ver; /* also called arch */ @@ -132,7 +132,7 @@ typedef struct pixis { u8 res4[33]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8641HPCN) +#elif defined(CONFIG_TARGET_MPC8641HPCN) typedef struct pixis { u8 id; u8 ver; diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 1eb3786..d152a78 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8569MDS) +#if defined(CONFIG_TARGET_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 9ade947..100ba92 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -8,11 +8,11 @@ obj-y += corenet_ds.o obj-y += ddr.o -obj-$(CONFIG_P3041DS) += eth_hydra.o -obj-$(CONFIG_P4080DS) += eth_p4080.o -obj-$(CONFIG_P5020DS) += eth_hydra.o -obj-$(CONFIG_P5040DS) += eth_superhydra.o -obj-$(CONFIG_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_P5020DS) += p5020ds_ddr.o -obj-$(CONFIG_P5040DS) += p5040ds_ddr.o +obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o +obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o +obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o +obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o +obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o +obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o +obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o +obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 8a44a9a..93e1258 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -26,8 +26,8 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ - defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) unsigned int i; #endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; @@ -56,15 +56,15 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ - || defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } -#ifdef CONFIG_P5040DS +#ifdef CONFIG_TARGET_P5040DS /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ sw = in_8(&PIXIS_SW(9)); printf("Bank4=%sMhz ", freq[sw & 3]); @@ -136,8 +136,8 @@ int misc_init_r(void) unsigned int i; u8 sw; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ - || defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig index b0a7a8d..159bcc4 100644 --- a/board/freescale/p1010rdb/Kconfig +++ b/board/freescale/p1010rdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_P1010RDB +if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB config SYS_BOARD default "p1010rdb" diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 8eecb06..65bb575 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -54,7 +54,7 @@ static uint sd_ifc_mux; struct cpld_data { u8 cpld_ver; /* cpld revision */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) u8 pcba_ver; /* pcb revision number */ u8 twindie_ddr3; u8 res1[6]; @@ -69,7 +69,7 @@ struct cpld_data { u8 por1; /* POR Options */ u8 por2; /* POR Options */ u8 por3; /* POR Options */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) u8 rom_loc; #endif }; @@ -135,7 +135,7 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp; -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); switch (ctrl_type) { @@ -171,7 +171,7 @@ int config_board_mux(int ctrl_type) default: break; } -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) uint orig_bus = i2c_get_bus_num(); i2c_set_bus_num(I2C_PCA9557_BUS_NUM); @@ -245,7 +245,7 @@ int config_board_mux(int ctrl_type) return 0; } -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB int i2c_pca9557_read(int type) { u8 val; @@ -275,9 +275,9 @@ int checkboard(void) u8 val; cpu = gd->arch.cpu; -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) printf("Board: %sRDB-PA, ", cpu->name); -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) printf("Board: %sRDB-PB, ", cpu->name); i2c_set_bus_num(I2C_PCA9557_BUS_NUM); i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); @@ -290,10 +290,10 @@ int checkboard(void) config_board_mux(MUX_TYPE_IFC); #endif -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) val = (in_8(&cpld_data->pcba_ver) & 0xf); printf("PCB: v%x.0\n", val); -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) val = in_8(&cpld_data->cpld_ver); printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); @@ -544,7 +544,7 @@ int misc_init_r(void) else if (hwconfig("ifc")) config_board_mux(MUX_TYPE_IFC); -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif return 0; diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 9844194..c22e215 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -32,7 +32,7 @@ void board_init_f(ulong bootflag) /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index d3352d2..2f9640b 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,4 +1,11 @@ -if TARGET_P1_P2_RDB_PC +if TARGET_P1020MBG || \ + TARGET_P1020RDB_PC || \ + TARGET_P1020RDB_PD || \ + TARGET_P1020UTM || \ + TARGET_P1021RDB || \ + TARGET_P1024RDB || \ + TARGET_P1025RDB || \ + TARGET_P2020RDB config SYS_BOARD default "p1_p2_rdb_pc" diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 1f3793b..fc38326 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -15,8 +15,8 @@ #ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_P1020RDB_PROTO) || \ - defined(CONFIG_P1021RDB) || \ - defined(CONFIG_P1020UTM) + defined(CONFIG_TARGET_P1021RDB) || \ + defined(CONFIG_TARGET_P1020UTM) /* Micron MT41J256M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, @@ -47,7 +47,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P2020RDB) +#elif defined(CONFIG_TARGET_P2020RDB) /* Micron MT41J128M16_15E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, @@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 30000, }; -#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -109,7 +109,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P1020RDB_PC) +#elif defined(CONFIG_TARGET_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -146,8 +146,8 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P1024RDB) || \ - defined(CONFIG_P1025RDB) +#elif defined(CONFIG_TARGET_P1024RDB) || \ + defined(CONFIG_TARGET_P1025RDB) /* * Samsung K4B2G0846C-HCH9 * The following timing are for "downshift" diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index d61c3a5..51217c5 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -39,7 +39,7 @@ #define GPIO_SLIC_PIN 30 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) #define GPIO_DDR_RST_PORT 1 #define GPIO_DDR_RST_PIN 8 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) @@ -47,7 +47,7 @@ #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) #endif -#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) #define PCA_IOPORT_I2C_ADDR 0x23 #define PCA_IOPORT_OUTPUT_CMD 0x2 #define PCA_IOPORT_CFG_CMD 0x6 @@ -58,14 +58,14 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GPIO */ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ #endif {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* QE_MUX_MDC */ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ @@ -150,7 +150,7 @@ void board_gpio_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) /* reset DDR3 */ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); udelay(1000); @@ -379,7 +379,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_QE) && \ - (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)) + (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)) static void fdt_board_fixup_qe_pins(void *blob) { unsigned int oldbus; @@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; -#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) const char *soc_usb_compat = "fsl-usb2-dr"; int usb_err, usb1_off, usb2_off; #endif @@ -448,7 +448,7 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", sizeof("okay"), 0); -#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) fdt_board_fixup_qe_pins(blob); #endif #endif @@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 1c0008b..7cba411 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif /* P1020MBG */ +#endif /* TARGET_P1020MBG */ #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig index 4d17798..6ee7468 100644 --- a/board/freescale/t102xqds/Kconfig +++ b/board/freescale/t102xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T102XQDS +if TARGET_T1024QDS config SYS_BOARD default "t102xqds" diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index 61bfb29..c9239b8 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -66,7 +66,7 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, ccb_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) +#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT) /* * There is T1040 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index 1affa0b..1b2f6b2 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -152,7 +152,7 @@ static int board_mux_lane_to_slot(void) return 0; } -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 static void board_mux_setup(void) { u8 brdcfg15; @@ -332,7 +332,7 @@ unsigned long get_board_ddr_clk(void) #define NUM_SRDS_PLL 2 int misc_init_r(void) { -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 board_mux_setup(); #endif return 0; diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig index 10d49f5..d538386 100644 --- a/board/freescale/t102xrdb/Kconfig +++ b/board/freescale/t102xrdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T102XRDB +if TARGET_T1023RDB || TARGET_T1024RDB config SYS_BOARD default "t102xrdb" diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index f28728d..e33d317 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -1,4 +1,6 @@ -if TARGET_T104XRDB +if TARGET_T1040RDB || TARGET_T1040D4RDB || \ + TARGET_T1042RDB || TARGET_T1042D4RDB || \ + TARGET_T1042RDB_PI config SYS_BOARD default "t104xrdb" diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index 0ce4e47..95ff6a7 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -69,7 +69,7 @@ static void cpld_dump_regs(void) printf("int_status = 0x%02x\n", CPLD_READ(int_status)); printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); -#if defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); #else printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 86de26c..7adf5e4 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,7 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ -#if defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) u8 int_mask; /* 0x15 - Interrupt mask Register */ #else u8 led_ctl_status; /* 0x15 - LED control and status register */ diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 52cd112..ab8c8bb 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,7 +43,7 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: /* T1040RDB & T1040D4RDB only supports SGMII on * DTSEC3 @@ -52,7 +52,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB case PHY_INTERFACE_MODE_SGMII: /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) @@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB case PHY_INTERFACE_MODE_SGMII: /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 * & DTSEC3 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6bad6a454..d4c3d4d 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -29,7 +29,7 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; -#ifdef CONFIG_T104XD4RDB +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) printf("Board: %sD4RDB\n", cpu->name); #else printf("Board: %sRDB\n", cpu->name); @@ -105,7 +105,7 @@ int misc_init_r(void) CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); -#if defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) if (hwconfig("qe-tdm")) { CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | MISC_MUX_QE_TDM); diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 4e329dd..26ef530 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T208XQDS +if TARGET_T2080QDS || TARGET_T2081QDS config SYS_BOARD default "t208xqds" diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index 845af3d..71e1130 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T208XRDB +if TARGET_T2080RDB config SYS_BOARD default "t208xrdb" diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig index 27a64b6..563a87c 100644 --- a/board/freescale/t4qds/Kconfig +++ b/board/freescale/t4qds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T4240QDS +if TARGET_T4160QDS || TARGET_T4240QDS config SYS_BOARD default "t4qds" diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 731ccb0..1eacbcc 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -7,7 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o +obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o +obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig index d93e453..67832da 100644 --- a/board/freescale/t4rdb/Kconfig +++ b/board/freescale/t4rdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T4240RDB +if TARGET_T4160RDB || TARGET_T4240RDB config SYS_BOARD default "t4rdb" diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 4f29eea..209983a 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -7,7 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o +obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index ffd6d31..22e87a2 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -8,6 +8,7 @@ #include <inttypes.h> #include <config.h> #include <dm.h> +#include <efi_loader.h> #include <fdt_support.h> #include <fdt_simplefb.h> #include <lcd.h> @@ -17,7 +18,6 @@ #include <asm/arch/mbox.h> #include <asm/arch/sdhci.h> #include <asm/global_data.h> -#include <dm/platform_data/serial_pl01x.h> #include <dm/platform_data/serial_bcm283x_mu.h> #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> @@ -28,42 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; /* From lowlevel_init.S */ extern unsigned long fw_dtb_pointer; -static const struct bcm2835_gpio_platdata gpio_platdata = { - .base = BCM2835_GPIO_BASE, -}; - -U_BOOT_DEVICE(bcm2835_gpios) = { - .name = "gpio_bcm2835", - .platdata = &gpio_platdata, -}; - -#ifdef CONFIG_PL01X_SERIAL -static const struct pl01x_serial_platdata serial_platdata = { -#ifndef CONFIG_BCM2835 - .base = 0x3f201000, -#else - .base = 0x20201000, -#endif - .type = TYPE_PL011, - .skip_init = true, -}; - -U_BOOT_DEVICE(bcm2835_serials) = { - .name = "serial_pl01x", - .platdata = &serial_platdata, -}; -#else -static struct bcm283x_mu_serial_platdata serial_platdata = { - .base = 0x3f215040, - .clock = 250000000, - .skip_init = true, -}; - -U_BOOT_DEVICE(bcm2837_serials) = { - .name = "serial_bcm283x_mu", - .platdata = &serial_platdata, -}; -#endif struct msg_get_arm_mem { struct bcm2835_mbox_hdr hdr; @@ -472,15 +436,6 @@ static void get_board_rev(void) printf("RPI %s (0x%x)\n", model->name, revision); } -int board_init(void) -{ - get_board_rev(); - - gd->bd->bi_boot_params = 0x100; - - return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); -} - #ifndef CONFIG_PL01X_SERIAL static bool rpi_is_serial_active(void) { @@ -500,17 +455,38 @@ static bool rpi_is_serial_active(void) return true; } + +/* Disable mini-UART I/O if it's not pinmuxed to our pins. + * The firmware only enables it if explicitly done in config.txt: enable_uart=1 + */ +static void rpi_disable_inactive_uart(void) +{ + struct udevice *dev; + struct bcm283x_mu_serial_platdata *plat; + + if (uclass_get_device_by_driver(UCLASS_SERIAL, + DM_GET_DRIVER(serial_bcm283x_mu), + &dev) || !dev) + return; + + if (!rpi_is_serial_active()) { + plat = dev_get_platdata(dev); + plat->disabled = true; + } +} #endif -int board_early_init_f(void) +int board_init(void) { #ifndef CONFIG_PL01X_SERIAL - /* Disable mini-UART I/O if it's not pinmuxed to our pins */ - if (!rpi_is_serial_active()) - serial_platdata.disabled = true; + rpi_disable_inactive_uart(); #endif - return 0; + get_board_rev(); + + gd->bd->bi_boot_params = 0x100; + + return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); } int board_mmc_init(bd_t *bis) @@ -543,5 +519,10 @@ int ft_board_setup(void *blob, bd_t *bd) */ lcd_dt_simplefb_add_node(blob); +#ifdef CONFIG_EFI_LOADER + /* Reserve the spin table */ + efi_add_memory_map(0, 1, EFI_RESERVED_MEMORY_TYPE, 0); +#endif + return 0; } diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c index bcadc67..fc2192a 100644 --- a/board/varisys/cyrus/eth.c +++ b/board/varisys/cyrus/eth.c @@ -19,7 +19,7 @@ #define FIRST_PORT_ADDR 3 #define SECOND_PORT_ADDR 7 -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 #define FIRST_PORT FM1_DTSEC5 #define SECOND_PORT FM2_DTSEC5 #else @@ -83,7 +83,7 @@ int board_eth_init(bd_t *bis) fm_disable_port(i); } -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 65d321a..db1f029 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -6,9 +6,9 @@ # obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o -obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o +obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o -obj-$(CONFIG_P2020) += fsl_8xxx_clk.o +obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index 2a604d4..e102b0c 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -22,7 +22,7 @@ unsigned long get_board_sys_clk(ulong dummy) if (in_be32(&gur->gpporcr) & 0x10000) return 66666666; else -#ifdef CONFIG_P2020 +#ifdef CONFIG_ARCH_P2020 return 100000000; #else return 50000000; @@ -42,7 +42,7 @@ unsigned long get_board_ddr_clk(ulong dummy) if (ddr_ratio == 0x7) return get_board_sys_clk(dummy); -#ifdef CONFIG_P2020 +#ifdef CONFIG_ARCH_P2020 if (in_be32(&gur->gpporcr) & 0x20000) return 66666666; else diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 510f638..6237571 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -55,7 +55,7 @@ void pci_init_board(void) } else { printf("PCI1: disabled\n"); } -#elif defined CONFIG_MPC8548 +#elif defined CONFIG_ARCH_MPC8548 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* PCI1 not present on MPC8572 */ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); |