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-rw-r--r--board/xilinx/microblaze-generic/xparameters.h11
-rw-r--r--board/xilinx/zynq/board.c13
-rw-r--r--board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c1577
-rw-r--r--board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h9
-rw-r--r--board/xilinx/zynqmp/MAINTAINERS7
-rw-r--r--board/xilinx/zynqmp/zynqmp.c125
6 files changed, 1483 insertions, 259 deletions
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index ccb528e..dc5645b 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -13,21 +13,10 @@
#define XILINX_BOARD_NAME microblaze-generic
-/* System Clock Frequency */
-#define XILINX_CLOCK_FREQ 100000000
-
/* Microblaze is microblaze_0 */
#define XILINX_USE_MSR_INSTR 1
#define XILINX_FSL_NUMBER 3
-/* Interrupt controller is opb_intc_0 */
-#define XILINX_INTC_BASEADDR 0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS 6
-
-/* Timer pheriphery is opb_timer_1 */
-#define XILINX_TIMER_BASEADDR 0x41c00000
-#define XILINX_TIMER_IRQ 0
-
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 2f17e97..4c20450 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -98,6 +98,19 @@ int checkboard(void)
}
#endif
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+ defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+ if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+ ethaddr, 6))
+ printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+ return 0;
+}
+
int dram_init(void)
{
int node;
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
index 2c0feca..83daf7b 100644
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
@@ -310,11 +310,11 @@ unsigned long ps7_clock_init_data_3_0[] = {
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
@@ -339,39 +339,39 @@ unsigned long ps7_clock_init_data_3_0[] = {
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -667,9 +667,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
@@ -677,7 +677,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
@@ -2020,6 +2020,35 @@ unsigned long ps7_mio_init_data_3_0[] = {
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -2194,6 +2223,267 @@ unsigned long ps7_mio_init_data_3_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -3063,6 +3353,35 @@ unsigned long ps7_mio_init_data_3_0[] = {
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -3139,6 +3458,64 @@ unsigned long ps7_mio_init_data_3_0[] = {
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
@@ -3277,11 +3654,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
@@ -3329,29 +3706,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -3390,24 +3744,50 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
@@ -3420,6 +3800,14 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
@@ -3660,29 +4048,6 @@ unsigned long ps7_post_config_3_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
/* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
@@ -3759,6 +4124,8 @@ unsigned long ps7_post_config_3_0[] = {
/* .. .. FINISH: AFI2 REGISTERS */
/* .. .. START: AFI3 REGISTERS */
/* .. .. FINISH: AFI3 REGISTERS */
+ /* .. .. START: AFI2 SECURE REGISTER */
+ /* .. .. FINISH: AFI2 SECURE REGISTER */
/* .. FINISH: AFI REGISTERS */
/* .. START: LOCK IT BACK */
/* .. LOCK_KEY = 0X767B */
@@ -4110,11 +4477,11 @@ unsigned long ps7_clock_init_data_2_0[] = {
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
@@ -4139,39 +4506,39 @@ unsigned long ps7_clock_init_data_2_0[] = {
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -4491,9 +4858,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
@@ -4501,7 +4868,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
@@ -5981,6 +6348,35 @@ unsigned long ps7_mio_init_data_2_0[] = {
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -6155,6 +6551,267 @@ unsigned long ps7_mio_init_data_2_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -7024,6 +7681,35 @@ unsigned long ps7_mio_init_data_2_0[] = {
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -7100,6 +7786,64 @@ unsigned long ps7_mio_init_data_2_0[] = {
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
@@ -7238,11 +7982,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
@@ -7296,29 +8040,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -7357,24 +8078,50 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
@@ -7387,6 +8134,14 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
@@ -7621,29 +8376,6 @@ unsigned long ps7_post_config_2_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
/* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
@@ -8071,11 +8803,11 @@ unsigned long ps7_clock_init_data_1_0[] = {
/* .. SRCSEL = 0x0 */
/* .. ==> 0XF8000154[5:4] = 0x00000000U */
/* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000154[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
/* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
/* .. .. START: TRACE CLOCK */
/* .. .. FINISH: TRACE CLOCK */
/* .. .. CLKACT = 0x1 */
@@ -8100,39 +8832,39 @@ unsigned long ps7_clock_init_data_1_0[] = {
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x3 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
- /* .. .. DIVISOR0 = 0x6 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
- /* .. .. SRCSEL = 0x2 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
- /* .. .. DIVISOR0 = 0x35 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
- /* .. .. DIVISOR1 = 0x2 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
/* .. .. SRCSEL = 0x0 */
/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
/* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
/* .. .. DIVISOR1 = 0x1 */
/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
/* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
/* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
/* .. .. CLK_621_TRUE = 0x1 */
/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -8452,9 +9184,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
/* .. .. reg_ddrc_burst_rdwr = 0x4 */
/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
/* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
/* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
@@ -8462,7 +9194,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
/* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
/* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
/* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
@@ -9875,6 +10607,35 @@ unsigned long ps7_mio_init_data_1_0[] = {
/* .. FINISH: DDRIOB SETTINGS */
/* .. START: MIO PROGRAMMING */
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000704[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -10049,6 +10810,267 @@ unsigned long ps7_mio_init_data_1_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF8000740[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 1 */
@@ -10918,6 +11940,35 @@ unsigned long ps7_mio_init_data_1_0[] = {
/* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
/* .. TRI_ENABLE = 1 */
/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
@@ -10994,6 +12045,64 @@ unsigned long ps7_mio_init_data_1_0[] = {
/* .. */
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
/* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. L0_SEL = 0 */
@@ -11132,11 +12241,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x3e */
- /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
@@ -11190,29 +12299,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -11251,24 +12337,50 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
/* .. .. .. .. START: DIR MODE BANK 0 */
/* .. .. .. .. FINISH: DIR MODE BANK 0 */
/* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: DIR MODE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
@@ -11281,6 +12393,14 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
@@ -11515,29 +12635,6 @@ unsigned long ps7_post_config_1_0[] = {
/* .. */
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
/* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: TPIU WIDTH IN CASE OF EMIO */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0XC5ACCE55 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. .. START: TRACE CURRENT PORT SIZE */
- /* .. .. a = 2 */
- /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
- /* .. .. FINISH: TRACE CURRENT PORT SIZE */
- /* .. .. START: TRACE LOCK ACCESS REGISTER */
- /* .. .. a = 0X0 */
- /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
- /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
/* .. START: FPGA RESETS TO 0 */
/* .. reserved_3 = 0 */
/* .. ==> 0XF8000240[31:25] = 0x00000000U */
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
index 62b8a58..22d9fd9 100644
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
@@ -62,7 +62,7 @@ extern unsigned long *ps7_peripherals_init_data;
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
+#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 108333336
#define WDT_FREQ 108333336
@@ -71,9 +71,10 @@ extern unsigned long *ps7_peripherals_init_data;
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 175000000
-#define FPGA2_FREQ 12264151
-#define FPGA3_FREQ 100000000
+#define FPGA1_FREQ 142857132
+#define FPGA2_FREQ 200000000
+#define FPGA3_FREQ 50000000
+
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 20ca652..69edbf2 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,7 +1,6 @@
-XILINX_ZYNQMP_EP BOARD
+XILINX_ZYNQMP BOARDS
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
F: board/xilinx/zynqmp/
-F: include/configs/xilinx_zynqmp.h
-F: include/configs/xilinx_zynqmp_ep.h
-F: configs/xilinx_zynqmp_ep_defconfig
+F: include/configs/xilinx_zynqmp*
+F: configs/xilinx_zynqmp*
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 44d347e..087578c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <netdev.h>
+#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clk.h>
@@ -50,12 +51,133 @@ int board_early_init_r(void)
return 0;
}
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+ const u32 *cell, int n)
+{
+ int i = 0, b, banks;
+ int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+ int address_cells = fdt_address_cells(fdt, parent_offset);
+ int size_cells = fdt_size_cells(fdt, parent_offset);
+ char *p = buf;
+ phys_addr_t val;
+ phys_size_t vals;
+
+ debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+ __func__, address_cells, size_cells, buf, cell);
+
+ /* Check memory bank setup */
+ banks = n % (address_cells + size_cells);
+ if (banks)
+ panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+ n, address_cells, size_cells);
+
+ banks = n / (address_cells + size_cells);
+
+ for (b = 0; b < banks; b++) {
+ debug("%s: Bank #%d:\n", __func__, b);
+ if (address_cells == 2) {
+ val = cell[i + 1];
+ val <<= 32;
+ val |= cell[i];
+ val = fdt64_to_cpu(val);
+ debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+ __func__, val, p, &cell[i]);
+ *(phys_addr_t *)p = val;
+ } else {
+ debug("%s: addr32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_addr_t);
+ i += address_cells;
+
+ debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+ sizeof(phys_addr_t));
+
+ if (size_cells == 2) {
+ vals = cell[i + 1];
+ vals <<= 32;
+ vals |= cell[i];
+ vals = fdt64_to_cpu(vals);
+
+ debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+ __func__, vals, p, &cell[i]);
+ *(phys_size_t *)p = vals;
+ } else {
+ debug("%s: size32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_size_t);
+ i += size_cells;
+
+ debug("%s: ps=%p, i=%x, size=%zu\n",
+ __func__, p, i, sizeof(phys_size_t));
+ }
+
+ /* Return the first address size */
+ return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+ int bank;
+
+ memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ debug("Bank #%d: start %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start);
+ debug("Bank #%d: size %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+ }
+}
+
+int dram_init(void)
+{
+ int node, len;
+ const void *blob = gd->fdt_blob;
+ const u32 *cell;
+
+ memset(&tmp, 0, sizeof(tmp));
+
+ /* find or create "/memory" node. */
+ node = fdt_subnode_offset(blob, 0, "memory");
+ if (node < 0) {
+ printf("%s: Can't get memory node\n", __func__);
+ return node;
+ }
+
+ /* Get pointer to cells and lenght of it */
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell) {
+ printf("%s: Can't get reg property\n", __func__);
+ return -1;
+ }
+
+ gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+ debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+
+ return 0;
+}
+#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+#endif
void reset_cpu(ulong addr)
{
@@ -64,6 +186,9 @@ void reset_cpu(ulong addr)
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
+#if defined(CONFIG_SATA_CEVA)
+ init_sata(0);
+#endif
ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
scsi_scan(1);
}
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