diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/amcc/ebony/Kconfig | 16 | ||||
| -rw-r--r-- | board/amcc/ebony/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/amcc/ebony/Makefile | 9 | ||||
| -rw-r--r-- | board/amcc/ebony/README | 136 | ||||
| -rw-r--r-- | board/amcc/ebony/config.mk | 16 | ||||
| -rw-r--r-- | board/amcc/ebony/ebony.c | 151 | ||||
| -rw-r--r-- | board/amcc/ebony/flash.c | 155 | ||||
| -rw-r--r-- | board/amcc/ebony/init.S | 41 |
8 files changed, 0 insertions, 530 deletions
diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig deleted file mode 100644 index ba73148..0000000 --- a/board/amcc/ebony/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_EBONY - -config SYS_BOARD - default "ebony" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "ebony" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/ebony/MAINTAINERS b/board/amcc/ebony/MAINTAINERS deleted file mode 100644 index bc62851..0000000 --- a/board/amcc/ebony/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EBONY BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/ebony/ -F: include/configs/ebony.h -F: configs/ebony_defconfig diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile deleted file mode 100644 index 5876486..0000000 --- a/board/amcc/ebony/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ebony.o flash.o -extra-y += init.o diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README deleted file mode 100644 index 4df00b3..0000000 --- a/board/amcc/ebony/README +++ /dev/null @@ -1,136 +0,0 @@ - AMCC Ebony Board - - Last Update: September 12, 2002 -======================================================================= - -This file contains some handy info regarding U-Boot and the AMCC -Ebony evaluation board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Here's what I've been using successfully. If you feel inclined to -change things ... please read the docs! - -DIPSW U46 U80 ------------------------- -SW 1 off on -SW 2 on on -SW 3 on on -SW 4 off on -SW 5 on off -SW 6 on on -SW 7 on off -SW 8 on off - -J41: strapped -J42: open - -All others are factory default. - - -I2C probe -===================== - -The i2c utilities have been tested on both Rev B. and Rev C. and -look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent -probing the CDCV850 clock controller at address 0x69 (since reading -it causes the i2c implementation to misbehave. The output of -'i2c probe' should look like this (assuming you are only using a single -SO-DIMM: - -=> i2c probe -Valid chip addresses: 50 53 54 -Excluded chip addresses: 69 - - -GETTING OUT OF I2C TROUBLE -=========================== - -If you're like me ... you may have screwed up your bootstrap serial -eeprom ... or worse, your SPD eeprom when experimenting with the -i2c commands. If so, here are some ideas on how to get out of -trouble: - -Serial bootstrap eeprom corruption: ------------------------------------ -Power down the board and set the following straps: - -J41 - open -J42 - strapped - -This will select the default sys0 and sys1 settings (the serial -eeproms are not used). Then power up the board and fix the serial -eeprom using the 'i2c mm' command. Here are the values I currently -use: - -=> i2c md 50 0 10 -0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ - -=> i2c md 54 0 10 -0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... - -Once you have the eeproms set correctly change the -J41/J42 straps as you desire. - -SPD eeprom corruption: ------------------------- -I've corrupted the SPD eeprom several times ... perhaps too much coffee -and not enough presence of mind ;-). By default, the ebony code uses -the SPD to initialize the DDR SDRAM control registers. So if the SPD -eeprom is corrupted, U-Boot will never get into ram. Here's how I got -out of this situation: - -0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then -use 'i2c md' to capture the various device contents to a file. Some day -you may be glad you did this ... trust me :-). Otherwise try the -following: - -1. In the include/configs/EBONY.h file find the line that defines -the CONFIG_SPD_EEPROM macro and undefine it. E.g: - -#undef CONFIG_SPD_EEPROM - -This will make the code use default SDRAM control register -settings without using the SPD eeprom. - -2. Rebuild U-Boot - -3. Load the new U-Boot image and reboot ebony. - -4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom -contents that work with the default SO-DIMM that comes with the -ebony board (micron 8VDDT164AG-265A1). Note: these are probably -_not_ the factory settings ... but they work. - -=> i2c md 53 0 10 80 -0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... -0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- -0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. -0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ -0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 -0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c -0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. -0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ - - -PCI DOUBLE-ENUMERATION WOES -=========================== - -If you're not using PCI-X cards and are simply using 32-bit and/or -33 MHz cards via extenders and the like, you may notice that the -initial pci scan reports various devices twice ... and configuration -does not succeed (one or more devices are enumerated twice). To correct -this we replaced the 2K ohm resistor on the IDSEL line(s) with a -22 ohm resistor and the problem went away. This change hasn't broken -anything yet -- use at your own risk. - -We never tested anything other than 33 MHz/32-bit cards. If you have -the chance to do this, please let me know how things turn out :-) - - -Regards, ---Scott -<smcnutt@artesyncp.com> diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk deleted file mode 100644 index f18b097..0000000 --- a/board/amcc/ebony/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c deleted file mode 100644 index eb42448..0000000 --- a/board/amcc/ebony/ebony.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram(void); - -int board_early_init_f(void) -{ - uint reg; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char status; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ - mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(PB7AP, 0x01015280); /* FPGA registers */ - mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ - - /* read FPGA_REG0 and set the bus controller */ - status = *fpga_base; - if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ - } else { - mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ - - /* set CS2 if FLASH_ONBD_N == 0 */ - if (!(status & FLASH_ONBD_N)) { - mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ - } - } - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -phys_size_t initdram(int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(); -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram(SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c deleted file mode 100644 index 5740a56..0000000 --- a/board/amcc/ebony/flash.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -/* - * Override the weak default mapping function with a board specific one - */ -u32 flash_get_bank_size(int cs, int idx) -{ - u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE); - - if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) { - /* - * cs0: small flash (512KiB) - * cs2: 2 * big flash (2 * 2MiB) - */ - if (cs == 0) - return flash_info[2].size; - if (cs == 2) - return flash_info[0].size + flash_info[1].size; - } else { - /* - * cs0: 2 * big flash (2 * 2MiB) - * cs2: small flash (512KiB) - */ - if (cs == 0) - return flash_info[0].size + flash_info[1].size; - if (cs == 2) - return flash_info[2].size; - } - - return 0; -} - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S deleted file mode 100644 index 904e648..0000000 --- a/board/amcc/ebony/init.S +++ /dev/null @@ -1,41 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end |