diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6qarm2/mt128x64mx32.cfg | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg index 0f9940d..3433fd3 100644 --- a/board/freescale/mx6qarm2/mt128x64mx32.cfg +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -134,9 +134,9 @@ DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up DATA 4 0x021b001c 0x00008000 // Chan 0 DATA 4 0x021b401c 0x00008000 // Chan 1 - -DATA 4 0x021b085c 0x1b5f0109 //LPDDR2 ZQ params -DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params +// Adjust ZQ delay for MMDC clock frequency at 400MHz +DATA 4 0x021b085c 0x1b4700c7 //LPDDR2 ZQ params +DATA 4 0x021b485c 0x1b4700c7 //LPDDR2 ZQ params //============================================================================= // Calibration setup. @@ -228,6 +228,13 @@ DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END // DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL +// Precharge all commands per JEDEC +// The memory controller may optionally issue a Precharge-All command +// prior to the MRW Reset command. +// This is strongly recommended to ensure a robust DRAM initialization +DATA 4 0x021b001c 0x00008010 // precharge-all commnad CS0 - Chan 0 +DATA 4 0x021b401c 0x00008010 // precharge-all commnad CS0 - Chan 1 + //============================================================================= // LPDDR2 Mode Register Writes //============================================================================= |