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-rw-r--r--board/freescale/common/Makefile10
-rw-r--r--board/freescale/common/arm_sleep.c95
-rw-r--r--board/freescale/common/ls102xa_stream_id.c18
-rw-r--r--board/freescale/common/mpc85xx_sleep.c88
-rw-r--r--board/freescale/common/ns_access.c30
-rw-r--r--board/freescale/common/qixis.h7
-rw-r--r--board/freescale/common/sleep.h21
-rw-r--r--board/freescale/ls1021aqds/MAINTAINERS3
-rw-r--r--board/freescale/ls1021aqds/ddr.c5
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c283
-rw-r--r--board/freescale/ls1021aqds/ls102xa_pbi.cfg12
-rw-r--r--board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg7
-rw-r--r--board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg14
-rw-r--r--board/freescale/ls1021atwr/MAINTAINERS2
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c151
-rw-r--r--board/freescale/ls1021atwr/ls102xa_pbi.cfg12
-rw-r--r--board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg14
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c49
-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c50
19 files changed, 854 insertions, 17 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 59ddeef..14af660 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -37,6 +37,12 @@ endif
obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
+endif
+
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
@@ -56,10 +62,14 @@ obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
+obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
obj-$(CONFIG_P3041DS) += p_corenet/
obj-$(CONFIG_P4080DS) += p_corenet/
obj-$(CONFIG_P5020DS) += p_corenet/
obj-$(CONFIG_P5040DS) += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
endif
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
new file mode 100644
index 0000000..8edf878
--- /dev/null
+++ b/board/freescale/common/arm_sleep.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#error " Deep sleep needs non-secure mode support. "
+#else
+#include <asm/secure.h>
+#endif
+#include <asm/armv7.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_LS102XA)
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_le32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache_all();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+ board_sleep_prepare();
+ armv7_init_nonsec();
+ cleanup_before_linux();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_le32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+ return 0;
+}
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
new file mode 100644
index 0000000..6154c9c
--- /dev/null
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+ uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ for (i = 0; i < num; i++)
+ out_be32(scfg + id[i].offset, id[i].stream_id);
+}
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
new file mode 100644
index 0000000..f924e7f
--- /dev/null
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ volatile u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_be32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+
+ board_sleep_prepare();
+
+ l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
+ enable_cpc();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_be32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ kernel_resume();
+
+ return 0;
+}
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
new file mode 100644
index 0000000..d7de982
--- /dev/null
+++ b/board/freescale/common/ns_access.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+ u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *reg;
+ uint32_t val;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ reg = base + ns_dev[i].ind / 2;
+ val = in_be32(reg);
+ if (ns_dev[i].ind % 2 == 0) {
+ val &= 0x0000ffff;
+ val |= ns_dev[i].val << 16;
+ } else {
+ val &= 0xffff0000;
+ val |= ns_dev[i].val;
+ }
+ out_be32(reg, val);
+ }
+}
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index d8fed14..52d2021 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg);
void qixis_write_i2c(unsigned int reg, u8 value);
#endif
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#else
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
#define QIXIS_WRITE_I2C(reg, value) \
diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h
new file mode 100644
index 0000000..c26c542
--- /dev/null
+++ b/board/freescale/common/sleep.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SLEEP_H
+#define __SLEEP_H
+
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+#define DDR_BUFF_LEN 128
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* disable console output */
+void fsl_dp_disable_console(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+#endif
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index e30e944..638833d 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -6,3 +6,6 @@ F: include/configs/ls1021aqds.h
F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_sdcard_defconfig
+F: configs/ls1021aqds_qspi_defconfig
+F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 5898e33..a539ff9 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -153,9 +153,12 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
-
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 0a7720a..f08e54f 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -8,12 +8,17 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
+#include <hwconfig.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
+#include <spl.h>
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
@@ -21,9 +26,22 @@
#include "../../../drivers/qe/qe.h"
#endif
+#define PIN_MUX_SEL_CAN 0x03
+#define PIN_MUX_SEL_IIC2 0xa0
+#define PIN_MUX_SEL_RGMII 0x00
+#define PIN_MUX_SEL_SAI 0x0c
+#define PIN_MUX_SEL_SDHC 0x00
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
+#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;
enum {
+ MUX_TYPE_CAN,
+ MUX_TYPE_IIC2,
+ MUX_TYPE_RGMII,
+ MUX_TYPE_SAI,
+ MUX_TYPE_SDHC,
MUX_TYPE_SD_PCI4,
MUX_TYPE_SD_PC_SA_SG_SG,
MUX_TYPE_SD_PC_SA_PC_SG,
@@ -32,11 +50,20 @@ enum {
int checkboard(void)
{
+#ifndef CONFIG_QSPI_BOOT
char buf[64];
+#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
u8 sw;
+#endif
puts("Board: LS1021AQDS\n");
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#elif CONFIG_QSPI_BOOT
+ puts("QSPI\n");
+#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -50,13 +77,16 @@ int checkboard(void)
printf("IFCCard\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+#ifndef CONFIG_QSPI_BOOT
printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
printf("FPGA: v%d (%s), build %d\n",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
+#endif
return 0;
}
@@ -101,8 +131,27 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int dram_init(void)
{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
return 0;
@@ -121,19 +170,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@@ -148,6 +184,10 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -158,13 +198,75 @@ int board_early_init_f(void)
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_NAND_BOOT
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 porsr1, pinctl;
+
+ /*
+ * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+ DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ pinctl);
+#endif
+
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+
+ get_clocks();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init_all();
+#endif
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
int config_board_mux(int ctrl_type)
{
- u8 reg12;
+ u8 reg12, reg14;
reg12 = QIXIS_READ(brdcfg[12]);
+ reg14 = QIXIS_READ(brdcfg[14]);
switch (ctrl_type) {
+ case MUX_TYPE_CAN:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
+ break;
+ case MUX_TYPE_IIC2:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
+ break;
+ case MUX_TYPE_RGMII:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
+ break;
+ case MUX_TYPE_SAI:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
+ break;
+ case MUX_TYPE_SDHC:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
+ break;
case MUX_TYPE_SD_PCI4:
reg12 = 0x38;
break;
@@ -183,6 +285,7 @@ int config_board_mux(int ctrl_type)
}
QIXIS_WRITE(brdcfg[12], reg12);
+ QIXIS_WRITE(brdcfg[14], reg14);
return 0;
}
@@ -216,15 +319,154 @@ int config_serdes_mux(void)
return 0;
}
-#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
+ int conflict_flag;
+
+ /* some signals can not enable simultaneous*/
+ conflict_flag = 0;
+ if (hwconfig("sdhc"))
+ conflict_flag++;
+ if (hwconfig("iic2"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("rgmii"))
+ conflict_flag++;
+ if (hwconfig("can"))
+ conflict_flag++;
+ if (hwconfig("sai"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ if (hwconfig("can"))
+ config_board_mux(MUX_TYPE_CAN);
+ else if (hwconfig("rgmii"))
+ config_board_mux(MUX_TYPE_RGMII);
+ else if (hwconfig("sai"))
+ config_board_mux(MUX_TYPE_SAI);
+
+ if (hwconfig("iic2"))
+ config_board_mux(MUX_TYPE_IIC2);
+ else if (hwconfig("sdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
+ return 0;
}
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
#endif
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -247,6 +489,13 @@ int board_init(void)
config_serdes_mux();
#endif
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
#ifdef CONFIG_U_QE
u_qe_init();
#endif
@@ -258,6 +507,10 @@ int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
return 0;
}
diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg
new file mode 100644
index 0000000..f1a1b63
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644
index 0000000..222c71d
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..9d99bd8
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index 8def0e5..9176706 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -5,3 +5,5 @@ F: board/freescale/ls1021atwr/
F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 3e8c37b..8ab229d 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -8,8 +8,11 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
@@ -17,6 +20,7 @@
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
+#include <spl.h>
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
@@ -70,6 +74,7 @@ struct cpld_data {
u8 rev2; /* Reserved */
};
+#ifndef CONFIG_QSPI_BOOT
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -105,11 +110,14 @@ void cpld_show(void)
in_8(&cpld_data->serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
+#ifndef CONFIG_QSPI_BOOT
cpld_show();
+#endif
return 0;
}
@@ -218,6 +226,7 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifndef CONFIG_QSPI_BOOT
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +258,7 @@ int config_serdes_mux(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
@@ -267,9 +277,135 @@ int board_early_init_f(void)
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -284,8 +420,17 @@ int board_init(void)
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#ifndef CONFIG_QSPI_BOOT
config_serdes_mux();
#endif
+#endif
+
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
#ifdef CONFIG_U_QE
u_qe_init();
@@ -307,6 +452,10 @@ int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
return 0;
}
@@ -329,6 +478,7 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+#ifndef CONFIG_QSPI_BOOT
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -511,3 +661,4 @@ U_BOOT_CMD(
" -change lane C & lane D to PCIeX2\n"
"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
);
+#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
new file mode 100644
index 0000000..f1a1b63
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..9c3e3b0
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00080000 881b7340 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#20000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20084800 881b7340 00000000 00000000
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index cac6d73..3834eec 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -20,6 +20,8 @@
#include <fsl_esdhc.h>
#include <mmc.h>
#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -238,6 +240,48 @@ static int setup_fec(void)
}
#endif
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OTG1 */
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
int board_early_init_f(void)
{
@@ -256,6 +300,11 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 8b959b9..fd8bc72 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -26,6 +26,8 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -212,6 +214,49 @@ int power_init_board(void)
return 0;
}
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
int board_phy_config(struct phy_device *phydev)
{
/*
@@ -242,6 +287,10 @@ int board_early_init_f(void)
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
@@ -322,7 +371,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-
int board_init(void)
{
/* Address of boot parameters */
generated by cgit v1.1 at 2024-12-28 07:40:19 +0000