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-rw-r--r--board/dbau1x00/Makefile41
-rw-r--r--board/dbau1x00/README53
-rw-r--r--board/dbau1x00/config.mk32
-rw-r--r--board/dbau1x00/dbau1x00.c110
-rw-r--r--board/dbau1x00/flash.c43
-rw-r--r--board/dbau1x00/memsetup.S118
-rw-r--r--board/dbau1x00/u-boot.lds68
7 files changed, 465 insertions, 0 deletions
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
new file mode 100644
index 0000000..d1cdc6b
--- /dev/null
+++ b/board/dbau1x00/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = memsetup.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/dbau1x00/README b/board/dbau1x00/README
new file mode 100644
index 0000000..024fbbe
--- /dev/null
+++ b/board/dbau1x00/README
@@ -0,0 +1,53 @@
+By Thomas.Lange@corelatus.se 2003-10-06
+----------------------------------------
+DbAu1000 is a development board from AMD containing
+an Alchemy AU1000 with mips32 core.
+
+Limitations & comments
+----------------------
+I assume that you set board to BIG endian!
+Little endian not tested, most probably broken.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+some day ( dbau1000, dbau1100 and dbau1500 ).
+
+I only have a dbau1000, so all testing is limited
+to this board!
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader deliviered with board.
+
+Ethernet only supported for mac0.
+
+Pcmcia only supported for slot 0, only 3.3V.
+
+Pcmcia IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+######## NOTE!!!!!! #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk
new file mode 100644
index 0000000..39eb60a
--- /dev/null
+++ b/board/dbau1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+TEXT_BASE = 0xbfc00000
+
+# RAM version
+#TEXT_BASE = 0x80100000
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
new file mode 100644
index 0000000..3b6fcec
--- /dev/null
+++ b/board/dbau1x00/dbau1x00.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN 0x0010
+#define BCSR_PCMCIA_PC0RST 0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+ u16 status;
+ volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
+ volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ u32 proc_id;
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_32bit_cp0_register(CP0_PRID);
+
+ switch(proc_id>>24){
+ case 0:
+ puts("Board: Merlot (DbAu1000)\n");
+ printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id>>8)&0xFF,proc_id&0xFF);
+ break;
+ default:
+ printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id);
+ }
+#ifdef CONFIG_IDE_PCMCIA
+ /* Enable 3.3 V on slot 0 ( VCC )
+ No 5V */
+ status = 4;
+ *pcmcia_bcsr = status;
+
+ status |= BCSR_PCMCIA_PC0DRVEN;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(300*1000);
+
+ status |= BCSR_PCMCIA_PC0RST;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(100*1000);
+
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+
+#if 0
+ /* We dont need theese unless we run whole pcmcia package */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+#endif
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+
+ /* Release reset of ethernet PHY chips */
+ /* Always do this, because linux does not know about it */
+ *phy = 3;
+
+ return 0;
+#endif
+}
diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c
new file mode 100644
index 0000000..3cf29e8
--- /dev/null
+++ b/board/dbau1x00/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ printf ("Skipping flash_init\n");
+ return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ printf ("write_buff not implemented\n");
+ return (-1);
+}
diff --git a/board/dbau1x00/memsetup.S b/board/dbau1x00/memsetup.S
new file mode 100644
index 0000000..34ba2da
--- /dev/null
+++ b/board/dbau1x00/memsetup.S
@@ -0,0 +1,118 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+
+ .globl memsetup
+memsetup:
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 8 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+/* SDCS 0,1 SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x64000C24 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x66000C24 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ /* Static memory controller */
+
+ /* RCE0 AMD 29LV640M MirrorBit Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00000003
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0x22080b20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11E03F80
+ sw t1, 0(t0)
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ j ra
+ nop
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
new file mode 100644
index 0000000..a2d19a8
--- /dev/null
+++ b/board/dbau1x00/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
generated by cgit v1.1 at 2024-11-28 10:30:44 +0000