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-rw-r--r--board/esd/plu405/config.mk2
-rw-r--r--board/freescale/common/fsl_diu_fb.c55
-rw-r--r--board/freescale/mpc8536ds/law.c8
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c44
4 files changed, 58 insertions, 51 deletions
diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk
index 0fb4efa..0a4dbaa 100644
--- a/board/esd/plu405/config.mk
+++ b/board/esd/plu405/config.mk
@@ -25,4 +25,4 @@
# esd PLU405 boards
#
-TEXT_BASE = 0xFFFA0000
+TEXT_BASE = 0xFFF80000
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index cbee8fe..e7f077e 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007, 2010 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
@@ -26,6 +26,7 @@
#include <common.h>
#include <i2c.h>
#include <malloc.h>
+#include <asm/io.h>
#include "fsl_diu_fb.h"
@@ -267,9 +268,9 @@ int fsl_diu_init(int xres,
memset(info->screen_base, 0, info->smem_len);
- dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
- dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
- dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
+ out_be32(&dr.diu_reg->desc[0], &dummy_ad);
+ out_be32(&dr.diu_reg->desc[1], &dummy_ad);
+ out_be32(&dr.diu_reg->desc[2], &dummy_ad);
debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
@@ -331,26 +332,26 @@ int fsl_diu_init(int xres,
/* Program DIU registers */
- hw->gamma = (unsigned int) gamma.paddr;
- hw->cursor= (unsigned int) cursor.paddr;
- hw->bgnd = 0x007F7F7F; /* BGND */
- hw->bgnd_wb = 0; /* BGND_WB */
- hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
- hw->wb_size = 0; /* WB SIZE */
- hw->wb_mem_addr = 0; /* WB MEM ADDR */
- hw->hsyn_para = var->left_margin << 22 | /* BP_H */
+ out_be32(&hw->gamma, gamma.paddr);
+ out_be32(&hw->cursor, cursor.paddr);
+ out_be32(&hw->bgnd, 0x007F7F7F);
+ out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
+ out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */
+ out_be32(&hw->wb_size, 0); /* WB SIZE */
+ out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
+ out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */
var->hsync_len << 11 | /* PW_H */
- var->right_margin; /* FP_H */
- hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
- var->vsync_len << 11 | /* PW_V */
- var->lower_margin; /* FP_V */
+ var->right_margin); /* FP_H */
- hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
- hw->thresholds = 0x00037800; /* The Thresholds */
- hw->int_status = 0; /* INTERRUPT STATUS */
- hw->int_mask = 0; /* INT MASK */
- hw->plut = 0x01F5F666;
+ out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */
+ var->vsync_len << 11 | /* PW_V */
+ var->lower_margin); /* FP_V */
+ out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
+ out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
+ out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
+ out_be32(&hw->int_mask, 0); /* INT MASK */
+ out_be32(&hw->plut, 0x01F5F666);
/* Pixel Clock configuration */
debug("DIU pixclock in ps - %d\n", var->pixclock);
diu_set_pixel_clock(var->pixclock);
@@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info)
struct diu_ad *ad = &fsl_diu_fb_ad;
debug("Entered: enable_panel\n");
- if (hw->desc[0] != (unsigned int)ad)
- hw->desc[0] = (unsigned int)ad;
+ if (in_be32(&hw->desc[0]) != (u32)ad)
+ out_be32(&hw->desc[0], ad);
debug("desc[0] = 0x%x\n", hw->desc[0]);
return 0;
}
@@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info)
struct diu *hw = dr.diu_reg;
debug("Entered: disable_panel\n");
- if (hw->desc[0] != (unsigned int)&dummy_ad)
- hw->desc[0] = (unsigned int)&dummy_ad;
+ if (in_be32(&hw->desc[0]) != (u32)&dummy_ad)
+ out_be32(&hw->desc[0], &dummy_ad);
return 0;
}
@@ -443,7 +444,7 @@ static void enable_lcdc(void)
debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
if (!fb_enabled) {
- hw->diu_mode = dr.mode;
+ out_be32(&hw->diu_mode, dr.mode);
fb_enabled++;
}
debug("diu_mode = %d\n", hw->diu_mode);
@@ -455,7 +456,7 @@ static void disable_lcdc(void)
debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
if (fb_enabled) {
- hw->diu_mode = 0;
+ out_be32(&hw->diu_mode, 0);
fb_enabled = 0;
}
}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 1f11563..61b7454 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -28,15 +28,7 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
- SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 253ed18..1968106 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,6 +30,7 @@
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
+#include <asm/fsl_serdes.h>
#include <spd.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -219,9 +220,13 @@ void pci_init_board(void)
puts("\n");
#ifdef CONFIG_PCIE3
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+ pcie_configured = is_serdes_configured(PCIE3);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+ LAW_TRGT_IF_PCIE_3);
+ set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_3);
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
@@ -239,9 +244,13 @@ void pci_init_board(void)
#endif
#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ pcie_configured = is_serdes_configured(PCIE1);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
+ LAW_TRGT_IF_PCIE_1);
+ set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_1);
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
@@ -259,9 +268,13 @@ void pci_init_board(void)
#endif
#ifdef CONFIG_PCIE2
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+ pcie_configured = is_serdes_configured(PCIE2);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+ set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
+ LAW_TRGT_IF_PCIE_2);
+ set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_2);
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
@@ -285,6 +298,10 @@ void pci_init_board(void)
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
+ LAW_TRGT_IF_PCI);
+ set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCI);
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
@@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy)
}
#endif
-int sata_initialize(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint sdrs2_io_sel =
- (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
- if (sdrs2_io_sel & 0x04)
- return 1;
-
- return __sata_initialize();
-}
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#else
+ ft_fsl_pci_setup(blob, "pci0", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#else
+ ft_fsl_pci_setup(blob, "pci1", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#else
+ ft_fsl_pci_setup(blob, "pci2", NULL);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
+#else
+ ft_fsl_pci_setup(blob, "pci3", NULL);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
generated by cgit v1.1 at 2024-11-23 11:52:23 +0000