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-rw-r--r--board/Marvell/guruplug/config.mk27
-rw-r--r--board/Marvell/guruplug/guruplug.c6
-rw-r--r--board/Marvell/mv88f6281gtw_ge/config.mk28
-rw-r--r--board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c6
-rw-r--r--board/Marvell/openrd_base/config.mk33
-rw-r--r--board/Marvell/openrd_base/openrd_base.c6
-rw-r--r--board/Marvell/rd6281a/config.mk28
-rw-r--r--board/Marvell/rd6281a/rd6281a.c6
-rw-r--r--board/Marvell/sheevaplug/config.mk28
-rw-r--r--board/Marvell/sheevaplug/sheevaplug.c6
-rw-r--r--board/a4m072/a4m072.c62
-rw-r--r--board/amcc/bamboo/init.S1
-rw-r--r--board/amcc/bluestone/init.S1
-rw-r--r--board/amcc/canyonlands/init.S1
-rw-r--r--board/amcc/sequoia/init.S1
-rw-r--r--board/amcc/yosemite/init.S1
-rw-r--r--board/barco/early_init.S1
-rw-r--r--board/bct-brettl2/cled.c2
-rw-r--r--board/cerf250/Makefile10
-rw-r--r--board/cerf250/cerf250.c22
-rw-r--r--board/cerf250/config.mk5
-rw-r--r--board/cerf250/lowlevel_init.S411
-rw-r--r--board/colibri_pxa270/Makefile10
-rw-r--r--board/colibri_pxa270/colibri_pxa270.c18
-rw-r--r--board/colibri_pxa270/config.mk1
-rw-r--r--board/cradle/Makefile10
-rw-r--r--board/cradle/config.mk2
-rw-r--r--board/cradle/cradle.c30
-rw-r--r--board/cradle/lowlevel_init.S515
-rw-r--r--board/csb226/Makefile10
-rw-r--r--board/csb226/config.mk15
-rw-r--r--board/csb226/csb226.c22
-rw-r--r--board/csb226/lowlevel_init.S437
-rw-r--r--board/davedenx/qong/fpga.c1
-rw-r--r--board/davinci/common/misc.c10
-rw-r--r--board/davinci/da8xxevm/config.mk43
-rw-r--r--board/delta/config.mk1
-rw-r--r--board/delta/delta.c378
-rw-r--r--board/delta/lowlevel_init.S146
-rw-r--r--board/delta/nand.c558
-rw-r--r--board/esd/du440/init.S1
-rw-r--r--board/esd/pmc440/init.S1
-rw-r--r--board/fads/fads.h5
-rw-r--r--board/freescale/mx51evk/config.mk1
-rw-r--r--board/freescale/mx51evk/mx51evk.c14
-rw-r--r--board/gdsys/405ep/405ep.c93
-rw-r--r--board/gdsys/405ep/Makefile (renamed from board/delta/Makefile)14
-rw-r--r--board/gdsys/405ep/io.c181
-rw-r--r--board/gdsys/405ep/iocon.c236
-rw-r--r--board/gdsys/common/Makefile (renamed from board/wepep250/Makefile)19
-rw-r--r--board/gdsys/common/fpga.h (renamed from board/palmtc/lowlevel_init.S)30
-rw-r--r--board/gdsys/common/miiphybb.c102
-rw-r--r--board/gdsys/common/osd.c247
-rw-r--r--board/gdsys/common/osd.h (renamed from board/trizepsiv/pxavoltage.S)12
-rw-r--r--board/gdsys/gdppc440etx/init.S1
-rw-r--r--board/gdsys/intip/init.S1
-rw-r--r--board/hidden_dragon/early_init.S1
-rw-r--r--board/icecube/icecube.c2
-rw-r--r--board/innokom/Makefile10
-rw-r--r--board/innokom/config.mk15
-rw-r--r--board/innokom/innokom.c23
-rw-r--r--board/innokom/lowlevel_init.S437
-rw-r--r--board/isee/igep0030/config.mk1
-rw-r--r--board/keymile/km_arm/config.mk28
-rw-r--r--board/keymile/km_arm/km_arm.c39
-rw-r--r--board/korat/init.S1
-rw-r--r--board/lubbock/Makefile10
-rw-r--r--board/lubbock/config.mk3
-rw-r--r--board/lubbock/lowlevel_init.S411
-rw-r--r--board/lubbock/lubbock.c22
-rw-r--r--board/lwmon5/init.S1
-rw-r--r--board/mpl/vcma9/vcma9.c41
-rw-r--r--board/netstal/hcu4/Makefile20
-rw-r--r--board/netstal/hcu5/Makefile17
-rw-r--r--board/netstal/mcu25/Makefile20
-rw-r--r--board/palmld/Makefile10
-rw-r--r--board/palmld/config.mk1
-rw-r--r--board/palmld/lowlevel_init.S45
-rw-r--r--board/palmld/palmld.c16
-rw-r--r--board/palmld/u-boot.lds56
-rw-r--r--board/palmtc/Makefile9
-rw-r--r--board/palmtc/config.mk1
-rw-r--r--board/palmtc/palmtc.c13
-rw-r--r--board/palmtc/u-boot.lds56
-rw-r--r--board/pcs440ep/init.S1
-rw-r--r--board/pleb2/Makefile10
-rw-r--r--board/pleb2/config.mk3
-rw-r--r--board/pleb2/lowlevel_init.S488
-rw-r--r--board/pleb2/pleb2.c22
-rw-r--r--board/prodrive/alpr/init.S1
-rw-r--r--board/pxa255_idp/Makefile10
-rw-r--r--board/pxa255_idp/config.mk3
-rw-r--r--board/pxa255_idp/lowlevel_init.S496
-rw-r--r--board/pxa255_idp/pxa_idp.c23
-rw-r--r--board/renesas/sh7785lcr/config.mk4
-rw-r--r--board/samsung/goni/goni.c2
-rw-r--r--board/samsung/smdk2400/smdk2400.c28
-rw-r--r--board/samsung/smdk2410/smdk2410.c36
-rw-r--r--board/sandpoint/early_init.S1
-rw-r--r--board/sbc2410x/sbc2410x.c44
-rw-r--r--board/t3corp/init.S1
-rw-r--r--board/trab/cmd_trab.c28
-rw-r--r--board/trab/rs485.c40
-rw-r--r--board/trab/trab.c67
-rw-r--r--board/trab/trab_fkt.c142
-rw-r--r--board/trab/tsc2000.c39
-rw-r--r--board/trab/tsc2000.h86
-rw-r--r--board/trab/vfd.c90
-rw-r--r--board/trizepsiv/Makefile10
-rw-r--r--board/trizepsiv/config.mk3
-rw-r--r--board/trizepsiv/conxs.c23
-rw-r--r--board/trizepsiv/lowlevel_init.S503
-rw-r--r--board/ttcontrol/vision2/config.mk4
-rw-r--r--board/ttcontrol/vision2/vision2.c82
-rw-r--r--board/wepep250/config.mk11
-rw-r--r--board/wepep250/flash.c324
-rw-r--r--board/wepep250/intel.h99
-rw-r--r--board/wepep250/lowlevel_init.S145
-rw-r--r--board/wepep250/wepep250.c68
-rw-r--r--board/xaeniax/Makefile10
-rw-r--r--board/xaeniax/config.mk2
-rw-r--r--board/xaeniax/lowlevel_init.S424
-rw-r--r--board/xaeniax/xaeniax.c22
-rw-r--r--board/xes/common/Makefile4
-rw-r--r--board/xes/common/board.c64
-rw-r--r--board/xes/common/fsl_8xxx_clk.c11
-rw-r--r--board/xes/common/fsl_8xxx_misc.c60
-rw-r--r--board/xes/common/fsl_8xxx_misc.h (renamed from board/colibri_pxa270/lowlevel_init.S)24
-rw-r--r--board/xes/common/fsl_8xxx_pci.c328
-rw-r--r--board/xes/xpedite517x/Makefile (renamed from board/xes/xpedite5170/Makefile)0
-rw-r--r--board/xes/xpedite517x/ddr.c (renamed from board/xes/xpedite5170/ddr.c)0
-rw-r--r--board/xes/xpedite517x/law.c (renamed from board/xes/xpedite5170/law.c)0
-rw-r--r--board/xes/xpedite517x/xpedite517x.c (renamed from board/xes/xpedite5170/xpedite5170.c)20
-rw-r--r--board/xes/xpedite520x/Makefile (renamed from board/xes/xpedite5200/Makefile)0
-rw-r--r--board/xes/xpedite520x/ddr.c (renamed from board/xes/xpedite5200/ddr.c)0
-rw-r--r--board/xes/xpedite520x/law.c (renamed from board/xes/xpedite5200/law.c)0
-rw-r--r--board/xes/xpedite520x/tlb.c (renamed from board/xes/xpedite5200/tlb.c)0
-rw-r--r--board/xes/xpedite520x/xpedite520x.c (renamed from board/xes/xpedite5200/xpedite5200.c)27
-rw-r--r--board/xes/xpedite537x/Makefile (renamed from board/xes/xpedite5370/Makefile)0
-rw-r--r--board/xes/xpedite537x/ddr.c (renamed from board/xes/xpedite5370/ddr.c)0
-rw-r--r--board/xes/xpedite537x/law.c (renamed from board/xes/xpedite5370/law.c)0
-rw-r--r--board/xes/xpedite537x/tlb.c (renamed from board/xes/xpedite5370/tlb.c)0
-rw-r--r--board/xes/xpedite537x/xpedite537x.c (renamed from board/xes/xpedite5370/xpedite5370.c)20
-rw-r--r--board/xes/xpedite550x/Makefile39
-rw-r--r--board/xes/xpedite550x/ddr.c164
-rw-r--r--board/xes/xpedite550x/law.c54
-rw-r--r--board/xes/xpedite550x/tlb.c98
-rw-r--r--board/xes/xpedite550x/xpedite550x.c107
-rw-r--r--board/xm250/Makefile10
-rw-r--r--board/xm250/config.mk35
-rw-r--r--board/xm250/lowlevel_init.S519
-rw-r--r--board/xm250/xm250.c27
-rw-r--r--board/xsengine/Makefile51
-rw-r--r--board/xsengine/config.mk1
-rw-r--r--board/xsengine/flash.c470
-rw-r--r--board/xsengine/lowlevel_init.S221
-rw-r--r--board/xsengine/xsengine.c75
157 files changed, 2286 insertions, 8704 deletions
diff --git a/board/Marvell/guruplug/config.mk b/board/Marvell/guruplug/config.mk
deleted file mode 100644
index 12d7737..0000000
--- a/board/Marvell/guruplug/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 4df4e9b..1f0e67a 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -30,7 +30,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
@@ -96,7 +96,11 @@ int board_init(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
diff --git a/board/Marvell/mv88f6281gtw_ge/config.mk b/board/Marvell/mv88f6281gtw_ge/config.mk
deleted file mode 100644
index 761c2bb..0000000
--- a/board/Marvell/mv88f6281gtw_ge/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index 93d1400..80fd20b 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -32,7 +32,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
@@ -98,7 +98,11 @@ int board_init(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
diff --git a/board/Marvell/openrd_base/config.mk b/board/Marvell/openrd_base/config.mk
deleted file mode 100644
index 5a49280..0000000
--- a/board/Marvell/openrd_base/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
index d006b2d..10109c1 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -35,7 +35,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
@@ -102,7 +102,11 @@ int board_init(void)
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
diff --git a/board/Marvell/rd6281a/config.mk b/board/Marvell/rd6281a/config.mk
deleted file mode 100644
index 761c2bb..0000000
--- a/board/Marvell/rd6281a/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index 0d76146..e69e035 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
@@ -97,7 +97,11 @@ int board_init(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk
deleted file mode 100644
index 761c2bb..0000000
--- a/board/Marvell/sheevaplug/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 173a7b8..d7dc80c 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -30,7 +30,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
@@ -96,7 +96,11 @@ int board_init(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index ae7ccbb..09a5a51 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -270,8 +270,6 @@ static u8 display_buf[DISPLAY_BUF_SIZE];
static u8 display_putc_pos;
static u8 display_out_pos;
-static u8 display_dot_enable;
-
void display_set(int cmd) {
if (cmd & DISPLAY_CLEAR) {
@@ -281,12 +279,6 @@ void display_set(int cmd) {
if (cmd & DISPLAY_HOME) {
display_putc_pos = 0;
}
-
- if (cmd & DISPLAY_MARK) {
- display_dot_enable = 1;
- } else {
- display_dot_enable = 0;
- }
}
#define SEG_A (1<<0)
@@ -314,10 +306,12 @@ void display_set(int cmd) {
* A..Z index 10..35
* - index 36
* _ index 37
+ * . index 38
*/
#define SYMBOL_DASH (36)
#define SYMBOL_UNDERLINE (37)
+#define SYMBOL_DOT (38)
static u8 display_char2seg7_tbl[]=
{
@@ -337,28 +331,29 @@ static u8 display_char2seg7_tbl[]=
SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
SEG_A | SEG_E | SEG_F | SEG_G, /* F */
- SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* g */
+ 0, /* g - not displayed */
SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
- SEG_E | SEG_F, /* I */
- SEG_B | SEG_C | SEG_D | SEG_E, /* J */
- SEG_A, /* K - special 1 */
+ SEG_B | SEG_C, /* I */
+ 0, /* J - not displayed */
+ 0, /* K - not displayed */
SEG_D | SEG_E | SEG_F, /* L */
- SEG_B, /* m - special 2 */
- SEG_C | SEG_E | SEG_G, /* n */
- SEG_C | SEG_D | SEG_E | SEG_G, /* o */
+ 0, /* m - not displayed */
+ 0, /* n - not displayed */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
- SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, /* q */
- SEG_E | SEG_G, /* r */
+ 0, /* q - not displayed */
+ 0, /* r - not displayed */
SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
SEG_D | SEG_E | SEG_F | SEG_G, /* t */
SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
- SEG_C | SEG_D | SEG_E | SEG_F, /* V */
- SEG_C, /* w - special 3 */
- SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* X */
+ 0, /* V - not displayed */
+ 0, /* w - not displayed */
+ 0, /* X - not displayed */
SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
- SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* Z */
+ 0, /* Z - not displayed */
SEG_G, /* - */
- SEG_D /* _ */
+ SEG_D, /* _ */
+ SEG_P /* . */
};
/* Convert char to the LED segments representation */
@@ -374,23 +369,20 @@ static u8 display_char2seg7(char c)
c -= 'A' - 10;
else if (c == '-')
c = SYMBOL_DASH;
- else if ((c == '_') || (c == '.'))
+ else if (c == '_')
c = SYMBOL_UNDERLINE;
+ else if (c == '.')
+ c = SYMBOL_DOT;
else
c = ' '; /* display unsupported symbols as space */
if (c != ' ')
val = display_char2seg7_tbl[(int)c];
- /* Handle DP LED here */
- if (display_dot_enable) {
- val |= SEG_P;
- }
-
return val;
}
-static inline int display_putc_nomark(char c)
+int display_putc(char c)
{
if (display_putc_pos >= DISPLAY_BUF_SIZE)
return -1;
@@ -403,13 +395,6 @@ static inline int display_putc_nomark(char c)
return c;
}
-int display_putc(char c)
-{
- /* Mark the codes from the "display" command with the DP LED */
- display_set(DISPLAY_MARK);
- return display_putc_nomark(c);
-}
-
/*
* Flush current symbol to the LED display hardware
*/
@@ -493,9 +478,8 @@ void show_boot_progress(int status)
if (a4m072_status2code(status, buf) < 0)
return;
- display_set(0); /* Clear DP Led */
- display_putc_nomark(buf[0]);
- display_putc_nomark(buf[1]);
+ display_putc(buf[0]);
+ display_putc(buf[1]);
display_set(DISPLAY_HOME);
display_out_pos = 0; /* reset output position */
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 6925921..3d9989d 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -23,6 +23,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S
index e969fcf..4b90c8d 100644
--- a/board/amcc/bluestone/init.S
+++ b/board/amcc/bluestone/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 64d5d42..680feaa 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 7139aae..419ef4f 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
index ed3741c..d23cdc7 100644
--- a/board/amcc/yosemite/init.S
+++ b/board/amcc/yosemite/init.S
@@ -19,6 +19,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/barco/early_init.S b/board/barco/early_init.S
index 531dcdf..61b4b55 100644
--- a/board/barco/early_init.S
+++ b/board/barco/early_init.S
@@ -25,6 +25,7 @@
#define __ASSEMBLY__ 1
#endif
+#include <asm-offsets.h>
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
index 9e73c57..dcb91bd 100644
--- a/board/bct-brettl2/cled.c
+++ b/board/bct-brettl2/cled.c
@@ -13,7 +13,7 @@
int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr = 0x20000000 + 0x200000; // AMS2
+ ulong addr = 0x20000000 + 0x200000; /* AMS2 */
uchar data;
if (argc < 2)
diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile
index a806b18..b111b51 100644
--- a/board/cerf250/Makefile
+++ b/board/cerf250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cerf250.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
index 59346bc..043afea 100644
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of cerf PXA Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
@@ -58,19 +59,18 @@ int board_late_init(void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk
deleted file mode 100644
index c2d46b2..0000000
--- a/board/cerf250/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Cerf board with PXA250 cpu
-#
-#
-CONFIG_SYS_TEXT_BASE = 0xa3080000
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
deleted file mode 100644
index 5bfe53c..0000000
--- a/board/cerf250/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field, set SDRAM clocks free running */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
-
- ldr r0, [r1, #MDREFR_OFFSET]
- bic r0, r0, r2
- bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
- orr r0, r0, r3
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
- MDREFR_K2RUN |MDREFR_K2DB2)
- and r4, r4, r2
- bic r0, r0, r2
- orr r0, r0, r4
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r0, r0, #(MDREFR_SLFRSH)
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
- MDREFR_K1FREE | MDREFR_K2FREE)
- and r4, r4, r2
- orr r0, r0, r4
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
-.rept 8
- str r2, [r3]
-.endr
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile
index ae570e1..f8b44ab 100644
--- a/board/colibri_pxa270/Makefile
+++ b/board/colibri_pxa270/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := colibri_pxa270.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 8aa7067..191fb33 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -42,8 +42,9 @@ struct serial_device *default_serial_console (void)
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
@@ -54,13 +55,18 @@ int board_init (void)
return 0;
}
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_USB
diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/colibri_pxa270/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/cradle/Makefile b/board/cradle/Makefile
index 1ae785d..720593c 100644
--- a/board/cradle/Makefile
+++ b/board/cradle/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cradle.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cradle/config.mk b/board/cradle/config.mk
deleted file mode 100644
index 6656bdd..0000000
--- a/board/cradle/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa0f80000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index c4a93f9..2bbf2d5 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -185,6 +185,10 @@ int
board_init (void)
/**********************************************************/
{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
led_code (0xf, YELLOW);
/* arch number of HHP Cradle */
@@ -206,24 +210,18 @@ board_init (void)
return 1;
}
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return (PHYS_SDRAM_1_SIZE +
- PHYS_SDRAM_2_SIZE +
- PHYS_SDRAM_3_SIZE +
- PHYS_SDRAM_4_SIZE );
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
deleted file mode 100644
index 39964b6..0000000
--- a/board/cradle/lowlevel_init.S
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
- .macro SET_LED val
- ldr r6, =GPCR2
- ldr r7, =0
- str r7, [r6]
- ldr r6, =GPSR2
- ldr r7, =\val
- str r7, [r6]
- .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- SET_LED 1
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- SET_LED 2
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End lowlevel_init
diff --git a/board/csb226/Makefile b/board/csb226/Makefile
index c12dbea..5e1332b 100644
--- a/board/csb226/Makefile
+++ b/board/csb226/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := csb226.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
deleted file mode 100644
index 9e46555..0000000
--- a/board/csb226/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 6eed9ad..dd29e62 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -69,8 +69,9 @@ int misc_init_r(void)
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of CSB226 board */
gd->bd->bi_arch_number = MACH_TYPE_CSB226;
@@ -82,21 +83,20 @@ int board_init (void)
}
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
-
/**
* csb226_set_led: - switch LEDs on or off
*
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
deleted file mode 100644
index 55169be..0000000
--- a/board/csb226/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
index f865eb4..656d5cd 100644
--- a/board/davedenx/qong/fpga.c
+++ b/board/davedenx/qong/fpga.c
@@ -92,4 +92,3 @@ int qong_fpga_init(void)
}
#endif
-
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index b60a46e..fa9dd9f 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -33,15 +33,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return(0);
-}
-#else
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -56,7 +47,6 @@ void dram_init_banksize(void)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
-#endif
#ifdef CONFIG_DRIVER_TI_EMAC
diff --git a/board/davinci/da8xxevm/config.mk b/board/davinci/da8xxevm/config.mk
deleted file mode 100644
index e176f7d..0000000
--- a/board/davinci/da8xxevm/config.mk
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
-# Physical Address:
-# C000'0000 to C400'0000
-#
-# Linux-Kernel is expected to be at C000'8000, entry C000'8000
-# (mem base + reserved)
-#
-# we load ourself to C108 '0000
-
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0xC1080000
diff --git a/board/delta/config.mk b/board/delta/config.mk
deleted file mode 100644
index 8b24044..0000000
--- a/board/delta/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x83008000
diff --git a/board/delta/delta.c b/board/delta/delta.c
deleted file mode 100644
index df23076..0000000
--- a/board/delta/delta.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <da9030.h>
-#include <malloc.h>
-#include <command.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static void init_DA9030(void);
-static void keys_init(void);
-static void get_pressed_keys(uchar *s);
-static uchar *key_match(uchar *kbd_data);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* arch number of Lubbock-Board mk@tbd: fix this! */
- gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef DELTA_CHECK_KEYBD
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- char *str;
- int i;
-#endif /* DELTA_CHECK_KEYBD */
-
- setenv("stdout", "serial");
- setenv("stderr", "serial");
-
-#ifdef DELTA_CHECK_KEYBD
- keys_init();
-
- memset(kbd_data, '\0', KEYBD_DATALEN);
-
- /* check for pressed keys and setup keybd_env */
- get_pressed_keys(kbd_data);
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-
-# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-# endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
-#endif /* DELTA_CHECK_KEYBD */
-
- init_DA9030();
- return 0;
-}
-
-/*
- * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
- */
-#ifdef DELTA_CHECK_KEYBD
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-/*
- * Get pressed keys
- * s is a buffer of size KEYBD_DATALEN-1
- */
-static void get_pressed_keys(uchar *s)
-{
- unsigned long val;
- val = readl(GPLR3);
-
- if(val & (1<<31))
- *s++ = KEYBD_KP_DKIN0;
- if(val & (1<<18))
- *s++ = KEYBD_KP_DKIN1;
- if(val & (1<<29))
- *s++ = KEYBD_KP_DKIN2;
- if(val & (1<<22))
- *s++ = KEYBD_KP_DKIN5;
-}
-
-static void keys_init()
-{
- writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
- udelay(100);
-
- /* Configure GPIOs */
- writel(0xa840, GPIO127); /* KP_DKIN0 */
- writel(0xa840, GPIO114); /* KP_DKIN1 */
- writel(0xa840, GPIO125); /* KP_DKIN2 */
- writel(0xa840, GPIO118); /* KP_DKIN5 */
-
- /* Configure GPIOs as inputs */
- writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
- writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
-
- udelay(100);
-}
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- /* uchar compare[KEYBD_DATALEN-1]; */
- uchar compare[KEYBD_DATALEN];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- /* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
- memcpy (compare, kbd_data, KEYBD_DATALEN);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
- printf ("### Check magic \"%s\"\n", magic);
-#endif
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
-#if 0
- printf ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
-#if 0
- printf ("### Delete PREBOOT\n");
-#endif
- *kbd_data = '\0';
- return (NULL);
-}
-
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- int i;
-
- /* Read keys */
- get_pressed_keys(kbd_data);
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-#endif /* DELTA_CHECK_KEYBD */
-
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
-}
-
-void i2c_init_board()
-{
- writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-
- /* setup I2C GPIO's */
- writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
- writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
-}
-
-/* initialize the DA9030 Power Controller */
-static void init_DA9030()
-{
- uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-
- writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
- udelay(100);
-
- /* Rising Edge on EXTON to reset DA9030 */
- writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
- writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
- writel((1<<17), GSDR0);
- writel((1<<17), GPCR0); /* drive GPIO17 low */
- writel((1<<17), GPSR0); /* drive GPIO17 high */
-
-#if CONFIG_SYS_DA9030_EXTON_DELAY
- udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
-#endif
- writel((1<<17), GPCR0); /* drive GPIO17 low */
-
- /* reset the watchdog and go active (0xec) */
- val = (SYS_CONTROL_A_HWRES_ENABLE |
- (0x6<<4) |
- SYS_CONTROL_A_WDOG_ACTION |
- SYS_CONTROL_A_WATCHDOG);
- if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
- printf("Error accessing DA9030 via i2c.\n");
- return;
- }
-
- val = 0x80;
- if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
- printf("Error accessing DA9030 via i2c.\n");
- return;
- }
-
- i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
- i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
- i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
- i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */
- i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */
- i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */
- i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */
- i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
- i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */
- i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */
- i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */
- i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */
- i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
- i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */
- i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
- i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
- i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */
-
- val = i2c_reg_read(addr, STATUS);
- if(val & STATUS_CHDET)
- printf("Charger detected, turning on LED.\n");
- else {
- printf("No charger detetected.\n");
- /* undervoltage? print error and power down */
- }
-}
-
-
-#if 0
-/* reset the DA9030 watchdog */
-void hw_watchdog_reset(void)
-{
- uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
- val = i2c_reg_read(addr, SYS_CONTROL_A);
- val |= SYS_CONTROL_A_WATCHDOG;
- i2c_reg_write(addr, SYS_CONTROL_A, val);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
deleted file mode 100644
index 1664f3b..0000000
--- a/board/delta/lowlevel_init.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-.macro wait time
- ldr r2, =OSCR
- mov r3, #0
- str r3, [r2]
-0:
- ldr r3, [r2]
- cmp r3, \time
- bls 0b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- /* Set up GPIO pins first */
- mov r10, lr
-
- /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
- ldr r0, =GPIO97
- ldr r1, =0x801
- str r1, [r0]
-
- ldr r0, =GPIO98
- ldr r1, =0x801
- str r1, [r0]
-
- /* tebrandt - ASCR, clear the RDH bit */
- ldr r0, =ASCR
- ldr r1, [r0]
- bic r1, r1, #0x80000000
- str r1, [r0]
-
-mem_init:
- /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
- ldr r0, =ACCR
- ldr r1, [r0]
- orr r1, r1, #0x3000
- str r1, [r0]
- ldr r1, [r0]
-
- /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
- ldr r0, =MDCNFG
- ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
- /* ldr r1, =0x80000403 */
- str r1, [r0]
- ldr r1, [r0] /* delay until written */
-
- /* 3. wait nop power up waiting period (200ms)
- * optimization: Steps 4+6 can be done during this
- */
- wait #0x300
-
- /* 4. Perform an initial Rcomp-calibration cycle */
- ldr r0, =RCOMP
- ldr r1, =0x80000000
- str r1, [r0]
- ldr r1, [r0] /* delay until written */
- /* missing: program for automatic rcomp evaluation cycles */
-
- /* 5. DDR DRAM strobe delay calibration */
- ldr r0, =DDR_HCAL
- ldr r1, =0x88000007
- str r1, [r0]
- wait #5
- ldr r1, [r0] /* delay until written */
-
- /* Set MDMRS */
- ldr r0, =MDMRS
- ldr r1, =0x60000033
- str r1, [r0]
- wait #300
-
- /* Configure MDREFR */
- ldr r0, =MDREFR
- ldr r1, =0x00000006
- str r1, [r0]
- ldr r1, [r0]
-
- /* Enable the dynamic memory controller */
- ldr r0, =MDCNFG
- ldr r1, [r0]
- orr r1, r1, #MDCNFG_DMCEN
- str r1, [r0]
-
-#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
- /* scrub/init SDRAM if enabled/present */
- ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
- ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
- mov r0, #0 /* scrub with 0x0000:0000 */
- mov r1, #0
- mov r2, #0
- mov r3, #0
- mov r4, #0
- mov r5, #0
- mov r6, #0
- mov r7, #0
-10: /* fastScrubLoop */
- subs r9, r9, #32 /* 8 words/line */
- stmia r8!, {r0-r7}
- beq 15f
- b 10b
-#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
-
-15:
- /* Mask all interrupts */
- mov r1, #0
- mcr p6, 0, r1, c1, c0, 0 @ ICMR
-
- /* Disable software and data breakpoints */
- mov r0, #0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /* Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-endlowlevel_init:
- mov pc, lr
diff --git a/board/delta/nand.c b/board/delta/nand.c
deleted file mode 100644
index 119a587..0000000
--- a/board/delta/nand.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_DFC_DEBUG1
-# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG1(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG2
-# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG2(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG3
-# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG3(fmt, args...)
-#endif
-
-/* These really don't belong here, as they are specific to the NAND Model */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr delta_bbt_descr = {
- .options = 0,
- .offs = 0,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout delta_oob = {
- .eccbytes = 6,
- .eccpos = {2, 3, 4, 5, 6, 7},
- .oobfree = { {8, 2}, {12, 4} }
-};
-
-/*
- * not required for Monahans DFC
- */
-static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- return;
-}
-
-#if 0
-/* read device ready pin */
-static int dfc_device_ready(struct mtd_info *mtdinfo)
-{
- if(NDSR & NDSR_RDY)
- return 1;
- else
- return 0;
- return 0;
-}
-#endif
-
-/*
- * Write buf to the DFC Controller Data Buffer
- */
-static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- unsigned long bytes_multi = len & 0xfffffffc;
- unsigned long rest = len & 0x3;
- unsigned long *long_buf;
- int i;
-
- DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
- if(bytes_multi) {
- for(i=0; i<bytes_multi; i+=4) {
- long_buf = (unsigned long*) &buf[i];
- writel(*long_buf, NDDB);
- }
- }
- if(rest) {
- printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
- }
- return;
-}
-
-
-static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
-{
- int i=0, j;
-
- /* we have to be carefull not to overflow the buffer if len is
- * not a multiple of 4 */
- unsigned long bytes_multi = len & 0xfffffffc;
- unsigned long rest = len & 0x3;
- unsigned long *long_buf;
-
- DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
- /* if there are any, first copy multiple of 4 bytes */
- if(bytes_multi) {
- for(i=0; i<bytes_multi; i+=4) {
- long_buf = (unsigned long*) &buf[i];
- *long_buf = readl(NDDB);
- }
- }
-
- /* ...then the rest */
- if(rest) {
- unsigned long rest_data = NDDB;
- for(j=0;j<rest; j++)
- buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
- }
-
- return;
-}
-
-/*
- * read a word. Not implemented as not used in NAND code.
- */
-static u16 dfc_read_word(struct mtd_info *mtd)
-{
- printf("dfc_read_word: UNIMPLEMENTED.\n");
- return 0;
-}
-
-/* global var, too bad: mk@tbd: move to ->priv pointer */
-static unsigned long read_buf = 0;
-static int bytes_read = -1;
-
-/*
- * read a byte from NDDB Because we can only read 4 bytes from NDDB at
- * a time, we buffer the remaining bytes. The buffer is reset when a
- * new command is sent to the chip.
- *
- * WARNING:
- * This function is currently only used to read status and id
- * bytes. For these commands always 8 bytes need to be read from
- * NDDB. So we read and discard these bytes right now. In case this
- * function is used for anything else in the future, we must check
- * what was the last command issued and read the appropriate amount of
- * bytes respectively.
- */
-static u_char dfc_read_byte(struct mtd_info *mtd)
-{
- unsigned char byte;
- unsigned long dummy;
-
- if(bytes_read < 0) {
- read_buf = readl(NDDB);
- dummy = readl(NDDB);
- bytes_read = 0;
- }
- byte = (unsigned char) (read_buf>>(8 * bytes_read++));
- if(bytes_read >= 4)
- bytes_read = -1;
-
- DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
- return byte;
-}
-
-/* calculate delta between OSCR values start and now */
-static unsigned long get_delta(unsigned long start)
-{
- unsigned long cur = readl(OSCR);
-
- if(cur < start) /* OSCR overflowed */
- return (cur + (start^0xffffffff));
- else
- return (cur - start);
-}
-
-/* delay function, this doesn't belong here */
-static void wait_us(unsigned long us)
-{
- unsigned long start = readl(OSCR);
- us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
-
- while (get_delta(start) < us) {
- /* do nothing */
- }
-}
-
-static void dfc_clear_nddb(void)
-{
- writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
- wait_us(CONFIG_SYS_NAND_OTHER_TO);
-}
-
-/* wait_event with timeout */
-static unsigned long dfc_wait_event(unsigned long event)
-{
- unsigned long ndsr, timeout, start = readl(OSCR);
-
- if(!event)
- return 0xff000000;
- else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
- timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
- * OSCR_CLK_FREQ, 1000);
- else
- timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
- * OSCR_CLK_FREQ, 1000);
-
- while(1) {
- ndsr = readl(NDSR);
- if(ndsr & event) {
- writel(readl(NDSR) | event, NDSR);
- break;
- }
- if(get_delta(start) > timeout) {
- DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
- return 0xff000000;
- }
-
- }
- return ndsr;
-}
-
-/* we don't always wan't to do this */
-static void dfc_new_cmd(void)
-{
- int retry = 0;
- unsigned long status;
-
- while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
- /* Clear NDSR */
- writel(0xfff, NDSR);
-
- /* set NDCR[NDRUN] */
- if (!(readl(NDCR) & NDCR_ND_RUN))
- writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
-
- status = dfc_wait_event(NDSR_WRCMDREQ);
-
- if(status & NDSR_WRCMDREQ)
- return;
-
- DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
- dfc_clear_nddb();
- }
- DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
-}
-
-/* this function is called after Programm and Erase Operations to
- * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
- unsigned long ndsr=0, event=0;
- int state = this->state;
-
- if(state == FL_WRITING) {
- event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
- } else if(state == FL_ERASING) {
- event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
- }
-
- ndsr = dfc_wait_event(event);
-
- if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
- return(0x1); /* Status Read error */
- return 0;
-}
-
-/* cmdfunc send commands to the DFC */
-static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
- int column, int page_addr)
-{
- /* register struct nand_chip *this = mtd->priv; */
- unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
-
- /* clear the ugly byte read buffer */
- bytes_read = -1;
- read_buf = 0;
-
- switch (command) {
- case NAND_CMD_READ0:
- DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- dfc_new_cmd();
- ndcb0 = (NAND_CMD_READ0 | (4<<16));
- column >>= 1; /* adjust for 16 bit bus */
- ndcb1 = (((column>>1) & 0xff) |
- ((page_addr<<8) & 0xff00) |
- ((page_addr<<8) & 0xff0000) |
- ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_READ1:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
- goto end;
- case NAND_CMD_READOOB:
- DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
- goto end;
- case NAND_CMD_READID:
- dfc_new_cmd();
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
- ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_PAGEPROG:
- /* sent as a multicommand in NAND_CMD_SEQIN */
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
- goto end;
- case NAND_CMD_ERASE1:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- dfc_new_cmd();
- ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
- ndcb1 = (page_addr & 0x00ffffff);
- goto write_cmd;
- case NAND_CMD_ERASE2:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
- goto end;
- case NAND_CMD_SEQIN:
- /* send PAGE_PROG command(0x1080) */
- dfc_new_cmd();
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
- column >>= 1; /* adjust for 16 bit bus */
- ndcb1 = (((column>>1) & 0xff) |
- ((page_addr<<8) & 0xff00) |
- ((page_addr<<8) & 0xff0000) |
- ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
- event = NDSR_WRDREQ;
- goto write_cmd;
- case NAND_CMD_STATUS:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
- dfc_new_cmd();
- ndcb0 = NAND_CMD_STATUS | (4<<21);
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_RESET:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
- ndcb0 = NAND_CMD_RESET | (5<<21);
- event = NDSR_CS0_CMDD;
- goto write_cmd;
- default:
- printk("dfc_cmdfunc: error, unsupported command.\n");
- goto end;
- }
-
- write_cmd:
- writel(ndcb0, NDCB0);
- writel(ndcb1, NDCB0);
- writel(ndcb2, NDCB0);
-
- /* wait_event: */
- dfc_wait_event(event);
- end:
- return;
-}
-
-static void dfc_gpio_init(void)
-{
- DFC_DEBUG2("Setting up DFC GPIO's.\n");
-
- /* no idea what is done here, see zylonite.c */
- writel(0x1, GPIO4);
-
- writel(0x00000001, DF_ALE_nWE1);
- writel(0x00000001, DF_ALE_nWE2);
- writel(0x00000001, DF_nCS0);
- writel(0x00000001, DF_nCS1);
- writel(0x00000001, DF_nWE);
- writel(0x00000001, DF_nRE);
- writel(0x00000001, DF_IO0);
- writel(0x00000001, DF_IO8);
- writel(0x00000001, DF_IO1);
- writel(0x00000001, DF_IO9);
- writel(0x00000001, DF_IO2);
- writel(0x00000001, DF_IO10);
- writel(0x00000001, DF_IO3);
- writel(0x00000001, DF_IO11);
- writel(0x00000001, DF_IO4);
- writel(0x00000001, DF_IO12);
- writel(0x00000001, DF_IO5);
- writel(0x00000001, DF_IO13);
- writel(0x00000001, DF_IO6);
- writel(0x00000001, DF_IO14);
- writel(0x00000001, DF_IO7);
- writel(0x00000001, DF_IO15);
-
- writel(0x1901, DF_nWE);
- writel(0x1901, DF_nRE);
- writel(0x1900, DF_CLE_nOE);
- writel(0x1901, DF_ALE_nWE1);
- writel(0x1900, DF_INT_RnB);
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand_new.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
- unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
-
- /* set up GPIO Control Registers */
- dfc_gpio_init();
-
- /* turn on the NAND Controller Clock (104 MHz @ D0) */
- writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
-
-#undef CONFIG_SYS_TIMING_TIGHT
-#ifndef CONFIG_SYS_TIMING_TIGHT
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tCH);
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
- DFC_MAX_tCS);
- tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWH);
- tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWP);
- tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tRH);
- tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
- DFC_MAX_tRP);
- tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tR);
- tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWHR);
- tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tAR);
-#else /* this is the tight timing */
-
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
- DFC_MAX_tCH);
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
- DFC_MAX_tCS);
- tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
- DFC_MAX_tWH);
- tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
- DFC_MAX_tWP);
- tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
- DFC_MAX_tRH);
- tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
- DFC_MAX_tRP);
- tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
- DFC_MAX_tR);
- tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
- DFC_MAX_tWHR);
- tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
- DFC_MAX_tAR);
-#endif /* CONFIG_SYS_TIMING_TIGHT */
-
-
- DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
-
- /* tRP value is split in the register */
- if(tRP & (1 << 4)) {
- tRP_high = 1;
- tRP &= ~(1 << 4);
- } else {
- tRP_high = 0;
- }
-
- writel((tCH << 19) |
- (tCS << 16) |
- (tWH << 11) |
- (tWP << 8) |
- (tRP_high << 6) |
- (tRH << 3) |
- (tRP << 0),
- NDTR0CS0);
-
- writel((tR << 16) |
- (tWHR << 4) |
- (tAR << 0),
- NDTR1CS0);
-
- /* If it doesn't work (unlikely) think about:
- * - ecc enable
- * - chip select don't care
- * - read id byte count
- *
- * Intentionally enabled by not setting bits:
- * - dma (DMA_EN)
- * - page size = 512
- * - cs don't care, see if we can enable later!
- * - row address start position (after second cycle)
- * - pages per block = 32
- * - ND_RDY : clears command buffer
- */
- /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
-
- writel(NDCR_SPARE_EN | /* use the spare area */
- NDCR_DWIDTH_C | /* 16bit DFC data bus width */
- NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
- (2 << 16) | /* read id count = 7 ???? mk@tbd */
- NDCR_ND_ARB_EN | /* enable bus arbiter */
- NDCR_RDYM | /* flash device ready ir masked */
- NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
- NDCR_CS1_PAGEDM |
- NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
- NDCR_CS1_CMDDM |
- NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
- NDCR_CS1_BBDM |
- NDCR_DBERRM | /* double bit error ir masked */
- NDCR_SBERRM | /* single bit error ir masked */
- NDCR_WRDREQM | /* write data request ir masked */
- NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM, /* write command request ir masked */
- NDCR);
-
-
- /* wait 10 us due to cmd buffer clear reset */
- /* wait(10); */
-
-
- nand->cmd_ctrl = dfc_hwcontrol;
-/* nand->dev_ready = dfc_device_ready; */
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->ecc.layout = &delta_oob;
- nand->options = NAND_BUSWIDTH_16;
- nand->waitfunc = dfc_wait;
- nand->read_byte = dfc_read_byte;
- nand->read_word = dfc_read_word;
- nand->read_buf = dfc_read_buf;
- nand->write_buf = dfc_write_buf;
-
- nand->cmdfunc = dfc_cmdfunc;
- nand->badblock_pattern = &delta_bbt_descr;
- return 0;
-}
-
-#endif
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
index 351095a..88565d9 100644
--- a/board/esd/du440/init.S
+++ b/board/esd/du440/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 96f7206..b99a8e9 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -19,6 +19,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/fads/fads.h b/board/fads/fads.h
index 38abc70..3dc5358 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -164,9 +164,8 @@
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk
index 716fca9..6e90671 100644
--- a/board/freescale/mx51evk/config.mk
+++ b/board/freescale/mx51evk/config.mk
@@ -20,7 +20,6 @@
# MA 02111-1307 USA
#
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
CONFIG_SYS_TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
ALL += $(obj)u-boot.imx
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index c8d7d39..2160d5a 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -52,9 +52,9 @@ u32 get_board_rev(void)
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
return 0;
}
@@ -188,10 +188,10 @@ static void power_init(void)
val &= ~PWGT2SPIEN;
pmic_reg_write(REG_POWER_MISC, val);
- /* Write needed to update Charger 0 */
- pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
- ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
- OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+ /* Externally powered */
+ val = pmic_reg_read(REG_CHARGE);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(REG_CHARGE, val);
/* power up the system first */
pmic_reg_write(REG_POWER_MISC, PWUP);
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
new file mode 100644
index 0000000..d3bd233
--- /dev/null
+++ b/board/gdsys/405ep/405ep.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+int board_early_init_f(void)
+{
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ * -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * setup io-latches for reset
+ */
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+
+ /*
+ * wait for fpga-done
+ * fail ungraceful if fpga is not configuring properly
+ */
+ while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
+ ;
+
+ /*
+ * setup io-latches for boot (stop reset)
+ */
+ udelay(10);
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+ /*
+ * wait for fpga out of reset
+ * fail ungraceful if fpga is not working properly
+ */
+ while (1) {
+ fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
+ if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ }
+
+ return 0;
+}
diff --git a/board/delta/Makefile b/board/gdsys/405ep/Makefile
index 648e00c..13dff52 100644
--- a/board/delta/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -1,7 +1,6 @@
-
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -26,14 +25,17 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := delta.o nand.o
-SOBJS := lowlevel_init.o
+COBJS-$(CONFIG_IO) += io.o
+COBJS-$(CONFIG_IOCON) += iocon.o
+
+COBJS := $(BOARD).o $(COBJS-y)
+SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
new file mode 100644
index 0000000..80877b6
--- /dev/null
+++ b/board/gdsys/405ep/io.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#include "../common/fpga.h"
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+
+enum {
+ REG_VERSIONS = 0x0002,
+ REG_FPGA_FEATURES = 0x0004,
+ REG_FPGA_VERSION = 0x0006,
+ REG_QUAD_SERDES_RESET = 0x0012,
+};
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+ HWVER_121 = 2,
+ HWVER_122 = 3,
+};
+
+int configure_gbit_phy(unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+ goto err_out;
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ u16 versions = fpga_get_reg(REG_VERSIONS);
+ u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+ u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ printf("Board: ");
+
+ printf("CATCenter Io");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ puts("\n ");
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ case HWVER_121:
+ printf(" HW-Ver 1.21\n");
+ break;
+
+ case HWVER_122:
+ printf(" HW-Ver 1.22\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+
+ return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+ unsigned int k;
+
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k)
+ configure_gbit_phy(k);
+
+ /* take fpga serdes blocks out of reset */
+ fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+
+ return 0;
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
new file mode 100644
index 0000000..ecd6cb2
--- /dev/null
+++ b/board/gdsys/405ep/iocon.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+#include "../common/osd.h"
+
+enum {
+ REG_VERSIONS = 0x0002,
+ REG_FPGA_VERSION = 0x0004,
+ REG_FPGA_FEATURES = 0x0006,
+};
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_104 = 1,
+ HWVER_110 = 2,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+};
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ u16 versions = fpga_get_reg(REG_VERSIONS);
+ u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+ u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ printf("Board: ");
+
+ printf("IoCon");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ puts("\n ");
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_104:
+ printf(" HW-Ver 1.04\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s)", feature_carriers);
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ return osd_probe();
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ */
+void fpga_gpio_set(int pin)
+{
+ out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+}
+
+void fpga_gpio_clear(int pin)
+{
+ out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+}
+
+int fpga_gpio_get(int pin)
+{
+ return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+}
diff --git a/board/wepep250/Makefile b/board/gdsys/common/Makefile
index 0669b0e..93cde5a 100644
--- a/board/wepep250/Makefile
+++ b/board/gdsys/common/Makefile
@@ -1,6 +1,6 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -23,16 +23,23 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
-COBJS := wepep250.o flash.o
-SOBJS := lowlevel_init.o
+LIB = $(obj)lib$(VENDOR).a
+
+COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IOCON) += osd.o
+
+COBJS := $(COBJS-y)
+SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
diff --git a/board/palmtc/lowlevel_init.S b/board/gdsys/common/fpga.h
index 74050dc..c1434e7 100644
--- a/board/palmtc/lowlevel_init.S
+++ b/board/gdsys/common/fpga.h
@@ -1,7 +1,6 @@
/*
- * Palm Tungsten|C Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,18 +21,17 @@
* MA 02111-1307 USA
*/
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+static inline u16 fpga_get_reg(unsigned reg)
+{
+ return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
+}
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
+static inline void fpga_set_reg(unsigned reg, u16 val)
+{
+ return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
+}
- mov pc, lr
+#endif
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
new file mode 100644
index 0000000..e56e966
--- /dev/null
+++ b/board/gdsys/common/miiphybb.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+
+ return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+
+ return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = CONFIG_SYS_GBIT_MII_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ }
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
new file mode 100644
index 0000000..05800ff
--- /dev/null
+++ b/board/gdsys/common/osd.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "fpga.h"
+
+#define CH7301_I2C_ADDR 0x75
+
+#define PIXCLK_640_480_60 25180000
+
+#define BASE_WIDTH 32
+#define BASE_HEIGHT 16
+#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
+
+enum {
+ REG_CONTROL = 0x0010,
+ REG_MPC3W_CONTROL = 0x001a,
+ REG_VIDEOCONTROL = 0x0042,
+ REG_OSDVERSION = 0x0100,
+ REG_OSDFEATURES = 0x0102,
+ REG_OSDCONTROL = 0x0104,
+ REG_XY_SIZE = 0x0106,
+ REG_VIDEOMEM = 0x0800,
+};
+
+enum {
+ CH7301_CM = 0x1c, /* Clock Mode Register */
+ CH7301_IC = 0x1d, /* Input Clock Register */
+ CH7301_GPIO = 0x1e, /* GPIO Control Register */
+ CH7301_IDF = 0x1f, /* Input Data Format Register */
+ CH7301_CD = 0x20, /* Connection Detect Register */
+ CH7301_DC = 0x21, /* DAC Control Register */
+ CH7301_HPD = 0x23, /* Hot Plug Detection Register */
+ CH7301_TCTL = 0x31, /* DVI Control Input Register */
+ CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
+ CH7301_TPD = 0x34, /* DVI PLL Divide Register */
+ CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
+ CH7301_TPF = 0x36, /* DVI PLL Filter Register */
+ CH7301_TCT = 0x37, /* DVI Clock Test Register */
+ CH7301_TSTP = 0x48, /* Test Pattern Register */
+ CH7301_PM = 0x49, /* Power Management register */
+ CH7301_VID = 0x4a, /* Version ID Register */
+ CH7301_DID = 0x4b, /* Device ID Register */
+ CH7301_DSP = 0x56, /* DVI Sync polarity Register */
+};
+
+static void mpc92469ac_calc_parameters(unsigned int fout,
+ unsigned int *post_div, unsigned int *feedback_div)
+{
+ unsigned int n = *post_div;
+ unsigned int m = *feedback_div;
+ unsigned int a;
+ unsigned int b = 14745600 / 16;
+
+ if (fout < 50169600)
+ n = 8;
+ else if (fout < 100339199)
+ n = 4;
+ else if (fout < 200678399)
+ n = 2;
+ else
+ n = 1;
+
+ a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+ m = a / b;
+
+ *post_div = n;
+ *feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned int fout)
+{
+ unsigned int n;
+ unsigned int m;
+ unsigned int bitval = 0;
+ mpc92469ac_calc_parameters(fout, &n, &m);
+
+ switch (n) {
+ case 1:
+ bitval = 0x00;
+ break;
+ case 2:
+ bitval = 0x01;
+ break;
+ case 4:
+ bitval = 0x02;
+ break;
+ case 8:
+ bitval = 0x03;
+ break;
+ }
+
+ fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+}
+
+static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+{
+ unsigned int k;
+
+ for (k = 0; k < charcount; ++k) {
+ if (offset + k >= BUFSIZE)
+ return -1;
+ fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+ }
+
+ return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned x;
+ unsigned y;
+ unsigned charcount;
+ unsigned len;
+ u8 color;
+ unsigned int k;
+ u16 buf[BUFSIZE];
+ char *text;
+
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+ charcount = strlen(text);
+ len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+ for (k = 0; k < len; ++k)
+ buf[k] = (text[k] << 8) | color;
+
+ return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+}
+
+int osd_probe(void)
+{
+ u8 value;
+ u16 version = fpga_get_reg(REG_OSDVERSION);
+ u16 features = fpga_get_reg(REG_OSDFEATURES);
+ unsigned width;
+ unsigned height;
+
+ width = ((features & 0x3f00) >> 8) + 1;
+ height = (features & 0x001f) + 1;
+
+ printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ version/100, version%100, width, height);
+
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value != 0x17) {
+ printf(" Probing CH7301 failed, DID %02x\n", value);
+ return -1;
+ }
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+
+ mpc92469ac_set(PIXCLK_640_480_60);
+ fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
+ fpga_set_reg(REG_OSDCONTROL, 0x0049);
+
+ fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+
+ return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned x;
+ unsigned y;
+ unsigned k;
+ u16 buffer[BASE_WIDTH];
+ char *rp;
+ u16 *wp = buffer;
+ unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
+
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ rp = argv[3];
+
+
+ while (*rp) {
+ char substr[5];
+
+ memcpy(substr, rp, 4);
+ substr[4] = 0;
+ *wp = simple_strtoul(substr, NULL, 16);
+
+ rp += 4;
+ wp++;
+ if (wp - buffer > BASE_WIDTH)
+ break;
+ }
+
+ for (k = 0; k < count; ++k) {
+ unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
+ osd_write_videomem(offset, buffer, wp - buffer);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ osdw, 5, 0, osd_write,
+ "write 16-bit hex encoded buffer to osd memory",
+ "pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+ osdp, 5, 0, osd_print,
+ "write ASCII buffer to osd memory",
+ "pos_x pos_y color text\n"
+);
diff --git a/board/trizepsiv/pxavoltage.S b/board/gdsys/common/osd.h
index 9659c2b..4431cbc 100644
--- a/board/trizepsiv/pxavoltage.S
+++ b/board/gdsys/common/osd.h
@@ -1,6 +1,6 @@
/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -21,9 +21,9 @@
* MA 02111-1307 USA
*/
-#include <asm/arch/pxa-regs.h>
+#ifndef _OSD_H_
+#define _OSD_H_
- .global initPXAvoltage
+int osd_probe(void);
-initPXAvoltage:
- mov pc, lr
+#endif
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
index ba750cb..4a40e4b 100644
--- a/board/gdsys/gdppc440etx/init.S
+++ b/board/gdsys/gdppc440etx/init.S
@@ -24,6 +24,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
index 5a819c2..7513f1d 100644
--- a/board/gdsys/intip/init.S
+++ b/board/gdsys/intip/init.S
@@ -25,6 +25,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S
index 531dcdf..61b4b55 100644
--- a/board/hidden_dragon/early_init.S
+++ b/board/hidden_dragon/early_init.S
@@ -25,6 +25,7 @@
#define __ASSEMBLY__ 1
#endif
+#include <asm-offsets.h>
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 47b2195..a9e4448 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -80,7 +80,7 @@ void lite5200b_wakeup(void)
/* jump back to linux kernel code */
linux_wakeup = SAVED_ADDR;
printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
- linux_wakeup);
+ (unsigned long)linux_wakeup);
linux_wakeup();
}
#else
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
index afae217..ba248c0 100644
--- a/board/innokom/Makefile
+++ b/board/innokom/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := innokom.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/innokom/config.mk b/board/innokom/config.mk
deleted file mode 100644
index 9e46555..0000000
--- a/board/innokom/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 2c51125..e658c35 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -100,8 +100,9 @@ int misc_init_r(void)
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
gd->bd->bi_boot_params = 0xa0000100;
@@ -110,22 +111,20 @@ int board_init (void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
-
/**
* innokom_set_led: - switch LEDs on or off
*
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
deleted file mode 100644
index 55169be..0000000
--- a/board/innokom/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
index 35865e0..019f93f 100644
--- a/board/isee/igep0030/config.mk
+++ b/board/isee/igep0030/config.mk
@@ -31,4 +31,3 @@
# For use with external or internal boots.
TEXT_BASE = 0x80008000
-
diff --git a/board/keymile/km_arm/config.mk b/board/keymile/km_arm/config.mk
deleted file mode 100644
index df4828c..0000000
--- a/board/keymile/km_arm/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x004000000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 7c0b858..2e20644 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -143,7 +143,7 @@ int misc_init_r(void)
return 0;
}
-int board_init(void)
+int board_early_init_f(void)
{
u32 tmp;
@@ -160,14 +160,6 @@ int board_init(void)
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
@@ -179,6 +171,20 @@ int board_init(void)
kw_gpio_set_valid(SUEN3_ENV_WP, 38);
kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
return 0;
}
@@ -225,20 +231,6 @@ U_BOOT_CMD(
);
#endif
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
- kw_sdram_bs(i));
- }
-
- return 0;
-}
-#else
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -259,7 +251,6 @@ void dram_init_banksize(void)
kw_sdram_bs(i));
}
}
-#endif
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
diff --git a/board/korat/init.S b/board/korat/init.S
index bfc6bc1..3741277 100644
--- a/board/korat/init.S
+++ b/board/korat/init.S
@@ -19,6 +19,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile
index 6592307..2853bca 100644
--- a/board/lubbock/Makefile
+++ b/board/lubbock/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := lubbock.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk
deleted file mode 100644
index f30f695..0000000
--- a/board/lubbock/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
deleted file mode 100644
index db6f69d..0000000
--- a/board/lubbock/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- orr r4, r4, #(MDREFR_SLFRSH)
- bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index d8d6ffb..f791c5b 100644
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
@@ -55,19 +56,18 @@ int board_late_init(void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 8efc8a1..2014cd7 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -23,6 +23,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index eaeec82..978e6fd 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -78,42 +78,43 @@ int board_init(void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x002AAAAA;
- gpio->GPBUP = 0x000002BF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x000037F7;
- gpio->GPFCON = 0x00000000;
- gpio->GPFUP = 0x00000000;
- gpio->GPGCON = 0xFFEAFF5A;
- gpio->GPGUP = 0x0000F0DC;
- gpio->GPHCON = 0x0028AAAA;
- gpio->GPHUP = 0x00000656;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x002AAAAA;
+ gpio->gpbup = 0x000002BF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x000037F7;
+ gpio->gpfcon = 0x00000000;
+ gpio->gpfup = 0x00000000;
+ gpio->gpgcon = 0xFFEAFF5A;
+ gpio->gpgup = 0x0000F0DC;
+ gpio->gphcon = 0x0028AAAA;
+ gpio->gphup = 0x00000656;
/* setup correct IRQ modes for NIC */
- gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+ /* rising edge mode */
+ gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
/* select USB port 2 to be host or device (fix to host for now) */
- gpio->MISCCR |= 0x08;
+ gpio->misccr |= 0x08;
/* init serial */
gd->baudrate = CONFIG_BAUDRATE;
diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile
index 6722d53..cd62642 100644
--- a/board/netstal/hcu4/Makefile
+++ b/board/netstal/hcu4/Makefile
@@ -19,24 +19,24 @@
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
LIB = $(obj)lib$(BOARD).a
-# NOBJS : Netstal common objects
-NOBJS = fixed_sdram.o nm_bsp.o
-COBJS = $(BOARD).o
-SOBJS =
+COBJS = $(BOARD).o \
+ ../common/fixed_sdram.o \
+ ../common/nm_bsp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $^
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
index 4456771..d037552 100644
--- a/board/netstal/hcu5/Makefile
+++ b/board/netstal/hcu5/Makefile
@@ -19,22 +19,23 @@
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
LIB = $(obj)lib$(BOARD).a
-
-# NOBJS : Netstal common objects
-NOBJS = nm_bsp.o
-COBJS = $(BOARD).o sdram.o
+COBJS = $(BOARD).o \
+ sdram.o \
+ ../common/nm_bsp.o
SOBJS = init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/netstal/mcu25/Makefile b/board/netstal/mcu25/Makefile
index 6722d53..cd62642 100644
--- a/board/netstal/mcu25/Makefile
+++ b/board/netstal/mcu25/Makefile
@@ -19,24 +19,24 @@
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
LIB = $(obj)lib$(BOARD).a
-# NOBJS : Netstal common objects
-NOBJS = fixed_sdram.o nm_bsp.o
-COBJS = $(BOARD).o
-SOBJS =
+COBJS = $(BOARD).o \
+ ../common/fixed_sdram.o \
+ ../common/nm_bsp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $^
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
index bcb014d..0cca8ab 100644
--- a/board/palmld/Makefile
+++ b/board/palmld/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := palmld.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
deleted file mode 100644
index 1d650ac..0000000
--- a/board/palmld/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmld/lowlevel_init.S b/board/palmld/lowlevel_init.S
deleted file mode 100644
index e3382ee..0000000
--- a/board/palmld/lowlevel_init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Palm LifeDrive Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
-
- /* Enable GPIO reset */
- ldr r0, =PCFR
- mov r1, #0x30
- str r1, [r0]
-
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
-
- mov pc, lr
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
index 4f0087e..5588fe7 100644
--- a/board/palmld/palmld.c
+++ b/board/palmld/palmld.c
@@ -33,7 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- /* arch number of Lubbock-Board */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of PalmLD */
gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
/* adress of boot parameters */
@@ -52,12 +56,18 @@ struct serial_device *default_serial_console(void)
return &serial_ffuart_device;
}
+extern void pxa_dram_init(void);
int dram_init(void)
{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
diff --git a/board/palmld/u-boot.lds b/board/palmld/u-boot.lds
deleted file mode 100644
index fb4358b..0000000
--- a/board/palmld/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
-}
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
index 20ac4e1..3a12e66 100644
--- a/board/palmtc/Makefile
+++ b/board/palmtc/Makefile
@@ -24,17 +24,16 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := palmtc.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
deleted file mode 100644
index 1d650ac..0000000
--- a/board/palmtc/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
index 04cb33e..25186ae 100644
--- a/board/palmtc/palmtc.c
+++ b/board/palmtc/palmtc.c
@@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
/* Arch number of Palm Tungsten|C */
gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
@@ -51,9 +55,16 @@ struct serial_device *default_serial_console(void)
return &serial_ffuart_device;
}
+extern void pxa_dram_init(void);
int dram_init(void)
{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
}
diff --git a/board/palmtc/u-boot.lds b/board/palmtc/u-boot.lds
deleted file mode 100644
index fb4358b..0000000
--- a/board/palmtc/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
-}
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 9745c14..6bd8852 100644
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile
index faa2691..cb0c3d7 100644
--- a/board/pleb2/Makefile
+++ b/board/pleb2/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := pleb2.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk
deleted file mode 100644
index 079f58e..0000000
--- a/board/pleb2/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1F80000
-#CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S
deleted file mode 100644
index b95ff9c..0000000
--- a/board/pleb2/lowlevel_init.S
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
-@ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
- 1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
- #ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- mov pc, r10
-
-@ End lowlevel_init
diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c
index 97c37ea..5a16cc7 100644
--- a/board/pleb2/pleb2.c
+++ b/board/pleb2/pleb2.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
@@ -55,17 +56,16 @@ int board_late_init(void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 119bc53..d9961dd 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
index 4892b42..2835f37 100644
--- a/board/pxa255_idp/Makefile
+++ b/board/pxa255_idp/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := pxa_idp.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk
deleted file mode 100644
index f30f695..0000000
--- a/board/pxa255_idp/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S
deleted file mode 100644
index a50760f..0000000
--- a/board/pxa255_idp/lowlevel_init.S
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-/*
- * Memory setup
- */
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 3rd blink */
- bl blink
-#endif
-
- /* Set up GPIO pins first ----------------------------------------- */
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 4th debug blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 5th blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- orr r4, r4, #(MDREFR_SLFRSH)
- bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-#if 0
- /* FIXME turn on serial ports */
- /* look into moving this to board_init() */
- ldr r2, =(PXA_CS5_PHYS + 0x03C0002c)
- mov r3, #0x13
- str r3, [r2]
-#endif
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 6th blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
-#if 0
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#endif
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 7th blink */
- bl blink
-#endif
-
-endlowlevel_init:
-
- mov pc, r10
-
-
-#ifdef DEBUG_BLINK_ENABLE
-
-/* debug LED code */
-
-/* delay about 200ms */
-delay:
-
- /* reset OSCR to 0 */
- ldr r8, =OSCR
- mov r9, #0
- str r9, [r8]
-
- /* make sure new value has stuck */
-1:
- ldr r8, =OSCR
- ldr r9, [r8]
- mov r8, #0x10000
- cmp r9, r8
- bgt 1b
-
- /* now, wait for delay to expire */
-1:
- ldr r8, =OSCR
- ldr r9, [r8]
- mov r8, #0xd4000
- cmp r8, r9
- bgt 1b
-
- mov pc, lr
-
-/* blink code -- trashes r7, r8, r9 */
-
-.globl blink
-blink:
-
- mov r7, lr
-
- /* set GPIO10 as outout */
- ldr r8, =GPDR0
- ldr r9, [r8]
- orr r9, r9, #(1<<10)
- str r9, [r8]
-
- /* turn LED off */
- mov r9, #(1<<10)
- ldr r8, =GPCR0
- str r9, [r8]
- bl delay
-
- /* turn LED on */
- mov r9, #(1<<10)
- ldr r8, =GPSR0
- str r9, [r8]
- bl delay
-
- /* turn LED off */
- mov r9, #(1<<10)
- ldr r8, =GPCR0
- str r9, [r8]
-
- mov pc, r7
-
-#endif
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index 4ab8bd4..804d09c 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -43,8 +43,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
@@ -82,22 +83,20 @@ int board_late_init(void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
-
#ifdef DEBUG_BLINKC_ENABLE
void delay_c(void)
diff --git a/board/renesas/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk
index 1a9038c..6853d2b 100644
--- a/board/renesas/sh7785lcr/config.mk
+++ b/board/renesas/sh7785lcr/config.mk
@@ -24,6 +24,8 @@
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-ifndef CONFIG_SYS_TEXT_BASE
+ifdef CONFIG_SH_32BIT
+CONFIG_SYS_TEXT_BASE = 0x8FF80000
+else
CONFIG_SYS_TEXT_BASE = 0x0ff80000
endif
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 4336729..0b09eba 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -87,6 +87,6 @@ int board_mmc_init(bd_t *bis)
gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
}
- return s5p_mmc_init(0);
+ return s5p_mmc_init(0, 4);
}
#endif
diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c
index 1294d3f..895bd77 100644
--- a/board/samsung/smdk2400/smdk2400.c
+++ b/board/samsung/smdk2400/smdk2400.c
@@ -52,30 +52,30 @@ int board_init (void)
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
- clk_power->MPLLCON = 0x5c042;
- clk_power->CLKDIVN = 0;
+ clk_power->mpllcon = 0x5c042;
+ clk_power->clkdivn = 0;
/* set up the I/O ports */
- gpio->PACON = 0x3ffff;
- gpio->PBCON = 0xaaaaaaaa;
- gpio->PBUP = 0xffff;
- gpio->PECON = 0x0;
- gpio->PEUP = 0x0;
+ gpio->pacon = 0x3ffff;
+ gpio->pbcon = 0xaaaaaaaa;
+ gpio->pbup = 0xffff;
+ gpio->pecon = 0x0;
+ gpio->peup = 0x0;
#ifdef CONFIG_HWFLOW
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
/* 10, 10, 00, 00, 10, 00, 10 */
- gpio->PFCON=0xa22;
+ gpio->pfcon = 0xa22;
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
- gpio->PFUP=0x35;
+ gpio->pfup = 0x35;
#else
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
/* 00, 00, 00, 00, 10, 00, 10 */
- gpio->PFCON = 0x22;
+ gpio->pfcon = 0x22;
/* Disable pull-up on Rx and Tx pins */
- gpio->PFUP = 0x5;
+ gpio->pfup = 0x5;
#endif /* CONFIG_HWFLOW */
- gpio->PGCON = 0x0;
- gpio->PGUP = 0x0;
- gpio->OPENCR = 0x0;
+ gpio->pgcon = 0x0;
+ gpio->pgup = 0x0;
+ gpio->opencr = 0x0;
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
index 5d1a8bb..76a24bb 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -73,36 +73,36 @@ int board_init (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x00044555;
- gpio->GPBUP = 0x000007FF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x0000FFFF;
- gpio->GPFCON = 0x000055AA;
- gpio->GPFUP = 0x000000FF;
- gpio->GPGCON = 0xFF95FFBA;
- gpio->GPGUP = 0x0000FFFF;
- gpio->GPHCON = 0x002AFAAA;
- gpio->GPHUP = 0x000007FF;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x00044555;
+ gpio->gpbup = 0x000007FF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x0000FFFF;
+ gpio->gpfcon = 0x000055AA;
+ gpio->gpfup = 0x000000FF;
+ gpio->gpgcon = 0xFF95FFBA;
+ gpio->gpgup = 0x0000FFFF;
+ gpio->gphcon = 0x002AFAAA;
+ gpio->gphup = 0x000007FF;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S
index 531dcdf..61b4b55 100644
--- a/board/sandpoint/early_init.S
+++ b/board/sandpoint/early_init.S
@@ -25,6 +25,7 @@
#define __ASSEMBLY__ 1
#endif
+#include <asm-offsets.h>
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
index 3a93677..c82382d 100644
--- a/board/sbc2410x/sbc2410x.c
+++ b/board/sbc2410x/sbc2410x.c
@@ -80,40 +80,40 @@ int board_init (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x00044556;
- gpio->GPBUP = 0x000007FF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x0000FFFF;
- gpio->GPFCON = 0x000055AA;
- gpio->GPFUP = 0x000000FF;
- gpio->GPGCON = 0xFF95FF3A;
- gpio->GPGUP = 0x0000FFFF;
- gpio->GPHCON = 0x0016FAAA;
- gpio->GPHUP = 0x000007FF;
-
- gpio->EXTINT0=0x22222222;
- gpio->EXTINT1=0x22222222;
- gpio->EXTINT2=0x22222222;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x00044556;
+ gpio->gpbup = 0x000007FF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x0000FFFF;
+ gpio->gpfcon = 0x000055AA;
+ gpio->gpfup = 0x000000FF;
+ gpio->gpgcon = 0xFF95FF3A;
+ gpio->gpgup = 0x0000FFFF;
+ gpio->gphcon = 0x0016FAAA;
+ gpio->gphup = 0x000007FF;
+
+ gpio->extint0 = 0x22222222;
+ gpio->extint1 = 0x22222222;
+ gpio->extint2 = 0x22222222;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index ecd35ff..a24d6f3 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index ca4415c..dec3c61 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -637,28 +637,28 @@ static int adc_read (unsigned int channel)
adc_init ();
- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
- padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
- padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+ padc->adccon &= ~ADC_STDBM; /* select normal mode */
+ padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+ padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
while (j--) {
- if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+ if ((padc->adccon & ADC_ENABLE_START) == 0)
break;
udelay (1);
}
if (j == 0) {
printf("%s: ADC timeout\n", __FUNCTION__);
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
return -1;
}
- result = padc->ADCDAT & 0x3FF;
+ result = padc->adcdat & 0x3FF;
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
- (padc->ADCCON >> 3) & 0x7, result);
+ (padc->adccon >> 3) & 0x7, result);
/*
* Wait for ADC to be ready for next conversion. This delay value was
@@ -676,8 +676,8 @@ static void adc_init (void)
padc = s3c2400_get_base_adc();
- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
- padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+ padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+ padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
/*
* Wait some time to avoid problem with very first call of
@@ -699,10 +699,10 @@ static void led_set (unsigned int state)
switch (state) {
case 0: /* turn LED off */
- gpio->PADAT |= (1 << 12);
+ gpio->padat |= (1 << 12);
break;
case 1: /* turn LED on */
- gpio->PADAT &= ~(1 << 12);
+ gpio->padat &= ~(1 << 12);
break;
default:
break;
@@ -729,8 +729,8 @@ static void led_init (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPA12 as output and set to High -> LED off */
- gpio->PACON &= ~(1 << 12);
- gpio->PADAT |= (1 << 12);
+ gpio->pacon &= ~(1 << 12);
+ gpio->padat |= (1 << 12);
}
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
index 6a3a4cd..30336f2 100644
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -51,16 +51,16 @@ static void rs485_setbrg (void)
reg = (33000000 / (16 * 38400)) - 1;
/* FIFO enable, Tx/Rx FIFO clear */
- uart->UFCON = 0x07;
- uart->UMCON = 0x0;
+ uart->ufcon = 0x07;
+ uart->umcon = 0x0;
/* Normal,No parity,1 stop,8 bit */
- uart->ULCON = 0x3;
+ uart->ulcon = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- uart->UCON = 0x245;
- uart->UBRDIV = reg;
+ uart->ucon = 0x245;
+ uart->ubrdiv = reg;
for (i = 0; i < 100; i++);
}
@@ -69,16 +69,16 @@ static void rs485_cfgio (void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PFCON &= ~(0x3 << 2);
- gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */
+ gpio->pfcon &= ~(0x3 << 2);
+ gpio->pfcon |= (0x2 << 2); /* configure GPF1 as RXD1 */
- gpio->PFCON &= ~(0x3 << 6);
- gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */
+ gpio->pfcon &= ~(0x3 << 6);
+ gpio->pfcon |= (0x2 << 6); /* configure GPF3 as TXD1 */
- gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
- gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+ gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+ gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
- gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+ gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
}
/*
@@ -104,9 +104,10 @@ int rs485_getc (void)
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
+ while (!(uart->utrstat & 0x1))
+ ;
- return uart->URXH & 0xff;
+ return uart->urxh & 0xff;
}
/*
@@ -117,9 +118,10 @@ void rs485_putc (const char c)
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
+ while (!(uart->utrstat & 0x2))
+ ;
- uart->UTXH = c;
+ uart->utxh = c;
/* If \n, also do \r */
if (c == '\n')
@@ -133,7 +135,7 @@ int rs485_tstc (void)
{
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
- return uart->UTRSTAT & 0x1;
+ return uart->utrstat & 0x1;
}
void rs485_puts (const char *s)
@@ -172,9 +174,9 @@ static void set_rs485de(unsigned char rs485de_state)
/* This is on PORT A bit 11 */
if(rs485de_state)
- gpio->PADAT |= (1 << 11);
+ gpio->padat |= (1 << 11);
else
- gpio->PADAT &= ~(1 << 11);
+ gpio->padat &= ~(1 << 11);
}
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 828facd..0f74e8f 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -77,36 +77,36 @@ int board_init ()
#ifdef CONFIG_TRAB_50MHZ
/* change the clock to be 50 MHz 1:1:1 */
/* MDIV:0x5c PDIV:4 SDIV:2 */
- clk_power->MPLLCON = 0x5c042;
- clk_power->CLKDIVN = 0;
+ clk_power->mpllcon = 0x5c042;
+ clk_power->clkdivn = 0;
#else
/* change the clock to be 133 MHz 1:2:4 */
/* MDIV:0x7d PDIV:4 SDIV:1 */
- clk_power->MPLLCON = 0x7d041;
- clk_power->CLKDIVN = 3;
+ clk_power->mpllcon = 0x7d041;
+ clk_power->clkdivn = 3;
#endif
/* set up the I/O ports */
- gpio->PACON = 0x3ffff;
- gpio->PBCON = 0xaaaaaaaa;
- gpio->PBUP = 0xffff;
+ gpio->pacon = 0x3ffff;
+ gpio->pbcon = 0xaaaaaaaa;
+ gpio->pbup = 0xffff;
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
/* 00, 10, 10, 10, 10, 10, 10 */
- gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+ gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
#ifdef CONFIG_HWFLOW
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
- gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+ gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
#else
/* do not pull up RXD0, RXD1, TXD0, TXD1 */
- gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+ gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3);
#endif
- gpio->PGCON = 0x0;
- gpio->PGUP = 0x0;
- gpio->OPENCR= 0x0;
+ gpio->pgcon = 0x0;
+ gpio->pgup = 0x0;
+ gpio->opencr = 0x0;
/* suppress flicker of the VFDs */
- gpio->MISCCR = 0x40;
- gpio->PFCON |= (2<<12);
+ gpio->misccr = 0x40;
+ gpio->pfcon |= (2<<12);
gd->bd->bi_arch_number = MACH_TYPE_TRAB;
@@ -114,8 +114,8 @@ int board_init ()
gd->bd->bi_boot_params = 0x0c000100;
/* Make sure both buzzers are turned off */
- gpio->PDCON |= 0x5400;
- gpio->PDDAT &= ~0xE0;
+ gpio->pdcon |= 0x5400;
+ gpio->pddat &= ~0xE0;
#ifdef CONFIG_VFD
vfd_init_clocks();
@@ -132,7 +132,7 @@ int board_init ()
#ifdef CONFIG_DRIVER_S3C24X0_I2C
/* Configure I/O ports PG5 und PG6 for I2C */
- gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+ gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
#endif /* CONFIG_DRIVER_S3C24X0_I2C */
return 0;
@@ -341,14 +341,14 @@ static inline void SET_CS_TOUCH(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT &= 0x5FF;
+ gpio->pddat &= 0x5FF;
}
static inline void CLR_CS_TOUCH(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT |= 0x200;
+ gpio->pddat |= 0x200;
}
static void spi_init(void)
@@ -358,20 +358,20 @@ static void spi_init(void)
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
- gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
- gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
- gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+ gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+ gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+ gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+ gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
CLR_CS_TOUCH();
- spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
- spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
- spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+ spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+ spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+ spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
}
wait_transmit_done();
}
@@ -380,7 +380,8 @@ static void wait_transmit_done(void)
{
struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
- while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+ while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+ ;
}
static void tsc2000_write(unsigned int page, unsigned int reg,
@@ -394,13 +395,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg,
command |= (page << 11);
command |= (reg << 5);
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (data & 0xFF00) >> 8;
wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0x00FF);
+ spi->ch[0].sptdat = (data & 0x00FF);
wait_transmit_done();
CLR_CS_TOUCH();
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 268162e..fe3dab3 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -411,28 +411,28 @@ static int adc_read (unsigned int channel)
padc = s3c2400_get_base_adc();
channel &= 0x7;
- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
- padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
- padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+ padc->adccon &= ~ADC_STDBM; /* select normal mode */
+ padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+ padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
while (j--) {
- if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+ if ((padc->adccon & ADC_ENABLE_START) == 0)
break;
udelay (1);
}
if (j == 0) {
printf("%s: ADC timeout\n", __FUNCTION__);
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
return -1;
}
- result = padc->ADCDAT & 0x3FF;
+ result = padc->adcdat & 0x3FF;
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
- (padc->ADCCON >> 3) & 0x7, result);
+ (padc->adccon >> 3) & 0x7, result);
/*
* Wait for ADC to be ready for next conversion. This delay value was
@@ -450,8 +450,8 @@ static void adc_init (void)
padc = s3c2400_get_base_adc();
- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
- padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+ padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+ padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
/*
* Wait some time to avoid problem with very first call of
@@ -493,10 +493,10 @@ int do_power_switch (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPE7 as input */
- gpio->PECON &= ~(0x3 << (2 * 7));
+ gpio->pecon &= ~(0x3 << (2 * 7));
/* signal GPE7 from power switch is low active: 0=on , 1=off */
- result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+ result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
print_identifier ();
printf("%d\n", result);
@@ -561,17 +561,17 @@ int do_vfd_id (void)
/* try to red vfd board id from the value defined by pull-ups */
- pcup_old = gpio->PCUP;
- pccon_old = gpio->PCCON;
+ pcup_old = gpio->pcup;
+ pccon_old = gpio->pccon;
- gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pull-ups */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+ gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pull-ups */
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
* inputs */
udelay (10); /* allow signals to settle */
- vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
+ vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */
- gpio->PCCON = pccon_old;
- gpio->PCUP = pcup_old;
+ gpio->pccon = pccon_old;
+ gpio->pcup = pcup_old;
/* print vfd_board_id to console */
print_identifier ();
@@ -593,40 +593,40 @@ int do_buzzer (char * const *argv)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* set prescaler for timer 2, 3 and 4 */
- timers->TCFG0 &= ~0xFF00;
- timers->TCFG0 |= 0x0F00;
+ timers->tcfg0 &= ~0xFF00;
+ timers->tcfg0 |= 0x0F00;
/* set divider for timer 2 */
- timers->TCFG1 &= ~0xF00;
- timers->TCFG1 |= 0x300;
+ timers->tcfg1 &= ~0xF00;
+ timers->tcfg1 |= 0x300;
/* set frequency */
counter = (PCLK / BUZZER_FREQ) >> 9;
- timers->ch[2].TCNTB = counter;
- timers->ch[2].TCMPB = counter / 2;
+ timers->ch[2].tcntb = counter;
+ timers->ch[2].tcmpb = counter / 2;
if (strcmp (argv[2], "on") == 0) {
debug ("%s: frequency: %d\n", __FUNCTION__,
BUZZER_FREQ);
/* configure pin GPD7 as TOUT2 */
- gpio->PDCON &= ~0xC000;
- gpio->PDCON |= 0x8000;
+ gpio->pdcon &= ~0xC000;
+ gpio->pdcon |= 0x8000;
/* start */
- timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+ timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
~INVERT2;
- timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+ timers->tcon = (timers->tcon | START2) & ~UPDATE2;
return (0);
}
else if (strcmp (argv[2], "off") == 0) {
/* stop */
- timers->TCON &= ~(START2 | RELOAD2);
+ timers->tcon &= ~(START2 | RELOAD2);
/* configure GPD7 as output and set to low */
- gpio->PDCON &= ~0xC000;
- gpio->PDCON |= 0x4000;
- gpio->PDDAT &= ~0x80;
+ gpio->pdcon &= ~0xC000;
+ gpio->pdcon |= 0x4000;
+ gpio->pddat &= ~0x80;
return (0);
}
@@ -640,12 +640,12 @@ int do_led (char * const *argv)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PC14 and PC15 as output */
- gpio->PCCON &= ~(0xF << 28);
- gpio->PCCON |= (0x5 << 28);
+ gpio->pccon &= ~(0xF << 28);
+ gpio->pccon |= (0x5 << 28);
/* configure PD0 and PD4 as output */
- gpio->PDCON &= ~((0x3 << 8) | 0x3);
- gpio->PDCON |= ((0x1 << 8) | 0x1);
+ gpio->pdcon &= ~((0x3 << 8) | 0x3);
+ gpio->pdcon |= ((0x1 << 8) | 0x1);
switch (simple_strtoul(argv[2], NULL, 10)) {
@@ -655,30 +655,30 @@ int do_led (char * const *argv)
case 2:
if (strcmp (argv[3], "on") == 0)
- gpio->PCDAT |= (1 << 14);
+ gpio->pcdat |= (1 << 14);
else
- gpio->PCDAT &= ~(1 << 14);
+ gpio->pcdat &= ~(1 << 14);
return 0;
case 3:
if (strcmp (argv[3], "on") == 0)
- gpio->PCDAT |= (1 << 15);
+ gpio->pcdat |= (1 << 15);
else
- gpio->PCDAT &= ~(1 << 15);
+ gpio->pcdat &= ~(1 << 15);
return 0;
case 4:
if (strcmp (argv[3], "on") == 0)
- gpio->PDDAT |= (1 << 0);
+ gpio->pddat |= (1 << 0);
else
- gpio->PDDAT &= ~(1 << 0);
+ gpio->pddat &= ~(1 << 0);
return 0;
case 5:
if (strcmp (argv[3], "on") == 0)
- gpio->PDDAT |= (1 << 4);
+ gpio->pddat |= (1 << 4);
else
- gpio->PDDAT &= ~(1 << 4);
+ gpio->pddat &= ~(1 << 4);
return 0;
default:
@@ -695,22 +695,22 @@ int do_full_bridge (char * const *argv)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PD5 and PD6 as output */
- gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
- gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+ gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+ gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
if (strcmp (argv[2], "+") == 0) {
- gpio->PDDAT |= (1 << 5);
- gpio->PDDAT |= (1 << 6);
+ gpio->pddat |= (1 << 5);
+ gpio->pddat |= (1 << 6);
return 0;
}
else if (strcmp (argv[2], "-") == 0) {
- gpio->PDDAT &= ~(1 << 5);
- gpio->PDDAT |= (1 << 6);
+ gpio->pddat &= ~(1 << 5);
+ gpio->pddat |= (1 << 6);
return 0;
}
else if (strcmp (argv[2], "off") == 0) {
- gpio->PDDAT &= ~(1 << 5);
- gpio->PDDAT &= ~(1 << 6);
+ gpio->pddat &= ~(1 << 5);
+ gpio->pddat &= ~(1 << 6);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -804,15 +804,15 @@ int do_motor (char * const *argv)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* Configure I/O port */
- gpio->PGCON &= ~(0x3 << 0);
- gpio->PGCON |= (0x1 << 0);
+ gpio->pgcon &= ~(0x3 << 0);
+ gpio->pgcon |= (0x1 << 0);
if (strcmp (argv[2], "on") == 0) {
- gpio->PGDAT &= ~(1 << 0);
+ gpio->pgdat &= ~(1 << 0);
return 0;
}
if (strcmp (argv[2], "off") == 0) {
- gpio->PGDAT |= (1 << 0);
+ gpio->pgdat |= (1 << 0);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -832,36 +832,36 @@ int do_pwm (char * const *argv)
if (strcmp (argv[2], "on") == 0) {
/* configure pin GPD8 as TOUT3 */
- gpio->PDCON &= ~(0x3 << 8*2);
- gpio->PDCON |= (0x2 << 8*2);
+ gpio->pdcon &= ~(0x3 << 8*2);
+ gpio->pdcon |= (0x2 << 8*2);
/* set prescaler for timer 2, 3 and 4 */
- timers->TCFG0 &= ~0xFF00;
- timers->TCFG0 |= 0x0F00;
+ timers->tcfg0 &= ~0xFF00;
+ timers->tcfg0 |= 0x0F00;
/* set divider for timer 3 */
- timers->TCFG1 &= ~(0xf << 12);
- timers->TCFG1 |= (0x3 << 12);
+ timers->tcfg1 &= ~(0xf << 12);
+ timers->tcfg1 |= (0x3 << 12);
/* set frequency */
counter = (PCLK / PWM_FREQ) >> 9;
- timers->ch[3].TCNTB = counter;
- timers->ch[3].TCMPB = counter / 2;
+ timers->ch[3].tcntb = counter;
+ timers->ch[3].tcmpb = counter / 2;
/* start timer */
- timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
- timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+ timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+ timers->tcon = (timers->tcon | START3) & ~UPDATE3;
return 0;
}
if (strcmp (argv[2], "off") == 0) {
/* stop timer */
- timers->TCON &= ~(START2 | RELOAD2);
+ timers->tcon &= ~(START2 | RELOAD2);
/* configure pin GPD8 as output and set to 0 */
- gpio->PDCON &= ~(0x3 << 8*2);
- gpio->PDCON |= (0x1 << 8*2);
- gpio->PDDAT &= ~(1 << 8);
+ gpio->pdcon &= ~(0x3 << 8*2);
+ gpio->pdcon |= (0x1 << 8*2);
+ gpio->pddat &= ~(1 << 8);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index 5890624..426ed9c 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -50,21 +50,21 @@ void tsc2000_spi_init(void)
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
- gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
- gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
- gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+ gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+ gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+ gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+ gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
CLR_CS_TOUCH();
- spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
- spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
- spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+ spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+ spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+ spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
}
spi_wait_transmit_done();
}
@@ -74,7 +74,8 @@ void spi_wait_transmit_done(void)
{
struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
- while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+ while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+ ;
}
@@ -85,13 +86,13 @@ void tsc2000_write(unsigned short reg, unsigned short data)
SET_CS_TOUCH();
command = reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (data & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0x00FF);
+ spi->ch[0].sptdat = (data & 0x00FF);
spi_wait_transmit_done();
CLR_CS_TOUCH();
@@ -106,19 +107,19 @@ unsigned short tsc2000_read (unsigned short reg)
SET_CS_TOUCH();
command = 0x8000 | reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
spi_wait_transmit_done();
- data = spi->ch[0].SPRDAT;
- spi->ch[0].SPTDAT = 0xFF;
+ data = spi->ch[0].sprdat;
+ spi->ch[0].sptdat = 0xFF;
spi_wait_transmit_done();
CLR_CS_TOUCH();
- return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+ return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
}
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index 0b6253f..f3cecb9 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -29,45 +29,49 @@
#define _TSC2000_H_
/* temperature channel multiplexer definitions */
-#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0 (gpio->PCDAT |= 0x00010)
-
-#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1 (gpio->PCDAT |= 0x00020)
-
-#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF)
-
-#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F)
-
-#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF)
-
-#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF)
-
-#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
-#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400)
-
-#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
-#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800)
-
-#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
-#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000)
-
-#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
-#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000)
+#define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0 (gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0 (gpio->pcdat |= 0x00010)
+
+#define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1 (gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1 (gpio->pcdat |= 0x00020)
+
+#define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
+ 0x00100000)
+#define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400)
+
+#define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
+ 0x00400000)
+#define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800)
+
+#define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
+ 0x01000000)
+#define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000)
+
+#define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
+ 0x04000000)
+#define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000)
/* TSC2000 register definition */
#define TSC2000_REG_X ((0 << 11) | (0 << 5))
@@ -130,7 +134,7 @@ static inline void SET_CS_TOUCH(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT &= 0x5FF;
+ gpio->pddat &= 0x5FF;
}
@@ -138,7 +142,7 @@ static inline void CLR_CS_TOUCH(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT |= 0x200;
+ gpio->pddat |= 0x200;
}
#endif /* _TSC2000_H_ */
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index b7eb8cc..9a2b1ba 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -365,12 +365,12 @@ int vfd_init_clocks (void)
/* try to determine display type from the value
* defined by pull-ups
*/
- gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
+ gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pullups */
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
/* allow signals to settle */
for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */
__asm__("NOP");
- vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
+ vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */
VFD_DISABLE; /* activate blank for the vfd */
@@ -381,39 +381,39 @@ int vfd_init_clocks (void)
/* If new board revision, then use PWM 3 as cpld-clock */
/* Enable 500 Hz timer for fill level sensor to operate properly */
/* Configure TOUT3 as functional pin, disable pull-up */
- gpio->PDCON &= ~0x30000;
- gpio->PDCON |= 0x20000;
- gpio->PDUP |= (1 << 8);
+ gpio->pdcon &= ~0x30000;
+ gpio->pdcon |= 0x20000;
+ gpio->pdup |= (1 << 8);
/* Configure the prescaler */
- timers->TCFG0 &= ~0xff00;
- timers->TCFG0 |= 0x0f00;
+ timers->tcfg0 &= ~0xff00;
+ timers->tcfg0 |= 0x0f00;
/* Select MUX input (divider) for timer3 (1/16) */
- timers->TCFG1 &= ~0xf000;
- timers->TCFG1 |= 0x3000;
+ timers->tcfg1 &= ~0xf000;
+ timers->tcfg1 |= 0x3000;
/* Enable autoreload and set the counter and compare
* registers to values for the 500 Hz clock
* (for a given prescaler (15) and divider (16)):
* counter = (66000000 / 500) >> 9;
*/
- timers->ch[3].TCNTB = 0x101;
- timers->ch[3].TCMPB = 0x101 / 2;
+ timers->ch[3].tcntb = 0x101;
+ timers->ch[3].tcmpb = 0x101 / 2;
/* Start timer */
- timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
- timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+ timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+ timers->tcon = (timers->tcon | START3) & ~UPDATE3;
}
#endif
/* If old board revision, then use vm-signal as cpld-clock */
- lcd->LCDCON2 = 0x00FFC000;
- lcd->LCDCON3 = 0x0007FF00;
- lcd->LCDCON4 = 0x00000000;
- lcd->LCDCON5 = 0x00000400;
- lcd->LCDCON1 = 0x00000B75;
+ lcd->lcdcon2 = 0x00FFC000;
+ lcd->lcdcon3 = 0x0007FF00;
+ lcd->lcdcon4 = 0x00000000;
+ lcd->lcdcon5 = 0x00000400;
+ lcd->lcdcon1 = 0x00000B75;
/* VM (GPD1) is used as clock for the CPLD */
- gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+ gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
return 0;
}
@@ -485,40 +485,44 @@ int drv_vfd_init(void)
* see manual S3C2400
*/
/* Stopp LCD-Controller */
- lcd->LCDCON1 = 0x00000000;
+ lcd->lcdcon1 = 0x00000000;
/* frame buffer startadr */
- lcd->LCDSADDR1 = gd->fb_base >> 1;
+ lcd->lcdsaddr1 = gd->fb_base >> 1;
/* frame buffer endadr */
- lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
- lcd->LCDSADDR3 = ((256/4));
- lcd->LCDCON2 = 0x000DC000;
+ lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+ lcd->lcdsaddr3 = ((256/4));
+ lcd->lcdcon2 = 0x000DC000;
if(gd->vfd_type == VFD_TYPE_MN11236)
- lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */
+ lcd->lcdcon2 = 37 << 14; /* MN11236: 38 lines */
else
- lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */
- lcd->LCDCON3 = 0x0051000A;
- lcd->LCDCON4 = 0x00000001;
+ lcd->lcdcon2 = 55 << 14; /* T119C: 56 lines */
+ lcd->lcdcon3 = 0x0051000A;
+ lcd->lcdcon4 = 0x00000001;
if (gd->vfd_type && vfd_inv_data)
- lcd->LCDCON5 = 0x000004C0;
+ lcd->lcdcon5 = 0x000004C0;
else
- lcd->LCDCON5 = 0x00000440;
+ lcd->lcdcon5 = 0x00000440;
/* Port pins as LCD output */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
- gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
+ gpio->pdcon = (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
/* Synchronize VFD enable with LCD controller to avoid flicker */
- lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */
- while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
- while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
- while((lcd->LCDCON5 & 0x060000)==0x040000);
- while((lcd->LCDCON5 & 0x060000)!=0x000000);
+ lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller */
+ while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
+ ;
+ while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
+ ;
+ while ((lcd->lcdcon5 & 0x060000) == 0x040000)
+ ;
+ while ((lcd->lcdcon5 & 0x060000) != 0x000000)
+ ;
if(gd->vfd_type)
VFD_ENABLE;
- debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
- debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
- debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+ debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+ debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+ debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
return 0;
}
@@ -532,8 +536,8 @@ void disable_vfd (void)
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
VFD_DISABLE;
- gpio->PDCON &= ~0xC;
- gpio->PDUP &= ~0x2;
+ gpio->pdcon &= ~0xC;
+ gpio->pdup &= ~0x2;
}
/************************************************************************/
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
index 44c0d49..060ac89 100644
--- a/board/trizepsiv/Makefile
+++ b/board/trizepsiv/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := conxs.o eeprom.o
-SOBJS := lowlevel_init.o pxavoltage.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk
deleted file mode 100644
index f04eb74..0000000
--- a/board/trizepsiv/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =0xa1f00000
-# 0xa1700000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 0c67367..99f665b 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -104,8 +104,9 @@ void usb_board_stop(void)
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of ConXS Board */
gd->bd->bi_arch_number = 776;
@@ -138,18 +139,18 @@ struct serial_device *default_serial_console (void)
return &serial_ffuart_device;
}
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_DRIVER_DM9000
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
deleted file mode 100644
index 128d554..0000000
--- a/board/trizepsiv/lowlevel_init.S
+++ /dev/null
@@ -1,503 +0,0 @@
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPSR3
- ldr r1, =CONFIG_SYS_GPSR3_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR3
- ldr r1, =CONFIG_SYS_GPCR3_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GRER3
- ldr r1, =CONFIG_SYS_GRER3_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER3
- ldr r1, =CONFIG_SYS_GFER3_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR3
- ldr r1, =CONFIG_SYS_GPDR3_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_L
- ldr r1, =CONFIG_SYS_GAFR3_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_U
- ldr r1, =CONFIG_SYS_GAFR3_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
- ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- str r2, [r1, #FLYCNFG_OFFSET]
- str r2, [r1, #FLYCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r4, [r1, #MDREFR_OFFSET]
- ldr r2, =0xFFF
- bic r4, r4, r2
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- and r3, r3, r2
-
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
- orr r4, r4, #MDREFR_K0RUN
- orr r4, r4, #MDREFR_K0DB4
- orr r4, r4, #MDREFR_K0FREE
- orr r4, r4, #MDREFR_K0DB2
- orr r4, r4, #MDREFR_K1DB2
- bic r4, r4, #MDREFR_K1FREE
- bic r4, r4, #MDREFR_K2FREE
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- ldr r2, =CONFIG_SYS_SXCNFG_VAL
- str r2, [r1, #SXCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
- orr r4, r4, #MDREFR_K1RUN
- bic r4, r4, #MDREFR_K2DB2
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- bic r4, r4, #MDREFR_SLFRSH
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- orr r4, r4, #MDREFR_E1PIN
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- nop
- nop
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- mov r4, r3
- orr r3, r3, #MDCNFG_DE0
- str r3, [r1, #MDCNFG_OFFSET]
- mov r0, r3
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* enable APD */
- ldr r3, [r1, #MDREFR_OFFSET]
- orr r3, r3, #MDREFR_APD
- str r3, [r1, #MDREFR_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-
-
-setvoltage:
-
- mov r10, lr
- bl initPXAvoltage /* In case the board is rebooting with a */
- mov lr, r10 /* low voltage raise it up to a good one. */
-
-#if 1
- b initirqs
-#endif
-
-wakeup:
- /* Are we waking from sleep? */
- ldr r0, =RCSR
- ldr r1, [r0]
- and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r1, [r0]
- teq r1, #RCSR_SMR
-
- bne initirqs
-
- ldr r0, =PSSR
- mov r1, #PSSR_PH
- str r1, [r0]
-
- /* if so, resume at PSPR */
- ldr r0, =PSPR
- ldr r1, [r0]
- mov pc, r1
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off on-chip peripheral clocks (except for memory) */
- /* for re-configuration. */
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN
- str r2, [r1]
-
- /* ... and write the core clock config register */
- ldr r2, =CONFIG_SYS_CCCR
- ldr r1, =CCCR
- str r2, [r1]
-
- /* Turn on turbo mode */
- mrc p14, 0, r2, c6, c0, 0
- orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
- mcr p14, 0, r2, c6, c0, 0
-
- /* Re-write MDREFR */
- ldr r1, =MEMC_BASE
- ldr r2, [r1, #MDREFR_OFFSET]
- str r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#else
-#error "RTC not defined"
-#endif
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
- /* FIXME */
-
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/ttcontrol/vision2/config.mk b/board/ttcontrol/vision2/config.mk
index 59f3367..952037e 100644
--- a/board/ttcontrol/vision2/config.mk
+++ b/board/ttcontrol/vision2/config.mk
@@ -20,6 +20,6 @@
# MA 02111-1307 USA
#
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
-TEXT_BASE = 0x97800000
+CONFIG_SYS_TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
+ALL += $(obj)u-boot.imx
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index ce4cb78..f8ef4fc 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -37,14 +37,34 @@
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc13892.h>
+#include <linux/fb.h>
DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
+extern int mx51_fb_init(struct fb_videomode *mode);
+
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
+static struct fb_videomode nec_nl6448bc26_09c = {
+ "NEC_NL6448BC26-09C",
+ 60, /* Refresh */
+ 640, /* xres */
+ 480, /* yres */
+ 37650, /* pixclock = 26.56Mhz */
+ 48, /* left margin */
+ 16, /* right margin */
+ 31, /* upper margin */
+ 12, /* lower margin */
+ 96, /* hsync-len */
+ 2, /* vsync-len */
+ 0, /* sync */
+ FB_VMODE_NONINTERLACED, /* vmode */
+ 0, /* flag */
+};
+
void hw_watchdog_reset(void)
{
int val;
@@ -140,19 +160,8 @@ u32 get_board_rev(void)
int dram_init(void)
{
-#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-#if (CONFIG_NR_DRAM_BANKS > 1)
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
-#endif
-#else
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
-#endif
return 0;
}
@@ -423,6 +432,9 @@ static void setup_gpios(void)
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
+ /* PWM Output GPIO1_2 */
+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+
/*
* Set GPIO1_4 to high and output; it is used to reset
* the system on reboot
@@ -630,11 +642,35 @@ int board_early_init_f(void)
return 0;
}
+static void backlight(int on)
+{
+ if (on) {
+ mxc_gpio_set(65, 1);
+ udelay(10000);
+ mxc_gpio_set(68, 1);
+ } else {
+ mxc_gpio_set(65, 0);
+ mxc_gpio_set(68, 0);
+ }
+}
+
+void lcd_enable(void)
+{
+ int ret;
+
+ mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+
+ mxc_gpio_set(2, 1);
+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+
+ ret = mx51_fb_init(&nec_nl6448bc26_09c);
+ if (ret)
+ puts("LCD cannot be configured\n");
+}
+
int board_init(void)
{
-#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
- board_early_init_f();
-#endif
gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -709,3 +745,21 @@ int checkboard(void)
return 0;
}
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int on;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ on = (strcmp(argv[1], "on") == 0);
+ backlight(on);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+ "Vision2 Backlight",
+ "lcdbl [on|off]\n"
+);
diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk
deleted file mode 100644
index 60cbc24..0000000
--- a/board/wepep250/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
-#CONFIG_SYS_TEXT_BASE = 0xa1001000
diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c
deleted file mode 100644
index c6e9171..0000000
--- a/board/wepep250/flash.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- * hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-# define FLASH_BUS vu_char
-# define FLASH_BUS_RET u_char
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# else
-# error "With 8bit bus only one chip is allowed"
-# endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-# define FLASH_BUS vu_short
-# define FLASH_BUS_RET u_short
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( WEP_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 8 )| x )
-# else
-# error "With 16bit bus only 1 or 2 chip(s) are allowed"
-# endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-# define FLASH_BUS vu_long
-# define FLASH_BUS_RET u_long
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( WEP_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 16 )| x )
-# elif ( WEP_FLASH_INTERLEAVE == 4 )
-# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-# else
-# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-# endif
-
-#else
-# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
- FLASH_BUS *addr = (FLASH_BUS *) 0;
-
- *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
- return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
- int ok = 1;
-
- reset_timer_masked ();
- while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
- FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer_masked () > timeout && timeout != 0) {
- ok = 0;
- break;
- }
- }
- return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-# error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
- int i;
- FLASH_BUS address = WEP_FLASH_BASE;
-
- flash_info[0].size = WEP_FLASH_BANK_SIZE;
- flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[0].flash_id = INTEL_MANUFACT;
- memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
- flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
- /* Some devices are hw locked after start. */
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
- flash_ready (0);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
- address += WEP_FLASH_SECT_SIZE;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- printf (" Intel vendor\n");
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if (!(i % 5)) {
- printf ("\n");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, non_protected = 0, sector;
- int rc = ERR_OK;
-
- FLASH_BUS *address;
-
- for (sector = s_first; sector <= s_last; sector++) {
- if (!info->protect[sector]) {
- non_protected++;
- }
- }
-
- if (!non_protected) {
- return ERR_PROTECTED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
-
- /* Start erase on unprotected sectors */
- for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
- if (info->protect[sector]) {
- printf ("Protected sector %2d skipping...\n", sector);
- continue;
- } else {
- printf ("Erasing sector %2d ... ", sector);
- }
-
- address = (FLASH_BUS *) (info->start[sector]);
-
- *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
- *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
- if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- printf ("ok.\n");
- } else {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- break;
- }
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- }
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked (10000);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
- FLASH_BUS *address = (FLASH_BUS *) dest;
- int rc = ERR_OK;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*address & data) != data) {
- return ERR_NOT_ERASED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts ();
-
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
- *address = data;
-
- if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- }
-
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong read_addr, write_addr;
- FLASH_BUS data;
- int i, result = ERR_OK;
-
-
- read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
- write_addr = read_addr;
- if (read_addr != addr) {
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (read_addr < addr || cnt == 0) {
- data |= *((uchar *) read_addr) << i * 8;
- } else {
- data |= (*src++) << i * 8;
- cnt--;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- }
- for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
- if ((result = write_data (info, write_addr,
- *((FLASH_BUS *) src))) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- src += sizeof (FLASH_BUS);
- }
- if (cnt > 0) {
- read_addr = write_addr;
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (cnt > 0) {
- data |= (*src++) << i * 8;
- cnt--;
- } else {
- data |= *((uchar *) read_addr) << i * 8;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != 0) {
- return result;
- }
- }
- return ERR_OK;
-}
diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h
deleted file mode 100644
index 77498b6..0000000
--- a/board/wepep250/intel.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S
deleted file mode 100644
index 9bb091f..0000000
--- a/board/wepep250/lowlevel_init.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- * Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- * Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- * Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* setup memory - see 6.12 in [1]
- * Step 1 - wait 200 us
- */
- mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r0, r0, #1
- bne 1b
-/* TODO: complete step 1 for Synchronous Static memory*/
-
- ldr r0, =0x48000000 /* MC_BASE */
-
-
-/* step 1.a - setup MSCx
- */
- ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
- str r1, [r0, #0x8] /* MSC0_OFFSET */
-
-/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- * see AUTO REFRESH chapter in section D. in [2] and in [3]
- * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- * TODO: complete for Synchronous Static memory
- */
- ldr r1, [r0, #4] /* MDREFR_OFFSET */
- ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
- bic r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
- orr r1, r1, #48 /* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
- orr r1, r1, #24 /* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 2 - only for Synchronous Static memory (TODO)
- *
- * Step 3 - same as step 4
- *
- * Step 4
- *
- * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
- orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
- bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.b - clear MDREFR:SLFRSH */
- bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.c - set MDREFR:E1PIN */
- orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.d - automatically done
- *
- * Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
- ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
- ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 5 - wait at least 200 us for SDRAM
- * see section B. in [2]
- */
- mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r2, r2, #1
- bne 1b
-
-/* Step 6 - after reset dcache is disabled, so automatically done
- *
- * Step 7 - eight refresh cycles
- */
- mov r2, #0xA0000000
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
-
-/* Step 8 - we don't need dcache now
- *
- * Step 9 - enable SDRAM partition 0
- */
- orr r1, r1, #1 /* MDCNFG_DE0 */
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 10 - write MDMRS */
- mov r1, #0
- str r1, [r0, #0x40] /* MDMRS_OFFSET */
-
-/* Step 11 - optional (TODO) */
-
- mov pc,r10
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
deleted file mode 100644
index 6e41ea6..0000000
--- a/board/wepep250/wepep250.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
- gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
- writel(0x80, GPDR1);
- writel(0x8010, GAFR1_L);
-#elif defined( CONFIG_BTUART )
- writel(0x800, GPDR1);
- writel(0x900000, GAFR1_L);
-#endif
- writel(0x20, PSSR);
-
- return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
- gd->bd->bi_dram[0].start = WEP_SDRAM_1;
- gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
- gd->bd->bi_dram[1].start = WEP_SDRAM_2;
- gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
- gd->bd->bi_dram[2].start = WEP_SDRAM_3;
- gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
- gd->bd->bi_dram[3].start = WEP_SDRAM_4;
- gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
- return 0;
-}
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
index 7dd2ea0..554915a 100644
--- a/board/xaeniax/Makefile
+++ b/board/xaeniax/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := xaeniax.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk
deleted file mode 100644
index c639752..0000000
--- a/board/xaeniax/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa3FB0000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
deleted file mode 100644
index 57e1620..0000000
--- a/board/xaeniax/lowlevel_init.S
+++ /dev/null
@@ -1,424 +0,0 @@
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0,=GPSR0
- ldr r1,=CONFIG_SYS_GPSR0_VAL
- str r1,[r0]
-
- ldr r0,=GPSR1
- ldr r1,=CONFIG_SYS_GPSR1_VAL
- str r1,[r0]
-
- ldr r0,=GPSR2
- ldr r1,=CONFIG_SYS_GPSR2_VAL
- str r1,[r0]
-
- ldr r0,=GPCR0
- ldr r1,=CONFIG_SYS_GPCR0_VAL
- str r1,[r0]
-
- ldr r0,=GPCR1
- ldr r1,=CONFIG_SYS_GPCR1_VAL
- str r1,[r0]
-
- ldr r0,=GPCR2
- ldr r1,=CONFIG_SYS_GPCR2_VAL
- str r1,[r0]
-
- ldr r0,=GPDR0
- ldr r1,=CONFIG_SYS_GPDR0_VAL
- str r1,[r0]
-
- ldr r0,=GPDR1
- ldr r1,=CONFIG_SYS_GPDR1_VAL
- str r1,[r0]
-
- ldr r0,=GPDR2
- ldr r1,=CONFIG_SYS_GPDR2_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_L
- ldr r1,=CONFIG_SYS_GAFR0_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_U
- ldr r1,=CONFIG_SYS_GAFR0_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_L
- ldr r1,=CONFIG_SYS_GAFR1_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_U
- ldr r1,=CONFIG_SYS_GAFR1_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_L
- ldr r1,=CONFIG_SYS_GAFR2_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_U
- ldr r1,=CONFIG_SYS_GAFR2_U_VAL
- str r1,[r0]
-
- ldr r0,=PSSR /* enable GPIO pins */
- ldr r1,=CONFIG_SYS_PSSR_VAL
- str r1,[r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1,=MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2,=CONFIG_SYS_MSC0_VAL
- str r2,[r1, #MSC0_OFFSET]
- ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
-
- /* MSC1: nCS(2,3) */
- ldr r2,=CONFIG_SYS_MSC1_VAL
- str r2,[r1, #MSC1_OFFSET]
- ldr r2,[r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2,=CONFIG_SYS_MSC2_VAL
- str r2,[r1, #MSC2_OFFSET]
- ldr r2,[r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2,=CONFIG_SYS_MECR_VAL
- str r2,[r1, #MECR_OFFSET]
- ldr r2,[r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2,=CONFIG_SYS_MCMEM0_VAL
- str r2,[r1, #MCMEM0_OFFSET]
- ldr r2,[r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2,=CONFIG_SYS_MCMEM1_VAL
- str r2,[r1, #MCMEM1_OFFSET]
- ldr r2,[r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2,=CONFIG_SYS_MCATT0_VAL
- str r2,[r1, #MCATT0_OFFSET]
- ldr r2,[r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2,=CONFIG_SYS_MCATT1_VAL
- str r2,[r1, #MCATT1_OFFSET]
- ldr r2,[r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2,=CONFIG_SYS_MCIO0_VAL
- str r2,[r1, #MCIO0_OFFSET]
- ldr r2,[r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2,=CONFIG_SYS_MCIO1_VAL
- str r2,[r1, #MCIO1_OFFSET]
- ldr r2,[r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- @ get the mdrefr settings
- ldr r4,=CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- str r4,[r1, #MDREFR_OFFSET]
- ldr r4,[r1, #MDREFR_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #MDREFR_K1RUN
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #MDREFR_SLFRSH
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
- orr r4, r4, #(MDREFR_E1PIN)
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-
- /* Step 4d: */
- /* fetch platform value of mdcnfg */
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* get memory controller base address */
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r1, =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
- ldr r2, =ICMR
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
-test:
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size ?*/
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 4c19c4d..40b0f3b 100644
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of xaeniax */
gd->bd->bi_arch_number = 585;
@@ -58,19 +59,18 @@ int board_late_init(void)
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- /* gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
- /* gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
- /* gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
- /* gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
- /* gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
- /* gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
- return 0;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index d022831..16e0b66 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -32,7 +32,11 @@ LIB = $(obj)lib$(VENDOR).a
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
+COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
+COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
+COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/xes/common/board.c b/board/xes/common/board.c
new file mode 100644
index 0000000..738f0a6
--- /dev/null
+++ b/board/xes/common/board.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+ char name[] = CONFIG_SYS_BOARD_NAME;
+ char *s;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+ s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+ s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+ s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+ s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+ s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+ s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+ s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+ s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+ s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+ s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+ s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+ s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+ s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+ s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+ name[strlen(name) - 1] += get_board_derivative();
+ printf("Board: X-ES %s %s SBC\n", name, s);
+
+ /* Display board specific information */
+ puts(" ");
+ if ((s = getenv("board_rev")))
+ printf("Rev %s, ", s);
+ if ((s = getenv("serial#")))
+ printf("Serial# %s, ", s);
+ if ((s = getenv("board_cfg")))
+ printf("Cfg %s", s);
+ puts("\n");
+
+ return 0;
+}
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index f4a17b7..20d0a30 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
if (in_be32(&gur->gpporcr) & 0x10000)
return 66666666;
else
+#ifdef CONFIG_P2020
+ return 100000000;
+#else
return 50000000;
+#endif
}
#ifdef CONFIG_MPC85xx
@@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
+#ifdef CONFIG_P2020
+ if (in_be32(&gur->gpporcr) & 0x20000)
+ return 66666666;
+ else
+ return 100000000;
+#else
return 66666666;
+#endif
}
#endif
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
new file mode 100644
index 0000000..36e9146
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+ if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_NVM_WP)
+ return 1;
+
+ return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number. For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+ /*
+ * The top 4 lines of the local bus address are pulled low/high and
+ * can be read to determine the least significant digit of a board's
+ * model number.
+ */
+ return gur->gpporcr >> 28;
+}
diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/xes/common/fsl_8xxx_misc.h
index a43dac2..ecc70da 100644
--- a/board/colibri_pxa270/lowlevel_init.S
+++ b/board/xes/common/fsl_8xxx_misc.h
@@ -1,7 +1,8 @@
/*
- * Toradex Colibri PXA270 Lowlevel Hardware Initialization
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -10,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -19,18 +20,9 @@
* MA 02111-1307 USA
*/
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
+uint get_board_derivative(void);
- mov pc, lr
+#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index ece7882..f425cee 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -25,10 +25,10 @@
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <libfdt.h>
#include <fdt_support.h>
-int first_free_busno = 0;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
@@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
-#ifdef CONFIG_MPC8572
-/* Correlate host/agent POR bits to usable info. Table 4-14 */
-struct host_agent_cfg_t {
- uchar pcie_root[3];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{0, 0, 0}, 0},
- {{0, 1, 1}, 1},
- {{1, 0, 1}, 0},
- {{1, 1, 0}, 1},
- {{0, 0, 1}, 0},
- {{0, 1, 0}, 1},
- {{1, 0, 0}, 0},
- {{1, 1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-15 */
-struct io_port_cfg_t {
- uchar pcie_width[3];
- uchar rio_width;
-} io_port_cfg[16] = {
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{4, 0, 0}, 0},
- {{4, 4, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 4},
- {{4, 2, 2}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{4, 0, 0}, 4},
- {{4, 0, 0}, 4},
- {{0, 0, 0}, 4},
- {{0, 0, 0}, 4},
- {{8, 0, 0}, 0},
-};
-#elif defined CONFIG_MPC8548
-/* Correlate host/agent POR bits to usable info. Table 4-12 */
-struct host_agent_cfg_t {
- uchar pci_host[2];
- uchar pcie_root[1];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{1, 1}, {0}, 0},
- {{1, 1}, {1}, 0},
- {{1, 1}, {0}, 1},
- {{0, 0}, {0}, 0}, /* reserved */
- {{0, 1}, {1}, 0},
- {{1, 1}, {1}, 0},
- {{0, 1}, {1}, 1},
- {{1, 1}, {1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-13 */
-struct io_port_cfg_t {
- uchar pcie_width[1];
- uchar rio_width;
-} io_port_cfg[8] = {
- {{0}, 0},
- {{0}, 0},
- {{0}, 0},
- {{4}, 4},
- {{4}, 4},
- {{0}, 4},
- {{0}, 4},
- {{8}, 0},
-};
-#elif defined CONFIG_MPC86xx
-/* Correlate host/agent POR bits to usable info. Table 4-17 */
-struct host_agent_cfg_t {
- uchar pcie_root[2];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{0, 0}, 0},
- {{1, 0}, 1},
- {{0, 1}, 0},
- {{1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-16 */
-struct io_port_cfg_t {
- uchar pcie_width[2];
- uchar rio_width;
-} io_port_cfg[16] = {
- {{0, 0}, 0},
- {{0, 0}, 0},
- {{8, 0}, 0},
- {{8, 8}, 0},
- {{0, 0}, 0},
- {{8, 0}, 4},
- {{8, 0}, 4},
- {{8, 0}, 4},
- {{0, 0}, 0},
- {{0, 0}, 4},
- {{0, 0}, 4},
- {{0, 0}, 4},
- {{0, 0}, 0},
- {{0, 0}, 0},
- {{0, 8}, 0},
- {{8, 8}, 0},
-};
-#endif
-
/*
* 85xx and 86xx share naming conventions, but different layout.
* Correlate names to CPU-specific values to share common
@@ -173,22 +68,22 @@ struct io_port_cfg_t {
void pci_init_board(void)
{
- struct pci_controller *hose;
- volatile ccsr_fsl_pci_t *pci;
- int width;
- int host;
+ struct fsl_pci_info pci_info[3];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
+
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
- uint devdisr = in_be32(&gur->devdisr);
- uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
- uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
- MPC8xxx_PORBMSR_HA_SHIFT;
- struct pci_region *r;
#ifdef CONFIG_PCI1
uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
@@ -197,49 +92,19 @@ void pci_init_board(void)
uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
- width = 0; /* Silence compiler warning... */
- io_sel &= 0xf; /* Silence compiler warning... */
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- hose = &pci1_hose;
- host = host_agent_cfg[host_agent].pci_host[0];
- r = hose->regions;
-
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
pci_32 ? 32 : 64,
pcix ? "PCIX" : "PCI",
pci_spd_norm ? ">=" : "<=",
pcix ? freq * 2 : freq,
- host ? "host" : "agent",
+ pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
printf(" PCI1: disabled\n");
}
@@ -247,148 +112,53 @@ void pci_init_board(void)
/* PCI1 not present on MPC8572 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
-#ifdef CONFIG_PCIE1
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
- host = host_agent_cfg[host_agent].pcie_root[0];
- width = io_port_cfg[io_sel].pcie_width[0];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
- printf("\n PCIE1 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+#ifdef CONFIG_PCIE1
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf(" PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- hose = &pcie2_hose;
- host = host_agent_cfg[host_agent].pcie_root[1];
- width = io_port_cfg[io_sel].pcie_width[1];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
- printf("\n PCIE2 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf(" PCIE2 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+ } else {
+ printf(" PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
#endif /* CONFIG_PCIE2 */
#ifdef CONFIG_PCIE3
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- hose = &pcie3_hose;
- host = host_agent_cfg[host_agent].pcie_root[2];
- width = io_port_cfg[io_sel].pcie_width[2];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
- printf("\n PCIE3 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BASE,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE3 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+ printf(" PCIE3 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
+ } else {
+ printf(" PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
diff --git a/board/xes/xpedite5170/Makefile b/board/xes/xpedite517x/Makefile
index fea6686..fea6686 100644
--- a/board/xes/xpedite5170/Makefile
+++ b/board/xes/xpedite517x/Makefile
diff --git a/board/xes/xpedite5170/ddr.c b/board/xes/xpedite517x/ddr.c
index 1d57d09..1d57d09 100644
--- a/board/xes/xpedite5170/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
diff --git a/board/xes/xpedite5170/law.c b/board/xes/xpedite517x/law.c
index 0b7d9ef..0b7d9ef 100644
--- a/board/xes/xpedite5170/law.c
+++ b/board/xes/xpedite517x/law.c
diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite517x/xpedite517x.c
index 5822941..0f7fa6c 100644
--- a/board/xes/xpedite5170/xpedite5170.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -26,30 +26,12 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
#endif
-int checkboard(void)
-{
- char *s;
-
- printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- return 0;
-}
/*
* Print out which flash was booted from and if booting from the 2nd flash,
* swap flash chip selects to maintain consistent flash numbering/addresses.
diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite520x/Makefile
index 02fe8fc..02fe8fc 100644
--- a/board/xes/xpedite5200/Makefile
+++ b/board/xes/xpedite520x/Makefile
diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite520x/ddr.c
index c5616d5..c5616d5 100644
--- a/board/xes/xpedite5200/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite520x/law.c
index bbfcb9d..bbfcb9d 100644
--- a/board/xes/xpedite5200/law.c
+++ b/board/xes/xpedite520x/law.c
diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite520x/tlb.c
index bd7bff8..bd7bff8 100644
--- a/board/xes/xpedite5200/tlb.c
+++ b/board/xes/xpedite520x/tlb.c
diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite520x/xpedite520x.c
index a2627f8..dc5c965 100644
--- a/board/xes/xpedite5200/xpedite5200.c
+++ b/board/xes/xpedite520x/xpedite520x.c
@@ -36,33 +36,6 @@
extern void ft_board_pci_setup(void *blob, bd_t *bd);
-int checkboard(void)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- char *s;
-
- printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
- out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
- out_be32(&ecm->eedr, 0xffffffff); /* Clear ecm errors */
- out_be32(&ecm->eeer, 0xffffffff); /* Enable ecm errors */
-
- return 0;
-}
-
static void flash_cs_fixup(void)
{
int flash_sel;
diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite537x/Makefile
index 919397c..919397c 100644
--- a/board/xes/xpedite5370/Makefile
+++ b/board/xes/xpedite537x/Makefile
diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite537x/ddr.c
index 4d3f255..4d3f255 100644
--- a/board/xes/xpedite5370/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite537x/law.c
index daee676..daee676 100644
--- a/board/xes/xpedite5370/law.c
+++ b/board/xes/xpedite537x/law.c
diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite537x/tlb.c
index a465ce3..a465ce3 100644
--- a/board/xes/xpedite5370/tlb.c
+++ b/board/xes/xpedite537x/tlb.c
diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite537x/xpedite537x.c
index 2a060c2..89fa6c7 100644
--- a/board/xes/xpedite5370/xpedite5370.c
+++ b/board/xes/xpedite537x/xpedite537x.c
@@ -36,26 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_board_pci_setup(void *blob, bd_t *bd);
-int checkboard(void)
-{
- char *s;
-
- printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- return 0;
-}
-
static void flash_cs_fixup(void)
{
int flash_sel;
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
new file mode 100644
index 0000000..8980a4b
--- /dev/null
+++ b/board/xes/xpedite550x/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
new file mode 100644
index 0000000..38a4597
--- /dev/null
+++ b/board/xes/xpedite550x/ddr.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr3_spd_eeprom_t));
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+/*
+ * There are traditionally three board-specific SDRAM timing parameters
+ * which must be calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 3.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ * The P2020 processor provides an autoleveling option. Setting CPO to
+ * 0x1f enables this auto configuration.
+ */
+
+typedef struct {
+ unsigned short datarate_mhz_low;
+ unsigned short datarate_mhz_high;
+ unsigned char clk_adjust;
+ unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR3-600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ {
+ /* DDR3-800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ ulong ddr_freq;
+
+ /*
+ * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ }
+ }
+ }
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->twoT_en = 0;
+ }
+ pbsp++;
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+
+ /*
+ * Enable on-die termination.
+ * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+ * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
+ * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
+ */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 3;
+}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
new file mode 100644
index 0000000..4d4445d
--- /dev/null
+++ b/board/xes/xpedite550x/law.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
new file mode 100644
index 0000000..cf3ff4d
--- /dev/null
+++ b/board/xes/xpedite550x/tlb.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
new file mode 100644
index 0000000..2ad30a3
--- /dev/null
+++ b/board/xes/xpedite550x/xpedite550x.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/xm250/Makefile b/board/xm250/Makefile
index a174f66..11e2b30 100644
--- a/board/xm250/Makefile
+++ b/board/xm250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := xm250.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xm250/config.mk b/board/xm250/config.mk
deleted file mode 100644
index a3fa0e5..0000000
--- a/board/xm250/config.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys XM250 board:
-#
-
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S
deleted file mode 100644
index 8230550..0000000
--- a/board/xm250/lowlevel_init.S
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-/*
- .macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
- ldr r7, =0
- str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
- ldr r7, =\val
- str r7, [r6]
- .endm
-*/
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* SET_LED 1 */
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- * Initlialize Memory Controller
- *
- * See PXA250 Operating System Developer's Guide
- *
- * pause for 200 uSecs- allow internal clocks to settle
- * *Note: only need this if hard reset... doing it anyway for now
- */
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* SET_LED 2 */
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r4, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for FLASH clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank DRAM 0
- @
- orr r4, r4, #0x00010000
-
- @ set K2RUN for bank PLD
- @
- orr r4, r4, #0x00040000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End lowlevel_init
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index 246bdde..3188cf2 100644
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -56,6 +56,10 @@ int
board_init (void)
/**********************************************************/
{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
/* arch number of MicroSys XM250 */
gd->bd->bi_arch_number = MACH_TYPE_XM250;
@@ -65,21 +69,18 @@ board_init (void)
return 0;
}
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
- return (0);
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile
deleted file mode 100644
index fc23935..0000000
--- a/board/xsengine/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := xsengine.o flash.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk
deleted file mode 100644
index 821bb3b..0000000
--- a/board/xsengine/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
deleted file mode 100644
index 736905a..0000000
--- a/board/xsengine/flash.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define SWAP(x) __swab32(x)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Functions */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors */
- flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
- flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
- break;
- case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case AMD_MANUFACT:
- debug ("Manufacturer: AMD\n");
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- debug ("Manufacturer: FUJITSU\n");
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- debug ("Manufacturer: *** unknown ***\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
-
- case AMD_ID_MIRROR:
- debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
- addr[14], addr[15]);
- switch(addr[14]) {
- case AMD_ID_LV640U_2:
- if (addr[15] != AMD_ID_LV640U_3) {
- debug ("Chip: AMLV640U -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- } else {
- debug ("Chip: AMLV640U\n");
- info->flash_id += FLASH_AMLV640U;
- info->sector_count = 128;
- info->size = 0x01000000;
- }
- break; /* => 16 MB */
- case AMD_ID_GL064MT_2:
- if (addr[15] != AMD_ID_GL064MT_3) {
- debug ("Chip: S29GL064M-R3 -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- } else {
- debug ("Chip: S29GL064M-R3\n");
- info->flash_id += FLASH_S29GL064M;
- info->sector_count = 128;
- info->size = 0x01000000;
- }
- break; /* => 16 MB */
- default:
- debug ("Chip: *** unknown ***\n");
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- switch (value) {
- case AMD_ID_MIRROR:
- switch (info->flash_id & FLASH_TYPEMASK) {
- /* only known types here - no default */
- case FLASH_AMLV128U:
- case FLASH_AMLV640U:
- case FLASH_AMLV320U:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x20000;
- }
- break;
- case FLASH_AMLV320B:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- /*
- * The first 8 sectors are 8 kB,
- * all the other ones are 64 kB
- */
- base += (i < 8)
- ? 2 * ( 8 << 10)
- : 2 * (64 << 10);
- }
- break;
- }
- break;
-
- default:
- return (0);
- break;
- }
-
-#if 0
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-#endif
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 100000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, SWAP(data))) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, SWAP(data))) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, SWAP(data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
deleted file mode 100644
index 0d94ab6..0000000
--- a/board/xsengine/lowlevel_init.S
+++ /dev/null
@@ -1,221 +0,0 @@
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* ---- GPIO INITIALISATION ---- */
-/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
-
- /* General purpose set registers */
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- /* General purpose clear registers */
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- /* General rising edge registers */
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- /* General falling edge registers */
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- /* General edge detect registers */
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- /* General alternate function registers */
- ldr r0, =GAFR0_L /* [0:15] */
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
- ldr r0, =GAFR0_U /* [31:16] */
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
- ldr r0, =GAFR1_L /* [47:32] */
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
- ldr r0, =GAFR1_U /* [63:48] */
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
- ldr r0, =GAFR2_L /* [79:64] */
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
- ldr r0, =GAFR2_U /* [80] */
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* General purpose direction registers */
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- /* Power manager sleep status */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ---- MEMORY INITIALISATION ---- */
-/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
-/* pause for 200 uSecs- allow internal clocks to settle */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-/* get memory controller base address */
- ldr r1, =MEMC_BASE
-
-/* ---- FLASH INITIALISATION ---- */
-/* Write MSC0 and read back to ensure data change is accepted by cpu */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
-/* ---- SDRAM INITIALISATION ---- */
-/* get the MDREFR settings */
- ldr r2, =CONFIG_SYS_MDREFR_VAL
- str r2, [r1, #MDREFR_OFFSET]
-
-/* fetch platform value of MDCNFG */
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
-/* disable all sdram banks */
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
-/* write initial value of MDCNFG, w/o enabling sdram banks */
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* pause for 200 uSecs */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* about 200 usec */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-/* Access memory *not yet enabled* for CBR refresh cycles (8) */
-/* CBR is generated for all banks */
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
-/* get memory controller base address */
- ldr r2, =MEMC_BASE
-
-/* Enable SDRAM bank 0 in MDCNFG register */
- ldr r2, [r1, #MDCNFG_OFFSET]
- orr r2, r2, #MDCNFG_DE0
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-/* ---- INTERRUPT INITIALISATION ---- */
-/* Disable (mask) all interrupts at the interrupt controller */
-/* clear the interrupt level register (use IRQ, not FIQ) */
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
-/* Set interrupt mask register */
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
-/* ---- CLOCK INITIALISATION ---- */
-/* Disable the peripheral clocks, and set the core clock */
-
-/* Turn Off ALL on-chip peripheral clocks for re-configuration */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-/* set core clocks */
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
-/* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
-/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
-/* Turn on needed clocks */
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- mov pc, r10
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
deleted file mode 100644
index 4464fd4..0000000
--- a/board/xsengine/xsengine.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* arch number */
- gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int board_late_init (void)
-{
- setenv ("stdout", "serial");
- setenv ("stderr", "serial");
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif