diff options
Diffstat (limited to 'board')
53 files changed, 687 insertions, 241 deletions
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 4c3a9ba..263bb54 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -13,7 +13,7 @@ #include <command.h> #include <i2c.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* GPIO configuration */ - kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -77,7 +77,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3773587..17e6296 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -12,7 +12,7 @@ #include <common.h> #include <command.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); + mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -73,7 +73,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c index 2dc5018..8620e4b 100644 --- a/board/LaCie/wireless_space/wireless_space.c +++ b/board/LaCie/wireless_space/wireless_space.c @@ -12,7 +12,7 @@ #include <common.h> #include <command.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> @@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = { int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ kirkwood_mpp_conf(kwmpp_config, NULL); @@ -112,7 +112,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig new file mode 100644 index 0000000..f94a444 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -0,0 +1,23 @@ +if TARGET_DB_MV784MP_GP + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "db-mv784mp-gp" + +config SYS_VENDOR + string + default "Marvell" + +config SYS_SOC + string + default "armada-xp" + +config SYS_CONFIG_NAME + string + default "db-mv784mp-gp" + +endif diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS new file mode 100644 index 0000000..a095f89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_MV784MP_GP BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/Marvell/db-mv784mp-gp/ +F: include/configs/db-mv784mp-gp.h +F: configs/db-mv784mp-gp_defconfig diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile new file mode 100644 index 0000000..8f5a7fb --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-mv784mp-gp.o diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c new file mode 100644 index 0000000..b3dae89 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr) (1UL << (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka + * "RD-AXP-GP rev 1.0". + * + * GPPs + * MPP# NAME IN/OUT + * ---------------------------------------------- + * 21 SW_Reset_ OUT + * 25 Phy_Int# IN + * 28 SDI_WP IN + * 29 SDI_Status IN + * 54-61 On GPP Connector ? + * 62 Switch Interrupt IN + * 63-65 Reserved from SW Board ? + * 66 SW_BRD connected IN + */ +#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) +#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) +#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x00000000, MVEBU_MPP_BASE + 0x04); + writel(0x33000000, MVEBU_MPP_BASE + 0x08); + writel(0x11000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11111111, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000003, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-MV784MP-GP\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1545 PHY */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* Enable QSGMII AN */ + /* Set page to 4 */ + miiphy_write(name, devadr, 0x16, 4); + /* Enable AN */ + miiphy_write(name, devadr, 0x0, 0x1140); + /* Set page to 0 */ + miiphy_write(name, devadr, 0x16, 0); + + /* Phy C_ANEG */ + miiphy_read(name, devadr, 0x4, ®); + reg |= 0x1E0; + miiphy_write(name, devadr, 0x4, reg); + + /* Soft-Reset */ + miiphy_write(name, devadr, 22, 0x0000); + miiphy_write(name, devadr, 0, 0x9140); + + /* Power up the phy */ + miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + + printf("88E1545 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg new file mode 100644 index 0000000..d7ef407 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068 diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index b53c810..0887d92 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -12,7 +12,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "dreamplug.h" @@ -25,9 +25,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DREAMPLUG_OE_VAL_LOW, - DREAMPLUG_OE_VAL_HIGH, - DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); + mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW, + DREAMPLUG_OE_VAL_HIGH, + DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -90,7 +90,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 72bccc8..b0d5f1e 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "guruplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GURUPLUG_OE_VAL_LOW, - GURUPLUG_OE_VAL_HIGH, - GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); + mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, + GURUPLUG_OE_VAL_HIGH, + GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index e1652c0..ef08ad8 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -11,7 +11,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "mv88f6281gtw_ge.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); + mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, + MV88F6281GTW_GE_OE_VAL_HIGH, + MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -94,7 +94,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index a005a2f..55cf525 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -14,7 +14,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "openrd.h" @@ -27,9 +27,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -104,7 +104,7 @@ int board_init(void) #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 33ef0c7..b0020c9 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -10,7 +10,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "rd6281a.h" @@ -23,9 +23,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(RD6281A_OE_VAL_LOW, - RD6281A_OE_VAL_HIGH, - RD6281A_OE_LOW, RD6281A_OE_HIGH); + mvebu_config_gpio(RD6281A_OE_VAL_LOW, + RD6281A_OE_VAL_HIGH, + RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -93,7 +93,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 87e49f4..8907fb5 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "sheevaplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, - SHEEVAPLUG_OE_VAL_HIGH, - SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); + mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW, + SHEEVAPLUG_OE_VAL_HIGH, + SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index ff6a6a0..83ab1bc 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -11,7 +11,7 @@ #include <common.h> #include <miiphy.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> #include <asm/io.h> @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DOCKSTAR_OE_VAL_LOW, - DOCKSTAR_OE_VAL_HIGH, - DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); + mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW, + DOCKSTAR_OE_VAL_HIGH, + DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -96,7 +96,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -143,7 +143,7 @@ void reset_phy(void) static void set_leds(u32 leds, u32 blinking) { - struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE; + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; u32 oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index a6598e9..1f4fb92 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -14,7 +14,7 @@ #include <common.h> #include <miiphy.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> #include <asm/io.h> @@ -83,9 +83,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GOFLEXHOME_OE_VAL_LOW, - GOFLEXHOME_OE_VAL_HIGH, - GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); + mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW, + GOFLEXHOME_OE_VAL_HIGH, + GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -98,7 +98,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking) u32 oe; u32 bl; - r = (struct kwgpio_registers *)KW_GPIO1_BASE; + r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 659a124..b0d49c4 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -13,11 +13,12 @@ #include <malloc.h> #include <netdev.h> #include <miiphy.h> -#include <asm/arch/kirkwood.h> +#include <spi.h> +#include <spi_flash.h> +#include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> -#include <spi_flash.h> #include "lsxl.h" @@ -51,9 +52,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(LSXL_OE_VAL_LOW, - LSXL_OE_VAL_HIGH, - LSXL_OE_LOW, LSXL_OE_HIGH); + mvebu_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); /* * Multi-Purpose Pins Functionality configuration @@ -167,7 +168,7 @@ static void set_led(int state) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; set_led(LED_POWER_BLINKING); diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index 4f2ac89..27ebe78 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o +obj-y += coreboot_start.o coreboot.o diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c new file mode 100644 index 0000000..0240c34 --- /dev/null +++ b/board/chromebook-x86/coreboot/coreboot.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cros_ec.h> + +int arch_early_init_r(void) +{ + if (cros_ec_board_init()) + return -1; + + return 0; +} diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 0e63258..8309d06 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -13,7 +13,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "pogo_e02.h" @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(POGO_E02_OE_VAL_LOW, - POGO_E02_OE_VAL_HIGH, - POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + mvebu_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -64,7 +64,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index fdb8ebf..f77ff48 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -9,11 +9,13 @@ */ #include <common.h> +#include <dm.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> #include <fdt_support.h> #include <sata.h> +#include <serial_mxc.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> @@ -69,16 +71,23 @@ static iomux_v3_cfg_t const sata_pads[] = { IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void cm_fx6_setup_issd(void) +static int cm_fx6_setup_issd(void) { + int ret, i; + SETUP_IOMUX_PADS(sata_pads); - /* Make sure this gpio has logical 0 value */ - gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); - udelay(100); - cm_fx6_sata_power(0); - mdelay(250); - cm_fx6_sata_power(1); + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); + if (ret) + return ret; + } + + ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); + if (ret) + return ret; + + return 0; } #define CM_FX6_SATA_INIT_RETRIES 10 @@ -86,7 +95,14 @@ int sata_initialize(void) { int err, i; - cm_fx6_setup_issd(); + /* Make sure this gpio has logical 0 value */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); + udelay(100); + + cm_fx6_sata_power(0); + mdelay(250); + cm_fx6_sata_power(1); + for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { err = setup_sata(); if (err) { @@ -109,6 +125,8 @@ int sata_initialize(void) return err; } +#else +static int cm_fx6_setup_issd(void) { return 0; } #endif #ifdef CONFIG_SYS_I2C_MXC @@ -141,49 +159,68 @@ I2C_PADS(i2c2_pads, IMX_GPIO_NR(1, 6)); -static void cm_fx6_setup_i2c(void) +static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) +{ + int ret; + + ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); + if (ret) + printf("Warning: I2C%d setup failed: %d\n", busnum, ret); + + return ret; +} + +static int cm_fx6_setup_i2c(void) { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads)); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads)); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads)); + int ret = 0, err; + + /* i2c<x>_pads are wierd macro variables; we can't use an array */ + err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); + if (err) + ret = err; + + return ret; } #else -static void cm_fx6_setup_i2c(void) { } +static int cm_fx6_setup_i2c(void) { return 0; } #endif #ifdef CONFIG_USB_EHCI_MX6 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define MX6_USBNC_BASEADDR 0x2184800 +#define USBNC_USB_H1_PWR_POL (1 << 9) -static int cm_fx6_usb_hub_reset(void) +static int cm_fx6_setup_usb_host(void) { int err; err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); - if (err) { - printf("USB hub rst gpio request failed: %d\n", err); - return -1; - } + if (err) + return err; + SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); - gpio_direction_output(CM_FX6_USB_HUB_RST, 0); - udelay(10); - gpio_direction_output(CM_FX6_USB_HUB_RST, 1); - mdelay(1); return 0; } -static int cm_fx6_init_usb_otg(void) +static int cm_fx6_setup_usb_otg(void) { - int ret; + int err; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); - if (ret) { - printf("USB OTG pwr gpio request failed: %d\n", ret); - return ret; + err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); + if (err) { + printf("USB OTG pwr gpio request failed: %d\n", err); + return err; } SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); @@ -194,25 +231,27 @@ static int cm_fx6_init_usb_otg(void) return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); } -#define MX6_USBNC_BASEADDR 0x2184800 -#define USBNC_USB_H1_PWR_POL (1 << 9) int board_ehci_hcd_init(int port) { + int ret; u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); - switch (port) { - case 0: - return cm_fx6_init_usb_otg(); - case 1: - SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | - MUX_PAD_CTRL(NO_PAD_CTRL)); + /* Only 1 host controller in use. port 0 is OTG & needs no attention */ + if (port != 1) + return 0; - /* Set PWR polarity to match power switch's enable polarity */ - setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); - return cm_fx6_usb_hub_reset(); - default: - break; - } + /* Set PWR polarity to match power switch's enable polarity */ + setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); + if (ret) + return ret; + + udelay(10); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); + if (ret) + return ret; + + mdelay(1); return 0; } @@ -224,6 +263,9 @@ int board_ehci_power(int port, int on) return 0; } +#else +static int cm_fx6_setup_usb_otg(void) { return 0; } +static int cm_fx6_setup_usb_host(void) { return 0; } #endif #ifdef CONFIG_FEC_MXC @@ -318,12 +360,17 @@ static int handle_mac_address(void) int board_eth_init(bd_t *bis) { - int res = handle_mac_address(); - if (res) + int err; + + err = handle_mac_address(); + if (err) puts("No MAC address found\n"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ + err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); + if (err) + printf("Etnernet NRST gpio request failed: %d\n", err); gpio_direction_output(CM_FX6_ENET_NRST, 0); udelay(500); gpio_set_value(CM_FX6_ENET_NRST, 1); @@ -394,6 +441,16 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_MXC_SPI +int cm_fx6_setup_ecspi(void) +{ + cm_fx6_set_ecspi_iomux(); + return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); +} +#else +int cm_fx6_setup_ecspi(void) { return 0; } +#endif + #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd) { @@ -409,9 +466,37 @@ void ft_board_setup(void *blob, bd_t *bd) int board_init(void) { + int ret; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; cm_fx6_setup_gpmi_nand(); - cm_fx6_setup_i2c(); + + ret = cm_fx6_setup_ecspi(); + if (ret) + printf("Warning: ECSPI setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_otg(); + if (ret) + printf("Warning: USB OTG setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_host(); + if (ret) + printf("Warning: USB host setup failed: %d\n", ret); + + /* + * cm-fx6 may have iSSD not assembled and in this case it has + * bypasses for a (m)SATA socket on the baseboard. The socketed + * device is not controlled by those GPIOs. So just print a warning + * if the setup fails. + */ + ret = cm_fx6_setup_issd(); + if (ret) + printf("Warning: iSSD setup failed: %d\n", ret); + + /* Warn on failure but do not abort boot */ + ret = cm_fx6_setup_i2c(); + if (ret) + printf("Warning: I2C setup failed: %d\n", ret); return 0; } @@ -481,3 +566,11 @@ u32 get_board_rev(void) return cl_eeprom_get_board_rev(); } +static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { + .reg = (struct mxc_uart *)UART4_BASE, +}; + +U_BOOT_DEVICE(cm_fx6_serial) = { + .name = "serial_mxc", + .platdata = &cm_fx6_mxc_serial_plat, +}; diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index ff70e94..a022daf 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -14,7 +14,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> #include "dns325.h" @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, - DNS325_OE_LOW, DNS325_OE_HIGH); + mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, + DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index ccf4513..e30e944 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/ls1021aqds/ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig +F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..5fafc85 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -13,6 +13,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -213,6 +214,15 @@ int config_serdes_mux(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 4e5bc15..8def0e5 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig +F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..50d5640 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -16,6 +16,7 @@ #include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -280,6 +281,15 @@ int board_init(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index c3443bd..086a473 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -9,7 +9,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "iconnect.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(ICONNECT_OE_VAL_LOW, - ICONNECT_OE_VAL_HIGH, - ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + mvebu_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -87,7 +87,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index ed0575c..35546d2 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -8,7 +8,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/io.h> @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); + mvebu_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -97,7 +97,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 35402c8..1c7c108 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -20,7 +20,7 @@ #include <spi.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "../common/common.h" @@ -222,11 +222,11 @@ int board_early_init_f(void) u32 tmp; /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); + tmp = readl(MVEBU_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); #endif /* adjust SDRAM size for bank 0 */ - kw_sdram_size_adjust(0); + mvebu_sdram_size_adjust(0); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -234,7 +234,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; /* * The KM_FLASH_GPIO_PIN switches between using a diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig new file mode 100644 index 0000000..d34e2ab --- /dev/null +++ b/board/maxbcm/Kconfig @@ -0,0 +1,19 @@ +if TARGET_MAXBCM + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "maxbcm" + +config SYS_SOC + string + default "armada-xp" + +config SYS_CONFIG_NAME + string + default "maxbcm" + +endif diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS new file mode 100644 index 0000000..3c8af21 --- /dev/null +++ b/board/maxbcm/MAINTAINERS @@ -0,0 +1,6 @@ +MAXBCM BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/maxbcm/ +F: include/configs/maxbcm.h +F: configs/maxbcm_defconfig diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile new file mode 100644 index 0000000..37c17d6 --- /dev/null +++ b/board/maxbcm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := maxbcm.o diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg new file mode 100644 index 0000000..5a3bc67 --- /dev/null +++ b/board/maxbcm/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/maxbcm/binary.0 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c new file mode 100644 index 0000000..7fc83ee --- /dev/null +++ b/board/maxbcm/maxbcm.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Base addresses for the external device chip selects */ +#define DEV_CS0_BASE 0xe0000000 +#define DEV_CS1_BASE 0xe1000000 +#define DEV_CS2_BASE 0xe2000000 +#define DEV_CS3_BASE 0xe3000000 + +/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + +int board_early_init_f(void) +{ + /* + * Don't configure MPP (pin multiplexing) and GPIO here, + * its already done in bin_hdr + */ + + /* + * Setup some board specific mbus address windows + */ + mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); + mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); + mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); + mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: maxBCM\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E6185 switch */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* todo: fill this with the real setup / config code */ + + printf("88E6185 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d01abce..03f055d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -114,9 +114,8 @@ int board_init(void) clock_init(); clock_verify(); -#ifdef CONFIG_FDT_SPI +#ifdef CONFIG_TEGRA_SPI pin_mux_spi(); - spi_init(); #endif #ifdef CONFIG_PWM_TEGRA diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 976ba4c..f01fb1c 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -11,7 +11,7 @@ #include <miiphy.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include "ib62x0.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(IB62x0_OE_VAL_LOW, - IB62x0_OE_VAL_HIGH, - IB62x0_OE_LOW, IB62x0_OE_HIGH); + mvebu_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); @@ -62,7 +62,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 220bb90..447c940 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -16,15 +16,26 @@ #include <common.h> #include <config.h> +#include <dm.h> #include <fdt_support.h> #include <lcd.h> #include <mmc.h> +#include <asm/gpio.h> #include <asm/arch/mbox.h> #include <asm/arch/sdhci.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +static const struct bcm2835_gpio_platdata gpio_platdata = { + .base = BCM2835_GPIO_BASE, +}; + +U_BOOT_DEVICE(bcm2835_gpios) = { + .name = "gpio_bcm2835", + .platdata = &gpio_platdata, +}; + struct msg_get_arm_mem { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 5eedbf8..3aad532 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -9,6 +9,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmc.h> +#include <spi.h> #include <spi_flash.h> int checkboard(void) diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index 42b920f..9f64945 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -9,6 +9,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmc.h> +#include <spi.h> #include <spi_flash.h> int checkboard(void) diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 1464f48..ddcf275 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -9,6 +9,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmc.h> +#include <spi.h> #include <spi_flash.h> int checkboard(void) diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 83fd3bd..881d080 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -6,9 +6,9 @@ #include <common.h> #include <usb.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> #include <asm/arch/power.h> DECLARE_GLOBAL_DATA_PTR; @@ -19,6 +19,8 @@ int board_usb_init(int index, enum usb_init_type init) /* Configure gpios for usb 3503 hub: * disconnect, toggle reset and connect */ + gpio_request(EXYNOS5_GPIO_D17, "usb_connect"); + gpio_request(EXYNOS5_GPIO_X35, "usb_reset"); gpio_direction_output(EXYNOS5_GPIO_D17, 0); gpio_direction_output(EXYNOS5_GPIO_X35, 0); diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 5c3c5bb..e1fc123 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -13,10 +13,10 @@ #include <tmu.h> #include <netdev.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/board.h> #include <asm/arch/cpu.h> #include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> @@ -87,9 +87,6 @@ int board_init(void) boot_temp_check(); #endif -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif return exynos_init(); } diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 8766f0c..4538ac7 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -14,7 +14,6 @@ #include <malloc.h> #include <linux/sizes.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <asm/gpio.h> #include <linux/input.h> #include <power/pmic.h> @@ -412,6 +411,8 @@ void check_boot_mode(void) void keys_init(void) { /* Set direction to input */ + gpio_request(KEY_VOL_UP_GPIO, "volume-up"); + gpio_request(KEY_VOL_DOWN_GPIO, "volume-down"); gpio_direction_input(KEY_VOL_UP_GPIO); gpio_direction_input(KEY_VOL_DOWN_GPIO); } diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index eb0f9bf..58cf96e 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -7,7 +7,7 @@ */ #include <common.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/mmc.h> #include <power/pmic.h> #include <usb/s3c_udc.h> @@ -33,6 +33,16 @@ int board_init(void) return 0; } +#ifdef CONFIG_SYS_I2C_INIT_BOARD +void i2c_init_board(void) +{ + gpio_request(S5PC110_GPIO_J43, "i2c_clk"); + gpio_request(S5PC110_GPIO_J40, "i2c_data"); + gpio_direction_output(S5PC110_GPIO_J43, 1); + gpio_direction_output(S5PC110_GPIO_J40, 1); +} +#endif + int power_init_board(void) { int ret; @@ -80,6 +90,7 @@ int board_mmc_init(bd_t *bis) int i, ret, ret_sd = 0; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ + gpio_request(S5PC110_GPIO_J27, "massmemory_en"); gpio_direction_output(S5PC110_GPIO_J27, 1); /* @@ -108,6 +119,7 @@ int board_mmc_init(bd_t *bis) * SD card (T_FLASH) detect and init * T_FLASH_DETECT: EINT28: GPH3[4] input mode */ + gpio_request(S5PC110_GPIO_H34, "t_flash_detect"); gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT); gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP); diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index a539267..99a2fac 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index d6ce133..53ff706 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static void board_enable_audio_codec(void) { /* Enable MAX98095 Codec */ + gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); gpio_direction_output(EXYNOS5_GPIO_X17, 1); gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } @@ -199,16 +200,19 @@ static int board_dp_bridge_setup(void) /* Setup the GPIOs */ /* PD is ACTIVE_LOW, and initially de-asserted */ + gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd"); gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE); gpio_direction_output(EXYNOS5_GPIO_Y25, 1); /* Reset is ACTIVE_LOW */ + gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset"); gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE); gpio_direction_output(EXYNOS5_GPIO_X15, 0); udelay(10); gpio_set_value(EXYNOS5_GPIO_X15, 1); + gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd"); gpio_direction_input(EXYNOS5_GPIO_X07); /* @@ -236,10 +240,12 @@ static int board_dp_bridge_setup(void) void exynos_cfg_lcd_gpio(void) { /* For Backlight */ + gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ + gpio_request(EXYNOS5_GPIO_X15, "lcd_power"); gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); gpio_set_value(EXYNOS5_GPIO_X15, 1); @@ -276,6 +282,7 @@ void exynos_backlight_on(unsigned int on) mdelay(10); /* board_dp_backlight_en */ + gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); gpio_direction_output(EXYNOS5_GPIO_X30, 1); #endif } diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 270ee83..a691222 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -11,9 +11,9 @@ #include <lcd.h> #include <spi.h> #include <errno.h> +#include <asm/gpio.h> #include <asm/arch/board.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/system.h> #include <asm/arch/dp_info.h> @@ -74,9 +74,12 @@ void exynos_lcd_power_on(void) mdelay(5); /* TODO(ajaykumar.rs@samsung.com): Use device tree */ + gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ mdelay(10); + gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); @@ -88,6 +91,7 @@ void exynos_lcd_power_on(void) void exynos_backlight_on(unsigned int onoff) { /* For PWM */ + gpio_request(EXYNOS5420_GPIO_B20, "backlight_on"); gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1)); gpio_set_value(EXYNOS5420_GPIO_B20, 1); diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index e009564..66b6a98 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -7,9 +7,9 @@ */ #include <common.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/sromc.h> -#include <asm/arch/gpio.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 8eca358..cb7f9b0 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -5,10 +5,10 @@ */ #include <common.h> +#include <asm/gpio.h> #include <asm/io.h> #include <netdev.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 3dd340b..e163e45 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -10,8 +10,8 @@ #include <common.h> #include <lcd.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch/mipi_dsim.h> @@ -63,6 +63,8 @@ void i2c_init_board(void) } /* I2C_8 -> FG */ + gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk"); + gpio_request(EXYNOS4_GPIO_Y41, "i2c_data"); gpio_direction_output(EXYNOS4_GPIO_Y40, 1); gpio_direction_output(EXYNOS4_GPIO_Y41, 1); } @@ -346,12 +348,17 @@ int exynos_power_init(void) static unsigned int get_hw_revision(void) { int hwrev = 0; + char str[10]; int i; /* hw_rev[3:0] == GPE1[3:0] */ - for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) { - gpio_cfg_pin(i, S5P_GPIO_INPUT); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); + for (i = 0; i < 4; i++) { + int pin = i + EXYNOS4_GPIO_E10; + + sprintf(str, "hw_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + gpio_set_pull(pin, S5P_GPIO_PULL_NONE); } udelay(1); @@ -517,6 +524,7 @@ static void board_power_init(void) static void exynos_uart_init(void) { /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ + gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); gpio_direction_output(EXYNOS4_GPIO_Y47, 1); } @@ -534,6 +542,7 @@ int exynos_early_init_f(void) void exynos_reset_lcd(void) { + gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); gpio_direction_output(EXYNOS4_GPIO_Y45, 1); udelay(10000); gpio_direction_output(EXYNOS4_GPIO_Y45, 0); diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index fa26e61..a737749 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -8,6 +8,7 @@ #include <common.h> #include <lcd.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/mipi_dsim.h> @@ -32,6 +33,7 @@ static inline u32 get_model_rev(void); static void check_hw_revision(void) { int modelrev = 0; + char str[12]; int i; /* @@ -40,13 +42,22 @@ static void check_hw_revision(void) * TRM say that it may cause unexcepted state and leakage current. * and pull-none is only for output function. */ - for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++) - gpio_cfg_pin(i, S5P_GPIO_INPUT); + for (i = 0; i < 2; i++) { + int pin = i + EXYNOS4X12_GPIO_M10; + + sprintf(str, "model_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + } /* GPM1[5:2]: HW_REV[3:0] */ - for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) { - gpio_cfg_pin(i, S5P_GPIO_INPUT); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); + for (i = 0; i < 4; i++) { + int pin = i + EXYNOS4X12_GPIO_M12; + + sprintf(str, "hw_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + gpio_set_pull(pin, S5P_GPIO_PULL_NONE); } /* GPM1[1:0]: MODEL_REV[1:0] */ @@ -102,10 +113,14 @@ static void board_init_i2c(void) } /* I2C_8 */ + gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk"); + gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data"); gpio_direction_output(EXYNOS4X12_GPIO_F14, 1); gpio_direction_output(EXYNOS4X12_GPIO_F15, 1); /* I2C_9 */ + gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk"); + gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data"); gpio_direction_output(EXYNOS4X12_GPIO_M21, 1); gpio_direction_output(EXYNOS4X12_GPIO_M20, 1); } @@ -387,6 +402,7 @@ void exynos_lcd_power_on(void) struct pmic *p = pmic_get("MAX77686_PMIC"); /* LCD_2.2V_EN: GPC0[1] */ + gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en"); gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); @@ -399,6 +415,7 @@ void exynos_lcd_power_on(void) void exynos_reset_lcd(void) { /* reset lcd */ + gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset"); gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); udelay(10); gpio_set_value(EXYNOS4X12_GPIO_F21, 1); diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 47e7f53..22b0849 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/adc.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/watchdog.h> #include <ld9040.h> @@ -202,53 +201,6 @@ int exynos_early_init_f(void) return 0; } -#ifdef CONFIG_SOFT_SPI -static void soft_spi_init(void) -{ - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, - CONFIG_SOFT_SPI_MODE & SPI_CPOL); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); - gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); - SPI_SCL(1); - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void universal_spi_scl(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit); -} - -void universal_spi_sda(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit); -} - -int universal_spi_read(void) -{ - return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO); -} -#endif - static void init_pmic_lcd(void) { unsigned char val; @@ -331,9 +283,8 @@ void exynos_cfg_lcd_gpio(void) } /* gpio pad configuration for LCD reset. */ + gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); - - spi_init(); } int mipi_power(void) @@ -387,6 +338,7 @@ int exynos_init(void) * you should set it HIGH since it removes the inverter */ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ + gpio_request(EXYNOS4_GPIO_E36, "ldo_en"); gpio_direction_output(EXYNOS4_GPIO_E36, 0); break; default: @@ -395,13 +347,11 @@ int exynos_init(void) * But set it as HIGH to ensure */ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ + gpio_request(EXYNOS4_GPIO_E13, "massmemory_en"); gpio_direction_output(EXYNOS4_GPIO_E13, 1); break; } -#ifdef CONFIG_SOFT_SPI - soft_spi_init(); -#endif check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); diff --git a/board/ti/ks2_evm/README_K2HK b/board/ti/ks2_evm/README index 7426b8d..a551e28 100644 --- a/board/ti/ks2_evm/README_K2HK +++ b/board/ti/ks2_evm/README @@ -1,46 +1,56 @@ -U-Boot port for Texas Instruments XTCIEVMK2X -============================================ +U-Boot port for Texas Instruments Keystone II EVM boards +======================================================== Author: Murali Karicheri <m-karicheri2@ti.com> -This README has information on the u-boot port for XTCIEVMK2X EVM board. +This README has information on the u-boot port for K2HK, K2E boards. Documentation for this board can be found at - http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx +http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html -The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. +The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. More details on these SoCs are available at company websites K2K: http://www.ti.com/product/tci6638k2k K2H: http://www.ti.com/product/tci6638k2h +The K2E SoC details are available at + K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + Board configuration: ==================== -Some of the peripherals that are configured by u-boot are:- +Some of the peripherals that are configured by u-boot ++------+-------+-------+-----------+-----------+-------+-------+----+ +| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI | ++------+-------+-------+-----------+-----------+-------+-------+----+ +|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | +|K2E |4 |512MB |2MB |8(2) |2 |3 |3 | ++------+-------+-------+-----------+-----------+-------+-------+----+ -1. 2GB DDR3 (can support 8GB SO DIMM as well) -2. 512M NAND (over ti emif16 bus) -3. 6MB MSM SRAM (part of the SoC) -4. two 1GBit Ethernet ports (SoC supports upto 4) -5. two UART ports -6. three i2c interfaces -7. three spi interfaces (only 1 interface supported in driver) +There are only 2 eth port installed on the boards. -There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. +There are separate PLLs to drive clocks to Tetris ARM and Peripherals. To bring up SMP Linux on this board, there is a boot monitor code that will be installed in MSMC SRAM. There is command available to install this image from u-boot. The port related files can be found at following folders keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ - K2HK evm board files: board/ti/k2hk_evm/ + EVMs board files: board/ti/k2s_evm/ + +Board configuration files: +include/configs/k2hk_evm.h +include/configs/k2e_evm.h -board configuration file: include/configs/k2hk_evm.h +As u-boot is migrating to Kconfig there is also board defconfig files +configs/k2e_evm_defconfig +configs/k2hk_evm_defconfig Supported boot modes: - SPI NOR boot - AEMIF NAND boot -Supported image formats:- +Supported image formats: - u-boot.bin: for loading and running u-boot.bin through Texas instruments code composure studio (CCS) - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot @@ -48,29 +58,32 @@ Supported image formats:- Build instructions: =================== +Examples for k2hk, for k2e just replace k2hk prefix accordingly. +Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin - >make k2hk_evm_config + >make k2hk_evm_defconfig >make u-boot-spi.gph To build u-boot-spi.gph - >make k2hk_evm_config + >make k2hk_evm_defconfig >make u-boot-spi.gph To build u-boot-nand.gph - >make k2hk_evm_config + >make k2hk_evm_defconfig >make u-boot-nand.gph -Load and Run U-Boot on K2HK EVM using CCS +Load and Run U-Boot on keystone EVMs using CCS ========================================= Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin on EVM. See instructions at below link for installing CCS on a Windows PC. http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading annd running u-boot binary +Use u-boot.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at -http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" and Power ON the EVM. Follow instructions to connect serial port of EVM to PC and start TeraTerm or Hyper Terminal. @@ -82,7 +95,7 @@ The instructions provided in the above link uses a script for loading the u-boot binary on the target EVM. Instead do the following:- 1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D - isconnected: Unknown)" at the debug window (This is created once Target + is connected: Unknown)" at the debug window (This is created once Target configuration is launched) and select "Connect Target". 2. Once target connect is successful, choose Tools->Load Memory option from the top level menu. At the Load Memory window, choose the file u-boot.bin @@ -109,28 +122,28 @@ Hit any key to stop autoboot: 0 SPI NOR Flash programming instructions ====================================== U-Boot image can be flashed to first 512KB of the NOR flash using following -instructions:- +instructions: 1. Start CCS and run U-boot as described above. 2. Suspend Target. Select Run -> Suspend from top level menu CortexA15_1 (Free Running)" 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +4. Free Run the target as described earlier (step 4) to get u-boot prompt 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x87000000 setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000> run burn_uboot_spi Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "SPI Little Endian Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. 6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. AEMIF NAND Flash programming instructions ====================================== U-Boot image can be flashed to first 1024KB of the NAND flash using following -instructions:- +instructions: 1. Start CCS and run U-boot as described above. 2. Suspend Target. Select Run -> Suspend from top level menu @@ -138,11 +151,11 @@ instructions:- 3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +4. Free Run the target as described earlier (step 4) to get u-boot prompt 5. At the U-Boot console type following to setup u-boot environment variables. setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000> run burn_uboot_nand Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "ARM NAND Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. 6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. |