diff options
Diffstat (limited to 'board')
111 files changed, 2575 insertions, 2569 deletions
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 54c0ffe..bb388ed 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> +#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -90,3 +91,38 @@ int board_init(void) return 0; } + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..88e62b2 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_BASE_H +#define __EDMINIV2_BASE_H + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __EDMINIV2_BASE_H */ diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 4652672..3c37557 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -167,13 +167,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk deleted file mode 100644 index dab2740..0000000 --- a/board/altera/ep1c20/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index 761f605..a11add5 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -35,6 +35,16 @@ #define CONFIG_SMC91111 #define CONFIG_SMC_USE_32_BIT +/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ +#define EPCS_CONTROLLER_REG_BASE 0x82100200 +#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } +#define CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ #define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c index 6c9c6c2..d449684 100644 --- a/board/altera/nios2-generic/gpio.c +++ b/board/altera/nios2-generic/gpio.c @@ -15,6 +15,11 @@ static u32 pio_data_reg; static u32 pio_dir_reg; +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + int gpio_direction_input(unsigned gpio) { u32 mask = 1 << gpio; diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index 258d1ea..2ab8bc2 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -339,13 +339,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index ed47360..64c6d17 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -179,13 +179,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 5cd7aa7..91efc07 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -284,13 +284,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 8fa0449..f92b20f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -291,13 +291,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index c11a5c3..4f7d935 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -47,7 +47,7 @@ int board_early_init_f (void) int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 85b350f..ff1ac4c 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -14,6 +14,7 @@ #include <spi.h> #include <asm/blackfin.h> #include <asm/net.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/otp.h> #include <asm/sdh.h> @@ -61,6 +62,7 @@ static void board_init_enetaddr(uchar *mac_addr) #define KSZ_WRITE 0x02 #define KSZ_READ 0x03 +#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */ #define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */ #define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */ #define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */ @@ -78,15 +80,17 @@ static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data) return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din); } -static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg) { - int ret = 0; + int ret; unsigned char din[3]; + ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); + return ret ? ret : din[2]; +} - ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); - ret |= ksz8893m_reg_set(slave, reg, din[2] & mask); - - return ret; +static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +{ + return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask); } static int ksz8893m_reset(struct spi_slave *slave) @@ -107,16 +111,16 @@ static int ksz8893m_reset(struct spi_slave *slave) int board_eth_init(bd_t *bis) { - static bool switch_is_alive = false; + static bool switch_is_alive = false, phy_is_ksz = true; int ret; if (!switch_is_alive) { struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3); if (slave) { if (!spi_claim_bus(slave)) { - ret = ksz8893m_reset(slave); - if (!ret) - switch_is_alive = true; + phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88); + ret = phy_is_ksz ? ksz8893m_reset(slave) : 0; + switch_is_alive = (ret == 0); spi_release_bus(slave); } spi_free_slave(slave); @@ -143,18 +147,11 @@ int misc_init_r(void) int board_early_init_f(void) { -#if !defined(CONFIG_SYS_NO_FLASH) - /* setup BF518-EZBRD GPIO pin PG11 to AMS2. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11); - -# if !defined(CONFIG_BFIN_SPI) - /* setup BF518-EZBRD GPIO pin PG15 to AMS3. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15); -# endif -#endif - return 0; + /* connect async banks by default */ + const unsigned short pins[] = { + P_AMS2, P_AMS3, 0, + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_BFIN_SDH diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index a9ff760..f2bd2c2 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -30,7 +30,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o -COBJS-$(CONFIG_STATUS_LED) += status-led.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/bf526-ezbrd/status-led.c b/board/bf526-ezbrd/status-led.c deleted file mode 100644 index 6327022..0000000 --- a/board/bf526-ezbrd/status-led.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * U-boot - status leds - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <status_led.h> - -static void set_led_f(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break; - } -} -static void set_led_g(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led_f(PF8, state); - if (mask & 0x2) set_led_g(PG11, state); - if (mask & 0x4) set_led_g(PG12, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8)); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12)); - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8)); - bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12)); - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8)); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile new file mode 100644 index 0000000..f2bd2c2 --- /dev/null +++ b/board/bf527-ad7160-eval/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c new file mode 100644 index 0000000..b06d5ab --- /dev/null +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/pll.h> + +int checkboard(void) +{ + printf("Board: ADI BF527 AD7160-EVAL board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + *pVR_CTL |= CLKBUFOE; + return 0; +} diff --git a/board/altera/ep1s40/config.mk b/board/bf527-ad7160-eval/config.mk index dab2740..f85bef5 100644 --- a/board/altera/ep1s40/config.mk +++ b/board/bf527-ad7160-eval/config.mk @@ -1,6 +1,8 @@ # -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -21,11 +23,11 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index a911880..211cf24 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -12,6 +12,7 @@ #include <net.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> @@ -75,9 +76,7 @@ void board_musb_init(void) /* * BF527 EZ-KITs require PG13 to be high for HOST mode */ - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13); - bfin_write_PORTGIO_SET(PG13); - SSYNC(); + gpio_request(GPIO_PG13, "musb-vbus"); + gpio_direction_output(GPIO_PG13, 1); } #endif diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 8f6ea23..891070b 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -11,6 +11,7 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <spi.h> #include <linux/types.h> @@ -171,13 +172,11 @@ void DisablePPI(void) void Init_Ports(void) { - *pPORTF_MUX &= ~PORT_x_MUX_0_MASK; - *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1; - *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7; - - *pPORTG_MUX &= ~PORT_x_MUX_1_MASK; - *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1; - *pPORTG_FER |= PG5; + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); } void Init_PPI(void) diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 4abad08..935aad2 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -27,8 +27,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> -#include "bf533-stamp.h" +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,15 +45,10 @@ int checkboard(void) */ void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); - SSYNC(); - bfin_write_FIO_FLAG_C(PF1); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_request(GPIO_PF1, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); + gpio_direction_output(GPIO_PF1, 0); SSYNC(); } @@ -75,24 +69,23 @@ int misc_init_r(void) #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 +static int gpio_setup; + static void stamp_led_set(int LED1, int LED2, int LED3) { - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); - - if (LED1 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF2; - else - *pFIO_FLAG_C = PF2; - if (LED2 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF3; - else - *pFIO_FLAG_C = PF3; - if (LED3 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF4; - else - *pFIO_FLAG_C = PF4; - SSYNC(); + if (!gpio_setup) { + gpio_request(GPIO_PF2, "boot_progress"); + gpio_request(GPIO_PF3, "boot_progress"); + gpio_request(GPIO_PF4, "boot_progress"); + gpio_direction_output(GPIO_PF2, LED1); + gpio_direction_output(GPIO_PF3, LED2); + gpio_direction_output(GPIO_PF4, LED3); + gpio_setup = 1; + } else { + gpio_set_value(GPIO_PF2, LED1); + gpio_set_value(GPIO_PF3, LED2); + gpio_set_value(GPIO_PF4, LED3); + } } void show_boot_progress(int status) @@ -134,43 +127,6 @@ void show_boot_progress(int status) } #endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> - -static void set_led(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break; - case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break; - case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led(PF2, state); - if (mask & 0x2) set_led(PF3, state); - if (mask & 0x4) set_led(PF4, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} - -#endif - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h deleted file mode 100644 index ebd39c7..0000000 --- a/board/bf533-stamp/bf533-stamp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * U-boot - stamp.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __STAMP_H__ -#define __STAMP_H__ - -extern void init_Flags(void); - -extern volatile unsigned long *ambctl0; -extern volatile unsigned long *ambctl1; -extern volatile unsigned long *amgctl; - -/* Definitions used in Compact Flash Boot support */ -#define FIO_EDGE_CF_BITS 0x0000 -#define FIO_POLAR_CF_BITS 0x0000 -#define FIO_EDGE_BITS 0x1E0 -#define FIO_POLAR_BITS 0x160 - -/* Compact flash status bits in status register */ -#define CF_STAT_BITS 0x00000060 - -/* CF Flags used to switch between expansion and external - * memory banks - */ -#define CF_PF0 0x0001 -#define CF_PF1 0x0002 -#define CF_PF1_PF0 0x0003 - -#endif diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c index 23e786b..3e4080e 100644 --- a/board/bf533-stamp/ide-cf.c +++ b/board/bf533-stamp/ide-cf.c @@ -11,7 +11,6 @@ #include <common.h> #include <config.h> #include <asm/blackfin.h> -#include "bf533-stamp.h" void cf_outb(unsigned char val, volatile unsigned char *addr) { @@ -66,6 +65,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) swap_to(FLASH); } +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + void cf_ide_init(void) { int i, cf_stat; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index f728e2c..4f8985b 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,9 +29,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o cmd_bf537led.o +COBJS-y := $(BOARD).o COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o -COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o COBJS-$(CONFIG_POST) += post.o post-memory.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 3911be6..ec888d4 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -46,11 +46,8 @@ int checkboard(void) void board_reset(void) { /* workaround for weak pull ups on ssel */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10); - bfin_write_PORTFIO_SET(PF10); - udelay(1); - } + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) + bfin_reset_boot_spi_cs(GPIO_PF10); } #ifdef CONFIG_BFIN_MAC diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c deleted file mode 100644 index 7d8f3ea..0000000 --- a/board/bf537-stamp/cmd_bf537led.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * U-boot - cmd_bf537led.c - * - * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <config.h> -#include <command.h> -#include <asm/blackfin.h> -#include <asm/string.h> -#ifdef CONFIG_BF537_STAMP_LEDCMD - -/* Define the command usage in a reusable way */ -#define USAGE_LONG \ - "led <number> <action>\n" \ - " <number> - Index (0-5) of LED to change, or \"all\"\n" \ - " <action> - Must be one of:\n" \ - " on off toggle" - -/* Number of LEDs supported by the board */ -#define NUMBER_LEDS 6 -/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */ -#define LED_ALL_MASK 0x003F - -void show_cmd_usage(void); -void set_led_state(int index, int state); -void configure_GPIO_to_output(int index); - -/* Map of LEDs according to their GPIO ports. This can be rearranged or - * otherwise changed to account for different GPIO configurations. - */ -int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 }; - -#define ACTION_TOGGLE -1 -#define ACTION_OFF 0 -#define ACTION_ON 1 - -#define LED_STATE_OFF 0 -#define LED_STATE_ON 1 - -/* This is a trivial atoi implementation since we don't have one available */ -int atoi(char *string) -{ - int length; - int retval = 0; - int i; - int sign = 1; - - length = strlen(string); - for (i = 0; i < length; i++) { - if (0 == i && string[0] == '-') { - sign = -1; - continue; - } - if (string[i] > '9' || string[i] < '0') { - break; - } - retval *= 10; - retval += string[i] - '0'; - } - retval *= sign; - return retval; -} - -int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int led_mask = 0; - int led_current_state = 0; - int action = ACTION_OFF; - int temp; - - if (3 != argc) { - /* Not enough arguments, so just show usage information */ - show_cmd_usage(); - return 1; - } - - if (strcmp(argv[1], "all") == 0) { - led_mask = LED_ALL_MASK; - } else { - temp = atoi(argv[1]); - if (temp < 0 || temp >= NUMBER_LEDS) { - printf("Invalid LED number [%s]\n", argv[1]); - show_cmd_usage(); - return 2; - } - led_mask |= (1 << temp); - } - - if (strcmp(argv[2], "off") == 0) { - action = ACTION_OFF; - } else if (strcmp(argv[2], "on") == 0) { - action = ACTION_ON; - } else if (strcmp(argv[2], "toggle") == 0) { - action = ACTION_TOGGLE; - } else { - printf("Invalid action [%s]\n", argv[2]); - show_cmd_usage(); - return 3; - } - - for (temp = 0; temp < NUMBER_LEDS; temp++) { - if ((led_mask & (1 << temp)) > 0) { - /* - * It is possible that the user has wired one of PF6-PF11 to - * something other than an LED, so this will only change a pin - * to output if the user has indicated a state change. This may - * happen a lot, but this way is safer than just setting all pins - * to output. - */ - configure_GPIO_to_output(temp); - - led_current_state = - ((*pPORTFIO & led_ports[temp]) > - 0) ? LED_STATE_ON : LED_STATE_OFF; - /* - printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp], - led_current_state); - printf("*pPORTFIO is %x\n", *pPORTFIO); - */ - if (ACTION_ON == action - || (ACTION_TOGGLE == action - && 0 == led_current_state)) { - printf("Turning LED %d on\n", temp); - set_led_state(temp, LED_STATE_ON); - } else { - printf("Turning LED %d off\n", temp); - set_led_state(temp, LED_STATE_OFF); - } - } - } - - return 0; -} - -/* - * The GPIO pins that go to the LEDs on the BF537 stamp must be configured - * as output. This function simply configures them that way. This could - * be done to all of the GPIO lines at once, but if a user is using a - * custom board, this will try to be nice and only change the GPIO lines - * that the user specifically names. - */ -void configure_GPIO_to_output(int index) -{ - int port; - - port = led_ports[index]; - - /* Clear the Port F Function Enable Register */ - *pPORTF_FER &= ~port; - /* Set the Port F I/O direction register */ - *pPORTFIO_DIR |= port; - /* Clear the Port F I/O Input Enable Register */ - *pPORTFIO_INEN &= ~port; -} - -/* Enforce the given state on the GPIO line for the indicated LED */ -void set_led_state(int index, int state) -{ - int port; - - port = led_ports[index]; - - if (LED_STATE_OFF == state) { - /* Clear the bit to turn off the LED */ - *pPORTFIO &= ~port; - } else { - /* Set the bit to turn on the LED */ - *pPORTFIO |= port; - } -} - -/* Display usage information */ -void show_cmd_usage() -{ - printf("Usage:\n%s\n", USAGE_LONG); -} - -/* Register information for u-boot to find this command */ -U_BOOT_CMD(led, 3, 1, do_bf537led, - "Control BF537 stamp LEDs", USAGE_LONG); - -#endif diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c deleted file mode 100644 index 7b753ad..0000000 --- a/board/bf537-stamp/spi_flash.c +++ /dev/null @@ -1,996 +0,0 @@ -/* - * SPI flash driver - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* Configuration options: - * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK) - * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read - * WARNING: make sure your SCLK + SPI_BAUD is slow enough - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/mach-common/bits/spi.h> -#include <asm/mach-common/bits/dma.h> - -/* Forcibly phase out these */ -#ifdef CONFIG_SPI_FLASH_NUM_SECTORS -# error do not set CONFIG_SPI_FLASH_NUM_SECTORS -#endif -#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE -# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE -#endif - -#if defined(CONFIG_SPI) - -struct flash_info { - char *name; - uint16_t id; - uint16_t ext_id; - unsigned sector_size; - unsigned num_sectors; -}; - -/* SPI Speeds: 50 MHz / 33 MHz */ -static struct flash_info flash_spansion_serial_flash[] = { - { "S25FL016", 0x0215, 0, 64 * 1024, 32 }, - { "S25FL032", 0x0216, 0, 64 * 1024, 64 }, - { "S25FL064", 0x0217, 0, 64 * 1024, 128 }, - { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */ - { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */ - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 50 MHz / 20 MHz */ -static struct flash_info flash_st_serial_flash[] = { - { "m25p05", 0x2010, 0, 32 * 1024, 2 }, - { "m25p10", 0x2011, 0, 32 * 1024, 4 }, - { "m25p20", 0x2012, 0, 64 * 1024, 4 }, - { "m25p40", 0x2013, 0, 64 * 1024, 8 }, - { "m25p80", 0x20FF, 0, 64 * 1024, 16 }, - { "m25p16", 0x2015, 0, 64 * 1024, 32 }, - { "m25p32", 0x2016, 0, 64 * 1024, 64 }, - { "m25p64", 0x2017, 0, 64 * 1024, 128 }, - { "m25p128", 0x2018, 0, 256 * 1024, 64 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 20 MHz / 40 MHz */ -static struct flash_info flash_sst_serial_flash[] = { - { "SST25WF512", 0x2501, 0, 4 * 1024, 128 }, - { "SST25WF010", 0x2502, 0, 4 * 1024, 256 }, - { "SST25WF020", 0x2503, 0, 4 * 1024, 512 }, - { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 66 MHz / 33 MHz */ -static struct flash_info flash_atmel_dataflash[] = { - { "AT45DB011x", 0x0c, 0, 264, 512 }, - { "AT45DB021x", 0x14, 0, 264, 1025 }, - { "AT45DB041x", 0x1c, 0, 264, 2048 }, - { "AT45DB081x", 0x24, 0, 264, 4096 }, - { "AT45DB161x", 0x2c, 0, 528, 4096 }, - { "AT45DB321x", 0x34, 0, 528, 8192 }, - { "AT45DB642x", 0x3c, 0, 1056, 8192 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */ -static struct flash_info flash_winbond_serial_flash[] = { - { "W25X10", 0x3011, 0, 16 * 256, 32 }, - { "W25X20", 0x3012, 0, 16 * 256, 64 }, - { "W25X40", 0x3013, 0, 16 * 256, 128 }, - { "W25X80", 0x3014, 0, 16 * 256, 256 }, - { "W25P80", 0x2014, 0, 256 * 256, 16 }, - { "W25P16", 0x2015, 0, 256 * 256, 32 }, - { NULL, 0, 0, 0, 0 } -}; - -struct flash_ops { - uint8_t read, write, erase, status; -}; - -#ifdef CONFIG_SPI_FLASH_SLOW_READ -# define OP_READ 0x03 -#else -# define OP_READ 0x0B -#endif -static struct flash_ops flash_st_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0xD8, - .status = 0x05, -}; - -static struct flash_ops flash_sst_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -static struct flash_ops flash_atmel_ops = { - .read = OP_READ, - .write = 0x82, - .erase = 0x81, - .status = 0xD7, -}; - -static struct flash_ops flash_winbond_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -struct manufacturer_info { - const char *name; - uint8_t id; - struct flash_info *flashes; - struct flash_ops *ops; -}; - -static struct { - struct manufacturer_info *manufacturer; - struct flash_info *flash; - struct flash_ops *ops; - uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2; - unsigned int write_length; - unsigned long sector_size, num_sectors; -} flash; - -enum { - JED_MANU_SPANSION = 0x01, - JED_MANU_ST = 0x20, - JED_MANU_SST = 0xBF, - JED_MANU_ATMEL = 0x1F, - JED_MANU_WINBOND = 0xEF, -}; - -static struct manufacturer_info flash_manufacturers[] = { - { - .name = "Spansion", - .id = JED_MANU_SPANSION, - .flashes = flash_spansion_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "ST", - .id = JED_MANU_ST, - .flashes = flash_st_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "SST", - .id = JED_MANU_SST, - .flashes = flash_sst_serial_flash, - .ops = &flash_sst_ops, - }, - { - .name = "Atmel", - .id = JED_MANU_ATMEL, - .flashes = flash_atmel_dataflash, - .ops = &flash_atmel_ops, - }, - { - .name = "Winbond", - .id = JED_MANU_WINBOND, - .flashes = flash_winbond_serial_flash, - .ops = &flash_winbond_ops, - }, -}; - -#define TIMEOUT 5000 /* timeout of 5 seconds */ - -/* If part has multiple SPI flashes, assume SPI0 as that is - * the one we can boot off of ... - */ -#ifndef pSPI_CTL -# define pSPI_CTL pSPI0_CTL -# define pSPI_BAUD pSPI0_BAUD -# define pSPI_FLG pSPI0_FLG -# define pSPI_RDBR pSPI0_RDBR -# define pSPI_STAT pSPI0_STAT -# define pSPI_TDBR pSPI0_TDBR -#endif - -/* Default to the SPI SSEL that we boot off of: - * BF54x, BF537, (everything new?): SSEL1 - * BF51x, BF533, BF561: SSEL2 - */ -#ifndef CONFIG_SPI_FLASH_SSEL -# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL -#endif -#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL) - -static void SPI_INIT(void) -{ - /* [#3541] This delay appears to be necessary, but not sure - * exactly why as the history behind it is non-existant. - */ - *pSPI_CTL = 0; - udelay(CONFIG_CCLK_HZ / 25000000); - - /* enable SPI pins: SSEL, MOSI, MISO, SCK */ -#ifdef __ADSPBF54x__ - *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4); -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13); -#elif defined(__ADSPBF52x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4); -#elif defined(__ADSPBF51x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15); -#endif - - /* initate communication upon write of TDBR */ - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - *pSPI_BAUD = CONFIG_SPI_BAUD; -} - -static void SPI_DEINIT(void) -{ - *pSPI_CTL = 0; - *pSPI_BAUD = 0; - SSYNC(); -} - -static void SPI_ON(void) -{ - /* toggle SSEL to reset the device so it'll take a new command */ - *pSPI_FLG = 0xFF00 | SSEL_MASK; - SSYNC(); - - *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK; - SSYNC(); -} - -static void SPI_OFF(void) -{ - /* put SPI settings back to reset state */ - *pSPI_FLG = 0xFF00; - SSYNC(); -} - -static uint8_t spi_write_read_byte(uint8_t transmit) -{ - *pSPI_TDBR = transmit; - SSYNC(); - - while ((*pSPI_STAT & TXS)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & SPIF)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & RXS)) - if (ctrlc()) - break; - - /* Read dummy to empty the receive register */ - return *pSPI_RDBR; -} - -static uint8_t read_status_register(void) -{ - uint8_t status_register; - - /* send instruction to read status register */ - SPI_ON(); - spi_write_read_byte(flash.ops->status); - /* send dummy to receive the status register */ - status_register = spi_write_read_byte(0); - SPI_OFF(); - - return status_register; -} - -static int wait_for_ready_status(void) -{ - ulong start = get_timer(0); - - while (get_timer(0) - start < TIMEOUT) { - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - if (!(read_status_register() & 0x01)) - return 0; - break; - - case JED_MANU_ATMEL: - if (read_status_register() & 0x80) - return 0; - break; - } - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static int enable_writing(void) -{ - ulong start; - - if (flash.manufacturer_id == JED_MANU_ATMEL) - return 0; - - /* A write enable instruction must previously have been executed */ - SPI_ON(); - spi_write_read_byte(0x06); - SPI_OFF(); - - /* The status register will be polled to check the write enable latch "WREN" */ - start = get_timer(0); - while (get_timer(0) - start < TIMEOUT) { - if (read_status_register() & 0x02) - return 0; - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static void write_status_register(uint8_t val) -{ - if (flash.manufacturer_id != JED_MANU_SST) - hang(); - - if (enable_writing()) - return; - - /* send instruction to write status register */ - SPI_ON(); - spi_write_read_byte(0x01); - /* and clear it! */ - spi_write_read_byte(val); - SPI_OFF(); -} - -/* Request and read the manufacturer and device id of parts which - * are compatible with the JEDEC standard (JEP106) and use that to - * setup other operating conditions. - */ -static int spi_detect_part(void) -{ - uint16_t dev_id, dev_extid; - size_t i; - - static char called_init; - if (called_init) - return 0; - -#ifdef CONFIG_SPI_FLASH_M25P80 - flash.manufacturer_id = JED_MANU_ST; - flash.device_id1 = 0x20; - flash.device_id2 = 0xFF; -#else - SPI_ON(); - - /* Send the request for the part identification */ - spi_write_read_byte(0x9F); - - /* Now read in the manufacturer id bytes */ - do { - flash.manufacturer_id = spi_write_read_byte(0); - if (flash.manufacturer_id == 0x7F) - puts("Warning: unhandled manufacturer continuation byte!\n"); - } while (flash.manufacturer_id == 0x7F); - - /* Now read in the first device id byte */ - flash.device_id1 = spi_write_read_byte(0); - - /* Now read in the second device id byte */ - flash.device_id2 = spi_write_read_byte(0); - - /* Read extended device ids */ - flash.device_extid1 = spi_write_read_byte(0); - flash.device_extid2 = spi_write_read_byte(0); - - SPI_OFF(); -#endif - - dev_id = (flash.device_id1 << 8) | flash.device_id2; - dev_extid = (flash.device_extid1 << 8) | flash.device_extid2; - - for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) { - if (flash.manufacturer_id == flash_manufacturers[i].id) - break; - } - if (i == ARRAY_SIZE(flash_manufacturers)) - goto unknown; - - flash.manufacturer = &flash_manufacturers[i]; - flash.ops = flash_manufacturers[i].ops; - - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if (dev_id == flash.manufacturer->flashes[i].id && - (flash.manufacturer->flashes[i].ext_id == 0 || - flash.manufacturer->flashes[i].ext_id == dev_extid)) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - if (flash.manufacturer_id == JED_MANU_SST) - flash.write_length = 1; /* pwnt :( */ - else - flash.write_length = 256; - break; - - case JED_MANU_ATMEL: { - uint8_t status = read_status_register(); - - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if ((status & 0x3c) == flash.manufacturer->flashes[i].id) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - /* see if flash is in "power of 2" mode */ - if (status & 0x1) - flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1)); - - flash.write_length = flash.sector_size; - break; - } - } - - /* the SST parts power up with software protection enabled by default */ - if (flash.manufacturer_id == JED_MANU_SST) - write_status_register(0); - - called_init = 1; - return 0; - - unknown: - printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n", - flash.manufacturer_id, flash.device_id1, flash.device_id2); - return 1; -} - -/* - * Function: spi_init_f - * Description: Init SPI-Controller (ROM part) - * return: --- - */ -void spi_init_f(void) -{ -} - -/* - * Function: spi_init_r - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * return: --- - */ -void spi_init_r(void) -{ -#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI) - /* Our testing strategy here is pretty basic: - * - fill src memory with an 8-bit pattern - * - write the src memory to the SPI flash - * - read the SPI flash into the dst memory - * - compare src and dst memory regions - * - repeat a few times - * The variations we test for: - * - change the 8-bit pattern a bit - * - change the read/write block size so we know: - * - writes smaller/equal/larger than the buffer work - * - writes smaller/equal/larger than the sector work - * - change the SPI offsets so we know: - * - writing partial sectors works - */ - uint8_t *mem_src, *mem_dst; - size_t i, c, l, o; - size_t test_count, errors; - uint8_t pattern; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - eeprom_info(); - - ulong lengths[] = { - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2 - }; - ulong offsets[] = { - 0, - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.write_length / 4, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2, - flash.sector_size / 4, - }; - - /* the exact addresses are arbitrary ... they just need to not overlap */ - mem_src = (void *)(0); - mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2); - - test_count = 0; - errors = 0; - pattern = 0x00; - - for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */ - for (l = 0; l < ARRAY_SIZE(lengths); ++l) { - for (o = 0; o < ARRAY_SIZE(offsets); ++o) { - ulong len = lengths[l]; - ulong off = offsets[o]; - - printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off); - - /* setup the source memory region */ - memset(mem_src, pattern, len); - - test_count += 4; - for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */ - if (ctrlc()) { - puts("\nAbort\n"); - goto out; - } - - /* make sure background fill pattern != pattern */ - memset(mem_dst, pattern ^ 0xFF, len); - - /* write out the source memory and then read it back and compare */ - eeprom_write(0, off, mem_src, len); - eeprom_read(0, off, mem_dst, len); - - if (memcmp(mem_src, mem_dst, len)) { - for (c = 0; c < len; ++c) - if (mem_src[c] != mem_dst[c]) - break; - printf(" FAIL @ offset %u, skipping repeats ", c); - ++errors; - break; - } - - /* XXX: should shrink write region here to test with - * leading/trailing canaries so we know surrounding - * bytes don't get screwed. - */ - } - puts("\n"); - } - } - - /* invert the pattern every other run and shift out bits slowly */ - pattern ^= 0xFF; - if (i % 2) - pattern = (pattern | 0x01) << 1; - } - - if (errors) - printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors); - else - printf("SPI PASS: %i tests worked!\n", test_count); - - out: - SPI_DEINIT(); - -#endif -} - -static void transmit_address(uint32_t addr) -{ - /* Send the highest byte of the 24 bit address at first */ - spi_write_read_byte(addr >> 16); - /* Send the middle byte of the 24 bit address at second */ - spi_write_read_byte(addr >> 8); - /* Send the lowest byte of the 24 bit address finally */ - spi_write_read_byte(addr); -} - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ -#ifdef CONFIG_SPI_READFLASH_NODMA -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - size_t i, j; - - /* Send the read command to SPI device */ - SPI_ON(); - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - /* After the SPI device address has been placed on the MOSI pin the data can be */ - /* received on the MISO pin. */ - j = flash.sector_size << 1; - for (i = 1; i <= count; ++i) { - *buffer++ = spi_write_read_byte(0); - if (!j--) { - puts("."); - j = flash.sector_size; - } - } - - SPI_OFF(); - - return 0; -} -#else - -#ifdef __ADSPBF54x__ -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG -#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG -#elif defined(__ADSPBF561__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG -#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ - defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG -#else -#error "Please provide SPI DMA channel defines" -#endif - -struct dmadesc_array { - unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; -} __attribute__((packed)); - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ - -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - unsigned int ndsize; - struct dmadesc_array dma[2]; - /* Send the read command to SPI device */ - - if (!count) - return 0; - - dma[0].start_addr = (unsigned long)buffer; - dma[0].x_modify = 1; - if (count <= 65536) { - blackfin_dcache_flush_invalidate_range(buffer, buffer + count); - ndsize = NDSIZE_5; - dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[0].x_count = count; - } else { - blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1); - ndsize = NDSIZE_7; - dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D; - dma[0].x_count = 0; /* 2^16 */ - dma[0].y_count = count >> 16; /* count / 2^16 */ - dma[0].y_modify = 1; - dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF)); - dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[1].x_count = count & 0xFFFF; /* count % 2^16 */ - dma[1].x_modify = 1; - } - - bfin_write_DMA_SPI_CONFIG(0); - bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_DMA_SPI_CURR_DESC_PTR(dma); - - SPI_ON(); - - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN); - *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ); - SSYNC(); - - /* - * We already invalidated the first 64k, - * now while we just wait invalidate the remaining part. - * Its not likely that the DMA is going to overtake - */ - if (count > 65536) - blackfin_dcache_flush_invalidate_range(buffer + 65536, - buffer + count); - - while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE)) - if (ctrlc()) - break; - - SPI_OFF(); - - *pSPI_CTL = 0; - - bfin_write_DMA_SPI_CONFIG(0); - - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - - return 0; -} -#endif - -static long address_to_sector(unsigned long address) -{ - if (address > (flash.num_sectors * flash.sector_size) - 1) - return -1; - return address / flash.sector_size; -} - -static int erase_sector(int address) -{ - /* sector gets checked in higher function, so assume it's valid - * here and figure out the offset of the sector in flash - */ - if (enable_writing()) - return -1; - - /* - * Send the erase block command to the flash followed by the 24 address - * to point to the start of a sector - */ - SPI_ON(); - spi_write_read_byte(flash.ops->erase); - transmit_address(address); - SPI_OFF(); - - return wait_for_ready_status(); -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static long write_flash(unsigned long address, long count, uchar *buffer) -{ - long i, write_buffer_size; - - if (enable_writing()) - return -1; - - /* Send write command followed by the 24 bit address */ - SPI_ON(); - spi_write_read_byte(flash.ops->write); - transmit_address(address); - - /* Shoot out a single write buffer */ - write_buffer_size = min(count, flash.write_length); - for (i = 0; i < write_buffer_size; ++i) - spi_write_read_byte(buffer[i]); - - SPI_OFF(); - - /* Wait for the flash to do its thing */ - if (wait_for_ready_status()) { - puts("SPI Program Time out! "); - return -1; - } - - return i; -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static int write_sector(unsigned long address, long count, uchar *buffer) -{ - long write_cnt; - - while (count != 0) { - write_cnt = write_flash(address, count, buffer); - if (write_cnt == -1) - return -1; - - /* Now that we've sent some bytes out to the flash, update - * our counters a bit - */ - count -= write_cnt; - address += write_cnt; - buffer += write_cnt; - } - - /* return the appropriate error code */ - return 0; -} - -/* - * Function: spi_write - */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - int start_sector, end_sector; - int start_byte, end_byte; - uchar *temp = NULL; - int num, ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - - /* Get the start block number */ - start_sector = address_to_sector(offset); - if (start_sector == -1) { - puts("Invalid sector! "); - goto out; - } - end_sector = address_to_sector(offset + len - 1); - if (end_sector == -1) { - puts("Invalid sector! "); - goto out; - } - - /* Since flashes operate in sector units but the eeprom command - * operates as a continuous stream of bytes, we need to emulate - * the eeprom behavior. So here we read in the sector, overlay - * any bytes we're actually modifying, erase the sector, and - * then write back out the new sector. - */ - temp = malloc(flash.sector_size); - if (!temp) { - puts("Malloc for sector failed! "); - goto out; - } - - for (num = start_sector; num <= end_sector; num++) { - unsigned long address = num * flash.sector_size; - - /* XXX: should add an optimization when spanning sectors: - * No point in reading in a sector if we're going to be - * clobbering the whole thing. Need to also add a test - * case to make sure the optimization is correct. - */ - if (read_flash(address, flash.sector_size, temp)) { - puts("Read sector failed! "); - len = 0; - break; - } - - start_byte = max(address, offset); - end_byte = address + flash.sector_size - 1; - if (end_byte > (offset + len)) - end_byte = (offset + len - 1); - - memcpy(temp + start_byte - address, - buffer + start_byte - offset, - end_byte - start_byte + 1); - - if (erase_sector(address)) { - puts("Erase sector failed! "); - goto out; - } - - if (write_sector(address, flash.sector_size, temp)) { - puts("Write sector failed! "); - goto out; - } - - puts("."); - } - - ret = len; - - out: - free(temp); - - SPI_DEINIT(); - - return ret; -} - -/* - * Function: spi_read - */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - - SPI_INIT(); - - if (spi_detect_part()) - len = 0; - else { - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - read_flash(offset, len, buffer); - } - - SPI_DEINIT(); - - return len; -} - -/* - * Spit out some useful information about the SPI eeprom - */ -int eeprom_info(void) -{ - int ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - ret = 1; - else - printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n" - "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n" - "Flash Size: %lu mbit (%lu mbyte)\n" - "Status: 0x%02X\n", - flash.flash->name, flash.manufacturer_id, flash.manufacturer->name, - flash.device_id1, flash.device_id2, flash.num_sectors, - flash.sector_size, flash.write_length, - (flash.num_sectors * flash.sector_size) >> 17, - (flash.num_sectors * flash.sector_size) >> 20, - read_status_register()); - - SPI_DEINIT(); - - return ret; -} - -#endif diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 65fb81a..cb9ee86 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -7,10 +7,12 @@ */ #include <common.h> -#include <netdev.h> #include <config.h> #include <command.h> +#include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/sdh.h> DECLARE_GLOBAL_DATA_PTR; @@ -24,53 +26,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_SMC911X @@ -96,9 +58,7 @@ void board_musb_init(void) * be low for device mode and high for host mode. We set it high * here because we are in host mode. */ - bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7); - bfin_write_PORTE_DIR_SET(PE7); - bfin_write_PORTE_SET(PE7); - SSYNC(); + gpio_request(GPIO_PE7, "musb-vbus"); + gpio_direction_output(GPIO_PE7, 1); } #endif diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 10b08e2..af3d58b 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -173,22 +175,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index 6355c10..06d004a 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -13,7 +13,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,14 +27,8 @@ int checkboard(void) #ifdef SHARED_RESOURCES void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); - SSYNC(); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); SSYNC(); } #endif diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index da34b40..9df45c0 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -177,13 +177,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile index c2cd244..bad018a 100644 --- a/board/cm-bf527/Makefile +++ b/board/cm-bf527/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o gpio.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c deleted file mode 100644 index 7e0babe..0000000 --- a/board/cm-bf527/gpio.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Control GPIO pins on the fly - * - * Copyright (c) 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> - -#include <asm/blackfin.h> - -int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 3) { - show_usage: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* parse the behavior */ - ulong port_cmd = 0; - switch (argv[1][0]) { - case 'i': break; - case 's': port_cmd = (PORTFIO_SET - PORTFIO); break; - case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break; - case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break; - default: goto show_usage; - } - - /* parse the pin with format: [p]<fgh><#> */ - const char *str_pin = argv[2]; - - /* grab the [p]<fgh> portion */ - ulong port_base; - if (*str_pin == 'p') ++str_pin; - switch (*str_pin) { - case 'f': port_base = PORTFIO; break; - case 'g': port_base = PORTGIO; break; - case 'h': port_base = PORTHIO; break; - default: goto show_usage; - } - - /* grab the <#> portion */ - ulong pin = simple_strtoul(str_pin+1, NULL, 10); - ulong pin_mask = (1 << pin); - if (pin > 15) - goto show_usage; - - /* finally, let's do it: set direction and exec command */ - switch (*str_pin) { - case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break; - case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break; - case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break; - } - - ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO); - if (argv[1][0] == 'i') - bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask); - else { - bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask); - bfin_write16(port_base + port_cmd, pin_mask); - } - - printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]); - - return 0; -} - -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "gpio - set/clear/toggle gpio output pins\n", - "<s|c|t> <port><pin>\n" - " - set/clear/toggle the specified pin\n"); diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c index 7167680..f8ccc07 100644 --- a/board/cm-bf527/gpio_cfi_flash.c +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH9 +#define GPIO_PIN_1 GPIO_PH9 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PG11 +#define GPIO_PIN_2 GPIO_PG11 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,7 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537e/Makefile +++ b/board/cm-bf537e/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c deleted file mode 100644 index a4c1ec0..0000000 --- a/board/cm-bf537e/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4 GPIO flash bank switch\n", - "<pf4> - set PF4 GPIO pin state\n"); diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index a9e69cf..79ee844 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537u/Makefile +++ b/board/cm-bf537u/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c deleted file mode 100644 index 52abe79..0000000 --- a/board/cm-bf537u/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTHIO(); - printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0)); - } - - return 0; -} - -U_BOOT_CMD(ph, 3, 0, do_ph, - "set/clear PH0 GPIO flash bank switch\n", - "<ph0> - set PH0 GPIO pin state\n"); diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c index 68633ec..416c689 100644 --- a/board/cm-bf537u/gpio_cfi_flash.c +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH0 +#define GPIO_PIN_1 GPIO_PH0 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 3627586..90ce4c3 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -11,6 +11,7 @@ #include <command.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/portmux.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,53 +24,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } int board_eth_init(bd_t *bis) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 4097f09..d43f5a1 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -174,28 +176,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= - (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | - PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile new file mode 100644 index 0000000..44d73cc --- /dev/null +++ b/board/colibri_pxa270/Makefile @@ -0,0 +1,45 @@ +# +# Toradex Colibri PXA270 Support +# +# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := colibri_pxa270.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c new file mode 100644 index 0000000..d3822f0 --- /dev/null +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -0,0 +1,118 @@ +/* + * Toradex Colibri PXA270 Support + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(0x200); + UHCRHDA |= 0x100; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); + + /* enable port 2 */ + UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + return; +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/colibri_pxa270/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S new file mode 100644 index 0000000..a43dac2 --- /dev/null +++ b/board/colibri_pxa270/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Toradex Colibri PXA270 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> + +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup + + mov pc, lr diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index b0ebad7..96698e7 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -105,7 +105,7 @@ int misc_init_r() { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); + clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); return 0; } diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index af8a4a2..61b6c33 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -200,13 +200,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index df289aa..2d48d7e 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -42,6 +42,10 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o +COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o +COBJS-$(CONFIG_P1022DS) += ics307_clk.o +COBJS-$(CONFIG_P2020DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c new file mode 100644 index 0000000..89d8810 --- /dev/null +++ b/board/freescale/common/ics307_clk.c @@ -0,0 +1,88 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +#include "ics307_clk.h" + +#ifdef CONFIG_FSL_NGPIXIS +#include "ngpixis.h" +#else +#include "pixis.h" +#endif + +/* decode S[0-2] to Output Divider (OD) */ +static u8 ics307_s_to_od[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* + * Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. + */ +static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long rdw = cw2 & 0x7F; + unsigned long od = ics307_s_to_od[cw0 & 0x7]; + unsigned long freq; + + /* + * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) + * + * cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + * + */ + + freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(void) +{ + return ics307_clk_freq( + in_8(&pixis->sclk[0]), + in_8(&pixis->sclk[1]), + in_8(&pixis->sclk[2])); +} + +unsigned long get_board_ddr_clk(void) +{ + return ics307_clk_freq( + in_8(&pixis->dclk[0]), + in_8(&pixis->dclk[1]), + in_8(&pixis->dclk[2])); +} diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h new file mode 100644 index 0000000..db3dbc4 --- /dev/null +++ b/board/freescale/common/ics307_clk.h @@ -0,0 +1,30 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ICS_CLK_H_ +#define __ICS_CLK_H_ 1 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(void); +extern unsigned long get_board_ddr_clk(void); +#endif + +#endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 3c59ea8..089408b 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -45,7 +45,7 @@ typedef struct ngpixis { u8 sw; u8 en; } s[8]; -} ngpixis_t __attribute__ ((aligned(1))); +} __attribute__ ((packed)) ngpixis_t; /* Pointer to the PIXIS register set */ #define pixis ((ngpixis_t *)PIXIS_BASE) diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h new file mode 100644 index 0000000..7f86de7 --- /dev/null +++ b/board/freescale/common/pixis.h @@ -0,0 +1,182 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __PIXIS_H_ +#define __PIXIS_H_ 1 + +/* PIXIS register set. */ +#if defined(CONFIG_MPC8536DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 rst2; + u8 aux1; + u8 spd; + u8 aux2; + u8 csr2; + u8 watch; + u8 led; + u8 pwr; + u8 res[3]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[3]; + u8 sclk[3]; + u8 dclk[3]; + u8 i2cdacr; + u8 vcoreacc[4]; + u8 vcorecnt[3]; + u8 vcoremax[2]; + u8 vplatacc[4]; + u8 vplatcnt[3]; + u8 vplatmax[2]; + u8 vtempacc[4]; + u8 vtempcnt[3]; + u8 vtempmax[2]; + u8 res2[4]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8544DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux1; + u8 spd; + u8 res[8]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 vclkh; + u8 vclkl; + u8 watch; + u8 led; + u8 vspeed2; + u8 res2[34]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8572DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr1; + u8 aux1; + u8 spd; + u8 aux2; + u8 res[7]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[3]; + u8 res2[2]; + u8 sclk[3]; + u8 dclk[3]; + u8 res3[2]; + u8 watch; + u8 led; + u8 res4[25]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8610HPCD) +typedef struct pixis { + u8 id; + u8 ver; /* also called arch */ + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux; + u8 spd; + u8 brdcfg0; + u8 brdcfg1; + u8 res[4]; + u8 led; + u8 serno; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 res2; + u8 sclk[3]; + u8 res3; + u8 watch; + u8 res4[33]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8641HPCN) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux; + u8 spd; + u8 res[8]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 vclkh; + u8 vclkl; + u8 watch; + u8 res3[36]; +} __attribute__ ((packed)) pixis_t; +#else +#error Need to define pixis_t for this board +#endif + +/* Pointer to the PIXIS register set */ +#define pixis ((pixis_t *)PIXIS_BASE) + +#endif /* __PIXIS_H_ */ diff --git a/board/altera/ep1c20/Makefile b/board/freescale/mpc8308rdb/Makefile index acad2aa..e9bfa2b 100644 --- a/board/altera/ep1c20/Makefile +++ b/board/freescale/mpc8308rdb/Makefile @@ -1,6 +1,8 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010 +# Ilya Yanok, Emcraft Systems, yanok@emcraft.com # # See file CREDITS for list of people who contributed to this # project. @@ -22,15 +24,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := $(BOARD).o sdram.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8308rdb/config.mk b/board/freescale/mpc8308rdb/config.mk new file mode 100644 index 0000000..f768264 --- /dev/null +++ b/board/freescale/mpc8308rdb/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c new file mode 100644 index 0000000..a864189 --- /dev/null +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <vsc7385.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; + + return 0; +} + +static u8 read_board_info(void) +{ + u8 val8; + i2c_set_bus_num(0); + + if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) + return val8; + else + return 0; +} + +int checkboard(void) +{ + static const char * const rev_str[] = { + "1.0", + "<reserved>", + "<reserved>", + "<reserved>", + "<unknown>", + }; + u8 info; + int i; + + info = read_board_info(); + i = (!info) ? 4 : info & 0x03; + + printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); + + return 0; +} + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + clk83xx_t *clk = (clk83xx_t *)&immr->clk; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM , + SCCR_PCIEXP1CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg, 0); +} +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + return 1; + } +#endif + + return 0; +} +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rv, num_if = 0; + + /* Initialize TSECs first */ + if ((rv = cpu_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize TSECs.\n"); + + if ((rv = pci_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize PCI Ethernet.\n"); + + return num_if; +} diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c new file mode 100644 index 0000000..939c1b8 --- /dev/null +++ b/board/freescale/mpc8308rdb/sdram.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * This files is mostly identical to the original from + * board\freescale\mpc8315erdb\sdram.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void resume_from_sleep(void) +{ + u32 magic = *(u32 *)0; + + typedef void (*func_t)(void); + func_t resume = *(func_t *)4; + + if (magic == 0xf5153ae5) + resume(); + + gd->flags &= ~GD_FLG_SILENT; + puts("\nResume from sleep failed: bad magic word\n"); +} + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) { + out_be32(&im->ddr.sdram_cfg, + CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI); + } else { + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + } + + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) + resume_from_sleep(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 0c4fd68..7aede13 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -110,7 +110,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 61d1249..365ac37 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -192,7 +192,7 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; /* diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 7da39f1..5647579 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -221,15 +221,14 @@ int misc_init_f(void) 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 }; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbus = &immap->lbus; - lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM; - lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM; + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 */ - lbus->mamr = 0x08404440; + immap->im_lbc.mamr = 0x08404440; upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 4f55732..59ada9c 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -280,7 +280,7 @@ int checkboard(void) static int sdram_init(unsigned int base) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + fsl_lbc_t *lbc = LBC_BASE_ADDR; const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; int rem = base % sdram_size; uint *sdram_addr; @@ -293,8 +293,8 @@ static int sdram_init(unsigned int base) /* * Setup SDRAM Base and Option Registers */ - immap->lbus.bank[2].br = base | CONFIG_SYS_BR2; - immap->lbus.bank[2].or = CONFIG_SYS_OR2; + set_lbc_br(2, base | CONFIG_SYS_BR2); + set_lbc_or(2, CONFIG_SYS_OR2); immap->sysconf.lblaw[2].bar = base; immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c index 9ffffb4..92d56a3 100644 --- a/board/freescale/mpc8360erdk/nand.c +++ b/board/freescale/mpc8360erdk/nand.c @@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = { int board_nand_init(struct nand_chip *nand) { - fun.upm.mxmr = &im->lbus.mamr; - fun.upm.mdr = &im->lbus.mdr; - fun.upm.mar = &im->lbus.mar; + fun.upm.mxmr = &im->im_lbc.mamr; + fun.upm.mdr = &im->im_lbc.mdr; + fun.upm.mar = &im->im_lbc.mar; upm_setup(&fun.upm); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 1968106..50ca3ca 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -350,154 +350,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char -ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2) - ); -} - -unsigned long -get_board_ddr_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2) - ); -} -#else -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long -get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 9e3f677..f9ff827 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -117,7 +117,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -176,7 +176,7 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -185,8 +185,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index c30d966..0580fe7 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -291,7 +291,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -340,7 +340,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -352,16 +352,11 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 0be2d89..581d5f2 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -40,7 +40,7 @@ int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index aa3f32b..f016995 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -118,7 +118,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -154,7 +154,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -166,16 +166,11 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index ecddd0d..b7e0e0c 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -291,7 +291,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -340,7 +340,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -352,12 +352,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 2bca0f2..489f90b 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -322,7 +322,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -381,7 +381,7 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -390,8 +390,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 4ec13a9..036bf95 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -181,7 +181,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -214,7 +214,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; @@ -225,16 +225,13 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); asm("msync"); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1eddeef..81e8ff5 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -308,7 +308,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 6029a51..81d481a 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -284,149 +284,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2) - ); -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2) - ); -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile new file mode 100644 index 0000000..8ede2d6 --- /dev/null +++ b/board/freescale/p1022ds/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk new file mode 100644 index 0000000..4581d20 --- /dev/null +++ b/board/freescale/p1022ds/config.mk @@ -0,0 +1,14 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c new file mode 100644 index 0000000..7ecfb3e --- /dev/null +++ b/board/freescale/p1022ds/ddr.c @@ -0,0 +1,106 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int ret; + + /* + * The P1022 has only one DDR controller, and the board has only one + * DIMM slot. + */ + ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, + sizeof(ddr3_spd_eeprom_t)); + if (ret) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS1); + memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; /* Range: 0-8 */ + u32 cpo; /* Range: 2-31 */ + u32 write_data_delay; /* Range: 0-6 */ + u32 force_2T; +} board_specific_parameters_t; + +static const board_specific_parameters_t bsp[] = { +/* + * lo| hi| num| clk| cpo|wrdata|2T + * mhz| mhz|ranks|adjst| | delay| + */ + { 0, 333, 1, 5, 31, 3, 0}, + {334, 400, 1, 5, 31, 3, 0}, + {401, 549, 1, 5, 31, 3, 0}, + {550, 680, 1, 5, 31, 5, 0}, + {681, 850, 1, 5, 31, 5, 0}, + { 0, 333, 2, 5, 31, 3, 0}, + {334, 400, 2, 5, 31, 3, 0}, + {401, 549, 2, 5, 31, 3, 0}, + {550, 680, 2, 5, 31, 5, 0}, + {681, 850, 2, 5, 31, 5, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned long ddr_freq; + unsigned int i; + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < ARRAY_SIZE(bsp); i++) { + if (ddr_freq >= bsp[i].datarate_mhz_low && + ddr_freq <= bsp[i].datarate_mhz_high && + pdimm->n_ranks == bsp[i].n_ranks) { + popts->clk_adjust = bsp[i].clk_adjust; + popts->cpo_override = bsp[i].cpo; + popts->write_data_delay = bsp[i].write_data_delay; + popts->twoT_en = bsp[i].force_2T; + break; + } + } + + popts->half_strength_driver_enable = 1; + + /* Per AN4039, enable ZQ calibration. */ + popts->zq_en = 1; + + /* + * For wake-up on ARP, we need auto self refresh enabled + */ + popts->auto_self_refresh_en = 1; + popts->sr_it = 0xb; +} diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c new file mode 100644 index 0000000..b23b8f9 --- /dev/null +++ b/board/freescale/p1022ds/law.c @@ -0,0 +1,21 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c new file mode 100644 index 0000000..be692cb --- /dev/null +++ b/board/freescale/p1022ds/p1022ds.c @@ -0,0 +1,354 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> +#include <netdev.h> +#include <i2c.h> + +#include "../common/ngpixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, 0x1000); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* Set the pin muxing to enable ETSEC2. */ + clrbits_be32(&gur->pmuxcr2, 0x001F8000); + + return 0; +} + +int checkboard(void) +{ + u8 sw; + + puts("Board: P1022DS "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + + switch ((sw & PIXIS_LBMAP_MASK) >> 6) { + case 0: + printf ("vBank: %u\n", ((sw & 0x30) >> 4)); + break; + case 1: + printf ("NAND\n"); + break; + case 2: + case 3: + puts ("Promjet\n"); + break; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing....\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; + + puts(" DDR: "); + return dram_size; +} + +#define CONFIG_TFP410_I2C_ADDR 0x38 + +int misc_init_r(void) +{ + u8 temp; + + /* Enable the TFP410 Encoder */ + + temp = 0xBF; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n", temp); + + temp = 0x10; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n",temp); + + return 0; +} + +/* + * A list of PCI and SATA slots + */ +enum slot_id { + SLOT_PCIE1 = 1, + SLOT_PCIE2, + SLOT_PCIE3, + SLOT_PCIE4, + SLOT_PCIE5, + SLOT_SATA1, + SLOT_SATA2 +}; + +/* + * This array maps the slot identifiers to their names on the P1022DS board. + */ +static const char *slot_names[] = { + [SLOT_PCIE1] = "Slot 1", + [SLOT_PCIE2] = "Slot 2", + [SLOT_PCIE3] = "Slot 3", + [SLOT_PCIE4] = "Slot 4", + [SLOT_PCIE5] = "Mini-PCIe", + [SLOT_SATA1] = "SATA 1", + [SLOT_SATA2] = "SATA 2", +}; + +/* + * This array maps a given SERDES configuration and SERDES device to the PCI or + * SATA slot that it connects to. This mapping is hard-coded in the FPGA. + */ +static u8 serdes_dev_slot[][SATA2 + 1] = { + [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, + [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, + [PCIE2] = SLOT_PCIE5 }, + [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3 }, + [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1c] = { [PCIE1] = SLOT_PCIE1, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, + [0x1f] = { [PCIE1] = SLOT_PCIE1 }, +}; + + +/* + * Returns the name of the slot to which the PCIe or SATA controller is + * connected + */ +const char *serdes_slot_name(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + enum slot_id slot = serdes_dev_slot[srds_cfg][device]; + const char *name = slot_names[slot]; + + if (name) + return name; + else + return "Nothing"; +} + +static void configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected) +{ + static int bus_number = 0; + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf(" PCIE%u connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + bus_number = fsl_pci_init_port(info, hose, bus_number); +} + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pci_info pci_info; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info, 1); + configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); + } else { + printf(" PCIE1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info, 2); + configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); + } else { + printf(" PCIE2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info, 3); + configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); + } else { + printf(" PCIE3: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ +#endif +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +/* + * Initialize on-board and/or PCI Ethernet devices + * + * Returns: + * <0, error + * 0, no ethernet devices found + * >0, number of ethernet devices initialized + */ +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[2]; + unsigned int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci0", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); +#endif + +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); +#endif + +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); +#endif + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif +} +#endif + +#ifdef CONFIG_MP +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c new file mode 100644 index 0000000..e620112 --- /dev/null +++ b/board/freescale/p1022ds/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index f0ff209..be4b2eb 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -313,155 +313,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -unsigned long calculate_board_sys_clk(ulong dummy) -{ - ulong val; - - val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]), - in_8(&pixis->sclk[2])); - debug("sysclk val = %lu\n", val); - return val; -} - -unsigned long calculate_board_ddr_clk(ulong dummy) -{ - ulong val; - - val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]), - in_8(&pixis->dclk[2])); - debug("ddrclk val = %lu\n", val); - return val; -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - - i = in_8(&pixis->spd); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - - i = in_8(&pixis->spd); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index b5bebd4..d2ac7a5 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -16,3 +17,10 @@ int checkboard(void) printf(" Support: http://www.i-syst.com/\n"); return 0; } + +#ifdef CONFIG_DRIVER_AX88180 +int board_eth_init(bd_t *bis) +{ + return ax88180_initialize(bis); +} +#endif diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 7c27233..054d644 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -69,7 +69,7 @@ phys_size_t initdram (int board_type) long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -110,8 +110,8 @@ phys_size_t initdram (int board_type) gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 5353d73..a302b91 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -134,7 +134,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index b14a3d3..f9d92d9 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -290,7 +290,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index c7835de..e41c84c 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -387,13 +387,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 34861d4..50fae7c 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -160,7 +160,7 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts("\n SDRAM on Local Bus: "); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 194f6ab..d62cfd1 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -116,7 +116,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -152,7 +152,7 @@ sdram_init(void) #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; @@ -163,22 +163,14 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); - asm("msync"); - - out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); - asm("msync"); - - out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); - asm("msync"); - - out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); - asm("msync"); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); - out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); asm("msync"); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c40b5e3..10ba62f 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -269,7 +269,7 @@ phys_size_t initdram (int board_type) #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -310,8 +310,8 @@ phys_size_t initdram (int board_type) gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c index ebb70a2..ba59943 100644 --- a/board/sheldon/simpc8313/sdram.c +++ b/board/sheldon/simpc8313/sdram.c @@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer) phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc= &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index cb30b48..c2164c9 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -93,7 +93,7 @@ int misc_init_r(void) { int rc = 0; immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbus_t *lbus = &immap->lbus; + fsl_lbc_t *lbus = &immap->im_lbc; u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ /* UPM Table Configuration Code */ diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 9183c15..72e7401 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -87,8 +87,6 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - /* * Adjust flash start and offset to detected values */ @@ -99,8 +97,10 @@ int misc_init_r (void) * Check if boot FLASH isn't max size */ if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); + set_lbc_or(0, gd->bd->bi_flashstart | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); /* * Re-check to get correct base address @@ -112,8 +112,8 @@ int misc_init_r (void) * Check if only one FLASH bank is available */ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; + set_lbc_or(1, 0); + set_lbc_br(1, 0); /* * Re-do flash protection upon new addresses @@ -148,7 +148,7 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; @@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void) int lime_probe(void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint cfg_br2; uint cfg_or2; int type; - cfg_br2 = memctl->br2; - cfg_or2 = memctl->or2; + cfg_br2 = get_lbc_br(2); + cfg_or2 = get_lbc_or(2); /* Configure GPCM for CS2 */ - memctl->br2 = 0; - memctl->or2 = 0xfc000410; - memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; + set_lbc_br(2, 0); + set_lbc_or(2, 0xfc000410); + set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); /* Get controller type */ type = mb862xx_probe(CONFIG_SYS_LIME_BASE); /* Restore previous CS2 configuration */ - memctl->br2 = 0; - memctl->or2 = cfg_or2; - memctl->br2 = cfg_br2; + set_lbc_br(2, 0); + set_lbc_or(2, cfg_or2); + set_lbc_br(2, cfg_br2); return (type == MB862XX_TYPE_LIME) ? 1 : 0; } diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile index 3812ba1..bad018a 100644 --- a/board/tcm-bf537/Makefile +++ b/board/tcm-bf537/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c deleted file mode 100644 index 14055c6..0000000 --- a/board/tcm-bf537/flash.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc == 3) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - dflg = simple_strtoul(argv[2], NULL, 16); - faddr |= (dflg << 22); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i PF5:%i)\n", data, - !!(data & PF4), !!(data & PF5)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4/PF5 GPIO flash bank switch\n", - "<pf4> <pf5> - set PF4/PF5 GPIO pin state\n"); diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c index ac8587c..08ea7af 100644 --- a/board/tcm-bf537/gpio_cfi_flash.c +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PF5 +#define GPIO_PIN_2 GPIO_PF5 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTFIO_SET(GPIO_PIN_2); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,6 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index e564879..8d046f4 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -253,10 +253,10 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); /* set OR0 and BR0 */ - im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM); - im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) | - (BR_MS_GPCM | BR_PS_32 | BR_V); + set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | + (-(total_size) & OR_GPCM_AM)); + set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | + (BR_MS_GPCM | BR_PS_32 | BR_V)); return (0); } diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c index 3da689a..4b16c31 100644 --- a/board/tqc/tqm85xx/nand.c +++ b/board/tqc/tqm85xx/nand.c @@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt; */ static void upmb_write (u_char addr, ulong val) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); @@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val) /* * Initialize UPM for NAND flash access. */ -static void nand_upm_setup (volatile ccsr_lbc_t *lbc) +static void nand_upm_setup (volatile fsl_lbc_t *lbc) { uint i, j; uint or3 = CONFIG_SYS_OR3_PRELIM; uint clock = get_lbc_clock (); - out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ - out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM); + set_lbc_br(3, 0); /* disable bank and reset all bits */ + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); /* * Search appropriate UPM table for bus clock. @@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc) /* EAD must be set due to TQM8548 timing specification */ or3 |= OR_UPM_EAD; - out_be32 (&lbc->or3, or3); + set_lbc_or(3, or3); /* Assign address of table */ nand_upm_patt = upm_freq_table[i].upm_patt; @@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip) int board_nand_init (struct nand_chip *nand) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; if (!nand_upm_patt) nand_upm_setup (lbc); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 8c9d586..fc2a6cb 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -269,8 +269,6 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - /* * Adjust flash start and offset to detected values */ @@ -281,26 +279,27 @@ int misc_init_r (void) * Recalculate CS configuration if second FLASH bank is available */ if (flash_info[0].size > 0) { - memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CONFIG_SYS_OR1_PRELIM & 0x00007fff); - memctl->br1 = gd->bd->bi_flashstart | - (CONFIG_SYS_BR1_PRELIM & 0x00007fff); + set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) | + (CONFIG_SYS_OR1_PRELIM & 0x00007fff)); + set_lbc_br(1, gd->bd->bi_flashstart | + (CONFIG_SYS_BR1_PRELIM & 0x00007fff)); /* * Re-check to get correct base address for bank 1 */ flash_get_size (gd->bd->bi_flashstart, 0); } else { - memctl->or1 = 0; - memctl->br1 = 0; + set_lbc_or(1, 0); + set_lbc_br(1, 0); } /* * If bank 1 is equipped, bank 0 is mapped after bank 1 */ - memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff); - memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff); + set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); + /* * Re-check to get correct base address for bank 0 */ @@ -341,7 +340,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); @@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sys_info; ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -386,7 +385,7 @@ uint get_lbc_clock (void) void local_bus_init (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -502,10 +501,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); + set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); - out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); + set_lbc_or(2, CONFIG_SYS_OR2_CAN); + set_lbc_br(2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); diff --git a/board/altera/ep1s40/Makefile b/board/ve8313/Makefile index acad2aa..c95f90e 100644 --- a/board/altera/ep1s40/Makefile +++ b/board/ve8313/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,15 +22,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ve8313/config.mk b/board/ve8313/config.mk new file mode 100644 index 0000000..02dd33e --- /dev/null +++ b/board/ve8313/config.mk @@ -0,0 +1,7 @@ +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + +ifndef TEXT_BASE +TEXT_BASE = 0xfe000000 +endif diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c new file mode 100644 index 0000000..8ba1b19 --- /dev/null +++ b/board/ve8313/ve8313.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Author: Scott Wood <scottwood@freescale.com> + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <pci.h> +#include <mpc83xx.h> +#include <ns16550.h> +#include <nand.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void disable_addr_trans (void); +extern void enable_addr_trans (void); + +int checkboard(void) +{ + puts("Board: ve8313\n"); + return 0; +} + +static long fixed_sdram(void) +{ + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + __udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); + + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + + /* now check the real size */ + disable_addr_trans (); + msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans (); +#endif + + return msize; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &im->lbus; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + sync(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} + +#define VE8313_WDT_EN 0x00020000 +#define VE8313_WDT_TRIG 0x00040000 + +int board_early_init_f (void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; + +#if defined(CONFIG_HW_WATCHDOG) + /* enable WDT */ + clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); +#else + /* disable WDT */ + setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); +#endif + /* set WDT pins as output */ + setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG); + + return 0; +} + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; + unsigned long reg; + + reg = in_be32(&gpio->dat); + if (reg & VE8313_WDT_TRIG) + clrbits_be32(&gpio->dat, VE8313_WDT_TRIG); + else + setbits_be32(&gpio->dat, VE8313_WDT_TRIG); +} +#endif + + +#if defined(CONFIG_PCI) +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + setbits_be32(&clk->occr, 0xe0000000); + + /* + * Configure PCI Local Access Windows + */ + out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR); + out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); + out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB); + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/altera/ep1s10/config.mk b/board/vpac270/Makefile index dab2740..0f3eacd 100644 --- a/board/altera/ep1s10/config.mk +++ b/board/vpac270/Makefile @@ -1,6 +1,7 @@ + # -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -21,11 +22,27 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := vpac270.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include +-include .depend -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif +######################################################################### diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/altera/ep1s40/ep1s40.c b/board/vpac270/lowlevel_init.S index 6395de7..ec0d12c 100644 --- a/board/altera/ep1s40/ep1s40.c +++ b/board/vpac270/lowlevel_init.S @@ -1,6 +1,8 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * Voipac PXA270 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * * * See file CREDITS for list of people who contributed to this * project. @@ -21,27 +23,18 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <netdev.h> - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1S40\n"); - return 0; -} +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> -phys_size_t initdram (int board_type) -{ - return (0); -} +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif + mov pc, lr diff --git a/board/altera/ep1s10/ep1s10.c b/board/vpac270/u-boot.lds index cf886da..58c371d 100644 --- a/board/altera/ep1s10/ep1s10.c +++ b/board/vpac270/u-boot.lds @@ -1,6 +1,6 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -21,32 +21,35 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS { - return 0; -} + . = 0x00000000; -int checkboard (void) -{ - puts ("BOARD : Altera EP-1S10\n"); - return 0; -} + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } -phys_size_t initdram (int board_type) -{ - return (0); -} + . = ALIGN(4); + .rodata : { *(.rodata) } -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; } -#endif diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c new file mode 100644 index 0000000..48e93ab --- /dev/null +++ b/board/vpac270/vpac270.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_VPAC270; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return 0; +} + +int usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(0x200); + UHCRHDA |= 0x100; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); + + /* enable port 2 */ + UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + return; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c index f4231a9..5822941 100644 --- a/board/xes/xpedite5170/xpedite5170.c +++ b/board/xes/xpedite5170/xpedite5170.c @@ -56,8 +56,6 @@ int checkboard(void) */ static void flash_cs_fixup(void) { - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - ccsr_lbc_t *lbc = &immap->im_lbc; int flash_sel; /* @@ -70,11 +68,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c index 7109771..a2627f8 100644 --- a/board/xes/xpedite5200/xpedite5200.c +++ b/board/xes/xpedite5200/xpedite5200.c @@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd); int checkboard(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); char *s; @@ -65,7 +65,6 @@ int checkboard(void) static void flash_cs_fixup(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); int flash_sel; /* @@ -78,11 +77,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c index 48d9fc8..2a060c2 100644 --- a/board/xes/xpedite5370/xpedite5370.c +++ b/board/xes/xpedite5370/xpedite5370.c @@ -58,7 +58,6 @@ int checkboard(void) static void flash_cs_fixup(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); int flash_sel; /* @@ -71,11 +70,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/altera/ep1s10/Makefile b/board/zipitz2/Makefile index acad2aa..2673835 100644 --- a/board/altera/ep1s10/Makefile +++ b/board/zipitz2/Makefile @@ -1,6 +1,9 @@ + +# +# Copyright (C) 2009 +# Marek Vasut <marek.vasut@gmail.com> # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Heavily based on pxa255_idp platform # # See file CREDITS for list of people who contributed to this # project. @@ -22,22 +25,18 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := zipitz2.o +SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/zipitz2/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/altera/ep1c20/ep1c20.c b/board/zipitz2/lowlevel_init.S index 82900f7..82a52e8 100644 --- a/board/altera/ep1c20/ep1c20.c +++ b/board/zipitz2/lowlevel_init.S @@ -1,6 +1,8 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * Aeronix Zipit Z2 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * * * See file CREDITS for list of people who contributed to this * project. @@ -21,32 +23,18 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1C20\n"); - return 0; -} +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> -phys_size_t initdram (int board_type) -{ - return (0); -} +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif + mov pc, lr diff --git a/board/zipitz2/u-boot.lds b/board/zipitz2/u-boot.lds new file mode 100644 index 0000000..fb4358b --- /dev/null +++ b/board/zipitz2/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c new file mode 100644 index 0000000..14d1d76 --- /dev/null +++ b/board/zipitz2/zipitz2.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2009 + * Marek Vasut <marek.vasut@gmail.com> + * + * Heavily based on pxa255_idp platform + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <serial.h> +#include <asm/arch/hardware.h> +#include <spi.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_SPI +void lcd_start(void); +#else +inline void lcd_start(void) {}; +#endif + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Enable LCD */ + lcd_start(); + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_stuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_SPI + +struct { + unsigned char reg; + unsigned short data; + unsigned char mdelay; +} lcd_data[] = { + { 0x07, 0x0000, 0 }, + { 0x13, 0x0000, 10 }, + { 0x11, 0x3004, 0 }, + { 0x14, 0x200F, 0 }, + { 0x10, 0x1a20, 0 }, + { 0x13, 0x0040, 50 }, + { 0x13, 0x0060, 0 }, + { 0x13, 0x0070, 200 }, + { 0x01, 0x0127, 0 }, + { 0x02, 0x0700, 0 }, + { 0x03, 0x1030, 0 }, + { 0x08, 0x0208, 0 }, + { 0x0B, 0x0620, 0 }, + { 0x0C, 0x0110, 0 }, + { 0x30, 0x0120, 0 }, + { 0x31, 0x0127, 0 }, + { 0x32, 0x0000, 0 }, + { 0x33, 0x0503, 0 }, + { 0x34, 0x0727, 0 }, + { 0x35, 0x0124, 0 }, + { 0x36, 0x0706, 0 }, + { 0x37, 0x0701, 0 }, + { 0x38, 0x0F00, 0 }, + { 0x39, 0x0F00, 0 }, + { 0x40, 0x0000, 0 }, + { 0x41, 0x0000, 0 }, + { 0x42, 0x013f, 0 }, + { 0x43, 0x0000, 0 }, + { 0x44, 0x013f, 0 }, + { 0x45, 0x0000, 0 }, + { 0x46, 0xef00, 0 }, + { 0x47, 0x013f, 0 }, + { 0x48, 0x0000, 0 }, + { 0x07, 0x0015, 30 }, + { 0x07, 0x0017, 0 }, + { 0x20, 0x0000, 0 }, + { 0x21, 0x0000, 0 }, + { 0x22, 0x0000, 0 }, +}; + +void zipitz2_spi_sda(int set) +{ + /* GPIO 13 */ + if (set) + GPSR0 = (1 << 13); + else + GPCR0 = (1 << 13); +} + +void zipitz2_spi_scl(int set) +{ + /* GPIO 22 */ + if (set) + GPCR0 = (1 << 22); + else + GPSR0 = (1 << 22); +} + +unsigned char zipitz2_spi_read(void) +{ + /* GPIO 40 */ + return !!(GPLR1 & (1 << 8)); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Always valid */ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* GPIO 88 low */ + GPCR2 = (1 << 24); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* GPIO 88 high */ + GPSR2 = (1 << 24); + +} + +void lcd_start(void) +{ + int i; + unsigned char reg[3] = { 0x74, 0x00, 0 }; + unsigned char data[3] = { 0x76, 0, 0 }; + unsigned char dummy[3] = { 0, 0, 0 }; + + /* PWM2 AF */ + GAFR0_L |= 0x00800000; + /* Enable clock to all PWM */ + CKEN |= 0x3; + /* Configure PWM2 */ + PWM_CTRL2 = 0x4f; + PWM_PWDUTY2 = 0x2ff; + PWM_PERVAL2 = 792; + + /* Toggle the reset pin to reset the LCD */ + GPSR0 = (1 << 19); + udelay(100000); + GPCR0 = (1 << 19); + udelay(20000); + GPSR0 = (1 << 19); + udelay(20000); + + /* Program the LCD init sequence */ + for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { + reg[0] = 0x74; + reg[1] = 0x0; + reg[2] = lcd_data[i].reg; + spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + data[0] = 0x76; + data[1] = lcd_data[i].data >> 8; + data[2] = lcd_data[i].data & 0xff; + spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + if (lcd_data[i].mdelay) + udelay(lcd_data[i].mdelay * 1000); + } + + GPSR0 = (1 << 11); +} +#endif |