diff options
Diffstat (limited to 'board')
21 files changed, 0 insertions, 1391 deletions
diff --git a/board/matrix_vision/mergerbox/Kconfig b/board/matrix_vision/mergerbox/Kconfig deleted file mode 100644 index 3857535..0000000 --- a/board/matrix_vision/mergerbox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MERGERBOX - -config SYS_BOARD - default "mergerbox" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MERGERBOX" - -endif diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS deleted file mode 100644 index 20bd073..0000000 --- a/board/matrix_vision/mergerbox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MERGERBOX BOARD -#M: Andre Schwarz <andre.schwarz@matrix-vision.de> -S: Orphan (since 2014-03) -F: board/matrix_vision/mergerbox/ -F: include/configs/MERGERBOX.h -F: configs/MERGERBOX_defconfig diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile deleted file mode 100644 index 11a7fd2..0000000 --- a/board/matrix_vision/mergerbox/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mergerbox.o pci.o fpga.o sm107.o diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README deleted file mode 100644 index 1994b65..0000000 --- a/board/matrix_vision/mergerbox/README +++ /dev/null @@ -1,59 +0,0 @@ -Matrix Vision MergerBox ------------------------ - -1. Board Description - - The MergerBox is a 120x160mm single board computing platform - for 3D Full-HD digital video processing. - - Power Supply is 10-32VDC. - -2 System Components - -2.1 CPU - Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. - 256 MByte DDR-II memory @ 333MHz data rate. - 64 MByte Nor Flash on local bus. - 1 GByte Nand Flash on FCM. - 1 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F with 4-Port hub. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. - 2 PCIe x1 busses on local mPCIe and cutom expansion connector. - 2 SATA host ports. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 Graphics - SM107 emebedded video controller driving a 5" 800x480 TFT panel. - Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. - -2.3 FPGA - Altera Cyclone-IV EP4C115 with several PCI DMA engines. - Connects to 7x Gennum 3G-SDI transceivers as video interconnect - as well as a HDMI v1.4 compliant output for 3D monitoring. - Utilizes two more DDR-II controllers providing 256MB memory. - -2.4 I2C - Bus1: - AD7418 @ 0x50 for voltage/temp. monitoring. - SX8650 @ 0x90 touch controller for HMI. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - Bus2: - mPCIe SMBus - SiI9022A @ 0x72/0xC0 HDMI transmitter. - TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. - LMH1983 @ 0xCA video PLL. - DS1338C @ 0xD0 real-time clock with embedded crystal. - 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. - -3 Flash layout. - - reset vector is 0x00000100, i.e. low boot. - - 00000000 u-boot binary. - 00100000 FPGA raw bit file. - 00300000 FIT image holding kernel, dtb and rescue squashfs. - 03d00000 u-boot environment. - 03e00000 splash image - - mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c deleted file mode 100644 index 57552c1..0000000 --- a/board/matrix_vision/mergerbox/fpga.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ACEX1K.h> -#include <command.h> -#include "mergerbox.h" -#include "fpga.h" - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mergerbox_init_fpga(void) -{ - debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - dvo &= ~FPGA_CONFIG; - gpio->dat = dvo; - udelay(5); - dvo |= FPGA_CONFIG; - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h deleted file mode 100644 index dbe9bff..0000000 --- a/board/matrix_vision/mergerbox/fpga.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mergerbox_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c deleted file mode 100644 index 5c891d1..0000000 --- a/board/matrix_vision/mergerbox/mergerbox.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz <andre.schwarz@matrix-vision.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <spi.h> -#include <asm/io.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <fdt_support.h> -#include <spd_sdram.h> -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static void setup_serdes(void) -{ - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -phys_size_t initdram(int board_type) -{ - u32 msize; - - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize_log2; - - msize = CONFIG_SYS_DDR_SIZE; - msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); -#endif - setup_serdes(); - - return msize << 20; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision MergerBox\n"); - - return 0; -} - -int misc_init_r(void) -{ - u16 dim; - int result; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; - unsigned char mac[6], mac_verify[6]; - char *s = getenv("reset_env"); - - for (dim = 10; dim < 180; dim += 5) { - mergerbox_tft_dim(dim); - udelay(100000); - } - - if (s) - mv_reset_environment(); - - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); - - /* check if Matrix Vision prefix present and export to env */ - if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { - printf("valid MAC found in eeprom: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - } else { - printf("no valid MAC found in eeprom.\n"); - - /* no: check the env */ - if (!eth_getenv_enetaddr("ethaddr", mac)) { - printf("no valid MAC found in env either.\n"); - /* TODO: ask for valid MAC */ - } else { - printf("valid MAC found in env: %pM\n", mac); - printf("updating MAC in eeprom.\n"); - - do { - result = test_and_clear_bit(20, &gpio->dat); - if (result) - printf("unprotect EEPROM failed !\n"); - udelay(20000); - } while(result); - - i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); - udelay(20000); - - do { - result = test_and_set_bit(20, &gpio->dat); - if (result) - printf("protect EEPROM failed !\n"); - udelay(20000); - } while(result); - - printf("verify MAC %pM ... ", mac); - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); - - if (!strncmp((char *)mac, (char *)mac_verify, 6)) - printf("ok.\n"); - else - /* TODO: retry or do something useful */ - printf("FAILED (got %pM) !\n", mac_verify); - } - } - - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~TFT_SPI_CPLD_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= TFT_SPI_CPLD_CS; -} - -/* control backlight pwm (display brightness). - * allow values 0-250 with 0 = turn off and 250 = max brightness - */ -void mergerbox_tft_dim(u16 value) -{ - struct spi_slave *slave; - u16 din; - u16 dout = 0; - - if (value > 0 && value < 250) - dout = 0x4000 | value; - - slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); - spi_claim_bus(slave); - spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - spi_free_slave(slave); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_dr_usb(blob, bd); - ft_pci_setup(blob, bd); -} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h deleted file mode 100644 index 53eab28..0000000 --- a/board/matrix_vision/mergerbox/mergerbox.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz <andre.schwarz@matrix-vision.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MERGERBOX_H__ -#define __MERGERBOX_H__ - -#define MV_GPIO - -/* - * GPIO Bank 1 - */ -#define TFT_SPI_EN (0x80000000>>0) -#define FPGA_CONFIG (0x80000000>>1) -#define FPGA_STATUS (0x80000000>>2) -#define FPGA_CONF_DONE (0x80000000>>3) -#define FPGA_DIN (0x80000000>>4) -#define FPGA_CCLK (0x80000000>>5) -#define MAN_RST (0x80000000>>6) -#define FPGA_SYS_RST (0x80000000>>7) -#define WD_WDI (0x80000000>>8) -#define TFT_RST (0x80000000>>9) -#define HISCON_GPIO1 (0x80000000>>10) -#define HISCON_GPIO2 (0x80000000>>11) -#define B2B_GPIO2 (0x80000000>>12) -#define CCU_GPIN (0x80000000>>13) -#define CCU_GPOUT (0x80000000>>14) -#define TFT_GPIO0 (0x80000000>>15) -#define TFT_GPIO1 (0x80000000>>16) -#define TFT_GPIO2 (0x80000000>>17) -#define TFT_GPIO3 (0x80000000>>18) -#define B2B_GPIO0 (0x80000000>>19) -#define B2B_GPIO1 (0x80000000>>20) -#define TFT_SPI_CPLD_CS (0x80000000>>21) -#define TFT_SPI_CS (0x80000000>>22) -#define CCU_PWR_EN (0x80000000>>23) -#define B2B_GPIO3 (0x80000000>>24) -#define CCU_PWR_STAT (0x80000000>>25) - -#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) -#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ - TFT_SPI_CPLD_CS) -#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) - -/* - * GPIO Bank 2 - */ -#define SPI_FLASH_WP (0x80000000>>10) -#define SYS_EEPROM_WP (0x80000000>>11) -#define SPI_FLASH_CS (0x80000000>>22) - -#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_ODE 0 - -void mergerbox_tft_dim(u16 value); - -#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c deleted file mode 100644 index 480f3ed..0000000 --- a/board/matrix_vision/mergerbox/pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz <andre.schwarz@matrix-vision.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc83xx.h> -#include <pci.h> -#include <asm/io.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI_MEM_BASE, - .phys_start = CONFIG_SYS_PCI_MEM_PHYS, - .size = CONFIG_SYS_PCI_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, - .size = CONFIG_SYS_PCI_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI_IO_BASE, - .phys_start = CONFIG_SYS_PCI_IO_PHYS, - .size = CONFIG_SYS_PCI_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - volatile gpio83xx_t *gpio; - gpio = (gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO1_DAT; - gpio->odr = MV_GPIO1_ODE; - gpio->dir = MV_GPIO1_OUT; - - gpio = (gpio83xx_t *)&immr->gpio[1]; - - gpio->dat = MV_GPIO2_DAT; - gpio->odr = MV_GPIO2_ODE; - gpio->dir = MV_GPIO2_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - - mergerbox_init_fpga(); - mv_load_fpga(); - - mergerbox_tft_dim(0); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c deleted file mode 100644 index d24f926..0000000 --- a/board/matrix_vision/mergerbox/sm107.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz <andre.schwarz@matrix-vision.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <ns16550.h> -#include <netdev.h> -#include <sm501.h> -#include <pci.h> -#include "../common/mv_common.h" - -#ifdef CONFIG_VIDEO -static const SMI_REGS init_regs_800x480[] = { - /* set endianess to little endian */ - {0x0005c, 0x00000000}, - /* PCI drive 12mA */ - {0x00004, 0x42401001}, - /* current clock */ - {0x0003c, 0x310a1818}, - /* clocks for pm0... */ - {0x00040, 0x0002184f}, - {0x00044, 0x2a1a0a01}, - /* GPIO */ - {0x10008, 0x00000000}, - {0x1000C, 0x00000000}, - /* panel control regs */ - {0x80000, 0x0f017106}, - {0x80004, 0x0}, - {0x80008, 0x0}, - {0x8000C, 0x00000000}, - {0x80010, 0x0c800c80}, - /* width 0x320 */ - {0x80014, 0x03200000}, - /* height 0x1e0 */ - {0x80018, 0x01E00000}, - {0x8001C, 0x0}, - {0x80020, 0x01df031f}, - {0x80024, 0x041f031f}, - {0x80028, 0x00800347}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00000000}, - /* ZV[0:7] */ - {0x00008, 0x00ff0000}, - /* 24-Bit TFT */ - {0x0000c, 0x3f000000}, - {0, 0} -}; - -/* - * Returns SM107 register base address. First thing called in the driver. - */ -unsigned int board_video_init(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, - (u32 *)&addr); - return addr & 0xfffffffe; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen(unsigned int base) -{ -} - -/* - * Returns SM107 framebuffer address - */ -unsigned int board_video_get_fb(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - printf("board_video_get_fb(): FAILED\n"); - - return 0; -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs(void) -{ - return init_regs_800x480; -} - -int board_get_width(void) -{ - return 800; -} - -int board_get_height(void) -{ - return 480; -} -#endif diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore deleted file mode 100644 index 469f1bc..0000000 --- a/board/matrix_vision/mvblm7/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvblm7/Kconfig b/board/matrix_vision/mvblm7/Kconfig deleted file mode 100644 index ea7a6f8..0000000 --- a/board/matrix_vision/mvblm7/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBLM7 - -config SYS_BOARD - default "mvblm7" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBLM7" - -endif diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS deleted file mode 100644 index 947a14e..0000000 --- a/board/matrix_vision/mvblm7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLM7 BOARD -#M: Andre Schwarz <andre.schwarz@matrix-vision.de> -S: Orphan (since 2014-03) -F: board/matrix_vision/mvblm7/ -F: include/configs/MVBLM7.h -F: configs/MVBLM7_defconfig diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile deleted file mode 100644 index caa6cfd..0000000 --- a/board/matrix_vision/mvblm7/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvblm7.o pci.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 deleted file mode 100644 index a0686f7..0000000 --- a/board/matrix_vision/mvblm7/README.mvblm7 +++ /dev/null @@ -1,84 +0,0 @@ -Matrix Vision mvBlueLYNX-M7 (mvBL-M7) -------------------------------------- - -1. Board Description - - The mvBL-M7 is a 120x120mm single board computing platform - with strong focus on stereo image processing applications. - - Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) - on any port (requires add-on board). - -2 System Components - -2.1 CPU - Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. - 512MByte DDR-II memory @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 SD-Card slot connected to SPI. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 PCI - A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. - -2.3 FPGA - Altera Cyclone-II EP2C20/35 with PCI DMA engines. - Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. - Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. - -2.3.1 I/O @ FPGA - 2x8 Outputs : Infineon High-Side Switches to Main Supply. - 2x8 Inputs : Programmable input threshold + trigger capabilities - 2 dedicated flash interfaces for illuminator boards. - Cross trigger for chaining several boards. - -2.4 I2C - Bus1: - MAX5381 DAC @ 0x60 for 1st digital input threshold. - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave addresses depend on sensor) - Bus2: - MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0xFFF00100, i.e. "HIGHBOOT". - - FF800000 environment - FF802000 redundant environment - FF804000 u-boot script image - FF806000 redundant u-boot script image - FF808000 device tree blob - FF80A000 redundant device tree blob - FF80C000 tbd. - FF80E000 tbd. - FF810000 kernel - FFC00000 root FS - FFF00000 u-boot - FFF80000 FPGA raw bit file - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF804000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript deleted file mode 100644 index dc385fd..0000000 --- a/board/matrix_vision/mvblm7/bootscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c deleted file mode 100644 index c0c5bed..0000000 --- a/board/matrix_vision/mvblm7/fpga.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ACEX1K.h> -#include <command.h> -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h deleted file mode 100644 index b480c09..0000000 --- a/board/matrix_vision/mvblm7/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c deleted file mode 100644 index f3c16a3..0000000 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <asm/mpc8349_pci.h> -#include <pci.h> -#include <spi.h> -#include <asm/mmu.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif - -#include "../common/mv_common.h" -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - char *s = getenv("ddr_size"); - - msize = CONFIG_SYS_DDR_SIZE; - if (s) { - u32 env_ddr_size = simple_strtoul(s, NULL, 10); - if (env_ddr_size == 512) - msize = 512; - } - - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - asm("sync;isync"); - udelay(600); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - asm("sync;isync"); - udelay(500); - - return msize; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - mv_reset_environment(); - } - - return 0; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h deleted file mode 100644 index de9fec7..0000000 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c deleted file mode 100644 index f14837a..0000000 --- a/board/matrix_vision/mvblm7/pci.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif -#include <pci.h> -#include <mpc83xx.h> -#include <fpga.h> -#include "mvblm7.h" -#include "fpga.h" -#include "../common/mv_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - int i; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - gpio->dir = MV_GPIO_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - mv_load_fpga(); - - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} |