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-rw-r--r--board/amcc/kilauea/init.S227
-rw-r--r--board/amcc/kilauea/memory.c5
-rw-r--r--board/amcc/makalu/Makefile2
-rw-r--r--board/amcc/makalu/init.S125
-rw-r--r--board/amcc/makalu/makalu.c5
-rw-r--r--board/amcc/makalu/memory.c188
6 files changed, 135 insertions, 417 deletions
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
index 8cd534c..bf47d6b 100644
--- a/board/amcc/kilauea/init.S
+++ b/board/amcc/kilauea/init.S
@@ -1,8 +1,11 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * Based on code provided from UDTech and AMCC
+ * Originally based on code provided from UDTech and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,125 +33,135 @@
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
- addi r4,0,reg ; \
- mtdcr memcfga,r4 ; \
- addis r4,0,value@h ; \
- ori r4,r4,value@l ; \
- mtdcr memcfgd,r4 ;
+ addi r4,0,reg ; \
+ mtdcr memcfga,r4 ; \
+ addis r4,0,value@h ; \
+ ori r4,r4,value@l ; \
+ mtdcr memcfgd,r4 ;
+
+#if defined(CONFIG_DDR_ECC)
+ .extern ecc_init
+#endif /* defined(CONFIG_DDR_ECC) */
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
+#if !defined(CFG_INIT_DCACHE_CS)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/*
- * DDR2 setup
+ * DDR2 SDRAM Controller Setup
*/
- /* Following the DDR Core Manual, here is the initialization */
-
- /* Step 1 */
-
- /* Step 2 */
-
- /* Step 3 */
-
- /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
- mtsdram_as(SDRAM_MB0CF, 0x00006701);
-
- /* SET SDRAM_MB1CF - Not enabled */
- mtsdram_as(SDRAM_MB1CF, 0x00000000);
-
- /* SET SDRAM_MB2CF - Not enabled */
- mtsdram_as(SDRAM_MB2CF, 0x00000000);
-
- /* SET SDRAM_MB3CF - Not enabled */
- mtsdram_as(SDRAM_MB3CF, 0x00000000);
-
- /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
- mtsdram_as(SDRAM_CLKTR, 0x80000000);
-
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtsdram_as(SDRAM_RTR, 0x06180000);
+ /* Set Memory Bank Configuration Registers */
+ mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
+ mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
+ mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
+ mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+
+ /* Set Memory Clock Timing Register */
+ mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+
+ /* Set Refresh Time Register */
+ mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
+
+ /* Set SDRAM Timing Registers */
+ mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
+ mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
+ mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+
+ /* Set Mode and Extended Mode Registers */
+ mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
+ mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+
+ /* Set Memory Controller Options 1 Register */
+ mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+
+ /* Set Manual Initialization Control Registers */
+ mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
+ mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
+ mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
+ mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
+ mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
+ mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
+ mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
+ mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
+ mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
+ mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
+ mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
+ mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
+ mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
+ mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
+ mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
+ mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+
+ /* Set On-Die Termination Registers */
+ mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
+ mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
+ mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+
+ /* Set Write Timing Register */
+ mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
- /* SDRAM_SDTR1 */
- mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
- /* SDRAM_SDTR2 */
- mtsdram_as(SDRAM_SDTR2, 0x32204232);
+ /*
+ * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
+ * SDRAM0_MCOPT2[IPTR] = 1
+ */
+ mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \
+ SDRAM_MCOPT2_IPTR_EXECUTE);
- /* SDRAM_SDTR3 */
- mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
+ /*
+ * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+ * completion of initialization.
+ *
+ * do {
+ * mfsdram(SDRAM_MCSTAT, val);
+ * } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
+ */
+ li r4,SDRAM_MCSTAT
+ lis r2,SDRAM_MCSTAT_MIC_COMP@h
+ ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l
+0: mtdcr memcfga,r4
+ mfdcr r3,memcfgd
+ clrrwi r3,r3,31
+ cmpw cr7,r3,r2
+ bne+ cr7,0b
+
+ /* Set Delay Control Registers */
+ mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+ mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
+ mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
+ mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
- mtsdram_as(SDRAM_MMODE, 0x00000442);
- mtsdram_as(SDRAM_MEMODE, 0x00000404);
+ /*
+ * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+ *
+ * mcopt2 = mfsdram(SDRAM_MCOPT2);
+ */
+ li r4,SDRAM_MCOPT2
+ mtdcr memcfga,r4
+ mfdcr r3,memcfgd
- /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
- mtsdram_as(SDRAM_MCOPT1, 0x04322000);
+ /*
+ * mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
+ */
+ mtdcr memcfga,r4
+ oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h
+ ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l
+ mtdcr memcfgd,r3
- /* NOP */
- mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR1, 0x81900400);
- /* EMR2 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR2, 0x81020000);
- /* EMR3 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR3, 0x81030000);
- /* EMR DLL ENABLE twr = 2tck */
- mtsdram_as(SDRAM_INITPLR4, 0x81010404);
- /* MR w/ DLL reset
- * Note: 5 is CL. May need to be changed
+#if defined(CONFIG_DDR_ECC)
+ /*
+ * ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
*/
- mtsdram_as(SDRAM_INITPLR5, 0x81000542);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR6, 0x81900400);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
- /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
- mtsdram_as(SDRAM_INITPLR11, 0x81000442);
- mtsdram_as(SDRAM_INITPLR12, 0x81010780);
- mtsdram_as(SDRAM_INITPLR13, 0x81010400);
- mtsdram_as(SDRAM_INITPLR14, 0x00000000);
- mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
- /* SET MCIF0_CODT Die Termination On */
- mtsdram_as(SDRAM_CODT, 0x0080f837);
- mtsdram_as(SDRAM_MODT0, 0x01800000);
- mtsdram_as(SDRAM_MODT1, 0x00000000);
-
- mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
- /* SDRAM0_MCOPT2 (0X21) Start initialization */
- mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
- /* Step 5 */
- lis r3,0x1 /* 400000 = wait 100ms */
- mtctr r3
-
-pll_wait:
- bdnz pll_wait
-
- /* Step 6 */
-
- /* SDRAM_DLCR */
- mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
- /* SDRAM_RDCC */
- mtsdram_as(SDRAM_RDCC, 0x40000000);
-
- /* SDRAM_RQDC */
- mtsdram_as(SDRAM_RQDC, 0x80000038);
-
- /* SDRAM_RFDC */
- mtsdram_as(SDRAM_RFDC, 0x00000209);
-
- /* Enable memory controller */
- mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+ mflr r13
+ lis r3,CFG_SDRAM_BASE@h
+ ori r3,r3,CFG_SDRAM_BASE@l
+ lis r4,(CFG_MBYTES_SDRAM << 20)@h
+ ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l
+ bl ecc_init
+ mtlr r13
+#endif /* defined(CONFIG_DDR_ECC) */
+#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+#endif /* !defined(CFG_INIT_DCACHE_CS) */
blr
diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c
index 1d7a3fa..b7e2344 100644
--- a/board/amcc/kilauea/memory.c
+++ b/board/amcc/kilauea/memory.c
@@ -1,4 +1,7 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@@ -30,10 +33,12 @@ void sdram_init(void)
return;
}
+#if defined(CONFIG_NAND_U_BOOT)
long int initdram(int board_type)
{
return (CFG_MBYTES_SDRAM << 20);
}
+#endif /* defined(CONFIG_NAND_U_BOOT) */
#if defined(CFG_DRAM_TEST)
int testdram (void)
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
index 39328c2..4def0d4 100644
--- a/board/amcc/makalu/Makefile
+++ b/board/amcc/makalu/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cmd_pll.o memory.o
+COBJS = $(BOARD).o cmd_pll.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
index 11c5b19..4d0f460 100644
--- a/board/amcc/makalu/init.S
+++ b/board/amcc/makalu/init.S
@@ -1,8 +1,11 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * Based on code provided from Senao and AMCC
+ * Originally based on code provided from Senao and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,126 +26,6 @@
* MA 02111-1307 USA
*/
-#include <config.h>
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#define mtsdram_as(reg, value) \
- addi r4,0,reg ; \
- mtdcr memcfga,r4 ; \
- addis r4,0,value@h ; \
- ori r4,r4,value@l ; \
- mtdcr memcfgd,r4 ;
-
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
-
- /*
- * DDR2 setup
- */
-
- /* Following the DDR Core Manual, here is the initialization */
-
- /* Step 1 */
-
- /* Step 2 */
-
- /* Step 3 */
-
- /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
- mtsdram_as(SDRAM_MB0CF, 0x00005201);
-
- /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
- mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
-
- /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
- mtsdram_as(SDRAM_CLKTR,0x80000000);
-
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtsdram_as(SDRAM_RTR, 0x06180000);
-
- /* SDRAM_SDTR1 */
- mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
- /* SDRAM_SDTR2 */
- mtsdram_as(SDRAM_SDTR2, 0x32204232);
-
- /* SDRAM_SDTR3 */
- mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
-
- mtsdram_as(SDRAM_MMODE, 0x00000442);
- mtsdram_as(SDRAM_MEMODE, 0x00000404);
-
- /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
- mtsdram_as(SDRAM_MCOPT1, 0x04322000);
-
- /* NOP */
- mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR1, 0x81900400);
- /* EMR2 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR2, 0x81020000);
- /* EMR3 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR3, 0x81030000);
- /* EMR DLL ENABLE twr = 2tck */
- mtsdram_as(SDRAM_INITPLR4, 0x81010404);
- /* MR w/ DLL reset
- * Note: 5 is CL. May need to be changed
- */
- mtsdram_as(SDRAM_INITPLR5, 0x81000542);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR6, 0x81900400);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
- /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
- mtsdram_as(SDRAM_INITPLR11, 0x81000442);
- mtsdram_as(SDRAM_INITPLR12, 0x81010780);
- mtsdram_as(SDRAM_INITPLR13, 0x81010400);
- mtsdram_as(SDRAM_INITPLR14, 0x00000000);
- mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
- /* SET MCIF0_CODT Die Termination On */
- mtsdram_as(SDRAM_CODT, 0x0080f837);
- mtsdram_as(SDRAM_MODT0, 0x01800000);
-#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
- mtsdram_as(SDRAM_MODT1, 0x00000000);
-#endif
-
- mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
- /* SDRAM0_MCOPT2 (0X21) Start initialization */
- mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
- /* Step 5 */
- lis r3,0x1 /* 400000 = wait 100ms */
- mtctr r3
-
-pll_wait:
- bdnz pll_wait
-
- /* Step 6 */
-
- /* SDRAM_DLCR */
- mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
- /* SDRAM_RDCC */
- mtsdram_as(SDRAM_RDCC, 0x40000000);
-
- /* SDRAM_RQDC */
- mtsdram_as(SDRAM_RQDC, 0x80000038);
-
- /* SDRAM_RFDC */
- mtsdram_as(SDRAM_RFDC, 0x00000209);
-
- /* Enable memory controller */
- mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-
blr
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9baec9a..adf604f 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -351,3 +351,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+void sdram_init(void)
+{
+ return;
+}
diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c
deleted file mode 100644
index b03b60b..0000000
--- a/board/amcc/makalu/memory.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-void sdram_init(void)
-{
- return;
-}
-
-long int initdram(int board_type)
-{
- /*
- * Same as on Kilauea, Makalu generates exception 0x200
- * (machine check) after trap_init() in board_init_f,
- * when SDRAM is initialized here (late) and d-cache is
- * used earlier as INIT_RAM.
- * So for now, initialize DDR2 in init.S very early and
- * also use it for INIT_RAM. Then this exception doesn't
- * occur.
- */
-#if 0
- u32 val;
-
- /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
- mtsdram(SDRAM_MB0CF, 0x00005201);
-
- /* SET SDRAM_MB1CF - Not enabled */
- mtsdram(SDRAM_MB1CF, 0x00000000);
-
- /* SET SDRAM_MB2CF - Not enabled */
- mtsdram(SDRAM_MB2CF, 0x00000000);
-
- /* SET SDRAM_MB3CF - Not enabled */
- mtsdram(SDRAM_MB3CF, 0x00000000);
-
- /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
- mtsdram(SDRAM_CLKTR, 0x80000000);
-
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtsdram(SDRAM_RTR, 0x06180000);
-
- /* SDRAM_SDTR1 */
- mtsdram(SDRAM_SDTR1, 0x80201000);
-
- /* SDRAM_SDTR2 */
- mtsdram(SDRAM_SDTR2, 0x32204232);
-
- /* SDRAM_SDTR3 */
- mtsdram(SDRAM_SDTR3, 0x080b0d1a);
-
- mtsdram(SDRAM_MMODE, 0x00000442);
- mtsdram(SDRAM_MEMODE, 0x00000404);
-
- /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
- mtsdram(SDRAM_MCOPT1, 0x04322000);
-
- /* NOP */
- mtsdram(SDRAM_INITPLR0, 0xa8380000);
- /* precharge 3 DDR clock cycle */
- mtsdram(SDRAM_INITPLR1, 0x81900400);
- /* EMR2 twr = 2tck */
- mtsdram(SDRAM_INITPLR2, 0x81020000);
- /* EMR3 twr = 2tck */
- mtsdram(SDRAM_INITPLR3, 0x81030000);
- /* EMR DLL ENABLE twr = 2tck */
- mtsdram(SDRAM_INITPLR4, 0x81010404);
- /* MR w/ DLL reset
- * Note: 5 is CL. May need to be changed
- */
- mtsdram(SDRAM_INITPLR5, 0x81000542);
- /* precharge 3 DDR clock cycle */
- mtsdram(SDRAM_INITPLR6, 0x81900400);
- /* Auto-refresh trfc = 26tck */
- mtsdram(SDRAM_INITPLR7, 0x8D080000);
- /* Auto-refresh trfc = 26tck */
- mtsdram(SDRAM_INITPLR8, 0x8D080000);
- /* Auto-refresh */
- mtsdram(SDRAM_INITPLR9, 0x8D080000);
- /* Auto-refresh */
- mtsdram(SDRAM_INITPLR10, 0x8D080000);
- /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
- mtsdram(SDRAM_INITPLR11, 0x81000442);
- mtsdram(SDRAM_INITPLR12, 0x81010780);
- mtsdram(SDRAM_INITPLR13, 0x81010400);
- mtsdram(SDRAM_INITPLR14, 0x00000000);
- mtsdram(SDRAM_INITPLR15, 0x00000000);
-
- /* SET MCIF0_CODT Die Termination On */
- mtsdram(SDRAM_CODT, 0x0080f837);
- mtsdram(SDRAM_MODT0, 0x01800000);
- mtsdram(SDRAM_MODT1, 0x00000000);
-
- mtsdram(SDRAM_WRDTR, 0x00000000);
-
- /* SDRAM0_MCOPT2 (0X21) Start initialization */
- mtsdram(SDRAM_MCOPT2, 0x20000000);
-
- /* Step 5 */
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
-
- /* Step 6 */
-
- /* SDRAM_DLCR */
- mtsdram(SDRAM_DLCR, 0x030000a5);
-
- /* SDRAM_RDCC */
- mtsdram(SDRAM_RDCC, 0x40000000);
-
- /* SDRAM_RQDC */
- mtsdram(SDRAM_RQDC, 0x80000038);
-
- /* SDRAM_RFDC */
- mtsdram(SDRAM_RFDC, 0x00000209);
-
- /* Enable memory controller */
- mfsdram(SDRAM_MCOPT2, val);
- val |= SDRAM_MCOPT2_DCEN_ENABLE;
- mtsdram(SDRAM_MCOPT2, val);
-#endif
- return (CFG_MBYTES_SDRAM << 20);
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- printf ("testdram\n");
-#if defined (CONFIG_NAND_U_BOOT)
- return 0;
-#endif
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) 0x00001000;
- uint *p;
-
- for (p = pstart; p < pend; p++) {
- *p = 0xaaaaaaaa;
- }
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
-#if !defined (CONFIG_NAND_SPL)
- printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++) {
- *p = 0x55555555;
- }
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
-#if !defined (CONFIG_NAND_SPL)
- printf ("SDRAM test fails at: %08x\n", (uint) p);
-#endif
- return 1;
- }
- }
-#if !defined (CONFIG_NAND_SPL)
- printf ("SDRAM test passed!!!\n");
-#endif
- return 0;
-}
-#endif