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-rw-r--r--board/davedenx/qong/Makefile53
-rw-r--r--board/davedenx/qong/config.mk1
-rw-r--r--board/davedenx/qong/lowlevel_init.S172
-rw-r--r--board/davedenx/qong/qong.c168
-rw-r--r--board/davedenx/qong/qong_fpga.h41
-rw-r--r--board/davedenx/qong/u-boot.lds58
-rw-r--r--board/emk/common/flash.c4
-rw-r--r--board/esd/pmc405/config.mk6
-rw-r--r--board/esd/pmc405/pmc405.c121
-rw-r--r--board/evb64260/flash.c3
-rw-r--r--board/tqc/tqm8xx/u-boot.lds1
11 files changed, 536 insertions, 92 deletions
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
new file mode 100644
index 0000000..93e1985
--- /dev/null
+++ b/board/davedenx/qong/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009
+# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := qong.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davedenx/qong/config.mk b/board/davedenx/qong/config.mk
new file mode 100644
index 0000000..d8d0a57
--- /dev/null
+++ b/board/davedenx/qong/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x8ff00000
diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S
new file mode 100644
index 0000000..198dd76
--- /dev/null
+++ b/board/davedenx/qong/lowlevel_init.S
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * Based on board/freescale/mx31ads/lowlevel_init.S
+ * by Guennadi Liakhovetski.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ init_drive_strength
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ /* Switch on Display Interface */
+ REG IPU_CONF, IPU_CONF_DI_EN
+ /* Clock Control Module: */
+ REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
+ /* Switch to MCU PLL */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ /* 399-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871650
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldr r1, MPCTL_PARAM_399
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldr r1, UPCTL_PARAM_240
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x00000208
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, ((3 << 21) | /* tXP */ \
+ (0 << 20) | /* tWTR */ \
+ (2 << 18) | /* tRP */ \
+ (1 << 16) | /* tMRD */ \
+ (0 << 15) | /* tWR */ \
+ (5 << 12) | /* tRAS */ \
+ (1 << 10) | /* tRRD */ \
+ (3 << 8) | /* tCAS */ \
+ (2 << 4) | /* tRCD */ \
+ (7 << 0) /* tRC */ )
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, ((1 << 31) | \
+ (0 << 28) | \
+ (0 << 27) | \
+ (3 << 24) | /* 14 rows */ \
+ (2 << 20) | /* 10 cols */ \
+ (2 << 16) | \
+ (4 << 13) | /* 3.91us (64ms/16384) */ \
+ (0 << 10) | \
+ (0 << 8) | \
+ (1 << 7) | \
+ (0 << 0))
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
+
+MPCTL_PARAM_399:
+ .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
+UPCTL_PARAM_240:
+ .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
new file mode 100644
index 0000000..13b3699
--- /dev/null
+++ b/board/davedenx/qong/qong.c
@@ -0,0 +1,168 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+int board_init (void)
+{
+ /* Chip selects */
+ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
+ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
+ __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
+ (0 << 30) | /* WP */
+ (0 << 28) | /* BCD */
+ (0 << 24) | /* BCS */
+ (0 << 22) | /* PSZ */
+ (0 << 21) | /* PME */
+ (0 << 20) | /* SYNC */
+ (0 << 16) | /* DOL */
+ (3 << 14) | /* CNC */
+ (21 << 8) | /* WSC */
+ (0 << 7) | /* EW */
+ (0 << 4) | /* WWS */
+ (6 << 0) /* EDC */
+ );
+
+ __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
+ (1 << 24) | /* OEN */
+ (3 << 20) | /* EBWA */
+ (3 << 16) | /* EBWN */
+ (1 << 12) | /* CSA */
+ (1 << 11) | /* EBC */
+ (5 << 8) | /* DSZ */
+ (1 << 4) | /* CSN */
+ (0 << 3) | /* PSR */
+ (0 << 2) | /* CRE */
+ (0 << 1) | /* WRAP */
+ (1 << 0) /* CSEN */
+ );
+
+ __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
+ (1 << 24) | /* EBRN */
+ (2 << 20) | /* RWA */
+ (2 << 16) | /* RWN */
+ (0 << 15) | /* MUM */
+ (0 << 13) | /* LAH */
+ (2 << 10) | /* LBN */
+ (0 << 8) | /* LBA */
+ (0 << 6) | /* DWW */
+ (0 << 4) | /* DCT */
+ (0 << 3) | /* WWU */
+ (0 << 2) | /* AGE */
+ (0 << 1) | /* CNC2 */
+ (0 << 0) /* FCE */
+ );
+
+#ifdef CONFIG_QONG_FPGA
+ /* CS1: FPGA/Network Controller/GPIO */
+ /* 16-bit, no DTACK */
+ __REG(CSCR_U(1)) = 0x00000A01;
+ __REG(CSCR_L(1)) = 0x20040501;
+ __REG(CSCR_A(1)) = 0x04020C00;
+
+ /* setup pins for FPGA */
+ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+#endif
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_QONG;
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf("Board: DAVE/DENX QongEVB-LITE\n");
+ return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_QONG_FPGA
+ u32 tmp;
+
+ /* FPGA reset */
+ /* rstn = 0 */
+ tmp = __REG(GPIO2_BASE + GPIO_DR);
+ tmp &= (~(1 << QONG_FPGA_RST_PIN));
+ __REG(GPIO2_BASE + GPIO_DR) = tmp;
+ /* set the GPIO as output */
+ tmp = __REG(GPIO2_BASE + GPIO_GDIR);
+ tmp |= (1 << QONG_FPGA_RST_PIN);
+ __REG(GPIO2_BASE + GPIO_GDIR) = tmp;
+ /* wait */
+ udelay(30);
+ /* rstn = 1 */
+ tmp = __REG(GPIO2_BASE + GPIO_DR);
+ tmp |= (1 << QONG_FPGA_RST_PIN);
+ __REG(GPIO2_BASE + GPIO_DR) = tmp;
+ /* set interrupt pin as input */
+ __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
+ /* wait while the FPGA starts */
+ udelay(300);
+
+ tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
+ printf("FPGA: ");
+ printf("version register = %u.%u.%u\n",
+ (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
+#endif
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
+ return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
+#else
+ return 0;
+#endif
+}
+
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
new file mode 100644
index 0000000..b1cb08a
--- /dev/null
+++ b/board/davedenx/qong/qong_fpga.h
@@ -0,0 +1,41 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef QONG_FPGA_H
+#define QONG_FPGA_H
+
+#ifdef CONFIG_QONG_FPGA
+#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
+#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
+#define QONG_FPGA_PERIPH_SIZE (1 << 24)
+
+#define QONG_FPGA_TCK_PIN 26
+#define QONG_FPGA_TMS_PIN 25
+#define QONG_FPGA_TDI_PIN 8
+#define QONG_FPGA_TDO_PIN 7
+#define QONG_FPGA_RST_PIN 16
+#define QONG_FPGA_IRQ_PIN 8
+#endif
+
+#endif /* QONG_FPGA_H */
+
diff --git a/board/davedenx/qong/u-boot.lds b/board/davedenx/qong/u-boot.lds
new file mode 100644
index 0000000..04e0642
--- /dev/null
+++ b/board/davedenx/qong/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c
index 330978b..8579cfa 100644
--- a/board/emk/common/flash.c
+++ b/board/emk/common/flash.c
@@ -82,7 +82,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
+flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
@@ -142,7 +142,7 @@ static void flash_reset(flash_info_t *info)
/*-----------------------------------------------------------------------
*/
-static flash_info_t *flash_get_info(ulong base)
+flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk
index fc2794d..5a3fc4b 100644
--- a/board/esd/pmc405/config.mk
+++ b/board/esd/pmc405/config.mk
@@ -21,8 +21,4 @@
# MA 02111-1307 USA
#
-#
-# esd PMC405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
+TEXT_BASE = 0xFFF80000
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 975b6d6..94caa6c 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -2,7 +2,7 @@
* (C) Copyright 2001-2003
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2009
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@@ -40,7 +41,6 @@ const unsigned char fpgadata[] =
};
int filesize = sizeof(fpgadata);
-
int board_early_init_f (void)
{
/*
@@ -55,107 +55,104 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ * EBC Configuration Register:
+ * set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000);
/*
* Setup GPIO pins
*/
-
- mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
- CONFIG_SYS_FPGA_DONE | \
- CONFIG_SYS_XEREADY | \
- CONFIG_SYS_NONMONARCH | \
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT |
+ CONFIG_SYS_FPGA_DONE |
+ CONFIG_SYS_XEREADY |
+ CONFIG_SYS_NONMONARCH |
CONFIG_SYS_REV1_2) << 5));
- if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+ if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
/* rev 1.2 boards */
- mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE |
CONFIG_SYS_SELF_RST) << 5));
}
- out32(GPIO0_OR, 0);
- out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
+ /* setup for output */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
+ CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
- /* - check if rev1_2 is low, then:
- * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
+ /*
+ * - check if rev1_2 is low, then:
+ * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
+ * in TCR to assert INTA# or SELFRST#
*/
-
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
+ /* deassert EREADY# */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
return (0);
}
ushort pmc405_pci_subsys_deviceid(void)
{
ulong val;
- val = in32(GPIO0_IR);
+
+ val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
- if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+ /* check monarch# signal */
+ if (val & CONFIG_SYS_NONMONARCH)
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
- }
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
}
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
/*
- * Check Board Identity:
+ * Check Board Identity
*/
int checkboard (void)
{
ulong val;
-
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_r("serial#", str, sizeof(str));
puts ("Board: ");
- if (i == -1) {
+ if (i == -1)
puts ("### No HW ID - assuming PMC405");
- } else {
+ else
puts(str);
- }
- val = in32(GPIO0_IR);
+ val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
puts(" rev1.2 (");
- if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+ if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
puts("non-");
- }
puts("monarch)");
- } else {
+ } else
puts(" <=rev1.1");
- }
putc ('\n');
return 0;
}
-/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
@@ -166,43 +163,3 @@ void reset_phy(void)
lxt971_no_sleep();
#endif
}
-
-
-int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- ulong addr;
- volatile uchar *ptr;
- volatile uchar val;
- int i;
-
- addr = simple_strtol (argv[1], NULL, 16) + 0x16;
-
- i = 0;
- for (;;) {
- ptr = (uchar *)addr;
- for (i=0; i<8; i++) {
- *ptr = i;
- val = *ptr;
-
- if (val != i) {
- printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
- return 0;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- ptr++;
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- cantest, 3, 1, do_cantest,
- "Test CAN controller",
- NULL
- );
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
index 115e8cd..825bbaf 100644
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -54,7 +54,6 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
*/
@@ -178,7 +177,7 @@ flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
-static flash_info_t *flash_get_info(ulong base)
+flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index 5af36c9..5c9b26c 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -63,7 +63,6 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
generated by cgit v1.1 at 2024-11-08 06:18:22 +0000