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-rw-r--r--board/cm_t35/Makefile47
-rw-r--r--board/cm_t35/cm_t35.c371
-rw-r--r--board/davinci/common/misc.c2
-rw-r--r--board/davinci/dm355evm/dm355evm.c41
-rw-r--r--board/davinci/dm365evm/dm365evm.c49
-rw-r--r--board/davinci/dm6467evm/dm6467evm.c26
-rw-r--r--board/efikamx/Makefile52
-rw-r--r--board/efikamx/config.mk (renamed from board/faraday/a320evb/config.mk)24
-rw-r--r--board/efikamx/efikamx.c689
-rw-r--r--board/efikamx/imximage.cfg122
-rw-r--r--board/faraday/a320evb/a320evb.c3
-rw-r--r--board/freescale/mx35pdk/Makefile49
-rw-r--r--board/freescale/mx35pdk/lowlevel_init.S363
-rw-r--r--board/freescale/mx35pdk/mx35pdk.c297
-rw-r--r--board/freescale/mx35pdk/mx35pdk.h101
-rw-r--r--board/freescale/mx51evk/mx51evk.c17
-rw-r--r--board/freescale/mx53evk/Makefile48
-rw-r--r--board/freescale/mx53evk/config.mk24
-rw-r--r--board/freescale/mx53evk/imximage.cfg112
-rw-r--r--board/freescale/mx53evk/mx53evk.c397
-rw-r--r--board/samsung/universal_c210/Makefile51
-rw-r--r--board/samsung/universal_c210/lowlevel_init.S395
-rw-r--r--board/samsung/universal_c210/onenand.c34
-rw-r--r--board/samsung/universal_c210/universal.c250
24 files changed, 3538 insertions, 26 deletions
diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile
new file mode 100644
index 0000000..862b8dc
--- /dev/null
+++ b/board/cm_t35/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := cm_t35.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
new file mode 100644
index 0000000..459df0b
--- /dev/null
+++ b/board/cm_t35/cm_t35.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2010
+ * CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Derived from omap3evm and Beagle Board by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <net.h>
+#include <i2c.h>
+#include <twl4030.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T35 board",
+ "NAND",
+};
+
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static u32 gpmc_nand_config[GPMC_MAX_REG] = {
+ SMNAND_GPMC_CONFIG1,
+ SMNAND_GPMC_CONFIG2,
+ SMNAND_GPMC_CONFIG3,
+ SMNAND_GPMC_CONFIG4,
+ SMNAND_GPMC_CONFIG5,
+ SMNAND_GPMC_CONFIG6,
+ 0,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
+ CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
+
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init I2C and display die ID
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
+
+ /* CM-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
+
+ /* serial interface */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
+
+ /* mUSB */
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
+
+ /* I2C1 */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
+
+ /* control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: setup_net_chip_gmpc
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip_gmpc(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
+ CM_T35_SMC911X_BASE, GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
+ SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+/*
+ * Routine: reset_net_chip
+ * Description: reset the Ethernet controller via TPS65930 GPIO
+ */
+static void reset_net_chip(void)
+{
+ /* Set GPIO1 of TPS65930 as output */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x03);
+ /* Send a pulse on the GPIO pin */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x0C);
+ udelay(1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x09);
+ udelay(1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x0C);
+}
+#else
+static inline void reset_net_chip(void) {}
+#endif
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int rc;
+
+ rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rc)
+ return 0;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ rc = i2c_read(0x50, 0, 1, enetaddr, 6);
+ if (rc)
+ return rc;
+#endif
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+#ifdef CONFIG_SMC911X
+ setup_net_chip_gmpc();
+ reset_net_chip();
+
+ rc1 = handle_mac_address();
+ if (rc1)
+ printf("CM-T35: No MAC address found\n");
+
+ rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+ if (rc1 > 0)
+ rc++;
+#endif
+
+ return rc;
+}
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index 08c898f..2bfdf23 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -80,7 +80,7 @@ err:
/*
* Set the mii mode as MII or RMII
*/
-#if defined(CONFIG_DRIVER_TI_EMAC)
+#if defined(CONFIG_SOC_DA8XX)
void davinci_emac_mii_mode_sel(int mode_sel)
{
int val;
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
index b9260b8..112851a 100644
--- a/board/davinci/dm355evm/dm355evm.c
+++ b/board/davinci/dm355evm/dm355evm.c
@@ -25,6 +25,10 @@
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -114,3 +118,40 @@ int board_nand_init(struct nand_chip *nand)
}
#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
index bc681f7..5fb7611 100644
--- a/board/davinci/dm365evm/dm365evm.c
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -25,6 +25,10 @@
#include <asm/arch/gpio_defs.h>
#include <netdev.h>
#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -101,3 +105,48 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+#define PUPDCTL1 0x01c4007c
+ /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
+ writel((readl(PINMUX4) | 0x55400000), PINMUX4);
+ writel((readl(PINMUX0) | 0x00010000), PINMUX0);
+
+ /* Configure MMC/SD pins as pullup */
+ writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
+
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
index 994a9aa..1a01c3c 100644
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ b/board/davinci/dm6467evm/dm6467evm.c
@@ -17,6 +17,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
@@ -28,8 +29,33 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
+ lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+ lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+ lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0x80000c0;
+
+ /* Select UART function on UART0 */
+ REG(PINMUX0) &= ~(0x0000003f << 18);
+ REG(PINMUX1) &= ~(0x00000003);
+
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
return 0;
}
+#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
new file mode 100644
index 0000000..ee4a16e
--- /dev/null
+++ b/board/efikamx/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := efikamx.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/faraday/a320evb/config.mk b/board/efikamx/config.mk
index b751d0d..6e90671 100644
--- a/board/faraday/a320evb/config.mk
+++ b/board/efikamx/config.mk
@@ -1,6 +1,8 @@
#
-# (C) Copyright 2009 Faraday Technology
-# Po-Yu Chuang <ratbert@faraday-tech.com>
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -18,18 +20,6 @@
# MA 02111-1307 USA
#
-# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
-#
-# see http://www.faraday-tech.com/ for more information
-
-# A320 has 1 bank of 64 MB DRAM
-#
-# 1000'0000 to 1400'0000
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-#
-# we load ourself to 13f8'0000
-#
-# download area is 1200'0000
-
-CONFIG_SYS_TEXT_BASE = 0x13f80000
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
new file mode 100644
index 0000000..4efbeaf
--- /dev/null
+++ b/board/efikamx/efikamx.c
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Compile-time error checking
+ */
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
+#endif
+
+/*
+ * Shared variables / local defines
+ */
+/* LED */
+#define EFIKAMX_LED_BLUE 0x1
+#define EFIKAMX_LED_GREEN 0x2
+#define EFIKAMX_LED_RED 0x4
+
+void efikamx_toggle_led(uint32_t mask);
+
+/* Board revisions */
+#define EFIKAMX_BOARD_REV_11 0x1
+#define EFIKAMX_BOARD_REV_12 0x2
+#define EFIKAMX_BOARD_REV_13 0x3
+#define EFIKAMX_BOARD_REV_14 0x4
+
+/*
+ * Board identification
+ */
+u32 get_efika_rev(void)
+{
+ u32 rev = 0;
+ /*
+ * Retrieve board ID:
+ * rev1.1: 1,1,1
+ * rev1.2: 1,1,0
+ * rev1.3: 1,0,1
+ * rev1.4: 1,0,0
+ */
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+ MXC_GPIO_DIRECTION_OUT);
+ /* set to 1 in order to get correct value on board rev1.1 */
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
+
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
+
+ mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
+
+ mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
+
+ return (~rev & 0x7) + 1;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev() | (get_efika_rev() << 8);
+}
+
+/*
+ * DRAM initialization
+ */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+/*
+ * UART configuration
+ */
+static void setup_iomux_uart(void)
+{
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+/*
+ * SPI configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+ /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+ /* Configure SS0 as a GPIO */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
+ MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
+
+ /* Configure SS1 as a GPIO */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
+ MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
+
+ /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+#else
+static inline void setup_iomux_spi(void) { }
+#endif
+
+/*
+ * PMIC configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg_read(REG_POWER_MISC);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(REG_POWER_MISC, val);
+
+ /* Externally powered */
+ val = pmic_reg_read(REG_CHARGE);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ val = pmic_reg_read(REG_SW_0);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg_read(REG_SW_1);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg_read(REG_SW_2);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg_read(REG_SW_4);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg_read(REG_SW_5);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+ val = pmic_reg_read(REG_SETTING_0);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ val = pmic_reg_read(REG_SETTING_1);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(REG_MODE_1, val);
+
+ val = pmic_reg_read(REG_POWER_CTL2);
+ val |= WDIRESET;
+ pmic_reg_write(REG_POWER_CTL2, val);
+
+ udelay(2500);
+}
+#else
+static inline void power_init(void) { }
+#endif
+
+/*
+ * MMC configuration
+ */
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC2_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *absent, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
+ else
+ *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
+
+ return 0;
+}
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* SDHC1 is used on all revisions, setup control pins first */
+ mxc_request_iomux(MX51_PIN_GPIO1_0,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_GPIO1_1,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_SRE_FAST);
+
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
+ MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
+ MXC_GPIO_DIRECTION_IN);
+
+ /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
+ if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
+ /* SDHC1 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ /* SDHC2 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD2_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ /* SDHC2 Control lines IOMUX */
+ mxc_request_iomux(MX51_PIN_GPIO1_7,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_GPIO1_8,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_SRE_FAST);
+
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
+ MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
+ MXC_GPIO_DIRECTION_IN);
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ if (!ret)
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+ } else { /* New boards use only SDHC1 */
+ /* SDHC1 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ }
+ return ret;
+}
+#endif
+
+/*
+ * ATA
+ */
+#ifdef CONFIG_MX51_PATA
+#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
+void setup_iomux_ata(void)
+{
+ mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
+}
+#else
+static inline void setup_iomux_ata(void) { }
+#endif
+
+/*
+ * LED configuration
+ */
+void setup_iomux_led(void)
+{
+ /* Blue LED */
+ mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+ MXC_GPIO_DIRECTION_OUT);
+ /* Green LED */
+ mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+ MXC_GPIO_DIRECTION_OUT);
+ /* Red LED */
+ mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+ MXC_GPIO_DIRECTION_OUT);
+}
+
+void efikamx_toggle_led(uint32_t mask)
+{
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+ mask & EFIKAMX_LED_BLUE);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+ mask & EFIKAMX_LED_GREEN);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+ mask & EFIKAMX_LED_RED);
+}
+
+/*
+ * Board initialization
+ */
+static void init_drive_strength(void)
+{
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+ /* Setting pad options */
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+int board_early_init_f(void)
+{
+ init_drive_strength();
+
+ setup_iomux_uart();
+ setup_iomux_spi();
+ setup_iomux_led();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX51_LANGE51;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_iomux_spi();
+
+ power_init();
+
+ setup_iomux_led();
+ setup_iomux_ata();
+
+ efikamx_toggle_led(EFIKAMX_LED_BLUE);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 system_rev = get_cpu_rev();
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ puts("Board: Efika MX ");
+
+ switch (system_rev & 0xff) {
+ case CHIP_REV_3_0:
+ puts("3.0 [");
+ break;
+ case CHIP_REV_2_5:
+ puts("2.5 [");
+ break;
+ case CHIP_REV_2_0:
+ puts("2.0 [");
+ break;
+ case CHIP_REV_1_1:
+ puts("1.1 [");
+ break;
+ case CHIP_REV_1_0:
+ default:
+ puts("1.0 [");
+ break;
+ }
+
+ cause = src_regs->srsr;
+ switch (cause) {
+ case 0x0001:
+ puts("POR");
+ break;
+ case 0x0009:
+ puts("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ puts("WDOG");
+ break;
+ default:
+ printf("unknown 0x%x", cause);
+ }
+ puts("]\n");
+
+ return 0;
+}
diff --git a/board/efikamx/imximage.cfg b/board/efikamx/imximage.cfg
new file mode 100644
index 0000000..6fe0ff9
--- /dev/null
+++ b/board/efikamx/imximage.cfg
@@ -0,0 +1,122 @@
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+BOOT_FROM spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x73fa88a0 0x000
+DATA 4 0x73fa850c 0x20c5
+DATA 4 0x73fa8510 0x20c5
+DATA 4 0x73fa883c 0x5
+DATA 4 0x73fa8848 0x5
+DATA 4 0x73fa84b8 0xe7
+DATA 4 0x73fa84bc 0x45
+DATA 4 0x73fa84c0 0x45
+DATA 4 0x73fa84c4 0x45
+DATA 4 0x73fa84c8 0x45
+DATA 4 0x73fa8820 0x0
+DATA 4 0x73fa84a4 0x5
+DATA 4 0x73fa84a8 0x5
+DATA 4 0x73fa84ac 0xe5
+DATA 4 0x73fa84b0 0xe5
+DATA 4 0x73fa84b4 0xe5
+DATA 4 0x73fa84cc 0xe5
+DATA 4 0x73fa84d0 0xe4
+
+DATA 4 0x73fa882c 0x4
+DATA 4 0x73fa88a4 0x4
+DATA 4 0x73fa88ac 0x4
+DATA 4 0x73fa88b8 0x4
+
+# Setting DDR for micron
+# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+# CAS=3 BL=4
+# ESDCTL_ESDCTL0
+DATA 4 0x83fd9000 0x82a20000
+# ESDCTL_ESDCTL1
+DATA 4 0x83fd9008 0x82a20000
+# ESDCTL_ESDMISC
+DATA 4 0x83fd9010 0xcaaaf6d0
+# ESDCTL_ESDCFG0
+DATA 4 0x83fd9004 0x3f3574aa
+# ESDCTL_ESDCFG1
+DATA 4 0x83fd900c 0x3f3574aa
+
+# Init DRAM on CS0
+# ESDCTL_ESDSCR
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x0000801a
+DATA 4 0x83fd9014 0x0000801b
+DATA 4 0x83fd9014 0x00448019
+DATA 4 0x83fd9014 0x07328018
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x06328018
+DATA 4 0x83fd9014 0x03808019
+DATA 4 0x83fd9014 0x00408019
+DATA 4 0x83fd9014 0x00008000
+
+# Init DRAM on CS1
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x0000801e
+DATA 4 0x83fd9014 0x0000801f
+DATA 4 0x83fd9014 0x0000801d
+DATA 4 0x83fd9014 0x0732801c
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x0632801c
+DATA 4 0x83fd9014 0x0380801d
+DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x00008004
+
+# Write to CTL0
+DATA 4 0x83fd9000 0xb2a20000
+# Write to CTL1
+DATA 4 0x83fd9008 0xb2a20000
+# ESDMISC
+DATA 4 0x83fd9010 0x000ad6d0
+#ESDCTL_ESDCDLYGD
+DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9014 0x00000000
diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c
index 85b11b9..b9343e4 100644
--- a/board/faraday/a320evb/a320evb.c
+++ b/board/faraday/a320evb/a320evb.c
@@ -46,8 +46,7 @@ int dram_init(void)
actual_size = get_ram_size((void *)sdram_base, expected_size);
- gd->bd->bi_dram[0].start = sdram_base;
- gd->bd->bi_dram[0].size = actual_size;
+ gd->ram_size = actual_size;
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile
new file mode 100644
index 0000000..b4a60d6
--- /dev/null
+++ b/board/freescale/mx35pdk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx35pdk.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S
new file mode 100644
index 0000000..9b0f1b5
--- /dev/null
+++ b/board/freescale/mx35pdk/lowlevel_init.S
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+#include "mx35pdk.h"
+
+/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+ ldr \tmp, =IIM_BASE_ADDR
+ ldr \ret, [\tmp, #IIM_SREV]
+ cmp \ret, #0x00
+ moveq \tmp, #ROMPATCH_REV
+ ldreq \ret, [\tmp]
+ moveq \ret, \ret, lsl #4
+ addne \ret, \ret, #0x10
+.endm
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_MPR_CONFIG
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_OPACR_CONFIG
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =MAX_BASE_ADDR
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =MAX_MPR_CONFIG
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =MAX_SGPCR_CONFIG
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =MAX_MGPCR_CONFIG
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =M3IF_BASE_ADDR
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =M3IF_CONFIG
+ str r0, [r1] /* M3IF control reg */
+.endm
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+ ldr r0, =DBG_BASE_ADDR
+ ldr r1, =DBG_CSCR_U_CONFIG
+ str r1, [r0, #0x00]
+ ldr r1, =DBG_CSCR_L_CONFIG
+ str r1, [r0, #0x04]
+ ldr r1, =DBG_CSCR_A_CONFIG
+ str r1, [r0, #0x08]
+.endm
+
+/* clock setup */
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+
+ /* default CLKO to 1/32 of the ARM core*/
+ ldr r1, [r0, #CLKCTL_COSR]
+ bic r1, r1, #0x00000FF00
+ bic r1, r1, #0x0000000FF
+ mov r2, #0x00006C00
+ add r2, r2, #0x67
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_COSR]
+
+ ldr r2, =CCM_CCMR_CONFIG
+ str r2, [r0, #CLKCTL_CCMR]
+
+ check_soc_version r1, r2
+ cmp r1, #CHIP_REV_2_0
+ ldrhs r3, =CCM_MPLL_532_HZ
+ bhs 1f
+ ldr r2, [r0, #CLKCTL_PDR0]
+ tst r2, #CLKMODE_CONSUMER
+ ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
+ ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
+1:
+ str r3, [r0, #CLKCTL_MPCTL]
+
+ ldr r1, =CCM_PPLL_300_HZ
+ str r1, [r0, #CLKCTL_PPCTL]
+
+ ldr r1, =CCM_PDR0_CONFIG
+ bic r1, r1, #0x800000
+ str r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, [r0, #CLKCTL_CGR0]
+ orr r1, r1, #0x0C300000
+ str r1, [r0, #CLKCTL_CGR0]
+
+ ldr r1, [r0, #CLKCTL_CGR1]
+ orr r1, r1, #0x00000C00
+ orr r1, r1, #0x00000003
+ str r1, [r0, #CLKCTL_CGR1]
+.endm
+
+.macro setup_sdram
+ ldr r0, =ESDCTL_BASE_ADDR
+ mov r3, #0x2000
+ str r3, [r0, #0x0]
+ str r3, [r0, #0x8]
+
+ /*ip(r12) has used to save lr register in upper calling*/
+ mov fp, lr
+
+ mov r5, #0x00
+ mov r2, #0x00
+ mov r1, #CSD0_BASE_ADDR
+ bl setup_sdram_bank
+ cmp r3, #0x0
+ orreq r5, r5, #1
+ eorne r2, r2, #0x1
+ blne setup_sdram_bank
+
+ mov lr, fp
+
+1:
+ ldr r3, =ESDCTL_DELAY_LINE5
+ str r3, [r0, #0x30]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r10, lr
+
+ mrc 15, 0, r1, c1, c0, 0
+
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+
+ /* Set unaligned access enable */
+ orr r1, r1, #(1<<22)
+
+ /* Set low int latency enable */
+ orr r1, r1, #(1<<21)
+
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+
+ /* Set branch prediction enable */
+ mcr 15, 0, r0, c15, c2, 4
+
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /*
+ * initializes very early AIPS
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF
+ * Also setup the Peripheral Port Remap register inside the core
+ */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_clock
+ init_debug_board
+
+ cmp pc, #PHYS_SDRAM_1
+ blo init_sdram_start
+ cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+ blo skip_sdram_setup
+
+init_sdram_start:
+ /*init_sdram*/
+ setup_sdram
+
+skip_sdram_setup:
+ mov lr, r10
+ mov pc, lr
+
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_bank:
+ mov r3, #0xE
+ tst r2, #0x1
+ orreq r3, r3, #0x300 /*DDR2*/
+ str r3, [r0, #0x10]
+ bic r3, r3, #0x00A
+ str r3, [r0, #0x10]
+ beq 2f
+
+ mov r3, #0x20000
+1: subs r3, r3, #1
+ bne 1b
+
+2: tst r2, #0x1
+ ldreq r3, =ESDCTL_DDR2_CONFIG
+ ldrne r3, =ESDCTL_MDDR_CONFIG
+ cmp r1, #CSD1_BASE_ADDR
+ strlo r3, [r0, #0x4]
+ strhs r3, [r0, #0xC]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+ tst r2, #0x1
+ bne skip_set_mode
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_DDR2_EMR2
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EMR3
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EN_DLL
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_RESET_DLL
+ strb r3, [r1, r4]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+skip_set_mode:
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xA2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ strb r3, [r1]
+ strb r3, [r1]
+
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ tst r2, #0x1
+ ldreq r4, =ESDCTL_DDR2_MR
+ ldrne r4, =ESDCTL_MDDR_MR
+ mov r3, #0xDA
+ strb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
+ streqb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_EN_DLL
+ ldrne r4, =ESDCTL_MDDR_EMR
+ strb r3, [r1, r4]
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0x82228080
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+
+ tst r2, #0x1
+ moveq r4, #0x20000
+ movne r4, #0x200
+1: subs r4, r4, #1
+ bne 1b
+
+ str r3, [r1, #0x100]
+ ldr r4, [r1, #0x100]
+ cmp r3, r4
+ movne r3, #1
+ moveq r3, #0
+
+ mov pc, lr
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
new file mode 100644
index 0000000..da926e5
--- /dev/null
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <fsl_pmic.h>
+#include <mc9sdz60.h>
+#include <mc13892.h>
+#include <linux/types.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef BOARD_LATE_INIT
+#error "BOARD_LATE_INIT must be set for this board"
+#endif
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ /* setup pins for I2C1 */
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ int pad;
+
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+ pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
+
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_IPU_MASK,
+ &ccm->cgr1);
+
+ /* Setup NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+static inline int pmic_detect(void)
+{
+ int id;
+
+ id = pmic_reg_read(REG_IDENTIFICATION);
+
+ id = (id >> 6) & 0x7;
+ if (id == 0x7)
+ return 1;
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev;
+
+ rev = pmic_detect();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+int board_late_init(void)
+{
+ u8 val;
+ u32 pmic_val;
+
+ if (pmic_detect()) {
+ mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
+ MUX_CONFIG_ALT1);
+
+ pmic_val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
+ pmic_val = pmic_reg_read(REG_MODE_0);
+ pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
+
+ mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+
+ mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(37, 1);
+ }
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
+ mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
+ mdelay(200);
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+ mdelay(200);
+
+ val |= 0x80;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 cpu_rev = get_cpu_rev();
+
+ /*
+ * Be sure that I2C is initialized to check
+ * the board revision
+ */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* Print board revision */
+ printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
+
+ /* Print CPU revision */
+ printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
+
+ switch (readl(&ccm->rcsr) & 0x0F) {
+ case 0x0000:
+ puts("POR");
+ break;
+ case 0x0002:
+ puts("JTAG");
+ break;
+ case 0x0004:
+ puts("RST");
+ break;
+ case 0x0008:
+ puts("WDT");
+ break;
+ default:
+ puts("unknown");
+ }
+ puts("]\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+ cpu_eth_init(bis);
+
+ return rc;
+}
diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h
new file mode 100644
index 0000000..409aeb2
--- /dev/null
+++ b/board/freescale/mx35pdk/mx35pdk.h
@@ -0,0 +1,101 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define DBG_BASE_ADDR WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG 0x0000D843
+#define DBG_CSCR_L_CONFIG 0x22252521
+#define DBG_CSCR_A_CONFIG 0x22220A00
+
+#define CCM_CCMR_CONFIG 0x003F4208
+#define CCM_PDR0_CONFIG 0x00801000
+
+#define PLL_BRM_OFFSET 31
+#define PLL_PD_OFFSET 26
+#define PLL_MFD_OFFSET 16
+#define PLL_MFI_OFFSET 10
+
+#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x) (x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+ (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+ _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/* MEMORY SETTING */
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+
+#define ESDCTL_PRECHARGE 0x00000400
+
+#define ESDCTL_MDDR_CONFIG 0x007FFC3F
+#define ESDCTL_MDDR_MR 0x00000033
+#define ESDCTL_MDDR_EMR 0x02000000
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+#endif /* __BOARD_MX35_3STACK_H */
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 2160d5a..02a765d 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -198,17 +198,17 @@ static void power_init(void)
/* Set core voltage to 1.1V */
val = pmic_reg_read(REG_SW_0);
- val = (val & (~0x1F)) | 0x14;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
pmic_reg_write(REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
val = pmic_reg_read(REG_SW_1);
- val = (val & (~0x1F)) | 0x1A;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
pmic_reg_write(REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
val = pmic_reg_read(REG_SW_2);
- val = (val & (~0x1F)) | 0x1A;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
pmic_reg_write(REG_SW_2, val);
udelay(50);
@@ -399,6 +399,14 @@ int board_mmc_init(bd_t *bis)
}
#endif
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
int board_init(void)
{
system_rev = get_cpu_rev();
@@ -407,9 +415,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- setup_iomux_uart();
- setup_iomux_fec();
-
return 0;
}
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
new file mode 100644
index 0000000..6b820f4
--- /dev/null
+++ b/board/freescale/mx53evk/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx53evk.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53evk/config.mk b/board/freescale/mx53evk/config.mk
new file mode 100644
index 0000000..0e60454
--- /dev/null
+++ b/board/freescale/mx53evk/config.mk
@@ -0,0 +1,24 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
new file mode 100644
index 0000000..dd7528c
--- /dev/null
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -0,0 +1,112 @@
+#
+# (C Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x53fa8554 0x00200000
+DATA 4 0x53fa8560 0x00200000
+DATA 4 0x53fa8594 0x00200000
+DATA 4 0x53fa8584 0x00200000
+DATA 4 0x53fa8558 0x00200040
+DATA 4 0x53fa8568 0x00200040
+DATA 4 0x53fa8590 0x00200040
+DATA 4 0x53fa857c 0x00200040
+DATA 4 0x53fa8564 0x00200040
+DATA 4 0x53fa8580 0x00200040
+DATA 4 0x53fa8570 0x00200000
+DATA 4 0x53fa8578 0x00200000
+DATA 4 0x53fa872c 0x00200000
+DATA 4 0x53fa8728 0x00200000
+DATA 4 0x53fa871c 0x00200000
+DATA 4 0x53fa8718 0x00200000
+DATA 4 0x53fa8574 0x00280000
+DATA 4 0x53fa8588 0x00280000
+DATA 4 0x53fa86f0 0x00280000
+DATA 4 0x53fa8720 0x00280000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa86f4 0x00000200
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8724 0x06000000
+DATA 4 0x63fd9088 0x34333936
+DATA 4 0x63fd9090 0x49434942
+DATA 4 0x63fd90F8 0x00000800
+DATA 4 0x63fd907c 0x01350138
+DATA 4 0x63fd9080 0x01380139
+DATA 4 0x63fd9018 0x00001710
+DATA 4 0x63fd9000 0xc4110000
+DATA 4 0x63fd900C 0x4d5122d2
+DATA 4 0x63fd9010 0x92d18a22
+DATA 4 0x63fd9014 0x00c70092
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f000e
+DATA 4 0x63fd9008 0x12272000
+DATA 4 0x63fd9004 0x00030012
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00008031
+DATA 4 0x63fd901c 0x0b5280b0
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x0a528030
+DATA 4 0x63fd901c 0x03c68031
+DATA 4 0x63fd901c 0x00448031
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00008039
+DATA 4 0x63fd901c 0x0b528138
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x0a528038
+DATA 4 0x63fd901c 0x03c68039
+DATA 4 0x63fd901c 0x00448039
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9058 0x00033335
+DATA 4 0x63fd901c 0x00000000
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x53fa8004 0x00194005
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
new file mode 100644
index 0000000..e71701b
--- /dev/null
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mxc_gpio.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ /* UART1 RXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+ /* UART1 TXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_i2c(unsigned int port_number)
+{
+ switch (port_number) {
+ case 0:
+ /* i2c1 SDA */
+ mxc_request_iomux(MX53_PIN_CSI0_D8,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ /* i2c1 SCL */
+ mxc_request_iomux(MX53_PIN_CSI0_D9,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ break;
+ case 1:
+ /* i2c2 SDA */
+ mxc_request_iomux(MX53_PIN_KEY_ROW3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+ /* i2c2 SCL */
+ mxc_request_iomux(MX53_PIN_KEY_COL3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ break;
+ default:
+ printf("Warning: Wrong I2C port number\n");
+ break;
+ }
+}
+
+void power_init(void)
+{
+ unsigned int val;
+
+ /* Set VDDA to 1.25V */
+ val = pmic_reg_read(REG_SW_2);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_25;
+ pmic_reg_write(REG_SW_2, val);
+
+ /*
+ * Need increase VCC and VDDA to 1.3V
+ * according to MX53 IC TO2 datasheet.
+ */
+ if (is_soc_rev(CHIP_REV_2_0) == 0) {
+ /* Set VCC to 1.3V for TO2 */
+ val = pmic_reg_read(REG_SW_1);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(REG_SW_1, val);
+
+ /* Set VDDA to 1.3V for TO2 */
+ val = pmic_reg_read(REG_SW_2);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(REG_SW_2, val);
+ }
+}
+
+static void setup_iomux_fec(void)
+{
+ /*FEC_MDIO*/
+ mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+ /*FEC_MDC*/
+ mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+ /* FEC RXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC RXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC TXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+ /* FEC TXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+ /* FEC TX_EN */
+ mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+ /* FEC TX_CLK */
+ mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC CRS */
+ mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *cd = mxc_gpio_get(77); /*GPIO3_13*/
+ else
+ *cd = mxc_gpio_get(75); /*GPIO3_11*/
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index;
+ s32 status = 0;
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA0,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA1,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA2,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA3,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_EIM_DA13,
+ IOMUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ break;
+ case 1:
+ mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_IORDY,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_DATA8,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA9,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA10,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA11,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA0,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA1,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA2,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA3,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_EIM_DA11,
+ IOMUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return status;
+ }
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ }
+
+ return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_i2c(1);
+ power_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ puts("Board: MX53EVK [");
+
+ cause = src_regs->srsr;
+ switch (cause) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ }
+ printf("]\n");
+ return 0;
+}
diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile
new file mode 100644
index 0000000..0200220
--- /dev/null
+++ b/board/samsung/universal_c210/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := universal.o onenand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
new file mode 100644
index 0000000..67635bb
--- /dev/null
+++ b/board/samsung/universal_c210/lowlevel_init.S
@@ -0,0 +1,395 @@
+/*
+ * Lowlevel setup for universal board based on S5PC210
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r7, =S5PC210_GPIO_PART1_BASE
+ ldr r6, =S5PC210_GPIO_PART2_BASE
+
+ /* System Timer */
+ ldr r0, =S5PC210_SYSTIMER_BASE
+ ldr r1, =0x5000
+ str r1, [r0, #0x0]
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x8]
+ ldr r1, =0x49
+ str r1, [r0, #0x4]
+
+ /* PMIC manual reset */
+ /* nPOWER: XEINT_23: GPX2[7] */
+ add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28) @ Output
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+ /* init system clock */
+ bl system_clock_init
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
+ str r5, [r0]
+
+ /* UART */
+ bl uart_asm_init
+
+ /* PMU init */
+ bl system_power_init
+
+ bl tzpc_init
+
+ mov lr, r11
+ mov pc, lr
+ nop
+ nop
+ nop
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /*
+ * setup UART0-UART4 GPIOs (part1)
+ * GPA1CON[3] = I2C_3_SCL (3)
+ * GPA1CON[2] = I2C_3_SDA (3)
+ */
+ mov r0, r7
+ ldr r1, =0x22222222
+ str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ ldr r1, =0x00223322
+ str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+
+ /* UART_SEL GPY4[7] (part2) at S5PC210 */
+ add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28)
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x8]
+ bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
+ orr r1, r1, #(0x3 << 14) @ Pull-up enabled
+ str r1, [r0, #0x8]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_clock_init:
+ ldr r0, =S5PC210_CLOCK_BASE
+
+ /* APLL(1), MPLL(1), CORE(0), HPM(0) */
+ ldr r1, =0x0101
+ ldr r2, =0x14200 @ CLK_SRC_CPU
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x10000
+1: subs r1, r1, #1
+ bne 1b
+
+ /*
+ * CLK_SRC_TOP0
+ * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
+ * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
+ * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
+ */
+ ldr r1, =0x10000110
+ ldr r2, =0x0C210 @ CLK_SRC_TOP
+ str r1, [r0, r2]
+
+ /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+ ldr r1, =0x0066666
+ ldr r2, =0x0C240 @ CLK_SRC_FSYS
+ str r1, [r0, r2]
+ /* UART[0:5], PWM: SCLKMPLL(6) */
+ ldr r1, =0x6666666
+ ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
+ str r1, [r0, r2]
+
+ /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
+ ldr r1, =0x0133730
+ ldr r2, =0x14500 @ CLK_DIV_CPU0
+ str r1, [r0, r2]
+ /* CPU1: COPY, HPM */
+ ldr r1, =0x03
+ ldr r2, =0x14504 @ CLK_DIV_CPU1
+ str r1, [r0, r2]
+ /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
+ ldr r1, =0x13111113
+ ldr r2, =0x10500 @ CLK_DIV_DMC0
+ str r1, [r0, r2]
+ /* DMC1: PWI, DVSEM, DPM */
+ ldr r1, =0x01010100
+ ldr r2, =0x10504 @ CLK_DIV_DMC1
+ str r1, [r0, r2]
+ /* LEFTBUS: GDL, GPL */
+ ldr r1, =0x13
+ ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
+ str r1, [r0, r2]
+ /* RIGHHTBUS: GDR, GPR */
+ ldr r1, =0x13
+ ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
+ str r1, [r0, r2]
+ /*
+ * CLK_DIV_TOP
+ * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
+ * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
+ */
+ ldr r1, =0x00005473
+ ldr r2, =0x0C510 @ CLK_DIV_TOP
+ str r1, [r0, r2]
+ /* MMC[0:1] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C544 @ CLK_DIV_FSYS1
+ str r1, [r0, r2]
+ /* MMC[2:3] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C548 @ CLK_DIV_FSYS2
+ str r1, [r0, r2]
+ /* MMC4 */
+ ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C54C @ CLK_DIV_FSYS3
+ str r1, [r0, r2]
+ /* UART[0:5] */
+ ldr r1, =0x774777
+ ldr r2, =0x0C550 @ CLK_DIV_PERIL0
+ str r1, [r0, r2]
+ /* SLIMBUS: ???, PWM */
+ ldr r1, =0x8
+ ldr r2, =0x0C55C @ CLK_DIV_PERIL3
+ str r1, [r0, r2]
+
+ /* PLL Setting */
+ ldr r1, =0x1C20
+ ldr r2, =0x14000 @ APLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x14008 @ MPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C010 @ EPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C020 @ VPLL_LOCK
+ str r1, [r0, r2]
+
+ /* APLL */
+ ldr r1, =0x8000001c
+ ldr r2, =0x14104 @ APLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14100 @ APLL_CON0
+ str r1, [r0, r2]
+ /* MPLL */
+ ldr r1, =0x8000001C
+ ldr r2, =0x1410C @ MPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14108 @ MPLL_CON0
+ str r1, [r0, r2]
+ /* EPLL */
+ ldr r1, =0x0
+ ldr r2, =0x0C114 @ EPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80300302 @ 96MHz
+ ldr r2, =0x0C110 @ EPLL_CON0
+ str r1, [r0, r2]
+ /* VPLL */
+ ldr r1, =0x11000400
+ ldr r2, =0x0C124 @ VPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80350302 @ 108MHz
+ ldr r2, =0x0C120 @ VPLL_CON0
+ str r1, [r0, r2]
+
+ /*
+ * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
+ * Turn off all
+ */
+ ldr r1, =0xFFF80000
+ ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C924 @ CLK_GATE_IP_VP
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFE0
+ ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFC00
+ ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
+ str r1, [r0, r2]
+
+ /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
+ ldr r1, =0xFFFFFFF1
+ ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
+ str r1, [r0, r2]
+
+ /*
+ * SMMUPCIE[18], NFCON[16] : 1111 1010
+ * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
+ * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
+ */
+ ldr r1, =0xFFFAB8A3
+ ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
+ str r1, [r0, r2]
+
+ /*
+ * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
+ * I2C2[8] : 1111 1110
+ */
+ ldr r1, =0xF1FFFEFF
+ ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
+ str r1, [r0, r2]
+
+ /*
+ * KEYIF[16] : 1111 1110
+ */
+ ldr r1, =0xFFFEFFFF
+ ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
+ str r1, [r0, r2]
+
+ /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
+ ldr r1, =0xFFFFFFD1
+ ldr r2, =0x0C970 @ CLK_GATE_BLOCK
+ str r1, [r0, r2]
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_power_init:
+ ldr r0, =S5PC210_POWER_BASE @ 0x10020000
+
+ ldr r2, =0x330C @ PS_HOLD_CONTROL
+ ldr r1, [r0, r2]
+ orr r1, r1, #(0x3 << 8) @ Data High, Output En
+ str r1, [r0, r2]
+
+ /* Power Down */
+ add r2, r0, #0x3000
+ str r5, [r2, #0xC20] @ TV_CONFIGURATION
+ str r5, [r2, #0xC40] @ MFC_CONFIGURATION
+ str r5, [r2, #0xC60] @ G3D_CONFIGURATION
+ str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
+ str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+tzpc_init:
+ ldr r0, =0x10110000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10120000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10130000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10140000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10150000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ mov pc, lr
diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c
new file mode 100644
index 0000000..20e1dc5
--- /dev/null
+++ b/board/samsung/universal_c210/onenand.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
new file mode 100644
index 0000000..b65bc6e
--- /dev/null
+++ b/board/samsung/universal_c210/universal.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+unsigned int board_rev;
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static int get_hwrev(void)
+{
+ return board_rev & 0xFF;
+}
+
+static void check_hw_revision(void);
+
+int board_init(void)
+{
+ gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+ gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static unsigned short get_adc_value(int channel)
+{
+ struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+ unsigned short ret = 0;
+ unsigned int reg;
+ unsigned int loop = 0;
+
+ writel(channel & 0xF, &adc->adcmux);
+ writel((1 << 14) | (49 << 6), &adc->adccon);
+ writel(1000 & 0xffff, &adc->adcdly);
+ writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+ udelay(10);
+ writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+ udelay(10);
+
+ do {
+ udelay(1);
+ reg = readl(&adc->adccon);
+ } while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+ ret = readl(&adc->adcdat0) & 0xFFF;
+
+ return ret;
+}
+
+static unsigned int get_hw_revision(void)
+{
+ int hwrev, mode0, mode1;
+
+ mode0 = get_adc_value(1); /* HWREV_MODE0 */
+ mode1 = get_adc_value(2); /* HWREV_MODE1 */
+
+ /*
+ * XXX Always set the default hwrev as the latest board
+ * ADC = (voltage) / 3.3 * 4096
+ */
+ hwrev = 3;
+
+#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
+ if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x0; /* 0.01V 0.01V */
+ if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x1; /* 610mV 0.01V */
+ if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x2; /* 1.16V 0.01V */
+ if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x3; /* 1.79V 0.01V */
+#undef IS_RANGE
+
+ debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+ return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+ int hwrev;
+
+ hwrev = get_hw_revision();
+
+ board_rev |= hwrev;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board:\tUniversal C210\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ switch (get_hwrev()) {
+ case 0:
+ /*
+ * Set the low to enable LDO_EN
+ * But when you use the test board for eMMC booting
+ * you should set it HIGH since it removes the inverter
+ */
+ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+ gpio_direction_output(&gpio1->e3, 6, 0);
+ break;
+ default:
+ /*
+ * Default reset state is High and there's no inverter
+ * But set it as HIGH to ensure
+ */
+ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+ gpio_direction_output(&gpio1->e1, 3, 1);
+ break;
+ }
+
+ /*
+ * eMMC GPIO:
+ * SDR 8-bit@48MHz at MMC0
+ * GPK0[0] SD_0_CLK(2)
+ * GPK0[1] SD_0_CMD(2)
+ * GPK0[2] SD_0_CDn -> Not used
+ * GPK0[3:6] SD_0_DATA[0:3](2)
+ * GPK1[3:6] SD_0_DATA[0:3](3)
+ *
+ * DDR 4-bit@26MHz at MMC4
+ * GPK0[0] SD_4_CLK(3)
+ * GPK0[1] SD_4_CMD(3)
+ * GPK0[2] SD_4_CDn -> Not used
+ * GPK0[3:6] SD_4_DATA[0:3](3)
+ * GPK1[3:6] SD_4_DATA[4:7](4)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK0[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k0, i, 0x2);
+ /* GPK0[0:6] pull disable */
+ gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
+ /* GPK0[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
+ }
+
+ for (i = 3; i < 7; i++) {
+ /* GPK1[3:6] special function 3 */
+ gpio_cfg_pin(&gpio2->k1, i, 0x3);
+ /* GPK1[3:6] pull disable */
+ gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
+ /* GPK1[3:6] drv 4x */
+ gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
+ }
+
+ /* T-flash detect */
+ gpio_cfg_pin(&gpio2->x3, 4, 0xf);
+ gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+
+ /*
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
+ */
+ err = s5p_mmc_init(0, 8);
+
+ /*
+ * Check the T-flash detect pin
+ * GPX3[4] T-flash detect pin
+ */
+ if (!gpio_get_value(&gpio2->x3, 4)) {
+ /*
+ * SD card GPIO:
+ * GPK2[0] SD_2_CLK(2)
+ * GPK2[1] SD_2_CMD(2)
+ * GPK2[2] SD_2_CDn -> Not used
+ * GPK2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK2[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k2, i, 0x2);
+ /* GPK2[0:6] pull disable */
+ gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+ /* GPK2[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+ }
+ err = s5p_mmc_init(2, 4);
+ }
+
+ return err;
+
+}
+#endif