diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/ixdp425/ixdp425.c | 22 | ||||
| -rw-r--r-- | board/omap2420h4/config.mk | 4 | ||||
| -rw-r--r-- | board/omap2420h4/flash.c | 3 | ||||
| -rw-r--r-- | board/omap2420h4/mem.c | 250 | ||||
| -rw-r--r-- | board/omap2420h4/omap2420h4.c | 77 | ||||
| -rw-r--r-- | board/omap2420h4/platform.S | 47 | ||||
| -rw-r--r-- | board/omap2420h4/sys_info.c | 107 |
7 files changed, 322 insertions, 188 deletions
diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index e56f477..80553ba 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -38,18 +38,16 @@ * Miscelaneous platform dependent initialisations */ -int -/**********************************************************/ -board_post_init (void) /**********************************************************/ + +int board_post_init (void) { return (0); } -int -/**********************************************************/ -board_init (void) /**********************************************************/ + +int board_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -62,10 +60,9 @@ board_init (void) return 0; } -int -/**********************************************************/ -dram_init (void) /**********************************************************/ + +int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -74,9 +71,14 @@ dram_init (void) return (0); } + +/**********************************************************/ + extern struct pci_controller hose; + void pci_init_board(void) { + extern void pci_ixp_init (struct pci_controller *hose); + pci_ixp_init(&hose); - return ; } diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk index 4f14be8..f2a533e 100644 --- a/board/omap2420h4/config.mk +++ b/board/omap2420h4/config.mk @@ -14,12 +14,10 @@ # (mem base + reserved) # For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. TEXT_BASE = 0x80e80000 # Used with full SRAM boot. # This is either with a GP system or a signed boot image. # easiest, and safest way to go if you can. -# Comment out CONFIG_PARTIAL_SRAM for this one. -# #TEXT_BASE = 0x40280000 + diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c index 3b6a69f..d5e106a 100644 --- a/board/omap2420h4/flash.c +++ b/board/omap2420h4/flash.c @@ -119,6 +119,7 @@ unsigned long flash_init (void) size += flash_info[i].size; } +#ifdef CFG_ENV_IS_IN_FLASH /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, @@ -128,7 +129,7 @@ unsigned long flash_init (void) flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - +#endif return size; } diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index 5e23d61..3ce38cc 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -38,9 +38,8 @@ *************************************************************/ void sdelay (unsigned long loops) { - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); } /********************************************************************************* @@ -50,12 +49,10 @@ void sdelay (unsigned long loops) void prcm_init(void) { u32 rev,div; -#ifdef CONFIG_PARTIAL_SRAM void (*f_lock_pll) (u32, u32, u32, u32); extern void *_end_vect, *_start; f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE); -#endif __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ @@ -75,45 +72,33 @@ void prcm_init(void) __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */ sdelay(1000); -#ifndef CONFIG_PARTIAL_SRAM - /* If running fully from SRAM this is OK. The Flash bus drops out for just a little. - * but then comes back. If running from Flash this sequence kills you, thus you need - * to run it using CONFIG_PARTIAL_SRAM. - */ - __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */ - wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */ - - /* set clock selection and dpll dividers. */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */ - __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */ - sdelay(10000); - __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */ - sdelay(10000); - wait_on_value(BIT0|BIT1, BIT2, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */ -#else -/* if running from flash, need to jump to small relocated code area in SRAM. - * This is the only safe spot to do configurations from. - */ - (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN); -#endif + if(running_in_sram()){ + /* If running fully from SRAM this is OK. The Flash bus drops out for just a little. + * but then comes back. If running from Flash this sequence kills you, thus you need + * to run it using CONFIG_PARTIAL_SRAM. + */ + __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */ + wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */ + sdelay(1000); + /* set clock selection and dpll dividers. */ + __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */ + __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */ + sdelay(10000); + __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */ + sdelay(10000); + wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */ + }else if(running_in_flash()){ + /* if running from flash, need to jump to small relocated code area in SRAM. + * This is the only safe spot to do configurations from. + */ + (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN); + } __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */ sdelay(1000); } -/*********************************************** - * memif_init() - init the gpmc and sdrc - * - early init routines, called from flash or - * SRAM. - ***********************************************/ -void memif_init(void) -{ - sdrc_init(); -#ifndef CONFIG_PARTIAL_SRAM /* don't init if calling from flash */ - gpmc_init(); -#endif -} /******************************************************** * mem_ok() - test used to see if timings are correct @@ -121,11 +106,17 @@ void memif_init(void) * we are currently using. *******************************************************/ u32 mem_ok(void) -{ u32 val; - __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ - __raw_writel(0x12345678, OMAP2420_SDRC_CS0);/* pattern to pos B */ - val = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ - if (val != 0) /* see if pos A value changed*/ +{ + u32 val1, val2; + u32 pattern = 0x12345678; + + __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ + __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ + __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ + val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ + val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ return(0); else return(1); @@ -142,122 +133,157 @@ void sdrc_init(void) do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ } -/********************************************************** +/************************************************************************* * do_sdrc_init(): initialize the SDRAM for use. * -called from low level code with stack only. * -code sets up SDRAM timing and muxing for 2422 or 2420. * -optimal settings can be placed here, or redone after i2c * inspection of board info * - * !!! When ES1 comes out need to conditionalize RFR value!!! - **********************************************************/ + * This is a bit ugly, but should handle all memory moduels + * used with the H4. The first time though this code from s_init() + * we configure the first chip select. Later on we come back and + * will configure the 2nd chip select if it exists. + * + **************************************************************************/ void do_sdrc_init(u32 offset, u32 early) { - u32 cpu, bug=0, rev, shared=0, cs0=0, pmask=0,first=1; + u32 cpu, bug=0, rev, common=0, cs0=0, pmask=0, pass_type; sdrc_data_t *sdata; /* do not change type */ + u32 a, b, r; static const sdrc_data_t sdrc_2422 = { - H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0, H4_2422_SDRC_ACTIM_CTRLA_0, - H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0, - H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL + H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0, + H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0_DDR, + 0, H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL }; static const sdrc_data_t sdrc_2420 = { - H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0, H4_2420_SDRC_ACTIM_CTRLA_0, - H4_2420_SDRC_ACTIM_CTRLB_0, H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0, + H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR, + H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, + H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL }; if (offset == SDRC_CS0_OSET) - cs0 = shared = 1; /* int regs shared between both chip select */ + cs0 = common = 1; /* int regs shared between both chip select */ cpu = get_cpu_type(); - /* warning generated, though code generation is correct. this may bite later, but is ok for now. - * there is only so much C code you can do on stack only operation. + /* warning generated, though code generation is correct. this may bite later, + * but is ok for now. there is only so much C code you can do on stack only + * operation. */ - if (cpu == CPU_2422) - sdata = &sdrc_2422; - else - sdata = &sdrc_2420; - __asm__ __volatile__("": : :"memory"); -#ifdef CONFIG_PARTIAL_SRAM - /* u-boot is compiled to run in DDR at 8xxxxxxx. If we use data here which is not pc relative - * we need to get the address correct. We need to find the current flash mapping to dress up - * the initial pointer load. As long as this is const data we should be ok. - */ - if(early) - sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); -#endif + if (cpu == CPU_2422){ + sdata = (sdrc_data_t *)&sdrc_2422; + pass_type = STACKED; + } + else{ + sdata = (sdrc_data_t *)&sdrc_2420; + pass_type = IP_DDR; + } - men_combo: + __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ - if (!early && get_mem_type() == DDR_COMBO) { /* combo part has a shared CKE signal, can't use feature */ + /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. + * If we are running in flash prior to relocation and we use data + * here which is not pc relative we need to get the address correct. + * We need to find the current flash mapping to dress up the initial + * pointer load. As long as this is const data we should be ok. + */ + if((early) && running_in_flash()){ + sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); + /* NOR internal boot offset is 0x4000 from xloader signature */ + if(running_from_internal_boot()) + sdata = (sdrc_data_t *)((u32)sdata + 0x4000); + } + if (!early && (get_mem_type() == DDR_COMBO)) {/* combo part has a shared CKE signal, can't use feature */ pmask = BIT2; - first = 0; /* trigger ddr_combo init */ + pass_type = COMBO_DDR; /* CS1 config */ } - if (shared) { - __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); - __raw_writel(SMART_IDLE|SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(SMART_IDLE, SDRC_SYSCONFIG); /* clear soft reset */ +next_mem_type: + if (common) { /* do a SDRC reset between types to clear regs*/ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ + __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER); + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); +#ifdef POWER_SAVE + __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); + __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); + __raw_writel((__raw_readl(SDRC_POWER)|BIT6) & ~pmask, SDRC_POWER); +#endif + } + + if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */ + __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset); + else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset); + } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */ + __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); } - if (first) - __raw_writel(sdata->sdrc_mdcfg_0, SDRC_MCFG_0+offset); - else { - __raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER); - __raw_writel(H4_2420_COMBO_MDCFG_0,SDRC_MCFG_0+offset); + + if(pass_type == IP_SDR){ /* SDRAM can run full speed only rated for 105MHz*/ + a = H4_242X_SDRC_ACTIM_CTRLA_0_100MHz; + b = H4_242X_SDRC_ACTIM_CTRLB_0_100MHz; + r = H4_2420_SDRC_RFR_CTRL; + } else { + a = sdata->sdrc_actim_ctrla_0; + b = sdata->sdrc_actim_ctrlb_0; + r = sdata->sdrc_rfr_ctrl; } if (cs0) { - __raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(a, SDRC_ACTIM_CTRLA_0); + __raw_writel(b, SDRC_ACTIM_CTRLB_0); } else { - __raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_1); - __raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_1); + __raw_writel(a, SDRC_ACTIM_CTRLA_1); + __raw_writel(b, SDRC_ACTIM_CTRLB_1); } - __raw_writel(sdata->sdrc_rfr_ctrl, SDRC_RFR_CTRL+offset); + __raw_writel(r, SDRC_RFR_CTRL+offset); - /* init sequence for _mDDR_ using manual commands (DDR is a bit different) */ + /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset); - sdelay(5000); /* susposed to be 100us per design spec for mddr*/ + sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset); __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); /* * CSx SDRC Mode Register - * Burst length = 4 - DDR memory + * Burst length = (4 - DDR) (2-SDR) * Serial mode * CAS latency = x */ - __raw_writel(sdata->sdrc_mr_0, SDRC_MR_0+offset); + if(pass_type == IP_SDR) + __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset); + else + __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); - /* NOTE: ES1 242x _BUG_ DLL */ + /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ rev = get_cpu_rev(); - if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1) + if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1){ bug = BIT0; + __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) + ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ + } /* enable & load up DLL with good value for 75MHz, and set phase to 90% */ - if (shared) { + if (common && (pass_type != IP_SDR)) { __raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL); __raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL); __raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL); __raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL); } - sdelay(9000); - if (!first || mem_ok()) /* passed test or 2nd bank init */ - return; - else { - first = 0; - goto men_combo; - } -} + sdelay(90000); + if(mem_ok()) + return; /* STACKED, other configued type */ + ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ + goto next_mem_type; +} /***************************************************** * gpmc_init(): init gpmc bus @@ -272,7 +298,11 @@ void gpmc_init(void) __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ __raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND_BOOT + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#else __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif /* discover bus connection from sysboot */ if (is_gpmc_muxed() == GPMC_MUXED) @@ -283,11 +313,22 @@ void gpmc_init(void) /* setup cs0 */ __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ sdelay(1000); + +#ifdef CFG_NAND_BOOT + __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); +#else __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); - /* __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); */ +#endif + +#ifdef PRCM_CONFIG_III + __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); +#endif __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); - /* __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); */ +#ifdef PRCM_CONFIG_III + __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); + __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); +#endif __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */ sdelay(2000); @@ -303,3 +344,4 @@ void gpmc_init(void) __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */ sdelay(2000); } + diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index bf398f6..697dfef 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -31,6 +31,11 @@ #include <asm/arch/mem.h> #include <i2c.h> #include <asm/mach-types.h> +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include <linux/mtd/nand.h> +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + static void wait_for_command_complete(unsigned int wd_base); @@ -40,9 +45,8 @@ static void wait_for_command_complete(unsigned int wd_base); ******************************************************/ static inline void delay (unsigned long loops) { - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); } /***************************************** @@ -52,11 +56,9 @@ static inline void delay (unsigned long loops) int board_init (void) { DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_PARTIAL_SRAM - s_init(0x0); /* full sram build, never skip clock and sdrc, no point */ -#else - gpmc_init(); -#endif + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ @@ -66,23 +68,23 @@ int board_init (void) /********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. + * - Called path is with sram stack. **********************************************************/ -void s_init(int skip) +void s_init(void) { + int in_sdram = running_in_sdram(); + watchdog_init(); set_muxconf_regs(); delay(100); - if (!skip) + if(!in_sdram) prcm_init(); peripheral_enable(); icache_enable(); -#ifndef CONFIG_APTIX - if (!skip) - memif_init(); -#endif + if (!in_sdram) + sdrc_init(); } /******************************************************* @@ -102,7 +104,7 @@ int misc_init_r (void) void watchdog_init(void) { int mode; -#define GP (BIT8|BIT9) + #define GP (BIT8|BIT9) /* There are 4 watch dogs. 1 secure, and 3 general purpose. * I would expect that the ROM takes care of the secure one, @@ -152,6 +154,8 @@ void ether_init (void) #ifdef CONFIG_DRIVER_LAN91C96 int cnt = 20; + __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ + __raw_writew(0x0, LAN_RESET_REGISTER); do { __raw_writew(0x1, LAN_RESET_REGISTER); @@ -189,7 +193,9 @@ int dram_init (void) DECLARE_GLOBAL_DATA_PTR; unsigned int size0=0,size1=0; u32 mtype, btype; -#define NOT_EARLY 0 + u8 chg_on = 0x5; /* enable charge of back up battery */ + u8 vmode_on = 0x8C; + #define NOT_EARLY 0 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */ @@ -197,13 +203,18 @@ int dram_init (void) mtype = get_mem_type(); display_board_info(btype); - if (btype == BOARD_H4_MENELAUS) - update_mux(btype,mtype); + if (btype == BOARD_H4_MENELAUS){ + update_mux(btype,mtype); /* combo part on menelaus */ + i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */ + i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */ + } if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ size0 = size1 = SZ_32M; - } else + } else if (mtype == SDR_DISCRETE) + size0 = SZ_128M; + else size0 = SZ_64M; gd->bd->bi_dram[0].start = PHYS_SDRAM_1; @@ -477,7 +488,7 @@ void muxSetupCamera(void) /* CAMERA_RSTZ pin configuration, PIN = Y16 */ /* CAM_RST is connected through the I2C IO expander.*/ /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/ - /* *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */ /* CAMERA_XCLK pin configuration, PIN = U3 */ MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK; @@ -661,7 +672,7 @@ void muxSetupHDQ(void) void muxSetupGPMC(void) { volatile uint8 *MuxConfigReg; - volatile unsigned int *MCR = 0x4800008C; + volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; /* gpmc_io_dir */ *MCR = 0x19000000; @@ -830,3 +841,25 @@ void update_mux(u32 btype,u32 mtype) } } } + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#endif +} +#endif + + + diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S index dc1b443..86bf5ba 100644 --- a/board/omap2420h4/platform.S +++ b/board/omap2420h4/platform.S @@ -33,8 +33,6 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -#ifdef CONFIG_PARTIAL_SRAM - /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute * R1 = SRAM destination address. @@ -159,41 +157,16 @@ pll_div_add: .word CM_CLKSEL1_PLL pll_div_val: .word DPLL_VAL /* DPLL setting (300MHz default) */ -#endif .globl platformsetup platformsetup: - mov r3, r0 /* save skip information */ -#ifdef CONFIG_APTIX - ldr r0, REG_SDRC_MCFG_0 - ldr r1, VAL_SDRC_MCFG_0 - str r1, [r0] - ldr r0, REG_SDRC_MR_0 - ldr r1, VAL_SDRC_MR_0 - str r1, [r0] - /* a ddr needs emr1 set here */ - ldr r0, REG_SDRC_SHARING - ldr r1, VAL_SDRC_SHARING - str r1, [r0] - ldr r0, REG_SDRC_RFR_CTRL_0 - ldr r1, VAL_SDRC_RFR_CTRL_0 - str r1, [r0] - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b -#endif -#ifdef CONFIG_PARTIAL_SRAM ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ bl s_init /* go setup pll,mux,memory */ ldr ip, [sp] /* restore save ip */ mov lr, ip /* restore link reg */ -#endif + /* map interrupt controller */ ldr r0, VAL_INTH_SETUP mcr p15, 0, r0, c15, c2, 4 @@ -211,21 +184,3 @@ VAL_INTH_SETUP: SRAM_STACK: .word LOW_LEVEL_SRAM_STACK -#ifdef CONFIG_APTIX -REG_SDRC_SHARING: - .word SDRC_SHARING -REG_SDRC_MCFG_0: - .word SDRC_MCFG_0 -REG_SDRC_MR_0: - .word SDRC_MR_0 -REG_SDRC_RFR_CTRL_0: - .word SDRC_RFR_CTRL -VAL_SDRC_SHARING: - .word VAL_H4_SDRC_SHARING -VAL_SDRC_MCFG_0: - .word VAL_H4_SDRC_MCFG_0 -VAL_SDRC_MR_0: - .word VAL_H4_SDRC_MR_0 -VAL_SDRC_RFR_CTRL_0: - .word VAL_H4_SDRC_RFR_CTRL_0 -#endif diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c index b5fe9e3..78b936c 100644 --- a/board/omap2420h4/sys_info.c +++ b/board/omap2420h4/sys_info.c @@ -70,13 +70,21 @@ u32 get_cpu_rev(void) *************************************************************/ u32 get_mem_type(void) { + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); + if (get_cpu_type() == CPU_2422) return(DDR_STACKED); if (get_board_type() == BOARD_H4_MENELAUS) - return(DDR_COMBO); + if(*burst == H4_2420_SDRC_MR_0_SDR) + return(SDR_DISCRETE); + else + return(DDR_COMBO); else - return(DDR_DISCRETE); + if(*burst == H4_2420_SDRC_MR_0_SDR) /* SDP + SDR kit */ + return(SDR_DISCRETE); + else + return(DDR_DISCRETE); /* origional SDP */ } /*********************************************************************** @@ -129,6 +137,8 @@ u32 is_gpmc_muxed(void) { u32 mux; mux = get_sysboot_value(); + if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) + return(GPMC_MUXED); /* NAND Boot mode */ if (mux & BIT1) /* if mux'ed */ return(GPMC_MUXED); else @@ -200,3 +210,96 @@ void display_board_info(u32 btype) db_s = db_ip; printf("TI H4 SDP Base Board with OMAP%s %s Daughter Board\n",cpu_s, db_s); } + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = 242x IP platform (first 2xx boards) + * 1 = 242x Menelaus platfrom. + *************************************************************************/ +u32 get_board_rev(void) +{ + u32 rev = 0; + u32 btype = get_board_type(); + + if (btype == BOARD_H4_MENELAUS){ + rev = 1; + } + return(rev); +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +static u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); + val &= 0xF0000000; + val >>= 28; + return(val); +} + +/******************************************************** + * get_base2(); get 2upper addr of current execution + *******************************************************/ +static u32 get_base2(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); + val &= 0xFF000000; + val >>= 24; + return(val); +} + + + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return(1); /* in flash */ + return(0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return(1); /* in SRAM */ + return(0); /* running in FLASH or SDRAM */ +} +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return(1); /* in sdram */ + return(0); /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I a signed NOR image. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v, base; + + v = get_sysboot_value() & BIT3; + base = get_base2(); + /* if running at mask rom flash address and + * sysboot3 says this was an internal boot + */ + if ((base == 0x08) && v) + return(1); + else + return(0); +} + |