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-rw-r--r--board/csb226/csb226.c2
-rw-r--r--board/csb226/memsetup.S6
-rw-r--r--board/trab/trab.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 1335fd7..1ed4034 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -40,7 +40,7 @@ int board_init (void)
/* so we do _nothing_ here */
/* arch number of CSB226 board */
- gd->bd->bi_arch_number = 0; /* FIXME */
+ gd->bd->bi_arch_number = 216;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S
index 5a584c1..d34ead4 100644
--- a/board/csb226/memsetup.S
+++ b/board/csb226/memsetup.S
@@ -232,7 +232,7 @@ mem_init:
ldr r4, =0x03ca4fff
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
ldr r4, =0x03ca4030
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
@@ -261,7 +261,7 @@ mem_init:
/* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
- orr r4, r4, #(MDREFR_K1RUN|MDREFR_K2RUN|MDREFR_K0RUN)
+ orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
@@ -286,7 +286,7 @@ mem_init:
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
- ldr r4, [r1, #MDCNFG_OFFSET]
+ ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 3f9b198..b4ab329 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -42,7 +42,7 @@ extern int do_mdm_init; /* defined in common/main.c */
* is that timers are not available yet, so we use a manually timed
* loop.
*/
-#define KBD_MDELAY 100000 /* 1000 */
+#define KBD_MDELAY 1000
static void mdelay_no_timer (int msec)
{
DECLARE_GLOBAL_DATA_PTR;