diff options
Diffstat (limited to 'board')
42 files changed, 2473 insertions, 140 deletions
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 15225b0..39afbba 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -12,6 +12,10 @@ #ifndef _BUR_COMMON_H_ #define _BUR_COMMON_H_ +#include <../../../drivers/video/am335x-fb.h> + +int load_lcdtiming(struct am335x_lcdpanel *panel); +void br_summaryscreen(void); void blink(u32 blinks, u32 intervall, u32 pin); void pmicsetup(u32 mpupll); void enable_uart0_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 25cbe62..18e1520 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -9,7 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ * */ - +#include <version.h> #include <common.h> #include <errno.h> #include <spl.h> @@ -26,10 +26,421 @@ #include <miiphy.h> #include <cpsw.h> #include <power/tps65217.h> +#include <lcd.h> +#include <fs.h> +#ifdef CONFIG_USE_FDT + #include <fdt_support.h> +#endif #include "bur_common.h" +#include "../../../drivers/video/am335x-fb.h" static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USE_FDT + #define FDTPROP(a, b, c) fdt_getprop_u32_default((void *)a, b, c, ~0UL) + #define PATHTIM "/panel/display-timings/default" + #define PATHINF "/panel/panel-info" +#endif /* --------------------------------------------------------------------------*/ +#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \ + !defined(CONFIG_SPL_BUILD) +int load_lcdtiming(struct am335x_lcdpanel *panel) +{ + struct am335x_lcdpanel pnltmp; +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + u32 dtbprop; + + if (dtbaddr == ~0UL) { + puts("load_lcdtiming: failed to get 'dtbaddr' from env!\n"); + return -1; + } + memcpy(&pnltmp, (void *)panel, sizeof(struct am335x_lcdpanel)); + + pnltmp.hactive = FDTPROP(dtbaddr, PATHTIM, "hactive"); + pnltmp.vactive = FDTPROP(dtbaddr, PATHTIM, "vactive"); + pnltmp.bpp = FDTPROP(dtbaddr, PATHINF, "bpp"); + pnltmp.hfp = FDTPROP(dtbaddr, PATHTIM, "hfront-porch"); + pnltmp.hbp = FDTPROP(dtbaddr, PATHTIM, "hback-porch"); + pnltmp.hsw = FDTPROP(dtbaddr, PATHTIM, "hsync-len"); + pnltmp.vfp = FDTPROP(dtbaddr, PATHTIM, "vfront-porch"); + pnltmp.vbp = FDTPROP(dtbaddr, PATHTIM, "vback-porch"); + pnltmp.vsw = FDTPROP(dtbaddr, PATHTIM, "vsync-len"); + pnltmp.pup_delay = FDTPROP(dtbaddr, PATHTIM, "pupdelay"); + pnltmp.pon_delay = FDTPROP(dtbaddr, PATHTIM, "pondelay"); + + /* calc. proper clk-divisor */ + dtbprop = FDTPROP(dtbaddr, PATHTIM, "clock-frequency"); + if (dtbprop != ~0UL) + pnltmp.pxl_clk_div = 192000000 / dtbprop; + else + pnltmp.pxl_clk_div = ~0UL; + + /* check polarity of control-signals */ + dtbprop = FDTPROP(dtbaddr, PATHTIM, "hsync-active"); + if (dtbprop == 0) + pnltmp.pol |= HSYNC_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "vsync-active"); + if (dtbprop == 0) + pnltmp.pol |= VSYNC_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-ctrl"); + if (dtbprop == 1) + pnltmp.pol |= HSVS_CONTROL; + dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-edge"); + if (dtbprop == 1) + pnltmp.pol |= HSVS_RISEFALL; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "pixelclk-active"); + if (dtbprop == 0) + pnltmp.pol |= PXCLK_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "de-active"); + if (dtbprop == 0) + pnltmp.pol |= DE_INVERT; +#else + pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL); + pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL); + pnltmp.bpp = getenv_ulong("ds1_bpp", 10, ~0UL); + pnltmp.hfp = getenv_ulong("ds1_hfp", 10, ~0UL); + pnltmp.hbp = getenv_ulong("ds1_hbp", 10, ~0UL); + pnltmp.hsw = getenv_ulong("ds1_hsw", 10, ~0UL); + pnltmp.vfp = getenv_ulong("ds1_vfp", 10, ~0UL); + pnltmp.vbp = getenv_ulong("ds1_vbp", 10, ~0UL); + pnltmp.vsw = getenv_ulong("ds1_vsw", 10, ~0UL); + pnltmp.pxl_clk_div = getenv_ulong("ds1_pxlclkdiv", 10, ~0UL); + pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL); + pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL); + pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL); +#endif + if ( + ~0UL == (pnltmp.hactive) || + ~0UL == (pnltmp.vactive) || + ~0UL == (pnltmp.bpp) || + ~0UL == (pnltmp.hfp) || + ~0UL == (pnltmp.hbp) || + ~0UL == (pnltmp.hsw) || + ~0UL == (pnltmp.vfp) || + ~0UL == (pnltmp.vbp) || + ~0UL == (pnltmp.vsw) || + ~0UL == (pnltmp.pxl_clk_div) || + ~0UL == (pnltmp.pol) || + ~0UL == (pnltmp.pup_delay) || + ~0UL == (pnltmp.pon_delay) + ) { + puts("lcd-settings in env/dtb incomplete!\n"); + printf("display-timings:\n" + "================\n" + "hactive: %d\n" + "vactive: %d\n" + "bpp : %d\n" + "hfp : %d\n" + "hbp : %d\n" + "hsw : %d\n" + "vfp : %d\n" + "vbp : %d\n" + "vsw : %d\n" + "pxlclk : %d\n" + "pol : 0x%08x\n" + "pondly : %d\n", + pnltmp.hactive, pnltmp.vactive, pnltmp.bpp, + pnltmp.hfp, pnltmp.hbp, pnltmp.hsw, + pnltmp.vfp, pnltmp.vbp, pnltmp.vsw, + pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay); + + return -1; + } + debug("lcd-settings in env complete, taking over.\n"); + memcpy((void *)panel, + (void *)&pnltmp, + sizeof(struct am335x_lcdpanel)); + + return 0; +} + +#ifdef CONFIG_USE_FDT +static int load_devicetree(void) +{ + char *dtbname = getenv("dtb"); + char *dtbdev = getenv("dtbdev"); + char *dtppart = getenv("dtbpart"); + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + loff_t dtbsize; + + if (!dtbdev || !dtbdev) { + puts("load_devicetree: <dtbdev>/<dtbpart> missing.\n"); + return -1; + } + + if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) { + puts("load_devicetree: set_blk_dev failed.\n"); + return -1; + } + if (dtbname && dtbaddr != ~0UL) { + if (fs_read(dtbname, dtbaddr, 0, 0, &dtbsize) == 0) { + gd->fdt_blob = (void *)dtbaddr; + gd->fdt_size = dtbsize; + debug("loaded %d bytes of dtb onto 0x%08x\n", + (u32)dtbsize, dtbaddr); + return dtbsize; + } + puts("load_devicetree: load dtb failed,file does not exist!\n"); + } + + puts("load_devicetree: <dtb>/<dtbaddr> missing!\n"); + return -1; +} + +static const char *dtbmacaddr(u32 ifno) +{ + int node, len; + char enet[16]; + const char *mac; + const char *path; + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("dtbmacaddr: failed to get 'dtbaddr' from env!\n"); + return NULL; + } + + node = fdt_path_offset((void *)dtbaddr, "/aliases"); + if (node < 0) + return NULL; + + sprintf(enet, "ethernet%d", ifno); + path = fdt_getprop((void *)dtbaddr, node, enet, NULL); + if (!path) { + printf("no alias for %s\n", enet); + return NULL; + } + + node = fdt_path_offset((void *)dtbaddr, path); + mac = fdt_getprop((void *)dtbaddr, node, "mac-address", &len); + if (mac && is_valid_ether_addr((u8 *)mac)) + return mac; + + return NULL; +} + +static void br_summaryscreen_printdtb(char *prefix, + char *name, + char *suffix) +{ + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + char buf[32] = { 0 }; + const char *nodep = buf; + char *mac = 0; + int nodeoffset; + int len; + + if (dtbaddr == ~0UL) { + puts("br_summaryscreen: failed to get 'dtbaddr' from env!\n"); + return; + } + + if (strcmp(name, "brmac1") == 0) { + mac = (char *)dtbmacaddr(0); + if (mac) + sprintf(buf, "%pM", mac); + } else if (strcmp(name, "brmac2") == 0) { + mac = (char *)dtbmacaddr(1); + if (mac) + sprintf(buf, "%pM", mac); + } else { + nodeoffset = fdt_path_offset((void *)dtbaddr, + "/factory-settings"); + if (nodeoffset < 0) { + puts("no 'factory-settings' in dtb!\n"); + return; + } + nodep = fdt_getprop((void *)dtbaddr, nodeoffset, name, &len); + } + if (nodep && strlen(nodep) > 1) + lcd_printf("%s %s %s", prefix, nodep, suffix); + else + lcd_printf("\n"); +} +int ft_board_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(blob, "/factory-settings"); + if (nodeoffset < 0) { + puts("set bootloader version 'factory-settings' not in dtb!\n"); + return -1; + } + if (fdt_setprop(blob, nodeoffset, "bl-version", + PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) { + puts("set bootloader version 'bl-version' prop. not in dtb!\n"); + return -1; + } + return 0; +} +#else + +static void br_summaryscreen_printenv(char *prefix, + char *name, char *altname, + char *suffix) +{ + char *envval = getenv(name); + if (0 != envval) { + lcd_printf("%s %s %s", prefix, envval, suffix); + } else if (0 != altname) { + envval = getenv(altname); + if (0 != envval) + lcd_printf("%s %s %s", prefix, envval, suffix); + } else { + lcd_printf("\n"); + } +} +#endif +void br_summaryscreen(void) +{ +#ifdef CONFIG_USE_FDT + br_summaryscreen_printdtb(" - B&R -", "order-no", "-\n"); + br_summaryscreen_printdtb(" Serial/Rev :", "serial-no", " /"); + br_summaryscreen_printdtb(" ", "hw-revision", "\n"); + br_summaryscreen_printdtb(" MAC (IF1) :", "brmac1", "\n"); + br_summaryscreen_printdtb(" MAC (IF2) :", "brmac2", "\n"); + lcd_puts(" Bootloader : " PLAIN_VERSION "\n"); + lcd_puts("\n"); +#else + br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n"); + br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n"); + br_summaryscreen_printenv(" MAC (IF1) :", "br_mac1", "ethaddr", "\n"); + br_summaryscreen_printenv(" MAC (IF2) :", "br_mac2", 0, "\n"); + lcd_puts(" Bootloader : " PLAIN_VERSION "\n"); + lcd_puts("\n"); +#endif +} + +void lcdpower(int on) +{ + u32 pin, swval, i; +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("lcdpower: failed to get 'dtbaddr' from env!\n"); + return; + } + pin = FDTPROP(dtbaddr, PATHINF, "pwrpin"); +#else + pin = getenv_ulong("ds1_pwr", 16, ~0UL); +#endif + if (pin == ~0UL) { + puts("no pwrpin in dtb/env, cannot powerup display!\n"); + return; + } + + for (i = 0; i < 3; i++) { + if (pin != 0) { + swval = pin & 0x80 ? 0 : 1; + if (on) + gpio_direction_output(pin & 0x7F, swval); + else + gpio_direction_output(pin & 0x7F, !swval); + + debug("switched pin %d to %d\n", pin & 0x7F, swval); + } + pin >>= 8; + } +} + +vidinfo_t panel_info = { + .vl_col = 1366, /* + * give full resolution for allocating enough + * memory + */ + .vl_row = 768, + .vl_bpix = 5, + .priv = 0 +}; + +void lcd_ctrl_init(void *lcdbase) +{ + struct am335x_lcdpanel lcd_panel; +#ifdef CONFIG_USE_FDT + /* TODO: is there a better place to load the dtb ? */ + load_devicetree(); +#endif + memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel)); + if (load_lcdtiming(&lcd_panel) != 0) + return; + + lcd_panel.panel_power_ctrl = &lcdpower; + + if (0 != am335xfb_init(&lcd_panel)) + printf("ERROR: failed to initialize video!"); + /* + * modifiy panel info to 'real' resolution, to operate correct with + * lcd-framework. + */ + panel_info.vl_col = lcd_panel.hactive; + panel_info.vl_row = lcd_panel.vactive; + + lcd_set_flush_dcache(1); +} + +void lcd_enable(void) +{ +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("lcdpower: failed to get 'dtbaddr' from env!\n"); + return; + } + unsigned int driver = FDTPROP(dtbaddr, PATHINF, "brightdrv"); + unsigned int bright = FDTPROP(dtbaddr, PATHINF, "brightdef"); + unsigned int pwmfrq = FDTPROP(dtbaddr, PATHINF, "brightfdim"); +#else + unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL); + unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50); + unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL); +#endif + unsigned int tmp; + struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE; + + bright = bright != ~0UL ? bright : 50; + + switch (driver) { + case 0: /* PMIC LED-Driver */ + /* brightness level */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, bright, 0xFF); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x0A, 0xFF); + break; + case 1: /* PWM using timer6 */ + if (pwmfrq != ~0UL) { + timerhw->tiocp_cfg = TCFG_RESET; + udelay(10); + while (timerhw->tiocp_cfg & TCFG_RESET) + ; + tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */ + timerhw->tldr = tmp; + timerhw->tcrr = tmp; + tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright; + timerhw->tmar = tmp; + timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) | + TCLR_CE | TCLR_AR | TCLR_ST); + } else { + puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n"); + } + break; + default: + puts("no suitable backlightdriver in env/dtb!\n"); + break; + } + br_summaryscreen(); +} +#elif CONFIG_SPL_BUILD +#else +#error "LCD-support with a suitable FB-Driver is mandatory !" +#endif /* CONFIG_LCD */ + void blink(u32 blinks, u32 intervall, u32 pin) { gpio_direction_output(pin, 0); @@ -43,6 +454,7 @@ void blink(u32 blinks, u32 intervall, u32 pin) gpio_set_value(pin, 0); } + #ifdef CONFIG_SPL_BUILD void pmicsetup(u32 mpupll) { @@ -115,6 +527,9 @@ void pmicsetup(u32 mpupll) /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + /* Set PWR_EN bit in Status Register */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF); } void set_uart_mux_conf(void) @@ -176,9 +591,9 @@ static struct cpsw_platform_data cpsw_data = { int board_eth_init(bd_t *bis) { int rv = 0; - uint8_t mac_addr[6]; + char mac_addr[6]; + const char *mac = 0; uint32_t mac_hi, mac_lo; - /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); @@ -192,14 +607,19 @@ int board_eth_init(bd_t *bis) #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { - printf("<ethaddr> not set. Validating first E-fuse MAC ... "); - - if (is_valid_ether_addr(mac_addr)) { - printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", - mac_addr[0], mac_addr[1], mac_addr[2], - mac_addr[3], mac_addr[4], mac_addr[5] - ); - eth_setenv_enetaddr("ethaddr", mac_addr); + #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT) + printf("<ethaddr> not set. trying DTB ... "); + mac = dtbmacaddr(0); + #endif + if (!mac) { + printf("<ethaddr> not set. validating E-fuse MAC ... "); + if (is_valid_ether_addr((const u8 *)mac_addr)) + mac = (const char *)mac_addr; + } + + if (mac) { + printf("using: %pM on ", mac); + eth_setenv_enetaddr("ethaddr", (const u8 *)mac); } } writel(MII_MODE_ENABLE, &cdev->miisel); diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 804765a..892311e 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -26,14 +26,13 @@ #include <i2c.h> #include <power/tps65217.h> #include "../common/bur_common.h" +#include <lcd.h> /* -------------------------------------------------------------------------*/ /* -- defines for used GPIO Hardware -- */ -#define KEY (0+4) -#define LCD_PWR (0+5) -#define PUSH_KEY (0+31) -#define USB2SD_NRST (32+29) -#define USB2SD_PWR (96+13) +#define ESC_KEY (0+19) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) /* -------------------------------------------------------------------------*/ /* -- PSOC Resetcontroller Register defines -- */ @@ -46,6 +45,13 @@ /* -- defines for RSTCTRL_CTRLREG -- */ #define RSTCTRL_FORCE_PWR_NEN 0x0404 +#define RSTCTRL_CAN_STB 0x4040 + +#define VXWORKS_BOOTLINE 0x80001100 +#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks" +#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget" + +DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_BUILD) /* TODO: check ram-timing ! */ @@ -107,10 +113,13 @@ void am33xx_spl_board_init(void) &cmper->epwmss0clkctrl, &cmper->epwmss1clkctrl, &cmper->epwmss2clkctrl, + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, 0 }; do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); - + /* setup LCD-Pixel Clock */ + writel(0x2, CM_DPLL + 0x34); /* power-OFF LCD-Display */ gpio_direction_output(LCD_PWR, 0); @@ -121,7 +130,7 @@ void am33xx_spl_board_init(void) /* power-ON 3V3 via Resetcontroller */ oldspeed = i2c_get_bus_speed(); if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { - buf = RSTCTRL_FORCE_PWR_NEN; + buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, (uint8_t *)&buf, sizeof(buf)); i2c_set_bus_speed(oldspeed); @@ -129,15 +138,6 @@ void am33xx_spl_board_init(void) puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); } -#if defined(CONFIG_AM335X_USB0) - /* power on USB2SD Controller */ - gpio_direction_output(USB2SD_PWR, 1); - mdelay(1); - /* give a reset Pulse to USB2SD Controller */ - gpio_direction_output(USB2SD_NRST, 0); - mdelay(1); - gpio_set_value(USB2SD_NRST, 1); -#endif pmicsetup(0); } @@ -166,59 +166,111 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - const unsigned int ton = 250; const unsigned int toff = 1000; unsigned int cnt = 3; unsigned short buf = 0xAAAA; + unsigned char scratchreg = 0; unsigned int oldspeed; - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + /* try to read out some boot-instruction from resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + &scratchreg, sizeof(scratchreg)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } - if (gpio_get_value(KEY)) { + if (gpio_get_value(ESC_KEY)) { do { - /* turn on light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x09, 0xFF); - mdelay(ton); - /* turn off light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x01, 0xFF); + lcd_position_cursor(1, 8); + switch (cnt) { + case 3: + lcd_puts( + "release ESC-KEY to enter SERVICE-mode."); + break; + case 2: + lcd_puts( + "release ESC-KEY to enter DIAGNOSE-mode."); + break; + case 1: + lcd_puts( + "release ESC-KEY to enter BOOT-mode. "); + break; + } mdelay(toff); cnt--; - if (!gpio_get_value(KEY) && + if (!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && 2 == cnt) { + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); + cnt = 4; + break; + } else if (!gpio_get_value(ESC_KEY) && gpio_get_value(PUSH_KEY) && 1 == cnt) { - puts("updating from USB ...\n"); + lcd_position_cursor(1, 8); + lcd_puts( + "updating U-BOOT from USB ... "); setenv("bootcmd", "run usbupdate"); + cnt = 4; + break; + } else if ((!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0) || + (gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0)) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; break; - } else if (!gpio_get_value(KEY)) { + } else if (!gpio_get_value(ESC_KEY)) { break; } } while (cnt); + } else if (scratchreg == 0xCC) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting vxworks from network ... "); + setenv("bootcmd", "run netboot"); + cnt = 4; + } else if (scratchreg == 0xCD) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; + } else if (scratchreg == 0xCE) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting AR from eMMC ... "); + setenv("bootcmd", "run mmcboot"); + cnt = 4; } + lcd_position_cursor(1, 8); switch (cnt) { case 0: - puts("3 blinks ... entering BOOT mode.\n"); + lcd_puts("entering BOOT-mode. "); + setenv("bootcmd", "run defaultAR"); buf = 0x0000; break; case 1: - puts("2 blinks ... entering DIAGNOSE mode.\n"); + lcd_puts("entering DIAGNOSE-mode. "); buf = 0x0F0F; break; case 2: - puts("1 blinks ... entering SERVICE mode.\n"); + lcd_puts("entering SERVICE mode. "); buf = 0xB4B4; break; case 3: - puts("0 blinks ... entering RUN mode.\n"); + lcd_puts("loading OS... "); buf = 0x0404; break; } - mdelay(ton); - /* turn on light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x09, 0xFF); /* write bootinfo into scratchregister of resetcontroller */ oldspeed = i2c_get_bus_speed(); if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { @@ -228,6 +280,30 @@ int board_late_init(void) } else { puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); } + /* setup vxworks bootline */ + char *vxworksbootline = (char *)VXWORKS_BOOTLINE; + + /* setup default IP, in case if there is nothing in environment */ + if (!getenv("ipaddr")) { + setenv("ipaddr", "192.168.60.1"); + setenv("netmask", "255.255.255.0"); + setenv("serverip", "192.168.60.254"); + setenv("gatewayip", "192.168.60.254"); + puts("net: had no IP! made default setup.\n"); + } + + sprintf(vxworksbootline, + "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x", + DEFAULT_BOOTLINE, + getenv("serverip"), + getenv("ipaddr"), getenv("netmask"), + getenv("gatewayip"), + VXWORKS_USER, + (unsigned int) gd->fb_base-0x20, + (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), + (u32)getenv_ulong("vx_romfsbase", 16, 0), + (u32)getenv_ulong("vx_romfssize", 16, 0)); + /* * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does * expect that vectors are there, original u-boot moves them to _start diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index ecb2e7a..9f89b5e 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -16,23 +16,17 @@ #include <asm/io.h> #include <i2c.h> -static struct module_pin_mux usb0_pin_mux[] = { - {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, - /* USB0 DrvBus Receiver disable (from romcode 0x20) */ - {OFFSET(usb0_drvvbus), (MODE(0))}, - /* USB1 DrvBus as GPIO due to HW-Workaround */ - {OFFSET(usb1_drvvbus), (MODE(7))}, - {-1}, -}; -static struct module_pin_mux spi1_pin_mux[] = { +static struct module_pin_mux spi0_pin_mux[] = { /* SPI1_SCLK */ - {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_D0 */ - {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_D1 */ - {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_CS0 */ - {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, + /* SPI1_CS1 */ + {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, {-1}, }; @@ -53,30 +47,34 @@ static struct module_pin_mux dcan1_pin_mux[] = { }; static struct module_pin_mux gpios[] = { - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, - /* GPIO0_4 (SPI D1) - TA602 */ - {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ - {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* GPIO0_7 (PWW0 OUT) - CAN TERM */ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ - {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, - /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_19 (DMA_INTR0) - TA602 */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, /* GPIO0_30 (GPMC_WAIT0) - TA601 */ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO1_29 (gpmc_csn0) - MMC nRST */ + {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)}, /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO2_4 (GPMC_nWE) - TST_BAST */ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, + /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ @@ -126,6 +124,10 @@ static struct module_pin_mux mii1_pin_mux[] = { }; static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ @@ -187,8 +189,7 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(usb0_pin_mux); - configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); configure_module_pin_mux(dcan0_pin_mux); configure_module_pin_mux(dcan1_pin_mux); configure_module_pin_mux(mmc1_pin_mux); diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index c0178e7..9402aa4 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -27,15 +27,15 @@ #include <i2c.h> #include <power/tps65217.h> #include "../common/bur_common.h" +#include <lcd.h> +#include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; /* --------------------------------------------------------------------------*/ /* -- defines for GPIO -- */ -#define ETHLED_ORANGE (96+16) /* GPIO3_16 */ #define REPSWITCH (0+20) /* GPIO0_20 */ - #if defined(CONFIG_SPL_BUILD) /* TODO: check ram-timing ! */ static const struct ddr_data ddr3_data = { @@ -82,7 +82,6 @@ static const struct ctrl_ioregs ddr3_ioregs = { int spl_start_uboot(void) { if (0 == gpio_get_value(REPSWITCH)) { - blink(5, 125, ETHLED_ORANGE); mdelay(1000); printf("SPL: entering u-boot instead kernel image.\n"); return 1; @@ -96,7 +95,35 @@ static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { - pmicsetup(1000); + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ + struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + + /* + * in TRM they write a reset value of 1 (=CLK_M_OSC) for the + * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set + * the source of timer6 clk to CLK_M_OSC + */ + writel(0x01, &cmdpll->clktimer6clk); + + /* enable additional clocks of modules which are accessed later */ + u32 *const clk_domains[] = { + &cmper->lcdcclkstctrl, + 0 + }; + + u32 *const clk_modules_tsspecific[] = { + &cmper->lcdclkctrl, + &cmper->timer5clkctrl, + &cmper->timer6clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); + + /* setup LCD-Pixel Clock */ + writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ + + pmicsetup(0); } const struct dpll_params *get_dpll_ddr_params(void) @@ -116,6 +143,9 @@ void sdram_init(void) /* Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND gpmc_init(); @@ -126,24 +156,12 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - gpio_direction_output(ETHLED_ORANGE, 0); - if (0 == gpio_get_value(REPSWITCH)) { - printf("\n\n\n" - "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" - "!!!!!!! recovery switch activated !!!!!!!\n" - "!!!!!!! running usbupdate !!!!!!!\n" - "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n"); - setenv("bootcmd", "sleep 2; run netupdate;"); + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); } - - printf("turning on display power+backlight ... "); - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1, - 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2, - 0x62, TPS65217_MASK_ALL_BITS); /* 100% */ - printf("ok.\n"); - return 0; } #endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 0ba25ee..2c87a63 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -25,6 +25,13 @@ static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, {-1}, }; +static struct module_pin_mux uart1_pin_mux[] = { + /* UART0_RXD */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; #ifdef CONFIG_MMC static struct module_pin_mux mmc1_pin_mux[] = { {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ @@ -131,9 +138,9 @@ static struct module_pin_mux gpIOs[] = { {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ - {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */ + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ + {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, @@ -168,7 +175,14 @@ static struct module_pin_mux gpIOs[] = { {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, - +#ifndef CONFIG_NAND + /* GPIO2_3 - NAND_OE */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_4 - NAND_WEN */ + {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_5 - NAND_BE_CLE */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, +#endif {-1}, }; @@ -229,5 +243,6 @@ void enable_board_pin_mux(void) #endif configure_module_pin_mux(spi0_pin_mux); configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(uart1_pin_mux); configure_module_pin_mux(gpIOs); } diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 5897318..20db812 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -143,5 +143,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif return rc; } diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig new file mode 100644 index 0000000..3380ed3 --- /dev/null +++ b/board/birdland/bav335x/Kconfig @@ -0,0 +1,33 @@ +if TARGET_BAV335X + +config SYS_BOARD + default "bav335x" + +config SYS_VENDOR + default "birdland" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "bav335x" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + +config BAV_VERSION + int "BAV335x Version (1=A, 2=B)" + range 1 2 + help + The BAV335x has various version of the board. Rev.A (mostly obsolete) + used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY. + Overwrite this if you have an older Rev.A and want ethernet support. + +endif diff --git a/board/birdland/bav335x/MAINTAINERS b/board/birdland/bav335x/MAINTAINERS new file mode 100644 index 0000000..45dcfcb --- /dev/null +++ b/board/birdland/bav335x/MAINTAINERS @@ -0,0 +1,13 @@ +BAV335x BOARD +M: Gilles Gameiro <gilles@gigadevices.com> +S: Maintained +F: include/configs/bav335x.h +F: board/birdland/bav335x/Kconfig +F: board/birdland/bav335x/Makefile +F: board/birdland/bav335x/README +F: board/birdland/bav335x/board.c +F: board/birdland/bav335x/board.h +F: board/birdland/bav335x/mux.c +F: board/birdland/bav335x/u-boot.lds +F: configs/birdland_bav335a_defconfig +F: configs/birdland_bav335b_defconfig diff --git a/board/birdland/bav335x/Makefile b/board/birdland/bav335x/Makefile new file mode 100644 index 0000000..2fc5614 --- /dev/null +++ b/board/birdland/bav335x/Makefile @@ -0,0 +1,11 @@ +# +# Makefile +# +# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/birdland/bav335x/README b/board/birdland/bav335x/README new file mode 100644 index 0000000..08c73ee --- /dev/null +++ b/board/birdland/bav335x/README @@ -0,0 +1,31 @@ +Summary +======= + +This document covers various features of the 'BAV335x' board build. +For more information about this board, visit http://birdland.com/oem + + +Hardware +======== + +The binary produced supports the bav335x Rev.A with 10/100 MB PHY +and Rev.B (default) with GB ethernet PHY. +If the BAV335x EEPROM is populated and programmed, the board will +automatically detect the version and extract proper serial# and +mac address from the EE. + + +Customization +============= + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c new file mode 100644 index 0000000..d1e1c8c --- /dev/null +++ b/board/birdland/bav335x/board.c @@ -0,0 +1,430 @@ +/* + * board.c + * + * Board functions for Birdland Audio BAV335x Network Processor + * + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include <environment.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 + +static __maybe_unused struct ctrl_dev *cdev = + (struct ctrl_dev *)CTRL_DEVICE_BASE; + + + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct board_eeconfig *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) + return -ENODEV; + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct board_eeconfig))) + return -EIO; + + if (header->magic != BOARD_MAGIC) { + /* read the i2c eeprom again using only a 1 byte address */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct board_eeconfig))) + return -EIO; + + if (header->magic != BOARD_MAGIC) + return -EINVAL; + } + return 0; +} + + + + +enum board_type get_board_type(bool debug) +{ + int ecode; + struct board_eeconfig header; + + ecode = read_eeprom(&header); + if (ecode == 0) { + if (header.version[1] == 'A') { + if (debug) + puts("=== Detected Board model BAV335x Rev.A"); + return BAV335A; + } else if (header.version[1] == 'B') { + if (debug) + puts("=== Detected Board model BAV335x Rev.B"); + return BAV335B; + } else if (debug) { + puts("### Un-known board model in serial-EE\n"); + } + } else if (debug) { + switch (ecode) { + case -ENODEV: + puts("### Board doesn't have a serial-EE\n"); + break; + case -EINVAL: + puts("### Board serial-EE signature is incorrect.\n"); + break; + default: + puts("### IO Error reading serial-EE.\n"); + break; + } + } + +#if (CONFIG_BAV_VERSION == 1) + if (debug) + puts("### Selecting BAV335A as per config\n"); + return BAV335A; +#elif (CONFIG_BAV_VERSION == 2) + if (debug) + puts("### Selecting BAV335B as per config\n"); + return BAV335B; +#endif +#if (NOT_DEFINED == 2) +#error "SHOULD NEVER DISPLAY THIS" +#endif + + if (debug) + puts("### Defaulting to model BAV335x Rev.B\n"); + return BAV335B; +} + + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +static const struct ddr_data ddr3_bav335x_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + + +static struct emif_regs ddr3_bav335x_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* debug print detect status */ + (void)get_board_type(true); + + /* Get the frequency */ + /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */ + dpll_mpu_opp100.m = MPUPLL_M_1000; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* Set the USB Current Limit */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + TPS65217_USB_INPUT_CUR_LIMIT_1800MA, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("! tps65217_reg_write: could not set USB limit\n"); + + /* Set the Core Voltage (DCDC3) to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("! tps65217_reg_write: could not set Core Voltage\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set the MPU Voltage (DCDC2) */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, + TPS65217_DCDC_VOLT_SEL_1325MV)) { + puts("! tps65217_reg_write: could not set MPU Voltage\n"); + return; + } + + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) + puts("! tps65217_reg_write: could not set LDO3\n"); + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) + puts("! tps65217_reg_write: could not set LDO4\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr_bone_black; +} + +void set_uart_mux_conf(void) +{ +#if CONFIG_CONS_INDEX == 1 + enable_uart0_pin_mux(); +#elif CONFIG_CONS_INDEX == 2 + enable_uart1_pin_mux(); +#elif CONFIG_CONS_INDEX == 3 + enable_uart2_pin_mux(); +#elif CONFIG_CONS_INDEX == 4 + enable_uart3_pin_mux(); +#elif CONFIG_CONS_INDEX == 5 + enable_uart4_pin_mux(); +#elif CONFIG_CONS_INDEX == 6 + enable_uart5_pin_mux(); +#endif +} + +void set_mux_conf_regs(void) +{ + enum board_type board; + + board = get_board_type(false); + enable_board_pin_mux(board); +} + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + + +void sdram_init(void) +{ + config_ddr(400, &ioregs_bonelt, + &ddr3_bav335x_data, + &ddr3_bav335x_cmd_ctrl_data, + &ddr3_bav335x_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "BAV335xB"); + setenv("board_rev", "B"); /* Fix me, but why bother.. */ +#endif + return 0; +} +#endif + + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + + +/* + * This function will: + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int ecode, rv, n; + uint8_t mac_addr[6]; + struct board_eeconfig header; + __maybe_unused enum board_type board; + + /* Default manufacturing address; used when no EE or invalid */ + n = 0; + mac_addr[0] = 0; + mac_addr[1] = 0x20; + mac_addr[2] = 0x18; + mac_addr[3] = 0x1C; + mac_addr[4] = 0x00; + mac_addr[5] = 0x01; + + ecode = read_eeprom(&header); + /* if we have a valid EE, get mac address from there */ + if ((ecode == 0) && + is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) { + memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6); + } + + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + + board = get_board_type(false); + + /* Rev.A uses 10/100 PHY in mii mode */ + if (board == BAV335A) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } + /* Rev.B (default) uses GB PHY in rmii mode */ + else { + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if + = PHY_INTERFACE_MODE_RGMII; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + +#endif + + return n; +} +#endif diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h new file mode 100644 index 0000000..b598ce1 --- /dev/null +++ b/board/birdland/bav335x/board.h @@ -0,0 +1,59 @@ +/* + * board.c + * + * Board functions for Birdland Audio BAV335x Network Processor + * + * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Serial MagicE: AA 55 BA BE */ +#define BOARD_MAGIC 0xBEBA55AA +enum board_type {UNKNOWN, BAV335A, BAV335B}; + + +/* + * The BAV335x may use a built-in read-only serial EEProm. + * The Evaluation board, disables the write-protect so the Serial-EE + * Can be programmed during manufacturing to store fields such as + * a board serial number, ethernet mac address and other user fields. + * Additionally, the Serial-EE can store the specific version of the + * board it runs on, and overwrite the defaults in _defconfig + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct board_eeconfig { + unsigned int magic; + char name[HDR_NAME_LEN]; /* BAV3354 */ + char version[4]; /* 0B20 - Rev.B2 */ + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +enum board_type get_board_type(bool verbose_debug_output); + + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(enum board_type board); + +#endif diff --git a/board/birdland/bav335x/mux.c b/board/birdland/bav335x/mux.c new file mode 100644 index 0000000..f18bfa4 --- /dev/null +++ b/board/birdland/bav335x/mux.c @@ -0,0 +1,190 @@ +/* + * mux.c + * + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + + +/* CPLD registers */ +#define I2C_CPLD_ADDR 0x35 +#define CFG_REG 0x10 + + +void enable_board_pin_mux(enum board_type board) +{ + configure_module_pin_mux(i2c1_pin_mux); + if (board == BAV335A) + configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */ + else + configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */ + + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); +} diff --git a/board/birdland/bav335x/u-boot.lds b/board/birdland/bav335x/u-boot.lds new file mode 100644 index 0000000..fc80f21 --- /dev/null +++ b/board/birdland/bav335x/u-boot.lds @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/birdland/bav335x/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index e8ea256..d46b8db 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -1018,5 +1018,6 @@ int misc_init_r(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + setenv_hex("reset_cause", get_imx_reset_cause()); return 0; } diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 2cd1794..4980bf7 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -5,9 +5,47 @@ */ #include <common.h> +#include <errno.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +int pfuze_mode_init(struct pmic *p, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id, ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + struct pmic *pfuze_common_init(unsigned char i2cbus) { struct pmic *p; diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h index 7a4126c..53cfc99 100644 --- a/board/freescale/common/pfuze.h +++ b/board/freescale/common/pfuze.h @@ -8,5 +8,6 @@ #define __PFUZE_BOARD_HELPER__ struct pmic *pfuze_common_init(unsigned char i2cbus); +int pfuze_mode_init(struct pmic *p, u32 mode); #endif diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 71a395c..01dac72 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -146,8 +146,8 @@ int board_late_init(void) if (!p) return -ENODEV; - /* Turn on Ethernet PHY supply */ - pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE); + /* Turn on Ethernet PHY and LCD supplies */ + pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA); return 0; } diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index efcf4b3..9ece6ec 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -366,22 +366,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 cpurev; - - cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", - (cpurev & 0xFF000) >> 12, - (cpurev & 0x000F0) >> 4, - (cpurev & 0x0000F) >> 0, - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - return 0; -} -#endif - /* * Do not overwrite the console * Use always serial for U-Boot console diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index a90360f..b76e4eb 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -29,6 +29,7 @@ #include <asm/arch/crm_regs.h> #include <pca953x.h> #include <power/pmic.h> +#include <power/pfuze100_pmic.h> #include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -494,11 +495,16 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) int power_init_board(void) { struct pmic *p; + unsigned int ret; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 2f7198d..bb2dd96 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -631,12 +631,16 @@ int board_init(void) int power_init_board(void) { struct pmic *p; - unsigned int reg; + unsigned int reg, ret; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); reg &= ~LDO_VOL_MASK; diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 838ea6c..7c18c90 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -13,13 +13,18 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/spi.h> #include <asm/io.h> #include <linux/sizes.h> #include <common.h> #include <fsl_esdhc.h> +#include <i2c.h> #include <mmc.h> #include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" #include <usb.h> #include <usb/ehci-fsl.h> @@ -40,6 +45,16 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_FAST) + #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) int dram_init(void) @@ -221,6 +236,34 @@ int board_mmc_init(bd_t *bis) return 0; } +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .sda = { + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, + .scl = { + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + return pfuze_mode_init(p, APS_PFM); +} +#endif + #ifdef CONFIG_FEC_MXC int board_eth_init(bd_t *bis) { @@ -247,7 +290,7 @@ static int setup_fec(void) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OTG1 */ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), /* OTG2 */ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -297,6 +340,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + #ifdef CONFIG_FEC_MXC setup_fec(); #endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index a2c9aae..2ff960e 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -199,12 +199,16 @@ static struct i2c_pads_info i2c_pad_info1 = { int power_init_board(void) { struct pmic *p; - unsigned int reg; + unsigned int reg, ret; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + /* Enable power of VGEN5 3V3, needed for SD3 */ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 11472eb..25480e4 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,10 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ -#ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); -#endif - tegra_spl_gpio_direction_output(GPIO_PI3, 0); + gpio_direction_output(GPIO_PI3, 0); } #endif diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig new file mode 100644 index 0000000..8df9421 --- /dev/null +++ b/board/quipos/cairo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_CAIRO + +config SYS_BOARD + default "cairo" + +config SYS_VENDOR + default "quipos" + +config SYS_CONFIG_NAME + default "omap3_cairo" + +endif diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile new file mode 100644 index 0000000..445088f --- /dev/null +++ b/board/quipos/cairo/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 DENX Software Engineering +# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cairo.o diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c new file mode 100644 index 0000000..b97a09a --- /dev/null +++ b/board/quipos/cairo/cairo.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014 DENX + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Derived from code written by Robert Aigner (ra@spiid.net) + * + * Itself derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <netdev.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> +#include <asm/omap_mmc.h> +#include "cairo.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. + */ +u8 omap3_evm_need_extvbus(void) +{ + u8 retval = 0; + + /* TODO: verify if cairo handheld platform needs extvbus programming */ + + return retval; +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_CAIRO(); +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + * + * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6 + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->sharing = SAMSUNG_SHARING; + timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); + timings->ctrla = SAMSUNG_V_ACTIMA_165; + timings->ctrlb = SAMSUNG_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = SAMSUNG_V_MR_165; +} +#endif + +static const struct ns16550_platdata cairo_serial = { + OMAP34XX_UART2, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(cairo_uart) = { + "serial_omap", + &cairo_serial +}; + +/* force SPL booting into U-Boot, not Linux */ +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h new file mode 100644 index 0000000..50734d0 --- /dev/null +++ b/board/quipos/cairo/cairo.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) DENX + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Original code (C) Copyright 2010 + * Robert Aigner (ra@spiid.net) + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _EVM_H_ +#define _EVM_H_ + + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 Cairo board", + "NAND", +}; + +/* + * OMAP3 Cairo handheld hardware revision + */ +enum { + OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */ + OMAP3_CAIRO_BOARD_GEN_2, +}; + +#define MUX_CAIRO() \ +MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \ + (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ + +#endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 6c7f59b..2e17da8 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -82,13 +82,19 @@ int board_init(void) } boot_temp_check(); #endif +#ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE + /* The last few MB of memory can be reserved for secure firmware */ + ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE; + gd->ram_size -= size; + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; +#endif return exynos_init(); } int dram_init(void) { - int i; + unsigned int i; u32 addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { @@ -100,7 +106,7 @@ int dram_init(void) void dram_init_banksize(void) { - int i; + unsigned int i; u32 addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 6f4b8ca..ae41c29 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -427,10 +427,6 @@ int exynos_early_init_f(void) int exynos_init(void) { - /* The last MB of memory is reserved for secure firmware */ - gd->ram_size -= SZ_1M; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; - board_gpio_init(); return 0; diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig new file mode 100644 index 0000000..dd9816e --- /dev/null +++ b/board/sysam/amcore/Kconfig @@ -0,0 +1,22 @@ +if TARGET_AMCORE + +config SYS_CPU + string + default "mcf530x" + +config SYS_BOARD + string + default "amcore" + +config SYS_VENDOR + string + default "sysam" + +config SYS_CONFIG_NAME + string + default "amcore" + +endif + + + diff --git a/board/sysam/amcore/MAINTAINERS b/board/sysam/amcore/MAINTAINERS new file mode 100644 index 0000000..fe5dd9b --- /dev/null +++ b/board/sysam/amcore/MAINTAINERS @@ -0,0 +1,6 @@ +AMCORE BOARD +M: Angelo Dureghello <angelo@sysam.it> +S: Maintained +F: board/sysam/amcore/ +F: include/configs/amcore.h +F: configs/amcore_defconfig diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile new file mode 100644 index 0000000..051186f --- /dev/null +++ b/board/sysam/amcore/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = amcore.o diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c new file mode 100644 index 0000000..42b7c23 --- /dev/null +++ b/board/sysam/amcore/amcore.c @@ -0,0 +1,101 @@ +/* + * Board functions for Sysam AMCORE (MCF5307 based) board + * + * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file copies memory testdram() from sandburst/common/sb_common.c + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +void init_lcd(void) +{ + /* setup for possible K0108 lcd connected on the parallel port */ + sim_t *sim = (sim_t *)(MMAP_SIM); + + out_be16(&sim->par, 0x300); + + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); + + out_be16(&gpio->paddr, 0xfcff); + out_be16(&gpio->padat, 0x0c00); +} + +int checkboard(void) +{ + puts("Board: "); + puts("AMCORE v.001(alpha)\n"); + + init_lcd(); + + return 0; +} + +/* + * in initdram we are here executing from flash + * case 1: + * is with no ACR/flash cache enabled + * nop = 40ns (scope measured) + */ +void fudelay(int usec) +{ + while (usec--) + asm volatile ("nop"); +} + +phys_size_t initdram(int board_type) +{ + u32 dramsize, RC; + + sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC); + + /* + * SDRAM MT48LC4M32B2 details + * Memory block 0: 16 MB of SDRAM at address $00000000 + * Port size: 32-bit port + * + * Memory block 0 wired as follows: + * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 + * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 + * + * Ensure that there is a delay of at least 100 microseconds from + * processor reset to the following code so that the SDRAM is ready + * for commands. + */ + fudelay(100); + + /* + * DCR + * set proper RC as per specification + */ + RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* 0x8000 is the faster option */ + out_be16(&dc->dcr, 0x8200 | RC); + + /* + * DACR0, page mode continuous, CMD on A20 0x0300 + */ + out_be32(&dc->dacr0, 0x00003304); + + dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; + out_be32(&dc->dmr0, dramsize|1); + + /* issue a PRECHARGE ALL */ + out_be32(&dc->dacr0, 0x0000330c); + out_be32((u32 *)0x00000004, 0xbeaddeed); + /* issue AUTOREFRESH */ + out_be32(&dc->dacr0, 0x0000b304); + /* let refresh occour */ + fudelay(1); + + out_be32(&dc->dacr0, 0x0000b344); + out_be32((u32 *)0x00000c00, 0xbeaddeed); + + return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); +} diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk new file mode 100644 index 0000000..d01a8bb --- /dev/null +++ b/board/sysam/amcore/config.mk @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/sysam/amcore/u-boot.lds b/board/sysam/amcore/u-boot.lds new file mode 100644 index 0000000..2f7a241 --- /dev/null +++ b/board/sysam/amcore/u-boot.lds @@ -0,0 +1,87 @@ +/* + * Linker script for Sysam AMCORE board + * + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text : + { + arch/m68k/cpu/mcf530x/start.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.sdata) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss*) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index dfa430e..42b166d 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -326,21 +326,25 @@ static void setup_display(void) reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); - /* select video pll for ldb_di0_clk */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); + /* gate ipu1_di0_clk */ + reg = readl(&ccm->CCGR3); + reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &ccm->CCGR3); - /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */ + /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | + (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | + (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); + + /* enable ipu1_di0_clk */ + reg = readl(&ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &ccm->CCGR3); } #endif /* CONFIG_VIDEO_IPUV3 */ diff --git a/board/warp/Kconfig b/board/warp/Kconfig new file mode 100644 index 0000000..7b569cc --- /dev/null +++ b/board/warp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WARP + +config SYS_BOARD + default "warp" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "warp" + +endif diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS new file mode 100644 index 0000000..ee2114d --- /dev/null +++ b/board/warp/MAINTAINERS @@ -0,0 +1,6 @@ +WaRP BOARD +M: Otavio Salvador <otavio@ossystems.com.br> +S: Maintained +F: board/warp/ +F: include/configs/warp.h +F: configs/warp_defconfig diff --git a/board/warp/Makefile b/board/warp/Makefile new file mode 100644 index 0000000..c555f87 --- /dev/null +++ b/board/warp/Makefile @@ -0,0 +1,8 @@ +# Copyright (C) 2014 O.S. Systems Software LTDA. +# Copyright (C) 2014 Kynetics LLC. +# Copyright (C) 2014 Revolution Robotics, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := warp.o diff --git a/board/warp/warp.c b/board/warp/warp.c new file mode 100644 index 0000000..21ac5e7 --- /dev/null +++ b/board/warp/warp.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. + * Copyright (C) 2014 Kynetics LLC. + * Copyright (C) 2014 Revolution Robotics, Inc. + * + * Author: Otavio Salvador <otavio@ossystems.com.br> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <linux/sizes.h> +#include <common.h> +#include <watchdog.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ + PAD_CTL_LVE) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ + PAD_CTL_LVE) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} + +int board_mmc_init(bd_t *bis) +{ + static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_DEVICE; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: WaRP Board\n"); + + return 0; +} |