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-rw-r--r--board/freescale/m54451evb/m54451evb.c32
-rw-r--r--board/freescale/m54455evb/m54455evb.c90
2 files changed, 66 insertions, 56 deletions
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <spi.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,14 +52,14 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
- if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
- (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+ if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+ (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(200);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
udelay(100);
#endif
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 2a84514..0ca268e 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
@@ -59,33 +60,34 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
udelay(500);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
@@ -105,26 +107,29 @@ int testdram(void)
int ide_preinit(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- gpio->par_feci2c |=
- (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
- GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
- gpio->par_ata |=
- (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
- | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- gpio->par_pci |=
- (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 tmp;
+
+ tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+ setbits_8(&gpio->par_fec, tmp);
+ tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+ (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+ setbits_be16(&gpio->par_feci2c, tmp);
+
+ setbits_be16(&gpio->par_ata,
+ GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+ GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ setbits_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) MMAP_ATA;
+ atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
@@ -136,24 +141,27 @@ void ide_set_reset(int idereset)
}; /* PIO 4 */
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(200000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif
generated by cgit v1.1 at 2024-12-21 00:26:26 +0000