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-rw-r--r--board/gdsys/405ep/405ep.c9
-rw-r--r--board/gdsys/405ep/dlvision-10g.c41
-rw-r--r--board/gdsys/common/osd.c57
3 files changed, 95 insertions, 12 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 86a3ec8..8b80533 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -110,6 +110,11 @@ int board_early_init_f(void)
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+ u16 *reflection_target = &fpga->reflection_low;
+#else
+ u16 *reflection_target = &fpga->reflection_high;
+#endif
/*
* wait for fpga out of reset
*/
@@ -117,9 +122,11 @@ int board_early_init_f(void)
while (1) {
out_le16(&fpga->reflection_low,
REFLECTION_TESTPATTERN);
- if (in_le16(&fpga->reflection_high) ==
+
+ if (in_le16(reflection_target) ==
REFLECTION_TESTPATTERN_INV)
break;
+
udelay(100000);
if (ctr++ > 5) {
gd->fpga_state[k] |=
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index df7fb14..0388541 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -31,6 +31,11 @@
#include "../common/osd.h"
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH2_MC2_PRESENT_N 0x0080
+
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
enum {
UNITTYPE_VIDEO_USER = 0,
UNITTYPE_MAIN_USER = 1,
@@ -60,6 +65,20 @@ enum {
RAM_DDR2_64 = 2,
};
+static unsigned int get_hwver(void)
+{
+ u16 latch3 = in_le16((void *)LATCH3_BASE);
+
+ return latch3 & 0x0003;
+}
+
+static unsigned int get_mc2_present(void)
+{
+ u16 latch2 = in_le16((void *)LATCH2_BASE);
+
+ return !(latch2 & LATCH2_MC2_PRESENT_N);
+}
+
static void print_fpga_info(unsigned dev)
{
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
@@ -206,7 +225,6 @@ static void print_fpga_info(unsigned dev)
*/
int checkboard(void)
{
- unsigned k;
char *s = getenv("serial#");
printf("Board: ");
@@ -220,20 +238,27 @@ int checkboard(void)
puts("\n");
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- print_fpga_info(k);
+ print_fpga_info(0);
+ if (get_mc2_present())
+ print_fpga_info(1);
return 0;
}
int last_stage_init(void)
{
- unsigned k;
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+ u16 versions = in_le16(&fpga->versions);
+
+ if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
+ return 0;
+
+ if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
+ osd_probe(0);
- for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
- if (!get_fpga_state(k)
- || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
- osd_probe(k);
+ if (get_mc2_present() &&
+ (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
+ osd_probe(1);
return 0;
}
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 4d8c046..5065f9d 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -30,7 +30,12 @@
#define CH7301_I2C_ADDR 0x75
#define ICS8N3QV01_I2C_ADDR 0x6E
-#define ICS8N3QV01_FREF 114285
+#define ICS8N3QV01_FREF 114285000
+#define ICS8N3QV01_FREF_LL 114285000LL
+#define ICS8N3QV01_F_DEFAULT_0 156250000LL
+#define ICS8N3QV01_F_DEFAULT_1 125000000LL
+#define ICS8N3QV01_F_DEFAULT_2 100000000LL
+#define ICS8N3QV01_F_DEFAULT_3 25175000LL
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
@@ -150,6 +155,41 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
#endif
#ifdef CONFIG_SYS_ICS8N3QV01
+
+static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+{
+ unsigned long long n;
+ unsigned long long mint;
+ unsigned long long mfrac;
+ u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+ unsigned long long fout_calc;
+
+ if (index > 3)
+ return 0;
+
+ reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
+ reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
+ reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
+ reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
+ reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+
+ mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+ mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+ | (reg_d >> 7);
+ n = reg_d & 0x7f;
+
+ fout_calc = (mint * ICS8N3QV01_FREF_LL
+ + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+ + ICS8N3QV01_FREF_LL / 524288LL
+ + n / 2)
+ / n
+ * 1000000
+ / (1000000 - 100);
+
+ return fout_calc;
+}
+
+
static void ics8n3qv01_calc_parameters(unsigned int fout,
unsigned int *_mint, unsigned int *_mfrac,
unsigned int *_n)
@@ -160,7 +200,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout,
unsigned int mint;
unsigned long long mfrac;
- n = 2550000000U / fout;
+ n = (2215000000U + fout / 2) / fout;
if ((n & 1) && (n > 5))
n -= 1;
@@ -184,9 +224,18 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
unsigned int n;
unsigned int mint;
unsigned int mfrac;
+ unsigned int fout_calc;
+ unsigned long long fout_prog;
+ long long off_ppm;
u8 reg0, reg4, reg8, reg12, reg18, reg20;
- ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+ fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+ off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
+ / ICS8N3QV01_F_DEFAULT_1;
+ printf(" PLL is off by %lld ppm\n", off_ppm);
+ fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
+ / ICS8N3QV01_F_DEFAULT_1;
+ ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
reg0 |= (mint & 0x1f) << 1;
@@ -327,6 +376,8 @@ int osd_probe(unsigned screen)
out_le16(&osd->control, 0x0049);
out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
+ out_le16(&osd->x_pos, 0x007f);
+ out_le16(&osd->y_pos, 0x005f);
return 0;
}
generated by cgit v1.1 at 2024-11-14 21:43:09 +0000