diff options
Diffstat (limited to 'board')
155 files changed, 6912 insertions, 5462 deletions
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 54f9b64..e98244b 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -59,8 +59,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - /* Enable Ctrlc */ - console_init_f(); /* Correct IRDA resistor problem / Set PA23_TXD in Output */ writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer); @@ -269,9 +267,9 @@ int drv_video_init(void) display_height = 256; printf("%ld x %ld pixel matrix\n", display_width, display_height); - /* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */ - csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) | - AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) | + /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */ + csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) | + AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) | AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; writel(csr, &mc->smc.csr[2]); diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index 62ed6fb..84b2060 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -244,9 +244,6 @@ int board_init(void) writel(pin, &pio->piod.odr); writel(pin, &pio->piod.owdr); - /* Enable Ctrlc */ - console_init_f(); - gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index 34ede87..f2b4284 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -165,8 +165,8 @@ static void board_setup_sdram(void) static void setup_iomux_uart3(void) { - mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7); - mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7); + mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7); + mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7); } static void setup_iomux_i2c(void) @@ -247,7 +247,7 @@ int board_early_init_f(void) /* enable clocks */ writel(readl(&ccm->cgr0) | MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EDIO_MASK | MXC_CCM_CGR0_EPIT1_MASK, &ccm->cgr0); diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg index 3b9c53f..55be3a3 100644 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -21,8 +21,8 @@ # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, # MA 02110-1301 USA # -# Refer docs/README.kwimage for more details about how-to configure -# and create kirkwood boot image +# Refer to doc/README.kwbimage for more details about how-to +# configure and create kirkwood boot images. # # Boot Media configurations diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c deleted file mode 100644 index 76626f0..0000000 --- a/board/apollon/apollon.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics. - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <netdev.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/mem.h> -#include <asm/mach-types.h> - -void wait_for_command_complete(unsigned int wd_base); - -DECLARE_GLOBAL_DATA_PTR; - -#define write_config_reg(reg, value) \ -do { \ - writeb(value, reg); \ -} while (0) - -#define mask_config_reg(reg, mask) \ -do { \ - char value = readb(reg) & ~(mask); \ - writeb(value, reg); \ -} while (0) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRM, finish GPMC */ - - gd->bd->bi_arch_number = 919; - /* adress of boot parameters */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100); - - return 0; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with sram stack. - **********************************************************/ -void s_init(void) -{ - watchdog_init(); - set_muxconf_regs(); - delay(100); - - peripheral_enable(); - icache_enable(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - return (0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * The ROM takes care of the secure one. Of the 3 GP ones, - * 1 can reset us directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); - -#define MPU_WD_CLOCKED 1 -#if MPU_WD_CLOCKED - /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ - __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR); - - __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); -#endif -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:board_eth_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - int cnt = 20; - - __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */ - - __raw_writew(0x0, LAN_RESET_REGISTER); - do { - __raw_writew(0x1, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto eth_reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); - - cnt = 20; - - do { - __raw_writew(0x0, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto eth_reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); - udelay(1000); - - mask_config_reg(ETH_CONTROL_REG, 0x01); - udelay(1000); - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -eth_reset_err_out: -#endif - return rc; -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - unsigned int size; - u32 mtype, btype; -#define NOT_EARLY 0 - - btype = get_board_type(); - mtype = get_mem_type(); - - display_board_info(btype); - - if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { - /* init other chip select */ - do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); - } - - size = get_sdr_cs_size(SDRC_CS0_OSET); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size; -#if CONFIG_NR_DRAM_BANKS > 1 - size = get_sdr_cs_size(SDRC_CS1_OSET); - - gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; - gd->bd->bi_dram[1].size = size; -#endif - - return 0; -} - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware - *********************************************************/ -void set_muxconf_regs(void) -{ - muxSetupSDRC(); - muxSetupGPMC(); - muxSetupUsb0(); /* USB Device */ - muxSetupUsbHost(); /* USB Host */ - muxSetupUART1(); - muxSetupLCD(); - muxSetupMMCSD(); - muxSetupTouchScreen(); -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void peripheral_enable(void) -{ - unsigned int v, if_clks = 0, func_clks = 0; - - /* Enable GP2 timer. */ - if_clks |= BIT4 | BIT3; - func_clks |= BIT4 | BIT3; - /* Sys_clk input OMAP2420_GPT2 */ - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CONFIG_SYS_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - /* Interface clocks on */ - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; - __raw_writel(v, CM_ICLKEN1_CORE); - /* Functional Clocks on */ - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif -} - -/**************************************** - * Routine: muxSetupUsb0 (ostboot) - * Description: Setup usb muxing - *****************************************/ -void muxSetupUsb0(void) -{ - mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f); -} - -/**************************************** - * Routine: muxSetupUSBHost (ostboot) - * Description: Setup USB Host muxing - *****************************************/ -void muxSetupUsbHost(void) -{ - /* V19 */ - write_config_reg(CONTROL_PADCONF_USB1_RCV, 1); - /* W20 */ - write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1); - /* N14 */ - write_config_reg(CONTROL_PADCONF_GPIO69, 3); - /* P15 */ - write_config_reg(CONTROL_PADCONF_GPIO70, 3); - /* L18 */ - write_config_reg(CONTROL_PADCONF_GPIO102, 3); - /* L19 */ - write_config_reg(CONTROL_PADCONF_GPIO103, 3); - /* K15 */ - write_config_reg(CONTROL_PADCONF_GPIO104, 3); - /* K14 */ - write_config_reg(CONTROL_PADCONF_GPIO105, 3); -} - -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -void muxSetupUART1(void) -{ - /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); - /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); - /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_TX, 0); - /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_RX, 0); -} - -/**************************************** - * Routine: muxSetupLCD (ostboot) - * Description: Setup lcd muxing - *****************************************/ -void muxSetupLCD(void) -{ - /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D0, 0); - /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D1, 0); - /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D2, 0); - /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D3, 0); - /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D4, 0); - /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D5, 0); - /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D6, 0); - /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D7, 0); - /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D8, 0); - /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D9, 0); - /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D10, 0); - /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D11, 0); - /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D12, 0); - /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D13, 0); - /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D14, 0); - /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D15, 0); - /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D16, 0); - /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D17, 0); - /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0); - /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0); - /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0); - /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0); -} - -/**************************************** - * Routine: muxSetupMMCSD (ostboot) - * Description: set up MMC muxing - *****************************************/ -void muxSetupMMCSD(void) -{ - /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0); - /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0); - /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CMD, 0); - /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0); - /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0); - /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0); - /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0); - /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0); - /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0); - /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0); - /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0); - /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0); -} - -/****************************************** - * Routine: muxSetupTouchScreen (ostboot) - * Description: Set up touch screen muxing - *******************************************/ -void muxSetupTouchScreen(void) -{ - /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0); - /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0); - /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0); - /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0); -#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1 - /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_GPIO85, 3); -} - -/*************************************************************** - * Routine: muxSetupGPMC (ostboot) - * Description: Configures balls which cam up in protected mode - ***************************************************************/ -void muxSetupGPMC(void) -{ - /* gpmc_io_dir, MCR */ - volatile unsigned int *MCR = (unsigned int *) 0x4800008C; - *MCR = 0x19000000; - - /* NOR FLASH CS0 */ - /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ - write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0); - /* MPDB(Multi Port Debug Port) CS1 */ - /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0); - /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0); - /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0); - /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0); - /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0); - /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0); - /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0); -} - -/**************************************************************** - * Routine: muxSetupSDRC (ostboot) - * Description: Configures balls which come up in protected mode - ****************************************************************/ -void muxSetupSDRC(void) -{ - /* It's set by IPL */ -} diff --git a/board/apollon/config.mk b/board/apollon/config.mk deleted file mode 100644 index 66005d4..0000000 --- a/board/apollon/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2005-2007 -# Samsung Electronics -# -# Samsung December board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# December has 1 bank of 128MB mDDR-SDRAM on CS0 -# December has 1 bank of 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x83e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -#CONFIG_SYS_TEXT_BASE = 0x40270000 - -# Handy to get symbols to debug ROM version. -#CONFIG_SYS_TEXT_BASE = 0x0 -#CONFIG_SYS_TEXT_BASE = 0x08000000 diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S deleted file mode 100644 index f066fe4..0000000 --- a/board/apollon/lowlevel_init.S +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include "mem.h" - -#define APOLLON_CS0_BASE 0x00000000 - -#ifdef PRCM_CONFIG_I -#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 -#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 -#define SDRC_RFR_CTRL_0_VAL 0x00044C01 -#elif defined(PRCM_CONFIG_II) -#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 -#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C -#define SDRC_RFR_CTRL_0_VAL 0x00030001 -#endif - -#define SDRAM_BASE_ADDRESS 0x80008000 - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - -#ifdef CONFIG_SYS_NOR_BOOT - /* Check running in SDRAM */ - mov r0, pc, lsr #28 - cmp r0, #8 - beq prcm_setup - -flash_setup: - /* In Flash */ - ldr r0, =WD2_BASE - ldr r1, =WD_UNLOCK1 - str r1, [r0, #WSPR] - - ldr r1, =WD_UNLOCK2 - str r1, [r0, #WSPR] - - /* Pin muxing for SDRC */ - mov r1, #0x00 - ldr r0, =0x480000A1 /* ball C12, mode 0 */ - strb r1, [r0] - - ldr r0, =0x48000032 /* ball D11, mode 0 */ - strb r1, [r0] - - ldr r0, =0x480000A3 /* ball B13, mode 0 */ - strb r1, [r0] - - /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE - ldr r1, =0x00000010 - str r1, [r0, #0x10] - - ldr r1, =0x00000100 - str r1, [r0, #0x44] - - /* SDRC CS0 configuration */ - ldr r1, =0x00d04011 - str r1, [r0, #0x80] - - ldr r1, =SDRC_ACTIM_CTRLA_0_VAL - str r1, [r0, #0x9C] - - ldr r1, =SDRC_ACTIM_CTRLB_0_VAL - str r1, [r0, #0xA0] - - ldr r1, =SDRC_RFR_CTRL_0_VAL - str r1, [r0, #0xA4] - - ldr r1, =0x00000041 - str r1, [r0, #0x70] - - /* Manual command sequence */ - ldr r1, =0x00000007 - str r1, [r0, #0xA8] - - ldr r1, =0x00000000 - str r1, [r0, #0xA8] - - ldr r1, =0x00000001 - str r1, [r0, #0xA8] - - ldr r1, =0x00000002 - str r1, [r0, #0xA8] - str r1, [r0, #0xA8] - - /* - * CS0 SDRC Mode register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - ldr r1, =0x00000032 - str r1, [r0, #0x84] - - /* Note: You MUST set EMR values */ - /* EMR1 & EMR2 */ - ldr r1, =0x00000000 - str r1, [r0, #0x88] - str r1, [r0, #0x8C] - -#ifdef OLD_SDRC_DLLA_CTRL - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00007306 - str r1, [r0, #0x60] - - ldr r1, =0x00007303 - str r1, [r0, #0x60] -#else - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x60] - - ldr r1, =0x00000503 - str r1, [r0, #0x60] -#endif - -#ifdef __BROKEN_FEATURE__ - /* SDRC_DLLB_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x68] - - ldr r1, =0x00000503 - str r1, [r0, #0x68] -#endif - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b - - /* Setup base address */ - ldr r0, =0x00000000 /* NOR address */ - ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */ - ldr r2, =0x20000 /* Size: 128KB */ - -copy_loop: - ldmia r0!, {r3-r10} - stmia r1!, {r3-r10} - cmp r0, r2 - ble copy_loop - - ldr r1, =SDRAM_BASE_ADDRESS - mov lr, pc - mov pc, r1 -#endif - -prcm_setup: - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ - bic r1, r1, #0x03 - orr r1, r1, #0x02 - str r1, [r0, #0x544] - - ldr r1, [r0, #0x500] - bic r1, r1, #0x03 - orr r1, r1, #0x01 - str r1, [r0, #0x500] - - ldr r1, [r0, #0x140] - bic r1, r1, #0x1f - orr r1, r1, #0x02 - str r1, [r0, #0x140] - -#ifdef PRCM_CONFIG_I - ldr r1, =0x000003C3 -#else - ldr r1, =0x00000343 -#endif - str r1, [r0, #0x840] - - ldr r1, =0x00000002 - str r1, [r0, #0x340] - - ldr r1, =CM_CLKSEL1_CORE -#ifdef PRCM_CONFIG_I - ldr r2, =0x08300C44 -#else - ldr r2, =0x04600C26 -#endif - str r2, [r1] - - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x01 - bne clkvalid - - b . - -clkvalid: - mov r1, #0x01 - str r1, [r0, #0x080] - -waitvalid: - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x00 - bne waitvalid - - ldr r0, =CM_CLKSEL1_PLL -#ifdef PRCM_CONFIG_I - ldr r1, =0x01837100 -#else - ldr r1, =0x01832100 -#endif - str r1, [r0] - - ldr r0, =PRCM_CLKCFG_CTRL - mov r1, #0x01 - str r1, [r0] - mov r6, #0x50 -loop1: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop1 - - ldr r0, =CM_CLKEN_PLL - mov r1, #0x0f - str r1, [r0] - - mov r6, #0x100 -loop2: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop2 - - ldr r0, =0x48008200 - ldr r1, =0xbfffffff - str r1, [r0] - - ldr r0, =0x48008210 - ldr r1, =0xfffffff9 - str r1, [r0] - - ldr r0, =0x4806a004 - ldr r1, =0x00 - strb r1, [r0] - - ldr r0, =0x4806a020 - ldr r1, =0x07 - strb r1, [r0] - - ldr r0, =0x4806a00c - ldr r1, =0x83 - strb r1, [r0] - - ldr r0, =0x4806a000 - ldr r1, =0x1a - strb r1, [r0] - - ldr r0, =0x4806a004 - ldr r1, =0x00 - strb r1, [r0] - - ldr r0, =0x4806a00c - ldr r1, =0x03 - strb r1, [r0] - - ldr r0, =0x4806a010 - ldr r1, =0x03 - strb r1, [r0] - - ldr r0, =0x4806a008 - ldr r1, =0x04 - strb r1, [r0] - - ldr r0, =0x4806a020 - ldr r1, =0x00 - strb r1, [r0] - -#if 0 - ldr r0, =0x4806a000 - mov r1, #'u' - strb r1, [r0] -#endif - -#if 0 - /* LED0 OFF */ - ldr r3, =0x480000E5 - mov r4, #0x0b - strb r4, [r3] -#endif - - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK diff --git a/board/apollon/mem.c b/board/apollon/mem.c deleted file mode 100644 index 36bf6e9..0000000 --- a/board/apollon/mem.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> - -#include "mem.h" - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in 12MHz bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/******************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * (config II default). - * -- called from SRAM, or Flash (using temp SRAM stack). - ********************************************************************/ -void prcm_init(void) { } - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontigious support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(SDRC_CS0_OSET); - size /= SZ_32M; /* find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); - -} - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in gussing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(void) -{ - u32 val1, val2; - u32 pattern = 0x12345678; - - /* clear pos A */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); - /* pattern to pos B */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); - /* remove pattern off the bus */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); - /* get pos A value */ - val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ - - /* see if pos A value changed */ - if ((val1 != 0) || (val2 != pattern)) - return (0); - else - return (1); -} - -/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ -#define EARLY_INIT 1 - /* only init up first bank here */ - do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -called from low level code with stack only. - * -code sets up SDRAM timing and muxing for 2422 or 2420. - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * This is a bit ugly, but should handle all memory moduels - * used with the APOLLON. The first time though this code from s_init() - * we configure the first chip select. Later on we come back and - * will configure the 2nd chip select if it exists. - * - **************************************************************************/ -void do_sdrc_init(u32 offset, u32 early) -{ -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - u32 mux = 0, mtype, mwidth, rev, tval; - - rev = get_cpu_rev(); - if (rev == CPU_2420_2422_ES1) - tval = 1; - else - tval = 0; /* disable bit switched meaning */ - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */ -#ifdef CONFIG_SYS_NAND_BOOT - /* set nWP, disable limited addr */ - __raw_writel(0x001, GPMC_CONFIG); -#else - /* set nWP, disable limited addr */ - __raw_writel(0x111, GPMC_CONFIG); -#endif - - /* discover bus connection from sysboot */ - if (is_gpmc_muxed() == GPMC_MUXED) - mux = BIT9; - mtype = get_gpmc0_type(); - mwidth = get_gpmc0_width(); - - /* setup cs0 */ - __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ - sdelay(1000); - -#ifdef CONFIG_SYS_NOR_BOOT - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); -#else - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, - GPMC_CONFIG1_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0); -#endif - sdelay(2000); - - /* setup cs1 */ - __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ - sdelay(1000); - - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); - sdelay(2000); - - /* setup cs2 */ - __raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */ - sdelay(1000); - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, - GPMC_CONFIG1_2); - /* It's same as cs 0 */ - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2); -#ifdef CONFIG_SYS_NOR_BOOT - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2); -#else - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2); -#endif - -#ifndef CONFIG_SYS_NOR_BOOT - /* setup cs3 */ - __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */ - sdelay(1000); - - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3); -#endif - -#ifndef ASYNC_NOR - __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa)); - __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554)); - __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE)); -#endif - sdelay(2000); -} diff --git a/board/apollon/mem.h b/board/apollon/mem.h deleted file mode 100644 index 09c4ea4..0000000 --- a/board/apollon/mem.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _APOLLON_OMAP24XX_MEM_H_ -#define _APOLLON_OMAP24XX_MEM_H_ - -/* Slower full frequency range default timings for x32 operation*/ -#define APOLLON_2420_SDRC_SHARING 0x00000100 -#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011 -#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032 - -/* optimized timings good for current shipping parts */ -#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485 -#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C - -#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907 -#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013 - -#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001 -#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01 - -#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306 -#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506 - -#ifdef PRCM_CONFIG_I -#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz -#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz -#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz -#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz -#elif PRCM_CONFIG_II -#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz -#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz -#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz -#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz -#endif - -/* GPMC settings */ -#ifdef PRCM_CONFIG_I /* L3 at 165MHz */ -/* CS0: OneNAND */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24)) - -/* CS1: Ethernet */ -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) - -/* CS2: OneNAND */ -/* It's same as CS0 */ -# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) - -/* CS3: NOR */ -#ifdef ASYNC_NOR -# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 -#else -# define SYNC_NOR_VALUE 0x24aaa -# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c -#endif /* ASYNC_NOR */ -# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24)) -#endif /* endif PRCM_CONFIG_I */ - -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -/* CS0: OneNAND */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) - -/* CS1: ethernet */ -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) - -/* CS2: OneNAND */ -/* It's same as CS0 */ -# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) - -/* CS3: NOR */ -#define ASYNC_NOR -#ifdef ASYNC_NOR -# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 -#else -# define SYNC_NOR_VALUE 0x24aaa -# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F -#endif /* ASYNC_NOR */ -# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24)) -#endif /* endif PRCM_CONFIG_II */ - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define APOLLON_24XX_GPMC_CONFIG1_0 0x0 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* NOR boot */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x3 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F -# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) -#endif /* endif CONFIG_SYS_PRCM_III */ - -#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */ diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c deleted file mode 100644 index 4f950ae..0000000 --- a/board/apollon/sys_info.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mem.h> /* get mem tables */ -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <i2c.h> - -/************************************************************************** - * get_prod_id() - get id info from chips - ***************************************************************************/ -static u32 get_prod_id(void) -{ - u32 p; - p = __raw_readl(PRODUCTION_ID); /* get production ID */ - return ((p & CPU_242X_PID_MASK) >> 16); -} - -/************************************************************************** - * get_cpu_type() - low level get cpu type - * - no C globals yet. - * - just looking to say if this is a 2422 or 2420 or ... - * - to start with we will look at switch settings.. - * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics - * (mux for 2420, non-mux for 2422). - ***************************************************************************/ -u32 get_cpu_type(void) -{ - u32 v; - - switch (get_prod_id()) { - case 1:; /* 2420 */ - case 2: - return (CPU_2420); - break; /* 2420 pop */ - case 4: - return (CPU_2422); - break; - case 8: - return (CPU_2423); - break; - default: - break; /* early 2420/2422's unmarked */ - } - - v = __raw_readl(TAP_IDCODE_REG); - v &= CPU_24XX_ID_MASK; - /* currently 2420 and 2422 have same id */ - if (v == CPU_2420_CHIPID) { - if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ - return (CPU_2420); - else - return (CPU_2422); - } else - return (CPU_2420); /* don't know, say 2420 */ -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return (v + 1); /* currently 2422 and 2420 match up */ -} - -/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); - if (*burst == H4_2420_SDRC_MR_0_SDR) - return (1); - return (0); -} - -/*********************************************************** - * get_mem_type() - identify type of mDDR part used. - * 2422 uses stacked DDR, 2 parts CS0/CS1. - * 2420 may have 1 or 2, no good way to know...only init 1... - * when eeprom data is up we can select 1 more. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 cpu, sdr = is_mem_sdr(); - - cpu = get_cpu_type(); - if (cpu == CPU_2422 || cpu == CPU_2423) - return (DDR_STACKED); - - if (get_prod_id() == 0x2) - return (XDR_POP); - - if (get_board_type() == BOARD_H4_MENELAUS) - if (sdr) - return (SDR_DISCRETE); - else - return (DDR_COMBO); - else if (sdr) /* SDP + SDR kit */ - return (SDR_DISCRETE); - else - return (DDR_DISCRETE); /* origional SDP */ -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 offset) -{ - u32 size; - size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */ - size &= 0x2FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ - return (size); -} - -/*********************************************************************** - * get_board_type() - get board type based on current production stats. - * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. - * when they are available we can get info from there. This should - * be correct of all known boards up until today. - ************************************************************************/ -u32 get_board_type(void) -{ - return (BOARD_H4_SDP); -} - -/****************************************************************** - * get_sysboot_value() - get init word settings (dip switch on h4) - ******************************************************************/ -inline u32 get_sysboot_value(void) -{ - return (0x00000FFF & __raw_readl(CONTROL_STATUS)); -} - -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = __raw_readl(GPMC_CONFIG7_0); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return (b); -} - -/***************************************************************** - * is_gpmc_muxed() - tells if address/data lines are multiplexed - *****************************************************************/ -u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) - return (GPMC_MUXED); /* NAND Boot mode */ - if (mux & BIT1) /* if mux'ed */ - return (GPMC_MUXED); - else - return (GPMC_NONMUXED); -} - -/************************************************************************ - * get_gpmc0_type() - read sysboot lines to see type of memory attached - ************************************************************************/ -u32 get_gpmc0_type(void) -{ - u32 type; - type = get_sysboot_value(); - if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2)) - return (TYPE_NAND); - else - return (TYPE_NOR); -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - u32 width; - width = get_sysboot_value(); - if ((width & 0xF) == (BIT3 | BIT2)) - return (WIDTH_8BIT); - else - return (WIDTH_16BIT); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -/********************************************************************* - * display_board_info() - print banner with board info. - *********************************************************************/ -void display_board_info(u32 btype) -{ - char cpu_2420[] = "2420"; /* cpu type */ - char cpu_2422[] = "2422"; - char cpu_2423[] = "2423"; - char mem_sdr[] = "mSDR"; /* memory type */ - char mem_ddr[] = "mDDR"; - char t_tst[] = "TST"; /* security level */ - char t_emu[] = "EMU"; - char t_hs[] = "HS"; - char t_gp[] = "GP"; - char unk[] = "?"; - - char *cpu_s, *mem_s, *sec_s; - u32 cpu, rev, sec; - - rev = get_cpu_rev(); - cpu = get_cpu_type(); - sec = get_device_type(); - - if (is_mem_sdr()) - mem_s = mem_sdr; - else - mem_s = mem_ddr; - - if (cpu == CPU_2423) - cpu_s = cpu_2423; - else if (cpu == CPU_2422) - cpu_s = cpu_2422; - else - cpu_s = cpu_2420; - - switch (sec) { - case TST_DEVICE: - sec_s = t_tst; - break; - case EMU_DEVICE: - sec_s = t_emu; - break; - case HS_DEVICE: - sec_s = t_hs; - break; - case GP_DEVICE: - sec_s = t_gp; - break; - default: - sec_s = unk; - } - - printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1); - printf("Samsung Apollon SDP Base Board + %s \n", mem_s); -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = 242x IP platform (first 2xx boards) - * 1 = 242x Menelaus platfrom. - *************************************************************************/ -u32 get_board_rev(void) -{ - u32 rev = 0; - u32 btype = get_board_type(); - - if (btype == BOARD_H4_MENELAUS) - rev = 1; - return (rev); -} - -/******************************************************** - * get_base(); get upper addr of current execution - *******************************************************/ -u32 get_base(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); - val &= 0xF0000000; - val >>= 28; - return (val); -} - -/******************************************************** - * get_base2(); get 2upper addr of current execution - *******************************************************/ -u32 get_base2(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); - val &= 0xFF000000; - val >>= 24; - return (val); -} - -/******************************************************** - * running_in_flash() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_flash(void) -{ - if (get_base() < 4) - return (1); /* in flash */ - return (0); /* running in SRAM or SDRAM */ -} - -/******************************************************** - * running_in_sram() - tell if currently running in - * sram. - *******************************************************/ -u32 running_in_sram(void) -{ - if (get_base() == 4) - return (1); /* in SRAM */ - return (0); /* running in FLASH or SDRAM */ -} - -/******************************************************** - * running_in_sdram() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_sdram(void) -{ - if (get_base() > 4) - return (1); /* in sdram */ - return (0); /* running in SRAM or FLASH */ -} - -/************************************************************* - * running_from_internal_boot() - am I a signed NOR image. - *************************************************************/ -u32 running_from_internal_boot(void) -{ - u32 v, base; - - v = get_sysboot_value() & BIT3; - base = get_base2(); - /* if running at mask rom flash address and - * sysboot3 says this was an internal boot - */ - if ((base == 0x08) && v) - return (1); - else - return (0); -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8); - return (mode >>= 8); -} diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c index 0b36d12..d5e109e 100644 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -33,6 +33,8 @@ * MA 02111-1307 USA */ #include <common.h> +#include <malloc.h> +#include <errno.h> #include <netdev.h> #include <asm/io.h> #include <asm/arch/systimer.h> @@ -90,8 +92,25 @@ int board_eth_init(bd_t *bis) int cpu_mmc_init(bd_t *bis) { int rc = 0; + (void) bis; #ifdef CONFIG_ARM_PL180_MMCI - rc = arm_pl180_mmci_init(); + struct pl180_mmc_host *host; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + strcpy(host->name, "MMC"); + host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; + host->voltages = VOLTAGE_WINDOW_MMC; + host->caps = 0; + host->clock_in = ARM_MCLK; + host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; + rc = arm_pl180_mmci_init(host); #endif return rc; } diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 47ab839..d30a1ee 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -242,9 +242,6 @@ void lcd_show_board_info(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - #ifdef CONFIG_AT91SAM9G10EK /* arch number of AT91SAM9G10EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 60ff1c0..abae93d 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -260,9 +260,6 @@ int board_early_init_f(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 5a04274..d02312c 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -258,9 +258,6 @@ int board_early_init_f(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9M10G45EK-Board */ #ifdef CONFIG_AT91SAM9M10G45EK gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index ef0ddd7..e92ec6e 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -192,9 +192,6 @@ int board_early_init_f(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9RLEK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; /* adress of boot parameters */ diff --git a/board/atmel/at91sam9x5ek/Makefile b/board/atmel/at91sam9x5ek/Makefile new file mode 100644 index 0000000..458d9a0 --- /dev/null +++ b/board/atmel/at91sam9x5ek/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2012 +# Bo Shen <voice.shen@atmel.com> +# Atmel corporation <www.atmel.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += at91sam9x5ek.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c new file mode 100644 index 0000000..ae408bc --- /dev/null +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2012 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <atmel_hlcdc.h> +#ifdef CONFIG_MACB +#include <net.h> +#endif +#include <netdev.h> +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> +#endif +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ +#ifdef CONFIG_CMD_NAND +static void at91sam9x5ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + /* NAND flash on D16 */ + csa |= AT91_MATRIX_NFD0_ON_D16; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_set_a_periph(AT91_PIO_PORTD, 13, 1); +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + if (has_emac0()) + rc = macb_eth_initialize(0, + (void *)ATMEL_BASE_EMAC0, 0x00); + if (has_emac1()) + rc = macb_eth_initialize(1, + (void *)ATMEL_BASE_EMAC1, 0x00); +#endif + return rc; +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 800, + .vl_row = 480, + .vl_clk = 24000000, + .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_clk_pol = 1, + .vl_hsync_len = 128, + .vl_left_margin = 64, + .vl_right_margin = 64, + .vl_vsync_len = 2, + .vl_upper_margin = 22, + .vl_lower_margin = 21, + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ + if (has_lcdc()) + at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ +} + +void lcd_disable(void) +{ + if (has_lcdc()) + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ +} + +static void at91sam9x5ek_lcd_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + if (has_lcdc()) { + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + } +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + if (has_lcdc()) { + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("(C) 2012 ATMEL Corp\n"); + lcd_printf("at91support@atmel.com\n"); + lcd_printf("%s CPU at %s MHz\n", + get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20); + } +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_pio_output(AT91_PIO_PORTA, 7, 0); + break; + case 0: + default: + at91_set_pio_output(AT91_PIO_PORTA, 14, 0); + break; + } +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_pio_output(AT91_PIO_PORTA, 7, 1); + break; + case 0: + default: + at91_set_pio_output(AT91_PIO_PORTA, 14, 1); + break; + } +} +#endif /* CONFIG_ATMEL_SPI */ + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + /* arch number of AT91SAM9X5EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + at91sam9x5ek_nand_hw_init(); +#endif + +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 0); + at91_spi0_hw_init(1 << 4); +#endif + +#ifdef CONFIG_MACB + at91_macb_hw_init(); +#endif + +#ifdef CONFIG_LCD + at91sam9x5ek_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/board/atmel/at91sam9x5ek/config.mk b/board/atmel/at91sam9x5ek/config.mk new file mode 100644 index 0000000..6589a12 --- /dev/null +++ b/board/atmel/at91sam9x5ek/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0x26f00000 diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile new file mode 100644 index 0000000..7fbd20d --- /dev/null +++ b/board/atmel/atngw100mkii/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c new file mode 100644 index 0000000..f4023b3 --- /dev/null +++ b/board/atmel/atngw100mkii/atngw100mkii.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2010 Atmel Corporation + * + * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <spi.h> +#include <netdev.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> +#include <asm/arch/portmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ + .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT, + .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 10, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 6, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE) + | HMATRIX_BIT(EBI_NAND_ENABLE)); + + portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND, + PORTMUX_DRIVE_HIGH); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 23, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH + | PORTMUX_DRIVE_MIN); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif +#if defined(CONFIG_ATMEL_SPI) + portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = uncached(EBI_SDRAM_BASE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + gd->bd->bi_phy_id[1] = 0x03; + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); + return 0; +} +#endif + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); +} +#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 2c14462..93f12ea 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -28,7 +28,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/board.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> @@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0, SD slot, with 4-bit bus */ - tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); + tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); return 0; } diff --git a/board/avionic-design/dts/tegra2-medcom.dts b/board/avionic-design/dts/tegra20-medcom.dts index fc52f9c..fc52f9c 100644 --- a/board/avionic-design/dts/tegra2-medcom.dts +++ b/board/avionic-design/dts/tegra20-medcom.dts diff --git a/board/avionic-design/dts/tegra2-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index cef49ad..cef49ad 100644 --- a/board/avionic-design/dts/tegra2-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts diff --git a/board/avionic-design/dts/tegra2-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index 9faebd8..bb3851b 100644 --- a/board/avionic-design/dts/tegra2-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -55,4 +55,15 @@ usb@c5004000 { status = "disabled"; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/medcom/Makefile +++ b/board/avionic-design/medcom/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB = $(obj)lib$(BOARD).o diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB = $(obj)lib$(BOARD).o diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB = $(obj)lib$(BOARD).o diff --git a/board/o2dnt/Makefile b/board/bluegiga/apx4devkit/Makefile index 9e5e21e..68ab8f3 100644 --- a/board/o2dnt/Makefile +++ b/board/bluegiga/apx4devkit/Makefile @@ -1,6 +1,5 @@ - # -# (C) Copyright 2005-2006 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -26,11 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o flash.o +ifndef CONFIG_SPL_BUILD +COBJS := apx4devkit.o +else +COBJS := spl_boot.o +endif -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c new file mode 100644 index 0000000..ae48ab5 --- /dev/null +++ b/board/bluegiga/apx4devkit/apx4devkit.c @@ -0,0 +1,150 @@ +/* + * Bluegiga APX4 Development Kit + * + * Copyright (C) 2012 Bluegiga Technologies Oy + * + * Authors: + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> + * Lauri Hintsala <lauri.hintsala@bluegiga.com> + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Functions */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + return mxsmmc_initialize(bis, 0, NULL); +} +#endif + + +#ifdef CONFIG_CMD_NET + +#define MII_PHY_CTRL2 0x1f +int fecmxc_mii_postcall(int phy) +{ + /* change PHY RMII clock to 50MHz */ + miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct eth_device *dev; + + ret = cpu_eth_init(bis); + if (ret) { + printf("FEC MXS: Unable to init FEC clocks\n"); + return ret; + } + + ret = fecmxc_initialize(bis); + if (ret) { + printf("FEC MXS: Unable to init FEC\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC"); + if (!dev) { + printf("FEC MXS: Unable to get FEC device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXS: Unable to register FEC MII postcall\n"); + return ret; + } + + return ret; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +#define MXS_OCOTP_MAX_TIMEOUT 1000000 +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; + + serialnr->high = 0; + serialnr->low = 0; + + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); + + if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + MXS_OCOTP_MAX_TIMEOUT)) { + printf("MXS: Can't get serial number from OCOTP\n"); + return; + } + + serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3); +} +#endif + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + if (getenv("revision#") != NULL) + return simple_strtoul(getenv("revision#"), NULL, 10); + return 0; +} +#endif diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c new file mode 100644 index 0000000..f7dbe41 --- /dev/null +++ b/board/bluegiga/apx4devkit/spl_boot.c @@ -0,0 +1,164 @@ +/* + * Bluegiga APX4 Development Kit + * + * Copyright (C) 2012 Bluegiga Technologies Oy + * + * Authors: + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> + * Lauri Hintsala <lauri.hintsala@bluegiga.com> + * + * Based on spl_boot.c: + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <config.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* LED */ + MX28_PAD_PWM3__GPIO_3_28, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, +}; + +void board_init_ll(void) +{ + mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + + /* switch LED on */ + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); +} + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* + * All address lines are routed from CPU to memory chip. + * ADDR_PINS field is set to zero. + */ + dram_vals[0x74 >> 2] = 0x0f02000a; + + /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ + dram_vals[0x7c >> 2] = 0x00000101; +} diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index fe15511..b3f31d6 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -158,7 +158,7 @@ static void set_led(int state) { switch (state) { case LED_OFF: - __set_led(0, 0, 0, 0, 0, 0); + __set_led(0, 0, 0, 1, 1, 1); break; case LED_ALARM_ON: __set_led(0, 0, 0, 0, 1, 1); @@ -192,6 +192,25 @@ int board_init(void) } #ifdef CONFIG_MISC_INIT_R +static void check_power_switch(void) +{ + if (kw_gpio_get_value(GPIO_POWER_SWITCH)) { + /* turn off HDD and USB power */ + kw_gpio_set_value(GPIO_HDD_POWER, 0); + kw_gpio_set_value(GPIO_USB_VBUS, 0); + set_led(LED_OFF); + + /* loop until released */ + while (kw_gpio_get_value(GPIO_POWER_SWITCH)) + ; + + /* turn power on again */ + kw_gpio_set_value(GPIO_HDD_POWER, 1); + kw_gpio_set_value(GPIO_USB_VBUS, 1); + set_led(LED_POWER_BLINKING); + } +} + void check_enetaddr(void) { uchar enetaddr[6]; @@ -261,6 +280,7 @@ static void check_push_button(void) int misc_init_r(void) { + check_power_switch(); check_enetaddr(); check_push_button(); diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index b6c8791..d3b3684 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -149,9 +149,6 @@ static void sbc35_a9g20_macb_hw_init(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index 31074d0..86e7e65 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -83,9 +83,6 @@ static void tny_a9260_nand_hw_init(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 700c184..6c2e95b 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -74,7 +74,7 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = { /* * Routine: board_init - * Description: Early hardware init. + * Description: hardware init. */ int board_init(void) { @@ -438,7 +438,7 @@ int board_eth_init(bd_t *bis) rc1 = handle_mac_address(); if (rc1) - printf("CM-T3x: No MAC address found\n"); + printf("No MAC address found! "); rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); if (rc1 > 0) diff --git a/board/compal/dts/tegra2-paz00.dts b/board/compal/dts/tegra20-paz00.dts index 9e3e169..9e3e169 100644 --- a/board/compal/dts/tegra2-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index 488e381..7f7287e 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -16,9 +16,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB = $(obj)lib$(BOARD).o diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index ec67874..0f8f167 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -16,7 +16,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> @@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra2_mmc_init(0, 4, -1, -1); + tegra_mmc_init(0, 4, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ - tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); + tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; } diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index db79e77..db79e77 100644 --- a/board/compulab/dts/tegra2-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index bf624f4..ff07879 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -24,9 +24,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB = $(obj)lib$(BOARD).o diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 1ac15f8..893cca8 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -24,7 +24,7 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> @@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ - tegra2_mmc_init(0, 4, -1, GPIO_PP1); + tegra_mmc_init(0, 4, -1, GPIO_PP1); /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ - tegra2_mmc_init(3, 4, -1, -1); + tegra_mmc_init(3, 4, -1, -1); return 0; } diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 004d5ad..0c7aabb 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -36,6 +36,11 @@ #include <asm/errno.h> #include <hwconfig.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DRIVER_TI_EMAC @@ -204,11 +209,32 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); + + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd0); +} +#endif + static const struct pinmux_config gpio_pins[] = { #ifdef CONFIG_USE_NOR /* GP0[11] is required for NOR to work on Rev 3 EVMs */ { pinmux(0), 8, 4 }, /* GP0[11] */ #endif +#ifdef CONFIG_DAVINCI_MMC + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif }; const struct pinmux_resource pinmuxes[] = { @@ -236,6 +262,9 @@ const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(emifa_pins_nor), #endif PINMUX_ITEM(gpio_pins), +#ifdef CONFIG_DAVINCI_MMC + PINMUX_ITEM(mmc0_pins), +#endif }; const int pinmuxes_size = ARRAY_SIZE(pinmuxes); @@ -246,6 +275,9 @@ const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_EMAC }, /* image download */ { DAVINCI_LPSC_UART2 }, /* console */ { DAVINCI_LPSC_GPIO }, +#ifdef CONFIG_DAVINCI_MMC + { DAVINCI_LPSC_MMC_SD }, +#endif }; const int lpsc_size = ARRAY_SIZE(lpsc); @@ -303,7 +335,7 @@ int board_early_init_f(void) int board_init(void) { -#ifdef CONFIG_USE_NOR +#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) u32 val; #endif @@ -316,11 +348,11 @@ int board_init(void) * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), @@ -354,6 +386,16 @@ int board_init(void) writel(val, GPIO_BANK0_REG_CLR_ADDR); #endif +#ifdef CONFIG_DAVINCI_MMC + /* Set the GPIO direction as output */ + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as high */ + val = readl(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + writel(val, GPIO_BANK0_REG_SET_ADDR); +#endif + #ifdef CONFIG_DRIVER_TI_EMAC davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg new file mode 100644 index 0000000..2b12b6c --- /dev/null +++ b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg @@ -0,0 +1,4 @@ +# PLL0CFG0 PLL0CFG1 +PLL0 0x00180001 0x00000205 +# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC +DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000 diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index b694258..156cb7f 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com> * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * Copyright (C) 2004 Texas Instruments. + * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>. * * ---------------------------------------------------------------------------- * This program is free software; you can redistribute it and/or modify @@ -28,6 +29,7 @@ #include <asm/io.h> #include <asm/arch/davinci_misc.h> #include <asm/arch/pinmux_defs.h> +#include <asm/arch/da8xx-usb.h> #include <ns16550.h> DECLARE_GLOBAL_DATA_PTR; @@ -89,3 +91,42 @@ int misc_init_r(void) return 0; } + +int usb_phy_on(void) +{ + u32 timeout; + u32 cfgchip2; + + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ | + CFGCHIP2_USB1PHYCLKMUX); + cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | + CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX | + CFGCHIP2_USB1SUSPENDM; + + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); + + /* wait until the usb phy pll locks */ + timeout = DA8XX_USB_OTG_TIMEOUT; + while (timeout--) + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + + /* USB phy was not turned on */ + return 0; +} + +void usb_phy_off(void) +{ + u32 cfgchip2; + + /* + * Power down the on-chip PHY. + */ + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM); + cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET; + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); +} diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 3d28ea8..9d6db65 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -49,8 +49,8 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + /* SSP2 clock at 160MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); @@ -72,7 +72,7 @@ int board_init(void) int dram_init(void) { - return mx28_dram_init(); + return mxs_dram_init(); } #ifdef CONFIG_CMD_MMC @@ -122,8 +122,8 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index 7a12592..49e8a75 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -218,5 +218,5 @@ const iomux_cfg_t iomux_setup[] = { void board_init_ll(void) { - mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd deleted file mode 100644 index c60615a..0000000 --- a/board/denx/m28evk/u-boot.bd +++ /dev/null @@ -1,14 +0,0 @@ -sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; -} - -section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; - hab call 0x8000; - - load u_boot > 0x40000100; - load ivt (entry = 0x40000100) > 0x8000; - hab call 0x8000; -} diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c deleted file mode 100644 index e88b2ed..0000000 --- a/board/efikamx/efikamx.c +++ /dev/null @@ -1,735 +0,0 @@ -/* - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> -#include <asm/gpio.h> -#include <asm/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <pmic.h> -#include <fsl_pmic.h> -#include <mc13892.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Compile-time error checking - */ -#ifndef CONFIG_MXC_SPI -#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" -#endif - -/* - * Shared variables / local defines - */ -/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4 - -void efikamx_toggle_led(uint32_t mask); - -/* Board revisions */ -#define EFIKAMX_BOARD_REV_11 0x1 -#define EFIKAMX_BOARD_REV_12 0x2 -#define EFIKAMX_BOARD_REV_13 0x3 -#define EFIKAMX_BOARD_REV_14 0x4 - -#define EFIKASB_BOARD_REV_13 0x1 -#define EFIKASB_BOARD_REV_20 0x2 - -/* - * Board identification - */ -u32 get_efikamx_rev(void) -{ - u32 rev = 0; - /* - * Retrieve board ID: - * rev1.1: 1,1,1 - * rev1.2: 1,1,0 - * rev1.3: 1,0,1 - * rev1.4: 1,0,0 - */ - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - /* set to 1 in order to get correct value on board rev1.1 */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); - - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; - - mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; - - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; - - return (~rev & 0x7) + 1; -} - -inline u32 get_efikasb_rev(void) -{ - u32 rev = 0; - - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; - - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; - - return rev; -} - -inline uint32_t get_efika_rev(void) -{ - if (machine_is_efikamx()) - return get_efikamx_rev(); - else - return get_efikasb_rev(); -} - -u32 get_board_rev(void) -{ - return get_cpu_rev() | (get_efika_rev() << 8); -} - -/* - * DRAM initialization - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -/* - * UART configuration - */ -static void setup_iomux_uart(void) -{ - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); -} - -/* - * SPI configuration - */ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* Configure SS0 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); - - /* Configure SS1 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} -#else -static inline void setup_iomux_spi(void) { } -#endif - -/* - * PMIC configuration - */ -#ifdef CONFIG_MXC_SPI -static void power_init(void) -{ - unsigned int val; - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - struct pmic *p; - - pmic_init(); - p = get_pmic(); - - /* Write needed to Power Gate 2 register */ - pmic_reg_read(p, REG_POWER_MISC, &val); - val &= ~PWGT2SPIEN; - pmic_reg_write(p, REG_POWER_MISC, val); - - /* Externally powered */ - pmic_reg_read(p, REG_CHARGE, &val); - val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(p, REG_CHARGE, val); - - /* power up the system first */ - pmic_reg_write(p, REG_POWER_MISC, PWUP); - - /* Set core voltage to 1.1V */ - pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; - pmic_reg_write(p, REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - pmic_reg_read(p, REG_SW_1, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - pmic_reg_read(p, REG_SW_2, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_2, val); - udelay(50); - - /* Raise the core frequency to 800MHz */ - writel(0x0, &mxc_ccm->cacrr); - - /* Set switchers in Auto in NORMAL mode & STANDBY mode */ - /* Setup the switcher mode for SW1 & SW2*/ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | - (SWMODE_MASK << SWMODE4_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(p, REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - pmic_reg_read(p, REG_SETTING_1, &val); - val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; - pmic_reg_write(p, REG_SETTING_1, val); - - /* Enable VGEN1, VGEN2, VDIG, VPLL */ - pmic_reg_read(p, REG_MODE_0, &val); - val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; - pmic_reg_write(p, REG_MODE_0, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(p, REG_MODE_1, val); - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(p, REG_MODE_1, val); - - pmic_reg_read(p, REG_POWER_CTL2, &val); - val |= WDIRESET; - pmic_reg_write(p, REG_POWER_CTL2, val); - - udelay(2500); -} -#else -static inline void power_init(void) { } -#endif - -/* - * MMC configuration - */ -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1}, - {MMC_SDHC2_BASE_ADDR, 1}, -}; - -static inline uint32_t efika_mmc_cd(void) -{ - if (machine_is_efikamx()) - return MX51_PIN_GPIO1_0; - else - return MX51_PIN_EIM_CS2; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efika_mmc_cd(); - int ret; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); - else - ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - uint32_t cd = efika_mmc_cd(); - - /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(cd, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(cd, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(cd)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); - - /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (machine_is_efikasb() || (machine_is_efikamx() && - (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 IOMUX */ - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 Control lines IOMUX */ - mxc_request_iomux(MX51_PIN_GPIO1_7, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_8, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_8, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (!ret) - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } else { /* New boards use only SDHC1 */ - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - } - - return ret; -} -#endif - -/* - * ATA - */ -#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{ - mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); -} -#else -static inline void setup_iomux_ata(void) { } -#endif - -/* - * EHCI USB - */ -#ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); -#else -static inline void setup_iomux_usb(void) { } -#endif - -/* - * LED configuration - */ -void setup_iomux_led(void) -{ - if (machine_is_efikamx()) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); - - /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); - - /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); - } else { - /* CAPS-LOCK LED */ - mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); - - /* ALARM-LED LED */ - mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); - } -} - -void efikamx_toggle_led(uint32_t mask) -{ - if (machine_is_efikamx()) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); - } else { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), - !(mask & EFIKAMX_LED_GREEN)); - } -} - -/* - * Board initialization - */ -static void init_drive_strength(void) -{ - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} - -int board_early_init_f(void) -{ - init_drive_strength(); - - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_led(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - setup_iomux_spi(); - - power_init(); - - setup_iomux_led(); - setup_iomux_ata(); - setup_iomux_usb(); - - if (machine_is_efikasb()) - setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); - - setup_iomux_led(); - - efikamx_toggle_led(EFIKAMX_LED_BLUE); - - return 0; -} - -int checkboard(void) -{ - u32 rev = get_efika_rev(); - - if (machine_is_efikamx()) { - printf("Board: Efika MX, rev1.%i\n", rev & 0xf); - return 0; - } else { - switch (rev) { - case EFIKASB_BOARD_REV_13: - printf("Board: Efika SB rev1.3\n"); - break; - case EFIKASB_BOARD_REV_20: - printf("Board: Efika SB rev2.0\n"); - break; - default: - printf("Board: Efika SB, rev Unknown\n"); - break; - } - } - - return 0; -} diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 0874e9c..3d2fe73 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -451,25 +451,15 @@ static char *enbw_cmc_getvalue(char *ptr, int *value) return ptr; } -static int enbw_cmc_config_switch(unsigned long addr) +static struct spi_slave *enbw_cmc_init_spi(void) { struct spi_slave *spi; - char *ptr = (char *)addr; - int value, reg; int ret; - int bus, cs, max_hz, spi_mode; - - debug("configure switch with file on addr: 0x%lx\n", addr); - - bus = 0; - cs = 0; - max_hz = 1000000; - spi_mode = 0; - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + spi = spi_setup_slave(0, 0, 1000000, 0); if (!spi) { printf("Failed to set up slave\n"); - return -EINVAL; + return NULL; } ret = spi_claim_bus(spi); @@ -480,25 +470,45 @@ static int enbw_cmc_config_switch(unsigned long addr) ret = enbw_cmc_switch_read_ident(spi); if (ret) - goto err_claim_bus; + goto err_read; + + return spi; +err_read: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return NULL; +} + +static int enbw_cmc_config_switch(unsigned long addr) +{ + struct spi_slave *spi; + char *ptr = (char *)addr; + int value, reg; + int ret = 0; + + debug("configure switch with file on addr: 0x%lx\n", addr); + + spi = enbw_cmc_init_spi(); + if (!spi) + return -EINVAL; - ptr = (char *)addr; while (ptr != NULL) { ptr = enbw_cmc_getvalue(ptr, ®); if (ptr != NULL) { ptr = enbw_cmc_getvalue(ptr, &value); if ((ptr != NULL) && (value >= 0)) - if (enbw_cmc_switch_write(spi, reg, value)) - goto err_read; + if (enbw_cmc_switch_write(spi, reg, value)) { + /* error writing to switch */ + ptr = NULL; + ret = -EINVAL; + } } } - return 0; -err_read: spi_release_bus(spi); -err_claim_bus: spi_free_slave(spi); - return -EINVAL; + return ret; } static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) @@ -524,8 +534,10 @@ U_BOOT_CMD(switch, 3, 1, do_switch, */ int board_eth_init(bd_t *bis) { + struct spi_slave *spi; const char *s; - size_t len; + size_t len = 0; + int config = 1; davinci_emac_mii_mode_sel(0); @@ -534,25 +546,49 @@ int board_eth_init(bd_t *bis) if (len) { unsigned long addr = simple_strtoul(s, NULL, 16); - enbw_cmc_config_switch(addr); + config = enbw_cmc_config_switch(addr); } + if (config) { + /* + * no valid config file -> do we have some args in + * hwconfig ? + */ + if ((hwconfig_subarg("switch", "lan", &len)) || + (hwconfig_subarg("switch", "lmn", &len))) { + /* If so start switch */ + spi = enbw_cmc_init_spi(); + if (spi) { + if (enbw_cmc_switch_write(spi, 1, 0)) + config = 0; + udelay(10000); + if (enbw_cmc_switch_write(spi, 1, 1)) + config = 0; + spi_release_bus(spi); + spi_free_slave(spi); + } + } else { + config = 0; + } + } if (!davinci_emac_initialize()) { printf("Error: Ethernet init failed!\n"); return -1; } - if (hwconfig_subarg_cmp("switch", "lan", "on")) - /* Switch port lan on */ - enbw_cmc_switch(1, 1); - else - enbw_cmc_switch(1, 0); + if (config) { + if (hwconfig_subarg_cmp("switch", "lan", "on")) + /* Switch port lan on */ + enbw_cmc_switch(1, 1); + else + enbw_cmc_switch(1, 0); - if (hwconfig_subarg_cmp("switch", "pwl", "on")) - /* Switch port pwl on */ - enbw_cmc_switch(2, 1); - else - enbw_cmc_switch(2, 0); + if (hwconfig_subarg_cmp("switch", "lmn", "on")) + /* Switch port pwl on */ + enbw_cmc_switch(2, 1); + else + enbw_cmc_switch(2, 0); + } return 0; } @@ -778,35 +814,6 @@ void arch_memory_failure_handle(void) } #endif -#if defined(CONFIG_BOOTCOUNT_LIMIT) -void bootcount_store(ulong a) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - - /* - * write RTC kick register to enable write - * for RTC Scratch registers. Scratch0 and 1 are - * used for bootcount values. - */ - writel(RTC_KICK0R_WE, ®->kick0r); - writel(RTC_KICK1R_WE, ®->kick1r); - out_be32(®->scratch0, a); - out_be32(®->scratch1, BOOTCOUNT_MAGIC); -} - -ulong bootcount_load(void) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - - if (in_be32(®->scratch1) != BOOTCOUNT_MAGIC) - return 0; - else - return in_be32(®->scratch0); -} -#endif - ulong post_word_load(void) { struct davinci_rtc *reg = diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c index 9ecf31d..e947330 100644 --- a/board/esg/ima3-mx53/ima3-mx53.c +++ b/board/esg/ima3-mx53/ima3-mx53.c @@ -172,7 +172,7 @@ static void setup_iomux_fec(void) } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 }; +struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR }; int board_mmc_getcd(struct mmc *mmc) { diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index f654f87..c74c3fc 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -43,8 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); /* arch number of CPUAT91-Board */ gd->bd->bi_arch_number = MACH_TYPE_CPUAT91; /* adress of boot parameters */ diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 5f99e2f..355cfed 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,34 +51,35 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_SDRAM_BASE1 - sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); asm("nop"); - sdram->mode = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); asm("nop"); udelay(100); diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index 9109edb..a9bec58 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,8 +48,8 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -59,36 +60,37 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); __asm__("nop"); udelay(1000); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); #endif diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index b9e6126..e9a568e 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,8 +40,8 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 dramsize, i, dramclk; /* @@ -48,14 +49,15 @@ phys_size_t initdram(int board_type) * the port-size of SDRAM. In this case it is necessary to enable * Data[15:0] on Port Address/Data. */ - gpio->par_ad = - GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | - GPIO_PAR_AD_DATAL; + out_8(&gpio->par_ad, + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL); /* Initialize PAR to enable SDRAM signals */ - gpio->par_sdram = - GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | - GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); + out_8(&gpio->par_sdram, + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | + GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | + GPIO_PAR_SDRAM_SDCS(3)); dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -64,25 +66,28 @@ phys_size_t initdram(int board_type) } i--; - if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { + if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); /* Initialize DRAM Control Register: DCR */ - sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | - SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); + out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | + SDRAMC_DCR_RC((15 * dramclk) >> 4)); /* Initialize DACR0 */ - sdram->dacr0 = - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | - SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; + out_be32(&sdram->dacr0, + SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | + SDRAMC_DARCn_PS_32); asm("nop"); /* Initialize DMR0 */ - sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; + out_be32(&sdram->dmr0, + ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V); asm("nop"); /* Set IP (bit 3) in DACR */ - sdram->dacr0 |= SDRAMC_DARCn_IP; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); /* Wait 30ns to allow banks to precharge */ for (i = 0; i < 5; i++) { @@ -93,7 +98,7 @@ phys_size_t initdram(int board_type) *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ - sdram->dacr0 |= SDRAMC_DARCn_RE; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); /* Wait for at least 8 auto refresh cycles to occur */ for (i = 0; i < 0x2000; i++) { @@ -101,7 +106,7 @@ phys_size_t initdram(int board_type) } /* Finish the configuration by issuing the MRS. */ - sdram->dacr0 |= SDRAMC_DARCn_IMRS; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); asm("nop"); /* Write to the SDRAM Mode Register */ diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 8ffb2cc..052993d 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -109,7 +109,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -120,7 +120,8 @@ void ide_set_reset(int idereset) }; if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(100); } else { mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); @@ -129,17 +130,19 @@ void ide_set_reset(int idereset) period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(2000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index ae69f67..658748b 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int checkboard(void) { @@ -101,7 +102,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -112,7 +113,8 @@ void ide_set_reset(int idereset) }; if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(100); } else { mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); @@ -121,17 +123,19 @@ void ide_set_reset(int idereset) period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(2000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 902ca3a..c3160ce 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -2,6 +2,8 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,6 +25,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int checkboard (void) { @@ -32,10 +35,10 @@ int checkboard (void) { }; phys_size_t initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); + sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); - sdp->sdram_sdtr = 0xf539; - sdp->sdram_sdcr = 0x4211; + out_be16(&sdp->sdram_sdtr, 0xf539); + out_be16(&sdp->sdram_sdcr, 0x4211); /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0; diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 35c9b20..1bbe5a3 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -4,6 +4,8 @@ * * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,6 +27,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> #define PERIOD 13 /* system bus period in ns */ #define SDRAM_TREFI 7800 /* in ns */ @@ -38,67 +41,68 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); - volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); + sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); + gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); - gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ + /* Enable SDRAM */ + out_be16(&gpio_reg->par_sdram, 0x3FF); /* Set up chip select */ - sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE; - sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; + out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); /* Set up timing */ - sdp->sdcfg1 = 0x83711630; - sdp->sdcfg2 = 0x46770000; + out_be32(&sdp->sdcfg1, 0x83711630); + out_be32(&sdp->sdcfg2, 0x46770000); /* Enable clock */ - sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE; + out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE); /* Set precharge */ - sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); /* Dummy write to start SDRAM */ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LEMR */ - sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR - | MCF_SDRAMC_SDMR_AD(0x0) - | MCF_SDRAMC_SDMR_CMD; + setbits_be32(&sdp->sdmr, + MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | + MCF_SDRAMC_SDMR_CMD); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LMR */ - sdp->sdmr = 0x058d0000; + out_be32(&sdp->sdmr, 0x058d0000); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ - sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); /* Set precharge */ - sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop manual precharge, send 2 IREF */ - sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); - sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; - /* Write mode register, clear reset DLL */ - sdp->sdmr = 0x018d0000; + + out_be32(&sdp->sdmr, 0x018d0000); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ - sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); - sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN); + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN); /* Turn on auto refresh, lock SDMR */ - sdp->sdcr = + out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_CKE | MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_MUX(1) /* 1 added to round up */ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) - | MCF_SDRAMC_SDCR_DQS_OE(0x3); + | MCF_SDRAMC_SDCR_DQS_OE(0x3)); return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index f331786..142485f 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,34 +51,35 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_SDRAM_BASE1 - sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); asm("nop"); - sdram->mode = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); asm("nop"); udelay(100); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index b4df22f..1c14b83 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,29 +51,30 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 16025f9..c70c98c 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* * set up pin configuration - enabled 2nd output buffer's signals * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) * to use nCE signal */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index 376de4b..8eb3512 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,29 +51,30 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index df8c03b..ed79e39 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - fbcs->csmr2 &= ~FBCS_CSMR_WP; + clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); /* * set up pin configuration - enabled 2nd output buffer's signals * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) * to use nCE signal */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c index 088c8c4..32a9374 100644 --- a/board/freescale/m54451evb/m54451evb.c +++ b/board/freescale/m54451evb/m54451evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <spi.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,14 +52,14 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) && - (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2)) + if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && + (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) return dramsize; for (i = 0x13; i < 0x20; i++) { @@ -67,32 +68,33 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); udelay(200); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000); udelay(100); #endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 2a84514..0ca268e 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,8 +48,8 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; @@ -59,33 +60,34 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408; - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); udelay(500); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); #endif @@ -105,26 +107,29 @@ int testdram(void) int ide_preinit(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; - gpio->par_feci2c |= - (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | - GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); - gpio->par_ata |= - (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | - GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 - | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | - GPIO_PAR_ATA_IORDY_IORDY); - gpio->par_pci |= - (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u32 tmp; + + tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; + setbits_8(&gpio->par_fec, tmp); + tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) | + (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW)); + setbits_be16(&gpio->par_feci2c, tmp); + + setbits_be16(&gpio->par_ata, + GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 | + GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + setbits_be16(&gpio->par_pci, + GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); return (0); } void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) MMAP_ATA; + atac_t *ata = (atac_t *) MMAP_ATA; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { @@ -136,24 +141,27 @@ void ide_set_reset(int idereset) }; /* PIO 4 */ if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(10000); } else { #define CALC_TIMING(t) (t + period - 1) / period period = 1000000000 / gd->bus_clk; /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(200000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 9f1ec38..fd9bddd 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,14 +41,14 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); udelay(100); diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index fbc0888..fb216d8 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,14 +41,14 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); udelay(100); diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index 5c54357..7e3fa1a 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -24,18 +24,56 @@ #include <common.h> #include <hwconfig.h> #include <i2c.h> +#include <spi.h> #include <libfdt.h> #include <fdt_support.h> #include <pci.h> #include <mpc83xx.h> #include <vsc7385.h> #include <netdev.h> +#include <fsl_esdhc.h> #include <asm/io.h> #include <asm/fsl_serdes.h> #include <asm/fsl_mpc83xx_serdes.h> DECLARE_GLOBAL_DATA_PTR; +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_MPC8XXX_SPI + +#define SPI_CS_MASK 0x00400000 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* active low */ + clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* inactive high */ + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} +#endif /* CONFIG_MPC8XXX_SPI */ + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + return fsl_esdhc_mmc_init(bd); +} +#endif + static u8 read_board_info(void) { u8 val8; @@ -109,6 +147,25 @@ void pci_init_board(void) */ int misc_init_r(void) { +#ifdef CONFIG_MPC8XXX_SPI + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* + * Set proper bits in SICRH to allow SPI on header J8 + * + * NOTE: this breaks the TSEC2 interface, attached to the Vitesse + * switch. The pinmux configuration does not have a fine enough + * granularity to support both simultaneously. + */ + clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); + puts("WARNING: SPI enabled, TSEC2 support is broken\n"); + + /* Set header J8 SPI chip select output, disabled */ + setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +#endif + #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { @@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); } #endif diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 40d8cf6..ae6eda3 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -173,12 +173,12 @@ const iomux_cfg_t iomux_setup[] = { #define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ ADDR_PINS << 8 | APREBIT) -void mx28_adjust_memory_params(uint32_t *dram_vals) +void mxs_adjust_memory_params(uint32_t *dram_vals) { dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; } void board_init_ll(void) { - mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 1bc83e9..d782aea 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -49,8 +49,8 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + /* SSP2 clock at 160MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); @@ -64,7 +64,7 @@ int board_early_init_f(void) int dram_init(void) { - return mx28_dram_init(); + return mxs_dram_init(); } int board_init(void) @@ -115,8 +115,8 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; diff --git a/board/freescale/mx28evk/u-boot.bd b/board/freescale/mx28evk/u-boot.bd deleted file mode 100644 index c60615a..0000000 --- a/board/freescale/mx28evk/u-boot.bd +++ /dev/null @@ -1,14 +0,0 @@ -sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; -} - -section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; - hab call 0x8000; - - load u_boot > 0x40000100; - load ivt (entry = 0x40000100) > 0x8000; - hab call 0x8000; -} diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README index 3d69ed5..7232b53 100644 --- a/board/freescale/mx35pdk/README +++ b/board/freescale/mx35pdk/README @@ -71,91 +71,17 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf Flashing U-Boot -------------------------------- -There are two options: the original bootloader in NAND can be replaced with -u-boot, or u-boot can be stored on the NOR flash without erasing -the delivered bootloader. +U-boot should be stored on the NOR flash. + The boot storage can be select using the switches on the personality board (SW1-SW2) and on the DEBUG board (SW4-SW10). -The second option is to be preferred if you have not a JTAG debugger. If something goes wrong flashing the bootloader, it is always possible to recover the board booting from the other device. -Replacing the bootloader on the NAND --------------------------------------- -To replace RedBoot with U-Boot, the easy way is to do this in linux. -Start the kernel with the suggested options. Make sure to have set the -mtdparts exactly as described, because this matches the layout on the -mx35pdk. - -You should see in your boot log the following entries for the NAND -flash: - -5 cmdlinepart partitions found on MTD device mxc_nand -Creating 5 MTD partitions on "mxc_nand": -0x000000000000-0x000000100000 : "boot" -0x000000100000-0x000000600000 : "linux" -0x000000600000-0x000006600000 : "root" -0x000006600000-0x000006e00000 : "cfg" -0x000006e00000-0x000080000000 : "user" - -You can use the utilities flash_eraseall and nandwrite to put -u-boot on the NAND. The bootloader is marked as "boot", and 1MB is -reserved. If everything is correct, this partition is accessed as -/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and -get the device node from the partition name: - -$ cat /proc/mtd | grep boot - -I suggest you try the utilities on a different partition to be sure -if everything works correctly. If not, and you remove RedBoot, you have to -reinstall it using the ATK tool as suggested by Freescale, or using a -JTAG debugger. - -I report the versions of the utilities I used (they are provided with ELDK): - --bash-3.2# nandwrite --version -nandwrite $Revision: 1.32 $ - -flash_eraseall --version -flash_eraseall $Revision: 1.22 $ - -nandwrite reports a warning if the file to be saved is not sector aligned. -This should have no consequences, but I preferred to pad u-boot.bin -to get no problem at all. -$ dd if=/dev/zero of=zeros bs=1 count=74800 -$ cat u-boot.bin zeros > u-boot-padded.bin - -To erase the partition: -$ flash_eraseall /dev/mtd4 - -Writing u-boot: - -$ nandwrite /dev/mtd4 u-boot-padded.bin - -Now U-Boot is stored on the booting partition. - -To boot from NAND, you have to select the switches as follows: - -Personality board - SW2 1, 4, 5 on - 2, 3, 6, 7, 8 off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 - - Saving U-Boot in the NOR flash --------------------------------- -The procedure to save in the NOR flash is quite the same as to write into the NAND. - Check the partition for boot in the NOR flash. Setting the mtdparts as reported, the boot partition should be /dev/mtd0. diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index bc415b8..7cb6b30 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -32,6 +32,8 @@ #include <i2c.h> #include <pmic.h> #include <fsl_pmic.h> +#include <mmc.h> +#include <fsl_esdhc.h> #include <mc9sdz60.h> #include <mc13892.h> #include <linux/types.h> @@ -168,7 +170,7 @@ int board_early_init_f(void) /* enable clocks */ writel(readl(&ccm->cgr0) | MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EDIO_MASK | MXC_CCM_CGR0_EPIT1_MASK, &ccm->cgr0); @@ -275,3 +277,26 @@ int board_eth_init(bd_t *bis) return rc; } + +#if defined(CONFIG_FSL_ESDHC) + +struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; + +int board_mmc_init(bd_t *bis) +{ + /* configure pins for SDHC1 only */ + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); +} +#endif diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 514a7ac..7a0682a 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -39,16 +39,16 @@ #include <linux/fb.h> #include <ipu_pixfmt.h> -#define MX51EVK_LCD_3V3 (3 * 32 + 9) /* GPIO4_9 */ -#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */ -#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4) /* GPIO3_4 */ +#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9) +#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10) +#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4) DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1}, - {MMC_SDHC2_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, }; #endif @@ -319,11 +319,11 @@ static void power_init(void) pmic_reg_write(p, REG_MODE_1, val); mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1); - gpio_direction_output(46, 0); + gpio_direction_output(IMX_GPIO_NR(2, 14), 0); udelay(500); - gpio_set_value(46, 1); + gpio_set_value(IMX_GPIO_NR(2, 14), 1); } #ifdef CONFIG_FSL_ESDHC @@ -333,14 +333,14 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); - gpio_direction_input(0); + gpio_direction_input(IMX_GPIO_NR(1, 0)); mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); - gpio_direction_input(6); + gpio_direction_input(IMX_GPIO_NR(1, 6)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(0); + ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); else - ret = !gpio_get_value(6); + ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); return ret; } @@ -536,12 +536,20 @@ int board_late_init(void) setup_iomux_spi(); power_init(); #endif - setenv("stdout", "serial"); return 0; } #endif +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int checkboard(void) { puts("Board: MX51EVK\n"); diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2d21584..08c7795 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -33,7 +33,7 @@ #include <fsl_esdhc.h> #include <asm/gpio.h> -#define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ +#define ETHERNET_INT IMX_GPIO_NR(2, 31) DECLARE_GLOBAL_DATA_PTR; @@ -79,8 +79,8 @@ static void setup_iomux_uart(void) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1 }, - {MMC_SDHC2_BASE_ADDR, 1 }, + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) @@ -89,14 +89,14 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); - gpio_direction_input(1); + gpio_direction_input(IMX_GPIO_NR(1, 1)); mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); - gpio_direction_input(4); + gpio_direction_input(IMX_GPIO_NR(1, 4)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(1); /* GPIO1_1 */ + ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); else - ret = !gpio_get_value(4); /* GPIO1_4 */ + ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); return ret; } diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 8a6e31d..b11a94c 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -28,6 +28,7 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/errno.h> +#include <asm/imx-common/boot_mode.h> #include <netdev.h> #include <i2c.h> #include <mmc.h> @@ -204,8 +205,8 @@ static void setup_iomux_fec(void) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1}, - {MMC_SDHC3_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC3_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) @@ -214,14 +215,14 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); - gpio_direction_input(75); + gpio_direction_input(IMX_GPIO_NR(3, 11)); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); - gpio_direction_input(77); + gpio_direction_input(IMX_GPIO_NR(3, 13)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(77); /* GPIO3_13 */ + ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); else - ret = !gpio_get_value(75); /* GPIO3_11 */ + ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); return ret; } @@ -367,11 +368,23 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, + {NULL, 0}, +}; +#endif + int board_late_init(void) { setup_i2c(1); power_init(); +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif return 0; } diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index cbdcfad..8f82125 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ #include <linux/fb.h> #include <ipu_pixfmt.h> -#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) DECLARE_GLOBAL_DATA_PTR; @@ -165,8 +165,8 @@ static void setup_iomux_fec(void) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1}, - {MMC_SDHC3_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC3_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) @@ -175,14 +175,14 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); - gpio_direction_input(75); + gpio_direction_input(IMX_GPIO_NR(3, 11)); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); - gpio_direction_input(77); + gpio_direction_input(IMX_GPIO_NR(3, 13)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(77); /* GPIO3_13 */ + ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); else - ret = !gpio_get_value(75); /* GPIO3_11 */ + ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); return ret; } @@ -495,14 +495,14 @@ int print_cpuinfo(void) return 0; } -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) { - setenv("stdout", "serial"); - - return 0; + return 1; } -#endif int board_init(void) { diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index c237980..7f35ddd 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -129,14 +129,14 @@ static void setup_iomux_fec(void) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { - {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); - gpio_direction_input(77); - return !gpio_get_value(77); /* GPIO3_13 */ + gpio_direction_input(IMX_GPIO_NR(3, 13)); + return !gpio_get_value(IMX_GPIO_NR(3, 13)); } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 340c4c4..d43b327 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -116,8 +116,8 @@ static void setup_iomux_enet(void) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR, 1}, - {USDHC4_BASE_ADDR, 1}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) @@ -126,8 +126,8 @@ int board_mmc_getcd(struct mmc *mmc) int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(171); /*GPIO6_11*/ - ret = !gpio_get_value(171); + gpio_direction_input(IMX_GPIO_NR(6, 11)); + ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); } else /* Don't have the CD GPIO pin on board */ ret = 1; diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 01e5083..4b4e89b 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -24,11 +24,13 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> #include <asm/arch/mx6x_pins.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> #include <micrel.h> @@ -85,12 +87,12 @@ struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC, - .gp = GPIO_NUMBER(3, 21) + .gp = IMX_GPIO_NR(3, 21) }, .sda = { .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC, - .gp = GPIO_NUMBER(3, 28) + .gp = IMX_GPIO_NR(3, 28) } }; @@ -99,12 +101,12 @@ struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC, - .gp = GPIO_NUMBER(4, 12) + .gp = IMX_GPIO_NR(4, 12) }, .sda = { .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC, - .gp = GPIO_NUMBER(4, 13) + .gp = IMX_GPIO_NR(4, 13) } }; @@ -113,12 +115,12 @@ struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC, .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC, - .gp = GPIO_NUMBER(1, 5) + .gp = IMX_GPIO_NR(1, 5) }, .sda = { .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC, .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC, - .gp = GPIO_NUMBER(7, 11) + .gp = IMX_GPIO_NR(7, 11) } }; @@ -195,18 +197,18 @@ static iomux_v3_cfg_t button_pads[] = { static void setup_iomux_enet(void) { - gpio_direction_output(87, 0); /* GPIO 3-23 */ - gpio_direction_output(190, 1); /* GPIO 6-30 */ - gpio_direction_output(185, 1); /* GPIO 6-25 */ - gpio_direction_output(187, 1); /* GPIO 6-27 */ - gpio_direction_output(188, 1); /* GPIO 6-28*/ - gpio_direction_output(189, 1); /* GPIO 6-29 */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(184, 1); /* GPIO 6-24 */ + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); - gpio_set_value(87, 1); /* GPIO 3-23 */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } @@ -227,9 +229,9 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); /* Reset USB hub */ - gpio_direction_output(GPIO_NUMBER(7, 12), 0); + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); mdelay(2); - gpio_set_value(GPIO_NUMBER(7, 12), 1); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); return 0; } @@ -237,8 +239,8 @@ int board_ehci_hcd_init(int port) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR, 1}, - {USDHC4_BASE_ADDR, 1}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) @@ -247,11 +249,11 @@ int board_mmc_getcd(struct mmc *mmc) int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(192); /*GPIO7_0*/ - ret = !gpio_get_value(192); + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); } else { - gpio_direction_input(38); /*GPIO2_6*/ - ret = !gpio_get_value(38); + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); } return ret; @@ -411,12 +413,12 @@ struct button_key { }; static struct button_key const buttons[] = { - {"back", GPIO_NUMBER(2, 2), 'B'}, - {"home", GPIO_NUMBER(2, 4), 'H'}, - {"menu", GPIO_NUMBER(2, 1), 'M'}, - {"search", GPIO_NUMBER(2, 3), 'S'}, - {"volup", GPIO_NUMBER(7, 13), 'V'}, - {"voldown", GPIO_NUMBER(4, 5), 'v'}, + {"back", IMX_GPIO_NR(2, 2), 'B'}, + {"home", IMX_GPIO_NR(2, 4), 'H'}, + {"menu", IMX_GPIO_NR(2, 1), 'M'}, + {"search", IMX_GPIO_NR(2, 3), 'S'}, + {"volup", IMX_GPIO_NR(7, 13), 'V'}, + {"voldown", IMX_GPIO_NR(4, 5), 'v'}, }; /* @@ -487,10 +489,23 @@ static void preboot_keys(void) } #endif +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + int misc_init_r(void) { #ifdef CONFIG_PREBOOT preboot_keys(); #endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif return 0; } diff --git a/board/efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile index bd2174f..f95356f 100644 --- a/board/efikamx/Makefile +++ b/board/genesi/mx51_efikamx/Makefile @@ -27,11 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := efikamx.o - -ifdef CONFIG_CMD_USB -COBJS += efikamx-usb.o -endif +COBJS := efikamx.o efikamx-usb.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index 618b39d..cf020c3 100644 --- a/board/efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -33,7 +33,7 @@ #include <usb/ulpi.h> #include <errno.h> -#include "../../drivers/usb/host/ehci.h" +#include "../../../drivers/usb/host/ehci.h" /* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ @@ -214,3 +214,15 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) if (port) mdelay(10); } + +/* + * Ethernet on the Smarttop is on the USB bus. Rather than give an error about + * "CPU Net Initialization Failed", just pass this test since no other settings + * are required. Smartbook doesn't have built-in Ethernet but we will let it + * pass anyway considering someone may have plugged in a USB stick and all + * they need to do is run "usb start". + */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c new file mode 100644 index 0000000..cfd2e93 --- /dev/null +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -0,0 +1,509 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2009-2012 Genesi USA, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx51.h> +#include <asm/gpio.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <pmic.h> +#include <fsl_pmic.h> +#include <mc13892.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Compile-time error checking + */ +#ifndef CONFIG_MXC_SPI +#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" +#endif + +/* + * Board revisions + * + * Note that we get these revisions here for convenience, but we only set + * up for the production model Smarttop (1.3) and Smartbook (2.0). + * + */ +#define EFIKAMX_BOARD_REV_11 0x1 +#define EFIKAMX_BOARD_REV_12 0x2 +#define EFIKAMX_BOARD_REV_13 0x3 +#define EFIKAMX_BOARD_REV_14 0x4 + +#define EFIKASB_BOARD_REV_13 0x1 +#define EFIKASB_BOARD_REV_20 0x2 + +/* + * Board identification + */ +static u32 get_mx_rev(void) +{ + u32 rev = 0; + /* + * Retrieve board ID: + * + * gpio: 16 17 11 + * ============== + * r1.1: 1+ 1 1 + * r1.2: 1 1 0 + * r1.3: 1 0 1 + * r1.4: 1 0 0 + * + * + note: r1.1 does not strap this pin properly so it needs to + * be hacked or ignored. + */ + + /* set to 1 in order to get correct value on board rev 1.1 */ + gpio_direction_output(IMX_GPIO_NR(3, 16), 1); + gpio_direction_input(IMX_GPIO_NR(3, 11)); + gpio_direction_input(IMX_GPIO_NR(3, 16)); + gpio_direction_input(IMX_GPIO_NR(3, 17)); + + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0; + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1; + rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2; + + return (~rev & 0x7) + 1; +} + +static iomux_v3_cfg_t efikasb_revision_pads[] = { + MX51_PAD_EIM_CS3__GPIO2_28, + MX51_PAD_EIM_CS4__GPIO2_29, +}; + +static inline u32 get_sb_rev(void) +{ + u32 rev = 0; + + imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, + ARRAY_SIZE(efikasb_revision_pads)); + gpio_direction_input(IMX_GPIO_NR(2, 28)); + gpio_direction_input(IMX_GPIO_NR(2, 29)); + + rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0; + rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1; + + return rev; +} + +inline uint32_t get_efikamx_rev(void) +{ + if (machine_is_efikamx()) + return get_mx_rev(); + else if (machine_is_efikasb()) + return get_sb_rev(); +} + +u32 get_board_rev(void) +{ + return get_cpu_rev() | (get_efikamx_rev() << 8); +} + +/* + * DRAM initialization + */ +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +/* + * UART configuration + */ +static iomux_v3_cfg_t efikamx_uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +}; + +/* + * SPI configuration + */ +static iomux_v3_cfg_t efikamx_spi_pads[] = { + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, +}; + +#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25) +#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6) + +/* + * PMIC configuration + */ +#ifdef CONFIG_MXC_SPI +static void power_init(void) +{ + unsigned int val; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Write needed to Power Gate 2 register */ + pmic_reg_read(p, REG_POWER_MISC, &val); + val &= ~PWGT2SPIEN; + pmic_reg_write(p, REG_POWER_MISC, val); + + /* Externally powered */ + pmic_reg_read(p, REG_CHARGE, &val); + val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; + pmic_reg_write(p, REG_CHARGE, val); + + /* power up the system first */ + pmic_reg_write(p, REG_POWER_MISC, PWUP); + + /* Set core voltage to 1.1V */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + pmic_reg_write(p, REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + pmic_reg_read(p, REG_SW_2, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + pmic_reg_read(p, REG_SW_4, &val); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(p, REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + pmic_reg_read(p, REG_SW_5, &val); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); + pmic_reg_write(p, REG_SW_5, val); + + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ + pmic_reg_read(p, REG_SETTING_0, &val); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(p, REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + pmic_reg_read(p, REG_SETTING_1, &val); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; + pmic_reg_write(p, REG_SETTING_1, val); + + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(p, REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(p, REG_MODE_1, val); + + pmic_reg_read(p, REG_POWER_CTL2, &val); + val |= WDIRESET; + pmic_reg_write(p, REG_POWER_CTL2, val); + + udelay(2500); +} +#else +static inline void power_init(void) { } +#endif + +/* + * MMC configuration + */ +#ifdef CONFIG_FSL_ESDHC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, +}; + +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__SD1_WP, +}; + +#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1) + +static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = { + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_EIM_CS2__SD1_CD, +}; + +#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0) +#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27) + +static iomux_v3_cfg_t efikasb_sdhc2_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, +}; + +#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8) +#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7) + +static inline uint32_t efikamx_mmc_getcd(u32 base) +{ + if (base == MMC_SDHC1_BASE_ADDR) + if (machine_is_efikamx()) + return EFIKAMX_SDHC1_CD; + else + return EFIKASB_SDHC1_CD; + else + return EFIKASB_SDHC2_CD; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base); + int ret = !gpio_get_value(cd); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* + * All Efika MX boards use eSDHC1 with a common write-protect GPIO + */ + imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, + ARRAY_SIZE(efikamx_sdhc1_pads)); + gpio_direction_input(EFIKAMX_SDHC1_WP); + + /* + * Smartbook and Smarttop differ on the location of eSDHC1 + * carrier-detect GPIO + */ + if (machine_is_efikamx()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); + gpio_direction_input(EFIKAMX_SDHC1_CD); + } else if (machine_is_efikasb()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); + gpio_direction_input(EFIKASB_SDHC1_CD); + } + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + if (machine_is_efikasb()) { + + imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, + ARRAY_SIZE(efikasb_sdhc2_pads)); + gpio_direction_input(EFIKASB_SDHC2_CD); + gpio_direction_input(EFIKASB_SDHC2_WP); + if (!ret) + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); + } + + return ret; +} +#endif + +/* + * PATA + */ +static iomux_v3_cfg_t efikamx_pata_pads[] = { + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, +}; + +/* + * EHCI USB + */ +#ifdef CONFIG_CMD_USB +extern void setup_iomux_usb(void); +#else +static inline void setup_iomux_usb(void) { } +#endif + +/* + * LED configuration + * + * Smarttop LED pad config is done in the DCD + * + */ +#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13) +#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14) +#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15) + +static iomux_v3_cfg_t efikasb_led_pads[] = { + MX51_PAD_GPIO1_3__GPIO1_3, + MX51_PAD_EIM_CS0__GPIO2_25, +}; + +#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25) +#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */ + +/* + * Board initialization + */ +int board_early_init_f(void) +{ + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, + ARRAY_SIZE(efikasb_led_pads)); + gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); + gpio_direction_output(EFIKASB_MESSAGE_LED, 1); + } else if (machine_is_efikamx()) { + /* + * Set up GPIO directions for LEDs. + * IOMUX has been done in the DCD already. + * Turn the red LED on for pre-relocation code. + */ + gpio_direction_output(EFIKAMX_LED_BLUE, 0); + gpio_direction_output(EFIKAMX_LED_GREEN, 0); + gpio_direction_output(EFIKAMX_LED_RED, 1); + } + + /* + * Both these pad configurations for UART and SPI are kind of redundant + * since they are the Power-On Defaults for the i.MX51. But, it seems we + * should make absolutely sure that they are set up correctly. + */ + imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, + ARRAY_SIZE(efikamx_uart_pads)); + imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, + ARRAY_SIZE(efikamx_spi_pads)); + + /* not technically required for U-Boot operation but do it anyway. */ + gpio_direction_input(EFIKAMX_PMIC_IRQ); + /* Deselect both CS for now, otherwise NOR doesn't probe properly. */ + gpio_direction_output(EFIKAMX_SPI_SS0, 0); + gpio_direction_output(EFIKAMX_SPI_SS1, 1); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + if (machine_is_efikamx()) { + /* + * Set up Blue LED for "In U-Boot" status. + * We're all relocated and ready to U-Boot! + */ + gpio_set_value(EFIKAMX_LED_RED, 0); + gpio_set_value(EFIKAMX_LED_GREEN, 0); + gpio_set_value(EFIKAMX_LED_BLUE, 1); + } + + power_init(); + + imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, + ARRAY_SIZE(efikamx_pata_pads)); + setup_iomux_usb(); + + return 0; +} + +int checkboard(void) +{ + u32 rev = get_efikamx_rev(); + + printf("Board: Genesi Efika MX "); + if (machine_is_efikamx()) + printf("Smarttop (1.%i)\n", rev & 0xf); + else if (machine_is_efikasb()) + printf("Smartbook\n"); + + return 0; +} diff --git a/board/efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..38fa760 100644 --- a/board/efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,5 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> +# Copyright (C) 2009-2012 Genesi USA, Inc. # # BASED ON: imx51evk # @@ -43,30 +45,32 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register -# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 +# Essential GPIO settings to be done as early as possible +# PCBIDn pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15 -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3 # Setting DDR for micron # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model diff --git a/board/efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg index 878146f..26d259f 100644 --- a/board/efikamx/imximage_sb.cfg +++ b/board/genesi/mx51_efikamx/imximage_sb.cfg @@ -1,5 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> +# Copyright (C) 2009-2012 Genesi USA, Inc. # # BASED ON: imx51evk # @@ -43,30 +45,22 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register -# Setting IOMUXC -DATA 4 0x73fa88a0 0x200 -DATA 4 0x73fa850c 0x20c3 -DATA 4 0x73fa8510 0x20c3 -DATA 4 0x73fa883c 0x2 -DATA 4 0x73fa8848 0x2 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe3 -DATA 4 0x73fa84b0 0xe3 -DATA 4 0x73fa84b4 0xe3 -DATA 4 0x73fa84cc 0xe3 -DATA 4 0x73fa84d0 0xe2 - -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa88a0 0x200 # GRP_INMODE1 +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa8848 0x4 # DDR_A1 +DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK +DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0 +DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1 +DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2 +DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3 +DATA 4 0x73fa8820 0x0 # DDRPKS +DATA 4 0x73fa84ac 0xe5 # SDWE +DATA 4 0x73fa84b0 0xe5 # SDCKE0 +DATA 4 0x73fa84b4 0xe5 # SDCKE1 +DATA 4 0x73fa84cc 0xe5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xe4 # DRAM_CS1 # Setting DDR for micron # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model @@ -108,7 +102,7 @@ DATA 4 0x83fd9014 0x00008014 DATA 4 0x83fd9014 0x00008014 DATA 4 0x83fd9014 0x0632801c DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0040801d +DATA 4 0x83fd9014 0x0042801d DATA 4 0x83fd9014 0x00008004 # Write to CTL0 diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 8f75af1..454ff0a 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define HOT_WATER_BUTTON 38 + #ifdef CONFIG_USB_EHCI static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, @@ -68,6 +70,27 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) { + puts("Failed to get hot-water-button pin\n"); + return -ENODEV; + } + gpio_direction_input(HOT_WATER_BUTTON); + + /* + * if hot-water-button is pressed + * change bootcmd + */ + if (gpio_get_value(HOT_WATER_BUTTON)) + return 0; + + setenv("bootcmd", "run swupdate"); + return 0; +} +#endif + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index d675a48..867cc9e 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -284,9 +284,14 @@ const omap3_sysinfo sysinfo = { /* HSUSB2_dat3 */\ /* CCDC */\ MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + /* CCDC_FIELD: gpio_95, uP-TXD4 */ \ + MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \ + /* CCDC_HD: gpio_96, uP-RTS4# */ \ + MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \ + /* CCDC_VD: gpio_97, uP-CTS4# */ \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \ + /* CCDC_WEN: gpio_98, uP-RXD4 */ \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile new file mode 100644 index 0000000..e05b9c1 --- /dev/null +++ b/board/ifm/o2dnt2/Makefile @@ -0,0 +1,34 @@ +# +# (C) Copyright 2005-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c new file mode 100644 index 0000000..40a5305 --- /dev/null +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -0,0 +1,400 @@ +/* + * Partially derived from board code for digsyMTC, + * (C) Copyright 2009 + * Grzegorz Bernacki, Semihalf, gjb@semihalf.com + * + * (C) Copyright 2012 + * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <miiphy.h> +#include <net.h> +#include <pci.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +enum ifm_sensor_type { + O2DNT = 0x00, /* !< O2DNT 32MB */ + O2DNT2 = 0x01, /* !< O2DNT2 64MB */ + O3DNT = 0x02, /* !< O3DNT 32MB */ + O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */ + UNKNOWN = 0xff, /* !< Unknow sensor */ +}; + +static enum ifm_sensor_type gt_ifm_sensor_type; + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start(int hi_addr) +{ + struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + long control = SDRAM_CONTROL | hi_addr_bit; + + /* unlock mode register */ + out_be32(&sdram->ctrl, control | 0x80000000); + + /* precharge all banks */ + out_be32(&sdram->ctrl, control | 0x80000002); + + /* auto refresh */ + out_be32(&sdram->ctrl, control | 0x80000004); + + /* set mode register */ + out_be32(&sdram->mode, SDRAM_MODE); + + /* normal operation */ + out_be32(&sdram->ctrl, control); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if + * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. + */ +phys_size_t initdram(int board_type) +{ + struct mpc5xxx_mmap_ctl *mmap_ctl = + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; + + if (gt_ifm_sensor_type == O2DNT2) { + /* activate SDRAM CS1 */ + setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000); + } + +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */ + out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */ + + /* setup config registers */ + out_be32(&sdram->config1, SDRAM_CONFIG1); + out_be32(&sdram->config2, SDRAM_CONFIG2); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32(&mmap_ctl->sdram0, + (0x13 + __builtin_ffs(dramsize >> 20) - 1)); + } else { + out_be32(&mmap_ctl->sdram0, 0); /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), + 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), + 0x80000000); + } + + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) + dramsize2 = 0; + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + out_be32(&mmap_ctl->sdram1, (dramsize | + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); + } else { + out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */ + } + +#else /* CONFIG_SYS_RAMBOOT */ + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) + out_be32(&sdram->sdelay, 0x04); + + return dramsize + dramsize2; +} + + +#define GPT_GPIO_IN 0x4 + +int checkboard(void) +{ + struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; + unsigned char board_config = 0; + int i; + + /* switch gpt0 - gpt7 to input */ + for (i = 0; i < 7; i++) + out_be32(&gpt[i].emsr, GPT_GPIO_IN); + + /* get configuration byte on timer-port */ + for (i = 0; i < 7; i++) + board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i); + + puts("Board: "); + + switch (board_config) { + case 0: + puts("O2DNT\n"); + gt_ifm_sensor_type = O2DNT; + break; + case 1: + puts("O3DNT\n"); + gt_ifm_sensor_type = O3DNT; + break; + case 2: + puts("O2DNT2\n"); + gt_ifm_sensor_type = O2DNT2; + break; + case 64: + puts("O3DNT Minerva\n"); + gt_ifm_sensor_type = O3DNT_MIN; + break; + default: + puts("Unknown\n"); + gt_ifm_sensor_type = UNKNOWN; + break; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB; + + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in flash. + */ + clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */ + /* disable CS_BOOT */ + clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); + /* enable CS0 */ + setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); + + return 0; +} + +#define MIIM_LXT971_LED_CFG_REG 0x14 +#define LXT971_LED_CFG_LINK_STATUS 0x4000 +#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700 +#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0 +#define LXT971_LED_CFG_PULSE_STRETCH 0x0002 +/* + * Additional PHY intialization after reset in mpc5xxx_fec_init_phy() + */ +void reset_phy(void) +{ + /* + * Set LED configuration bits. + * It can't be done in misc_init_r() since FEC is not + * initialized at this time. Therefore we do it here. + */ + miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG, + LXT971_LED_CFG_LINK_STATUS | + LXT971_LED_CFG_RX_TX_ACTIVITY | + LXT971_LED_CFG_LINK_ACTIVITY | + LXT971_LED_CFG_PULSE_STRETCH); +} + +#if defined(CONFIG_POST) +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + clrbits_be32(&gpio->port_config, 0x07000000); + setbits_be32(&gpio->port_config, 0x03000000); + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + setbits_be32(&gpio->simple_gpioe, 0x20000000); + + /* Configure GPIO_IRDA_1 as input */ + clrbits_be32(&gpio->simple_ddr, 0x20000000); + + return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1; +} +#endif + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) +static void ft_adapt_flash_base(void *blob) +{ + flash_info_t *dev = &flash_info[0]; + int off; + struct fdt_property *prop; + int len; + u32 *reg, *reg2; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); + if (off < 0) { + printf("Could not find fsl,mpc5200b-lpb node.\n"); + return; + } + + /* found compatible property */ + prop = fdt_get_property_w(blob, off, "ranges", &len); + if (prop) { + reg = reg2 = (u32 *)&prop->data[0]; + + reg[2] = dev->start[0]; + reg[3] = dev->size; + fdt_setprop(blob, off, "ranges", reg2, len); + } else + printf("Could not find ranges\n"); +} + +extern ulong flash_get_size(phys_addr_t base, int banknum); + +/* Update the flash baseaddr settings */ +int update_flash_size(int flash_size) +{ + struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; + flash_info_t *dev; + int i; + int size = 0; + unsigned long base = 0x0; + u32 *cs_reg = (u32 *)&mm->cs0_start; + + for (i = 0; i < 2; i++) { + dev = &flash_info[i]; + + if (dev->size) { + /* calculate new base addr for this chipselect */ + base -= dev->size; + out_be32(cs_reg, START_REG(base)); + cs_reg++; + out_be32(cs_reg, STOP_REG(base, dev->size)); + cs_reg++; + /* recalculate the sectoraddr in the cfi driver */ + size += flash_get_size(base, i); + } + } + flash_protect_default(); + gd->bd->bi_flashstart = base; + return 0; +} +#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ + +void ft_board_setup(void *blob, bd_t *bd) +{ + int phy_addr = CONFIG_PHY_ADDR; + char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; + + ft_cpu_setup(blob, bd); + +#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) +#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE + /* Update reg property in all nor flash nodes too */ + fdt_fixup_nor_flash_size(blob); +#endif + ft_adapt_flash_base(blob); +#endif + /* fix up the phy address */ + do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk deleted file mode 100644 index 7964621..0000000 --- a/board/isee/igep0020/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 971e31b..a8257a3 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -58,6 +58,46 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; +#else + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } +#endif +} +#endif + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -91,7 +131,7 @@ static void setup_net_chip(void) } #endif -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h index 3d6e15f..3335ecc 100644 --- a/board/isee/igep0020/igep0020.h +++ b/board/isee/igep0020/igep0020.h @@ -26,7 +26,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, "IGEP v2 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", +#else + "NAND", +#endif }; static void setup_net_chip(void); diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 653c1b5..107cb7f 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -45,7 +45,47 @@ int board_init(void) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; +#else + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } +#endif +} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h index b7ce5aa..a93339d 100644 --- a/board/isee/igep0030/igep0030.h +++ b/board/isee/igep0030/igep0030.h @@ -26,7 +26,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, "OMAP3 IGEP module", +#if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", +#else + "NAND", +#endif }; /* diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 2a29943..362f00a 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -34,14 +34,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FEC_MXC +#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) +#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) + void tx25_fec_init(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; - u32 val; u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; - struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; debug("tx25_fec_init\n"); @@ -66,18 +66,15 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ - val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->gpio_dr); - val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->gpio_dir); + gpio_direction_output(GPIO_FEC_RESET_B, 0); + gpio_direction_output(GPIO_FEC_ENABLE_B, 0); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->gpio_dr) | 1 << 9; - writel(val, &gpio4->gpio_dr); + gpio_set_value(GPIO_FEC_ENABLE_B, 1); mdelay(10); @@ -107,19 +104,16 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dr); - val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dir); + gpio_direction_output(IMX_GPIO_NR(3, 10), 1); + gpio_direction_output(IMX_GPIO_NR(3, 11), 1); + gpio_direction_output(IMX_GPIO_NR(3, 12), 1); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ - val = readl(&gpio4->gpio_dr) | 1 << 7; - writel(val, &gpio4->gpio_dr); - writel(val, &gpio4->gpio_dr); + gpio_set_value(GPIO_FEC_RESET_B, 1); mdelay(5); diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index 9bc3c21..eaa924f 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -163,7 +163,7 @@ static int ivm_findinventorystring(int type, if (addr == INVENTORYDATASIZE) { xcode = -1; printf("Error end of string not found\n"); - } else if ((size >= (maxlen - 1)) && + } else if ((size > (maxlen - 1)) && (buf[addr] != '\r')) { xcode = -1; printf("string too long till next CR\n"); diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2b2ca39..be8f51c 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -331,26 +331,6 @@ void board_spi_release_bus(struct spi_slave *slave) kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); } -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - /* Fix this */ - gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), - kw_sdram_bs(0)); - return 0; -} - -void dram_init_banksize(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), - kw_sdram_bs(i)); - } -} - #if (defined(CONFIG_KM_PIGGY4_88E6061)) #define PHY_LED_SEL_REG 0x18 @@ -408,57 +388,6 @@ int hush_init_var(void) } #endif -#if defined(CONFIG_BOOTCOUNT_LIMIT) -const ulong patterns[] = { 0x00000000, - 0xFFFFFFFF, - 0xFF00FF00, - 0x0F0F0F0F, - 0xF0F0F0F0}; -const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns); -const ulong OFFS_PATTERN = 3; -const ulong REPEAT_PATTERN = 1000; - -void bootcount_store(ulong a) -{ - ulong *save_addr; - ulong size = 0; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; - save_addr = (ulong *)(size - BOOTCOUNT_ADDR); - writel(a, save_addr); - writel(BOOTCOUNT_MAGIC, &save_addr[1]); - - for (i = 0; i < REPEAT_PATTERN; i++) - writel(patterns[i % NBR_OF_PATTERNS], - &save_addr[i+OFFS_PATTERN]); - -} - -ulong bootcount_load(void) -{ - ulong *save_addr; - ulong size = 0; - ulong counter = 0; - int i, tmp; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; - save_addr = (ulong *)(size - BOOTCOUNT_ADDR); - - counter = readl(&save_addr[0]); - - /* Is the counter reliable, check in the big pattern for bit errors */ - for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { - tmp = readl(&save_addr[i+OFFS_PATTERN]); - if (tmp != patterns[i % NBR_OF_PATTERNS]) - counter = 0; - } - return counter; -} -#endif - #if defined(CONFIG_SOFT_I2C) void set_sda(int state) { diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 8a5015c..b38e5ab 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -23,12 +23,12 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; #if defined(CONFIG_SYS_NAND_LARGEPAGE) struct system_control_regs *sc_regs = (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; @@ -43,8 +43,7 @@ int board_init(void) #ifdef CONFIG_FEC_MXC mx27_fec_init_pins(); imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31)); - writel(readl(®s->port[PORTC].dr) | (1 << 31), - ®s->port[PORTC].dr); + gpio_set_value(GPIO_PORTC | 31, 1); #endif #ifdef CONFIG_MXC_MMC #if defined(CONFIG_MAGNESIUM) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index e65fc9e..afe832a 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -25,7 +25,7 @@ #include <ns16550.h> #include <linux/compiler.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/sys_proto.h> #include <asm/arch/board.h> @@ -45,10 +45,11 @@ DECLARE_GLOBAL_DATA_PTR; -const struct tegra2_sysinfo sysinfo = { - CONFIG_TEGRA2_BOARD_STRING +const struct tegra_sysinfo sysinfo = { + CONFIG_TEGRA_BOARD_STRING }; +#ifndef CONFIG_SPL_BUILD /* * Routine: timer_init * Description: init the timestamp and lastinc value @@ -57,6 +58,7 @@ int timer_init(void) { return 0; } +#endif void __pin_mux_usb(void) { @@ -76,8 +78,8 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); */ static void power_det_init(void) { -#if defined(CONFIG_TEGRA2) - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; +#if defined(CONFIG_TEGRA20) + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; /* turn off power detects */ writel(0, &pmc->pmc_pwr_det_latch); @@ -130,7 +132,10 @@ int board_init(void) board_usb_init(gd->fdt_blob); #endif -#ifdef CONFIG_TEGRA2_LP0 +#ifdef CONFIG_TEGRA_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 8e4290c..739d4bd 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -28,7 +28,7 @@ #include <asm/arch/emc.h> #include <asm/arch/pmu.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 307937a..6b21758 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -24,7 +24,7 @@ #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart-spi-switch.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/tegra_spi.h> diff --git a/board/nvidia/dts/tegra2-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index 4f60a05..ca5facb 100644 --- a/board/nvidia/dts/tegra2-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -3,7 +3,7 @@ /include/ ARCH_CPU_DTS / { - model = "NVIDIA Tegra2 Harmony evaluation board"; + model = "NVIDIA Tegra20 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; aliases { @@ -54,4 +54,14 @@ usb@c5004000 { status = "disabled"; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 3352539..25a63a0 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -153,4 +153,14 @@ 0x1f04008a>; linux,fn-keymap = <0x05040002>; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/nvidia/dts/tegra2-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index 900e871..38b7b13 100644 --- a/board/nvidia/dts/tegra2-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -3,7 +3,7 @@ /include/ ARCH_CPU_DTS / { - model = "NVIDIA Tegra2 Ventana evaluation board"; + model = "NVIDIA Tegra20 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; aliases { diff --git a/board/nvidia/dts/tegra2-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index b22d407..38599bd 100644 --- a/board/nvidia/dts/tegra2-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -3,7 +3,7 @@ /include/ ARCH_CPU_DTS / { - model = "NVIDIA Tegra2 Whistler evaluation board"; + model = "NVIDIA Tegra20 Whistler evaluation board"; compatible = "nvidia,whistler", "nvidia,tegra20"; aliases { diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index b6efa1c..88b9dcf 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index f27ad37..b4a811d 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> @@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init SD slot J26\n"); /* init dev 0, SD slot J26, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); + tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); debug("board_mmc_init: init SD slot J5\n"); /* init dev 2, SD slot J5, with 4-bit bus */ - tegra2_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); + tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); return 0; } diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index b6efa1c..88b9dcf 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 36039c4..667f60a 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> @@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra2_mmc_init(0, 4, -1, -1); + tegra_mmc_init(0, 4, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 1, SD slot, with 4-bit bus */ - tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); + tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); return 0; } diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile index e3b7435..147d0bc 100644 --- a/board/nvidia/ventana/Makefile +++ b/board/nvidia/ventana/Makefile @@ -24,9 +24,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common $(obj)../seaboard) -endif +$(shell mkdir -p $(obj)../seaboard) LIB = $(obj)lib$(BOARD).o diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile index a910577..913f1ce 100644 --- a/board/nvidia/whistler/Makefile +++ b/board/nvidia/whistler/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 3ec24df..598b2e5 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -24,7 +24,7 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> @@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ - tegra2_mmc_init(0, 8, -1, -1); + tegra_mmc_init(0, 8, -1, -1); /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ - tegra2_mmc_init(1, 8, -1, -1); + tegra_mmc_init(1, 8, -1, -1); return 0; } diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c deleted file mode 100644 index 9f30880..0000000 --- a/board/o2dnt/flash.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * flash_real_protect() routine based on boards/alaska/flash.c - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* Intel-compatible flash commands */ -#define INTEL_ERASE 0x20 -#define INTEL_PROGRAM 0x40 -#define INTEL_CLEAR 0x50 -#define INTEL_LOCKBIT 0x60 -#define INTEL_PROTECT 0x01 -#define INTEL_STATUS 0x70 -#define INTEL_READID 0x90 -#define INTEL_READID 0x90 -#define INTEL_SUSPEND 0xB0 -#define INTEL_CONFIRM 0xD0 -#define INTEL_RESET 0xFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80 -#define INTEL_OK 0x80 - -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV -#define FLASH_ID_MASK 0xFF - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); -static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */ -static void flash_sync_real_protect (flash_info_t * info); -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - extern void flash_preinit(void); - extern void flash_afterinit(ulong); - - flash_preinit(); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Query flash chip */ - flash_info[0].size = - flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - size += flash_info[0].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - flash_afterinit(size); - return (size ? size : 1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) INTEL_RESET; /* Intel Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info); -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - fmt = "28F128J3 (128 Mbit, uniform sectors)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW) INTEL_READID; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Strataflash is configurable to 8/16bit Bus, - * but the Query-Structure is Word-orientated */ - if (info->flash_id != FLASH_UNKNOWN) { - switch ((FPW)addr[2]) { - case (FPW)INTEL_ID_28F128J3: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = (ulong)addr + (i * 0x20000); - break; /* => Intel Strataflash 16MB */ - default: - printf("Flash_id != %xd\n", (FPW)addr[2]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!", - prot); - - printf ("\n"); - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 80us for Intel - let's wait 1 ms */ - udelay (1000); - - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) INTEL_SUSPEND;/* suspend erase */ - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - res = write_data(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, FPWV *dest, FPW data) -{ - FPWV *addr = dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) INTEL_PROGRAM; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) INTEL_RESET; /* restore read mode */ - if (flag) - enable_interrupts(); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - FPWV *addr = (FPWV *) (info->start[sector]); - int flag = disable_interrupts (); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer (0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint) addr, (uint) * addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) { - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) { - start = get_timer (0); - addr = (FPWV *) (info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != - INTEL_FINISHED) { - if (get_timer (start) > - CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts (); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} - - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -static void flash_sync_real_protect (flash_info_t * info) -{ - int i; - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - udelay(1); - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer (0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* wait at least 35ns (W12) before reading */ - udelay(1); - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector] + 4; - ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c deleted file mode 100644 index c72a741..0000000 --- a/board/o2dnt/o2dnt.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <netdev.h> - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ - puts ("Board: O2DNT\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x800000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index 54415ce..1060a1f 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -157,32 +157,3 @@ void hw_watchdog_reset(void) davinci_hw_watchdog_reset(); } #endif - -#if defined(CONFIG_BOOTCOUNT_LIMIT) -void bootcount_store(ulong a) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - - /* - * write RTC kick register to enable write - * for RTC Scratch registers. Scratch0 and 1 are - * used for bootcount values. - */ - writel(RTC_KICK0R_WE, ®->kick0r); - writel(RTC_KICK1R_WE, ®->kick1r); - writel(a, ®->scratch0); - writel(BOOTCOUNT_MAGIC, ®->scratch1); -} - -ulong bootcount_load(void) -{ - struct davinci_rtc *reg = - (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - - if (readl(®->scratch1) != BOOTCOUNT_MAGIC) - return 0; - else - return readl(®->scratch0); -} -#endif diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c index 3583d01..d975209 100644 --- a/board/qi/qi_lb60/qi_lb60.c +++ b/board/qi/qi_lb60/qi_lb60.c @@ -69,7 +69,7 @@ static void gpio_init(void) static void cpm_init(void) { struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - uint32_t reg = readw(&cpm->clkgr); + uint32_t reg = readl(&cpm->clkgr); reg |= CPM_CLKGR_IPU | CPM_CLKGR_CIM | @@ -81,7 +81,7 @@ static void cpm_init(void) CPM_CLKGR_UDC | CPM_CLKGR_AIC1; - writew(reg, &cpm->clkgr); + writel(reg, &cpm->clkgr); } int board_early_init_f(void) diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi_b/Makefile new file mode 100644 index 0000000..9d0c377 --- /dev/null +++ b/board/raspberrypi/rpi_b/Makefile @@ -0,0 +1,34 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c new file mode 100644 index 0000000..688b0aa --- /dev/null +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = 0x100; + + return 0; +} diff --git a/board/isee/igep0030/config.mk b/board/samsung/common/Makefile index 059a878..0bcd594 100644 --- a/board/isee/igep0030/config.mk +++ b/board/samsung/common/Makefile @@ -1,9 +1,6 @@ # -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments +# Copyright (C) 2012 Samsung Electronics +# Lukasz Majewski <l.majewski@samsung.com> # # See file CREDITS for list of people who contributed to this # project. @@ -23,11 +20,24 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 + +include $(TOPDIR)/config.mk + +LIB = $(obj)libsamsung.o + +COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c new file mode 100644 index 0000000..d6c3d37 --- /dev/null +++ b/board/samsung/common/multi_i2c.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Lukasz Majewski <l.majewski@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> + +/* Handle multiple I2C buses instances */ +int get_multi_scl_pin(void) +{ + unsigned int bus = I2C_GET_BUS(); + + switch (bus) { + case I2C_0: /* I2C_0 definition - compatibility layer */ + case I2C_5: + return CONFIG_SOFT_I2C_I2C5_SCL; + case I2C_9: + return CONFIG_SOFT_I2C_I2C9_SCL; + default: + printf("I2C_%d not supported!\n", bus); + }; + + return 0; +} + +int get_multi_sda_pin(void) +{ + unsigned int bus = I2C_GET_BUS(); + + switch (bus) { + case I2C_0: /* I2C_0 definition - compatibility layer */ + case I2C_5: + return CONFIG_SOFT_I2C_I2C5_SDA; + case I2C_9: + return CONFIG_SOFT_I2C_I2C9_SDA; + default: + printf("I2C_%d not supported!\n", bus); + }; + + return 0; +} + +int multi_i2c_init(void) +{ + return 0; +} diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 30a5835..1effc9c 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -79,11 +79,7 @@ skip_check_didle: str r1, [r0, #0x0] @ GPIO_CON_OFFSET ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET -#ifdef CONFIG_ONENAND_IPL - orr r1, r1, #(1 << 1) @ 1 * 1-bit -#else bic r1, r1, #(1 << 1) -#endif str r1, [r0, #0x4] @ GPIO_DAT_OFFSET /* Don't setup at s5pc100 */ @@ -182,7 +178,6 @@ skip_check_didle: /* Do not release retention here for S5PC110 */ streq r1, [r0] -#ifndef CONFIG_ONENAND_IPL /* Disable Watchdog */ ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 @@ -193,7 +188,6 @@ skip_check_didle: ldrne r0, =S5PC110_SROMC_BASE ldr r1, =0x9 str r1, [r0] -#endif /* S5PC100 has 3 groups of interrupt sources */ ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 @@ -207,7 +201,6 @@ skip_check_didle: str r3, [r1, #0x14] @ INTENCLEAR str r3, [r2, #0x14] @ INTENCLEAR -#ifndef CONFIG_ONENAND_IPL /* Set all interrupts as IRQ */ str r5, [r0, #0xc] @ INTSELECT str r5, [r1, #0xc] @ INTSELECT @@ -217,120 +210,12 @@ skip_check_didle: str r5, [r0, #0xf00] @ INTADDRESS str r5, [r1, #0xf00] @ INTADDRESS str r5, [r2, #0xf00] @ INTADDRESS -#endif -#ifndef CONFIG_ONENAND_IPL /* for UART */ bl uart_asm_init bl internal_ram_init -#endif - -#ifdef CONFIG_ONENAND_IPL - /* init system clock */ - bl system_clock_init - - /* OneNAND Sync Read Support at S5PC110 only - * RM[15] : Sync Read - * BRWL[14:12] : 7 CLK - * BL[11:9] : Continuous - * VHF[3] : Very High Frequency Enable (Over 83MHz) - * HF[2] : High Frequency Enable (Over 66MHz) - * WM[1] : Sync Write - */ - cmp r7, r8 - ldrne r1, =0xE006 - ldrne r0, =0xB001E442 - strneh r1, [r0] - - /* - * GCE[26] : Gated Clock Enable - * RPE[17] : Enables Read Prefetch - */ - ldrne r1, =((1 << 26) | (1 << 17) | 0xE006) - ldrne r0, =0xB0600000 - strne r1, [r0, #0x100] @ ONENAND_IF_CTRL - ldrne r1, =0x1212 - strne r1, [r0, #0x108] - - /* Board detection to set proper memory configuration */ - cmp r7, r8 - moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ - movne r9, #2 /* r9 has 2Gib default at s5pc110 */ - - ldr r2, =0xE0200200 - ldr r4, [r2, #0x48] - - bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */ - bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */ - bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */ - str r1, [r2, #0x48] - /* For write completion */ - nop - nop - - ldr r3, [r2, #0x44] - and r1, r3, #(0x7 << 2) - mov r1, r1, lsr #2 - cmp r1, #0x5 - moveq r9, #3 - cmp r1, #0x6 - moveq r9, #1 - cmp r1, #0x7 - moveq r9, #2 - and r0, r3, #(0x1 << 1) - mov r0, r0, lsr #1 - orr r1, r1, r0, lsl #3 - cmp r1, #0x8 - moveq r9, #3 - and r1, r3, #(0x7 << 2) - mov r1, r1, lsr #2 - and r0, r3, #(0x1 << 7) - mov r0, r0, lsr #7 - orr r1, r1, r0, lsl #3 - cmp r1, #0x9 - moveq r9, #3 - str r4, [r2, #0x48] /* Restore PULLUP configuration */ - - bl mem_ctrl_asm_init - - /* Wakeup support. Don't know if it's going to be used, untested. */ - ldreq r0, =S5PC100_RST_STAT - ldrne r0, =S5PC110_RST_STAT - ldr r1, [r0] - biceq r1, r1, #0xfffffff7 - moveq r2, #(1 << 3) - bicne r1, r1, #0xfffeffff - movne r2, #(1 << 16) - cmp r1, r2 - bne 1f -wakeup: - /* turn off L2 cache */ - bl l2_cache_disable - - cmp r7, r8 - ldreq r0, =0xC100 - ldrne r0, =0xC110 - - /* invalidate L2 cache also */ - bl invalidate_dcache - - /* turn on L2 cache */ - bl l2_cache_enable - - cmp r7, r8 - /* Load return address and jump to kernel */ - ldreq r0, =S5PC100_INFORM0 - ldrne r0, =S5PC110_INFORM0 - - /* r1 = physical address of s5pc1xx_cpu_resume function */ - ldr r1, [r0] - /* Jump to kernel (sleep-s5pc1xx.S) */ - mov pc, r1 - nop - nop -#else cmp r7, r8 /* Clear wakeup status register */ ldreq r0, =S5PC100_WAKEUP_STAT @@ -347,7 +232,6 @@ wakeup: orr r1, r1, r2 str r1, [r0] -#endif b 1f didle_wakeup: @@ -517,7 +401,6 @@ system_clock_init: mov pc, lr -#ifndef CONFIG_ONENAND_IPL internal_ram_init: ldreq r0, =0xE3800000 ldrne r0, =0xF1500000 @@ -525,9 +408,7 @@ internal_ram_init: str r1, [r0] mov pc, lr -#endif -#ifndef CONFIG_ONENAND_IPL /* * uart_asm_init: Initialize UART's pins */ @@ -582,4 +463,3 @@ uart_asm_init: str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 200: mov pc, lr -#endif diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 226db1f..1474fa8 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -27,8 +27,9 @@ LIB = $(obj)lib$(BOARD).o SOBJS := lowlevel_init.o COBJS := clock_init.o -COBJS += dmc_init.o +COBJS += dmc_common.o dmc_init_ddr3.o COBJS += tzpc_init.o +COBJS += smdk5250_spl.o ifndef CONFIG_SPL_BUILD COBJS += smdk5250.o diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index 305842d..c009ae5 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -22,181 +22,645 @@ * MA 02111-1307 USA */ +#include <common.h> #include <config.h> -#include <version.h> #include <asm/io.h> +#include <asm/arch/clk.h> #include <asm/arch/clock.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> +#include <asm/arch/spl.h> + +#include "clock_init.h" #include "setup.h" -void system_clock_init() +DECLARE_GLOBAL_DATA_PTR; + +struct arm_clk_ratios arm_clk_ratios[] = { + { + .arm_freq_mhz = 600, + + .apll_mdiv = 0xc8, + .apll_pdiv = 0x4, + .apll_sdiv = 0x1, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x2, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x1, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 800, + + .apll_mdiv = 0x64, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x3, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1000, + + .apll_mdiv = 0x7d, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x4, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1200, + + .apll_mdiv = 0x96, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x5, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1400, + + .apll_mdiv = 0xaf, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1700, + + .apll_mdiv = 0x1a9, + .apll_pdiv = 0x6, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + } +}; +struct mem_timings mem_timings[] = { + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0xc8, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36650e, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0xc8, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36650e, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + } +}; + +/** + * Get the required memory type and speed (SPL version). + * + * In SPL we have no device tree, so we use the machine parameters + * + * @param mem_type Returns memory type + * @param frequency_mhz Returns memory speed in MHz + * @param arm_freq Returns ARM clock speed in MHz + * @param mem_manuf Return Memory Manufacturer name + * @return 0 if all ok + */ +static int clock_get_mem_selection(enum ddr_mode *mem_type, + unsigned *frequency_mhz, unsigned *arm_freq, + enum mem_manuf *mem_manuf) { - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + struct spl_machine_param *params; - /* - * MUX_APLL_SEL[0]: FINPLL = 0 - * MUX_CPU_SEL[6]: MOUTAPLL = 0 - * MUX_HPM_SEL[20]: MOUTAPLL = 0 - */ - writel(0x0, &clk->src_cpu); + params = spl_get_machine_params(); + *mem_type = params->mem_type; + *frequency_mhz = params->frequency_mhz; + *arm_freq = params->arm_freq_mhz; + *mem_manuf = params->mem_manuf; - /* MUX_MPLL_SEL[8]: FINPLL = 0 */ - writel(0x0, &clk->src_core1); + return 0; +} - /* - * VPLLSRC_SEL[0]: FINPLL = 0 - * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0 - */ - writel(0x0, &clk->src_top2); +/* Get the ratios for setting ARM clock */ +struct arm_clk_ratios *get_arm_ratios(void) +{ + struct arm_clk_ratios *arm_ratio; + enum ddr_mode mem_type; + enum mem_manuf mem_manuf; + unsigned frequency_mhz, arm_freq; + int i; + + if (clock_get_mem_selection(&mem_type, &frequency_mhz, + &arm_freq, &mem_manuf)) + ; + for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); + i++, arm_ratio++) { + if (arm_ratio->arm_freq_mhz == arm_freq) + return arm_ratio; + } + + /* will hang if failed to find clock ratio */ + while (1) + ; + + return NULL; +} - /* MUX_BPLL_SEL[0]: FINPLL = 0 */ - writel(0x0, &clk->src_cdrex); +struct mem_timings *clock_get_mem_timings(void) +{ + struct mem_timings *mem; + enum ddr_mode mem_type; + enum mem_manuf mem_manuf; + unsigned frequency_mhz, arm_freq; + int i; + + if (!clock_get_mem_selection(&mem_type, &frequency_mhz, + &arm_freq, &mem_manuf)) { + for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); + i++, mem++) { + if (mem->mem_type == mem_type && + mem->frequency_mhz == frequency_mhz && + mem->mem_manuf == mem_manuf) + return mem; + } + } + + /* will hang if failed to find memory timings */ + while (1) + ; + + return NULL; +} - /* MUX_ACLK_* Clock Selection */ - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); +void system_clock_init() +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + struct mem_timings *mem; + struct arm_clk_ratios *arm_clk_ratio; + u32 val, tmp; + + mem = clock_get_mem_timings(); + arm_clk_ratio = get_arm_ratios(); + + clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); + do { + val = readl(&clk->mux_stat_cpu); + } while ((val | MUX_APLL_SEL_MASK) != val); + + clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); + do { + val = readl(&clk->mux_stat_core1); + } while ((val | MUX_MPLL_SEL_MASK) != val); + + clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); + clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); + clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); + clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); + tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK + | MUX_GPLL_SEL_MASK; + do { + val = readl(&clk->mux_stat_top2); + } while ((val | tmp) != val); + + clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); + do { + val = readl(&clk->mux_stat_cdrex); + } while ((val | MUX_BPLL_SEL_MASK) != val); - /* MUX_ACLK_* Clock Selection */ - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + /* PLL locktime */ + writel(APLL_LOCK_VAL, &clk->apll_lock); - /* MUX_ACLK_* Clock Selection */ - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); + writel(MPLL_LOCK_VAL, &clk->mpll_lock); - /* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */ - writel(CLK_SRC_CORE0_VAL, &clk->src_core0); + writel(BPLL_LOCK_VAL, &clk->bpll_lock); - /* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */ - writel(CLK_SRC_LEX_VAL, &clk->src_lex); + writel(CPLL_LOCK_VAL, &clk->cpll_lock); - /* UART [0-5]: SCLKMPLL = 6 */ - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); + writel(GPLL_LOCK_VAL, &clk->gpll_lock); - /* Set Clock Ratios */ - writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + writel(EPLL_LOCK_VAL, &clk->epll_lock); + + writel(VPLL_LOCK_VAL, &clk->vpll_lock); + + writel(CLK_REG_DISABLE, &clk->pll_div2_sel); + + writel(MUX_HPM_SEL_MASK, &clk->src_cpu); + do { + val = readl(&clk->mux_stat_cpu); + } while ((val | HPM_SEL_SCLK_MPLL) != val); + + val = arm_clk_ratio->arm2_ratio << 28 + | arm_clk_ratio->apll_ratio << 24 + | arm_clk_ratio->pclk_dbg_ratio << 20 + | arm_clk_ratio->atb_ratio << 16 + | arm_clk_ratio->periph_ratio << 12 + | arm_clk_ratio->acp_ratio << 8 + | arm_clk_ratio->cpud_ratio << 4 + | arm_clk_ratio->arm_ratio; + writel(val, &clk->div_cpu0); + do { + val = readl(&clk->div_stat_cpu0); + } while (0 != val); - /* Set COPY and HPM Ratio */ writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); + do { + val = readl(&clk->div_stat_cpu1); + } while (0 != val); - /* CORED_RATIO, COREP_RATIO */ - writel(CLK_DIV_CORE0_VAL, &clk->div_core0); + /* Set APLL */ + writel(APLL_CON1_VAL, &clk->apll_con1); + val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, + arm_clk_ratio->apll_sdiv); + writel(val, &clk->apll_con0); + while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) + ; - /* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */ - writel(CLK_DIV_CORE1_VAL, &clk->div_core1); + /* Set MPLL */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); + writel(val, &clk->mpll_con0); + while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) + ; - /* ACLK_*_RATIO */ - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); + /* Set BPLL */ + writel(BPLL_CON1_VAL, &clk->bpll_con1); + val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); + writel(val, &clk->bpll_con0); + while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) + ; - /* ACLK_*_RATIO */ - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); + /* Set CPLL */ + writel(CPLL_CON1_VAL, &clk->cpll_con1); + val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); + writel(val, &clk->cpll_con0); + while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) + ; + + /* Set GPLL */ + writel(GPLL_CON1_VAL, &clk->gpll_con1); + val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); + writel(val, &clk->gpll_con0); + while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) + ; - /* CDREX Ratio */ - writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex); + /* Set EPLL */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); + writel(val, &clk->epll_con0); + while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) + ; - /* MCLK_EFPHY_RATIO[3:0] */ - writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2); + /* Set VPLL */ + writel(VPLL_CON2_VAL, &clk->vpll_con2); + writel(VPLL_CON1_VAL, &clk->vpll_con1); + val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); + writel(val, &clk->vpll_con0); + while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) + ; - /* {PCLK[4:6]|ATCLK[10:8]}_RATIO */ - writel(CLK_DIV_LEX_VAL, &clk->div_lex); + writel(CLK_SRC_CORE0_VAL, &clk->src_core0); + writel(CLK_DIV_CORE0_VAL, &clk->div_core0); + while (readl(&clk->div_stat_core0) != 0) + ; - /* PCLK_R0X_RATIO[3:0] */ - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); + writel(CLK_DIV_CORE1_VAL, &clk->div_core1); + while (readl(&clk->div_stat_core1) != 0) + ; - /* PCLK_R1X_RATIO[3:0] */ - writel(CLK_DIV_R1X_VAL, &clk->div_r1x); + writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); + while (readl(&clk->div_stat_sysrgt) != 0) + ; - /* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */ - writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); + writel(CLK_DIV_ACP_VAL, &clk->div_acp); + while (readl(&clk->div_stat_acp) != 0) + ; - /* UART[0-4] */ - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); + writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); + while (readl(&clk->div_stat_syslft) != 0) + ; - /* PWM_RATIO[3:0] */ - writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + writel(TOP2_VAL, &clk->src_top2); + writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - /* SATA_RATIO, USB_DRD_RATIO */ - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); + writel(CLK_DIV_TOP0_VAL, &clk->div_top0); + while (readl(&clk->div_stat_top0)) + ; - /* MMC[0-1] */ - writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); + writel(CLK_DIV_TOP1_VAL, &clk->div_top1); + while (readl(&clk->div_stat_top1)) + ; - /* MMC[2-3] */ - writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); + writel(CLK_SRC_LEX_VAL, &clk->src_lex); + while (1) { + val = readl(&clk->mux_stat_lex); + if (val == (val | 1)) + break; + } - /* MMC[4] */ - writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); + writel(CLK_DIV_LEX_VAL, &clk->div_lex); + while (readl(&clk->div_stat_lex)) + ; - /* ACLK|PLCK_ACP_RATIO */ - writel(CLK_DIV_ACP_VAL, &clk->div_acp); + writel(CLK_DIV_R0X_VAL, &clk->div_r0x); + while (readl(&clk->div_stat_r0x)) + ; - /* ISPDIV0_RATIO, ISPDIV1_RATIO */ - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); + writel(CLK_DIV_R0X_VAL, &clk->div_r0x); + while (readl(&clk->div_stat_r0x)) + ; - /* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */ - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); + writel(CLK_DIV_R1X_VAL, &clk->div_r1x); + while (readl(&clk->div_stat_r1x)) + ; - /* MPWMDIV_RATIO */ - writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); + writel(CLK_REG_DISABLE, &clk->src_cdrex); - /* PLL locktime */ - writel(APLL_LOCK_VAL, &clk->apll_lock); + writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); + while (readl(&clk->div_stat_cdrex)) + ; - writel(MPLL_LOCK_VAL, &clk->mpll_lock); + val = readl(&clk->src_cpu); + val |= CLK_SRC_CPU_VAL; + writel(val, &clk->src_cpu); - writel(BPLL_LOCK_VAL, &clk->bpll_lock); + val = readl(&clk->src_top2); + val |= CLK_SRC_TOP2_VAL; + writel(val, &clk->src_top2); - writel(CPLL_LOCK_VAL, &clk->cpll_lock); + val = readl(&clk->src_core1); + val |= CLK_SRC_CORE1_VAL; + writel(val, &clk->src_core1); - writel(EPLL_LOCK_VAL, &clk->epll_lock); + writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); + writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); + while (readl(&clk->div_stat_fsys0)) + ; + + writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); + writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - writel(VPLL_LOCK_VAL, &clk->vpll_lock); + writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); + writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - sdelay(0x10000); + writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); + writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); + writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); + writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); - /* Set APLL */ - writel(APLL_CON1_VAL, &clk->apll_con1); - writel(APLL_CON0_VAL, &clk->apll_con0); - sdelay(0x30000); + writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); + writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); + writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); + writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); + writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); - /* Set MPLL */ - writel(MPLL_CON1_VAL, &clk->mpll_con1); - writel(MPLL_CON0_VAL, &clk->mpll_con0); - sdelay(0x30000); - writel(BPLL_CON1_VAL, &clk->bpll_con1); - writel(BPLL_CON0_VAL, &clk->bpll_con0); - sdelay(0x30000); + /* FIMD1 SRC CLK SELECTION */ + writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - writel(CPLL_CON0_VAL, &clk->cpll_con0); - sdelay(0x30000); + val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET + | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET + | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET + | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; + writel(val, &clk->div_fsys2); +} - /* Set EPLL */ - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - writel(EPLL_CON0_VAL, &clk->epll_con0); - sdelay(0x30000); +void clock_init_dp_clock(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - /* Set VPLL */ - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - writel(VPLL_CON0_VAL, &clk->vpll_con0); - sdelay(0x30000); + /* DP clock enable */ + setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); - /* Set MPLL */ - /* After Initiallising th PLL select the sources accordingly */ - /* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */ - writel(CLK_SRC_CPU_VAL, &clk->src_cpu); - - /* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */ - writel(CLK_SRC_CORE1_VAL, &clk->src_core1); - - /* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/ - writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex); - - /* - * VPLLSRC_SEL[0]: FINPLL = 0 - * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1 - * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1 - */ - writel(CLK_SRC_TOP2_VAL, &clk->src_top2); + /* We run DP at 267 Mhz */ + setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h new file mode 100644 index 0000000..f751bcb --- /dev/null +++ b/board/samsung/smdk5250/clock_init.h @@ -0,0 +1,149 @@ +/* + * Clock initialization routines + * + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EXYNOS_CLOCK_INIT_H +#define __EXYNOS_CLOCK_INIT_H + +enum { + MEM_TIMINGS_MSR_COUNT = 4, +}; + +/* These are the ratio's for configuring ARM clock */ +struct arm_clk_ratios { + unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ + + unsigned apll_mdiv; + unsigned apll_pdiv; + unsigned apll_sdiv; + + unsigned arm2_ratio; + unsigned apll_ratio; + unsigned pclk_dbg_ratio; + unsigned atb_ratio; + unsigned periph_ratio; + unsigned acp_ratio; + unsigned cpud_ratio; + unsigned arm_ratio; +}; + +/* These are the memory timings for a particular memory type and speed */ +struct mem_timings { + enum mem_manuf mem_manuf; /* Memory manufacturer */ + enum ddr_mode mem_type; /* Memory type */ + unsigned frequency_mhz; /* Frequency of memory in MHz */ + + /* Here follow the timing parameters for the selected memory */ + unsigned apll_mdiv; + unsigned apll_pdiv; + unsigned apll_sdiv; + unsigned mpll_mdiv; + unsigned mpll_pdiv; + unsigned mpll_sdiv; + unsigned cpll_mdiv; + unsigned cpll_pdiv; + unsigned cpll_sdiv; + unsigned gpll_mdiv; + unsigned gpll_pdiv; + unsigned gpll_sdiv; + unsigned epll_mdiv; + unsigned epll_pdiv; + unsigned epll_sdiv; + unsigned vpll_mdiv; + unsigned vpll_pdiv; + unsigned vpll_sdiv; + unsigned bpll_mdiv; + unsigned bpll_pdiv; + unsigned bpll_sdiv; + unsigned pclk_cdrex_ratio; + unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; + + unsigned timing_ref; + unsigned timing_row; + unsigned timing_data; + unsigned timing_power; + + /* DQS, DQ, DEBUG offsets */ + unsigned phy0_dqs; + unsigned phy1_dqs; + unsigned phy0_dq; + unsigned phy1_dq; + unsigned phy0_tFS; + unsigned phy1_tFS; + unsigned phy0_pulld_dqs; + unsigned phy1_pulld_dqs; + + unsigned lpddr3_ctrl_phy_reset; + unsigned ctrl_start_point; + unsigned ctrl_inc; + unsigned ctrl_start; + unsigned ctrl_dll_on; + unsigned ctrl_ref; + + unsigned ctrl_force; + unsigned ctrl_rdlat; + unsigned ctrl_bstlen; + + unsigned fp_resync; + unsigned iv_size; + unsigned dfi_init_start; + unsigned aref_en; + + unsigned rd_fetch; + + unsigned zq_mode_dds; + unsigned zq_mode_term; + unsigned zq_mode_noterm; /* 1 to allow termination disable */ + + unsigned memcontrol; + unsigned memconfig; + + unsigned membaseconfig0; + unsigned membaseconfig1; + unsigned prechconfig_tp_cnt; + unsigned dpwrdn_cyc; + unsigned dsref_cyc; + unsigned concontrol; + /* Channel and Chip Selection */ + uint8_t dmc_channels; /* number of memory channels */ + uint8_t chips_per_channel; /* number of chips per channel */ + uint8_t chips_to_configure; /* number of chips to configure */ + uint8_t send_zq_init; /* 1 to send this command */ + unsigned impedance; /* drive strength impedeance */ + uint8_t gate_leveling_enable; /* check gate leveling is enabled */ +}; + +/** + * Get the correct memory timings for our selected memory type and speed. + * + * This function can be called from SPL or the main U-Boot. + * + * @return pointer to the memory timings that we should use + */ +struct mem_timings *clock_get_mem_timings(void); + +/* + * Initialize clock for the device + */ +void system_clock_init(void); +#endif diff --git a/board/samsung/smdk5250/dmc_common.c b/board/samsung/smdk5250/dmc_common.c new file mode 100644 index 0000000..109602a --- /dev/null +++ b/board/samsung/smdk5250/dmc_common.c @@ -0,0 +1,199 @@ +/* + * Mem setup common file for different types of DDR present on SMDK5250 boards. + * + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/spl.h> + +#include "clock_init.h" +#include "setup.h" + +#define ZQ_INIT_TIMEOUT 10000 + +int dmc_config_zq(struct mem_timings *mem, + struct exynos5_phy_control *phy0_ctrl, + struct exynos5_phy_control *phy1_ctrl) +{ + unsigned long val = 0; + int i; + + /* + * ZQ Calibration: + * Select Driver Strength, + * long calibration for manual calibration + */ + val = PHY_CON16_RESET_VAL; + val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; + val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; + val |= ZQ_CLK_DIV_EN; + writel(val, &phy0_ctrl->phy_con16); + writel(val, &phy1_ctrl->phy_con16); + + /* Disable termination */ + if (mem->zq_mode_noterm) + val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; + writel(val, &phy0_ctrl->phy_con16); + writel(val, &phy1_ctrl->phy_con16); + + /* ZQ_MANUAL_START: Enable */ + val |= ZQ_MANUAL_STR; + writel(val, &phy0_ctrl->phy_con16); + writel(val, &phy1_ctrl->phy_con16); + + /* ZQ_MANUAL_START: Disable */ + val &= ~ZQ_MANUAL_STR; + + /* + * Since we are manaully calibrating the ZQ values, + * we are looping for the ZQ_init to complete. + */ + i = ZQ_INIT_TIMEOUT; + while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + sdelay(100); + i--; + } + if (!i) + return -1; + writel(val, &phy0_ctrl->phy_con16); + + i = ZQ_INIT_TIMEOUT; + while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + sdelay(100); + i--; + } + if (!i) + return -1; + writel(val, &phy1_ctrl->phy_con16); + + return 0; +} + +void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) +{ + unsigned long val; + + if (mode == DDR_MODE_DDR3) { + val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; + writel(val, &dmc->phycontrol0); + } + + /* Update DLL Information: Force DLL Resyncronization */ + val = readl(&dmc->phycontrol0); + val |= FP_RSYNC; + writel(val, &dmc->phycontrol0); + + /* Reset Force DLL Resyncronization */ + val = readl(&dmc->phycontrol0); + val &= ~FP_RSYNC; + writel(val, &dmc->phycontrol0); +} + +void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) +{ + int channel, chip; + + for (channel = 0; channel < mem->dmc_channels; channel++) { + unsigned long mask; + + mask = channel << DIRECT_CMD_CHANNEL_SHIFT; + for (chip = 0; chip < mem->chips_to_configure; chip++) { + int i; + + mask |= chip << DIRECT_CMD_CHIP_SHIFT; + + /* Sending NOP command */ + writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + + /* + * TODO(alim.akhtar@samsung.com): Do we need these + * delays? This one and the next were not there for + * DDR3. + */ + sdelay(0x10000); + + /* Sending EMRS/MRS commands */ + for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { + writel(mem->direct_cmd_msr[i] | mask, + &dmc->directcmd); + sdelay(0x10000); + } + + if (mem->send_zq_init) { + /* Sending ZQINIT command */ + writel(DIRECT_CMD_ZQINIT | mask, + &dmc->directcmd); + + sdelay(10000); + } + } + } +} + +void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) +{ + int channel, chip; + + for (channel = 0; channel < mem->dmc_channels; channel++) { + unsigned long mask; + + mask = channel << DIRECT_CMD_CHANNEL_SHIFT; + for (chip = 0; chip < mem->chips_per_channel; chip++) { + mask |= chip << DIRECT_CMD_CHIP_SHIFT; + + /* PALL (all banks precharge) CMD */ + writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + sdelay(0x10000); + } + } +} + +void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) +{ + writel(mem->memconfig, &dmc->memconfig0); + writel(mem->memconfig, &dmc->memconfig1); + writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); + writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); +} + +void mem_ctrl_init() +{ + struct spl_machine_param *param = spl_get_machine_params(); + struct mem_timings *mem; + int ret; + + mem = clock_get_mem_timings(); + + /* If there are any other memory variant, add their init call below */ + if (param->mem_type == DDR_MODE_DDR3) { + ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size); + if (ret) { + /* will hang if failed to init memory control */ + while (1) + ; + } + } else { + /* will hang if unknow memory type */ + while (1) + ; + } +} diff --git a/board/samsung/smdk5250/dmc_init.c b/board/samsung/smdk5250/dmc_init.c deleted file mode 100644 index 7881074..0000000 --- a/board/samsung/smdk5250/dmc_init.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Memory setup for SMDK5250 board based on EXYNOS5 - * - * Copyright (C) 2012 Samsung Electronics - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/io.h> -#include <asm/arch/dmc.h> -#include <asm/arch/clock.h> -#include <asm/arch/cpu.h> -#include "setup.h" - -/* APLL : 1GHz */ -/* MCLK_CDREX: MCLK_CDREX_533*/ -/* LPDDR support: LPDDR2 */ -static void reset_phy_ctrl(void); -static void config_zq(struct exynos5_phy_control *, - struct exynos5_phy_control *); -static void update_reset_dll(struct exynos5_dmc *); -static void config_cdrex(void); -static void config_mrs(struct exynos5_dmc *); -static void sec_sdram_phy_init(struct exynos5_dmc *); -static void config_prech(struct exynos5_dmc *); -static void config_rdlvl(struct exynos5_dmc *, - struct exynos5_phy_control *, - struct exynos5_phy_control *); -static void config_memory(struct exynos5_dmc *); - -static void config_offsets(unsigned int, - struct exynos5_phy_control *, - struct exynos5_phy_control *); - -static void reset_phy_ctrl(void) -{ - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - - writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl); - sdelay(0x10000); -} - -static void config_zq(struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) -{ - unsigned long val = 0; - /* - * ZQ Calibration: - * Select Driver Strength, - * long calibration for manual calibration - */ - val = PHY_CON16_RESET_VAL; - SET_ZQ_MODE_DDS_VAL(val); - SET_ZQ_MODE_TERM_VAL(val); - val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); - - /* Disable termination */ - val |= ZQ_MODE_NOTERM; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); - - /* ZQ_MANUAL_START: Enable */ - val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); - sdelay(0x10000); - - /* ZQ_MANUAL_START: Disable */ - val &= ~ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); -} - -static void update_reset_dll(struct exynos5_dmc *dmc) -{ - unsigned long val; - /* - * Update DLL Information: - * Force DLL Resyncronization - */ - val = readl(&dmc->phycontrol0); - val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); - - /* Reset Force DLL Resyncronization */ - val = readl(&dmc->phycontrol0); - val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); -} - -static void config_mrs(struct exynos5_dmc *dmc) -{ - unsigned long channel, chip, mask = 0, val; - - for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) { - SET_CMD_CHANNEL(mask, channel); - for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) { - /* - * NOP CMD: - * Assert and hold CKE to logic high level - */ - SET_CMD_CHIP(mask, chip); - val = DIRECT_CMD_NOP | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - - /* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */ - val = DIRECT_CMD_MRS1 | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - - val = DIRECT_CMD_MRS2 | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - - /* MCLK_CDREX_533 */ - val = DIRECT_CMD_MRS3 | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - - val = DIRECT_CMD_MRS4 | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - } - } -} - -static void config_prech(struct exynos5_dmc *dmc) -{ - unsigned long channel, chip, mask = 0, val; - - for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) { - SET_CMD_CHANNEL(mask, channel); - for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) { - SET_CMD_CHIP(mask, chip); - /* PALL (all banks precharge) CMD */ - val = DIRECT_CMD_PALL | mask; - writel(val, &dmc->directcmd); - sdelay(0x10000); - } - } -} - -static void sec_sdram_phy_init(struct exynos5_dmc *dmc) -{ - unsigned long val; - val = readl(&dmc->concontrol); - val |= DFI_INIT_START; - writel(val, &dmc->concontrol); - sdelay(0x10000); - - val = readl(&dmc->concontrol); - val &= ~DFI_INIT_START; - writel(val, &dmc->concontrol); -} - -static void config_offsets(unsigned int state, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) -{ - unsigned long val; - /* Set Offsets to read DQS */ - val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL; - writel(val, &phy0_ctrl->phy_con4); - writel(val, &phy1_ctrl->phy_con4); - - /* Set Offsets to read DQ */ - val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL; - writel(val, &phy0_ctrl->phy_con6); - writel(val, &phy1_ctrl->phy_con6); - - /* Debug Offset */ - val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL; - writel(val, &phy0_ctrl->phy_con10); - writel(val, &phy1_ctrl->phy_con10); -} - -static void config_cdrex(void) -{ - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); - writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex); - sdelay(0x30000); -} - -static void config_ctrl_dll_on(unsigned int state, - unsigned int ctrl_force_val, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) -{ - unsigned long val; - val = readl(&phy0_ctrl->phy_con12); - CONFIG_CTRL_DLL_ON(val, state); - SET_CTRL_FORCE_VAL(val, ctrl_force_val); - writel(val, &phy0_ctrl->phy_con12); - - val = readl(&phy1_ctrl->phy_con12); - CONFIG_CTRL_DLL_ON(val, state); - SET_CTRL_FORCE_VAL(val, ctrl_force_val); - writel(val, &phy1_ctrl->phy_con12); -} - -static void config_ctrl_start(unsigned int state, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) -{ - unsigned long val; - val = readl(&phy0_ctrl->phy_con12); - CONFIG_CTRL_START(val, state); - writel(val, &phy0_ctrl->phy_con12); - - val = readl(&phy1_ctrl->phy_con12); - CONFIG_CTRL_START(val, state); - writel(val, &phy1_ctrl->phy_con12); -} - -#if defined(CONFIG_RD_LVL) -static void config_rdlvl(struct exynos5_dmc *dmc, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) -{ - unsigned long val; - - /* Disable CTRL_DLL_ON and set ctrl_force */ - config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl); - - /* - * Set ctrl_gateadj, ctrl_readadj - * ctrl_gateduradj, rdlvl_pass_adj - * rdlvl_rddataPadj - */ - val = SET_RDLVL_RDDATAPADJ; - writel(val, &phy0_ctrl->phy_con1); - writel(val, &phy1_ctrl->phy_con1); - - /* LPDDR2 Address */ - writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22); - writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22); - - /* Enable Byte Read Leveling set ctrl_ddr_mode */ - val = readl(&phy0_ctrl->phy_con0); - val |= BYTE_RDLVL_EN; - writel(val, &phy0_ctrl->phy_con0); - val = readl(&phy1_ctrl->phy_con0); - val |= BYTE_RDLVL_EN; - writel(val, &phy1_ctrl->phy_con0); - - /* rdlvl_en: Use levelling offset instead ctrl_shiftc */ - val = PHY_CON2_RESET_VAL | RDLVL_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); - sdelay(0x10000); - - /* Enable Data Eye Training */ - val = readl(&dmc->rdlvl_config); - val |= CTRL_RDLVL_DATA_EN; - writel(val, &dmc->rdlvl_config); - sdelay(0x10000); - - /* Disable Data Eye Training */ - val = readl(&dmc->rdlvl_config); - val &= ~CTRL_RDLVL_DATA_EN; - writel(val, &dmc->rdlvl_config); - - /* RdDeSkew_clear: Clear */ - val = readl(&phy0_ctrl->phy_con2); - val |= RDDSKEW_CLEAR; - writel(val, &phy0_ctrl->phy_con2); - val = readl(&phy1_ctrl->phy_con2); - val |= RDDSKEW_CLEAR; - writel(val, &phy1_ctrl->phy_con2); - - /* Enable CTRL_DLL_ON */ - config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl); - - update_reset_dll(dmc); - sdelay(0x10000); - - /* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */ - val = readl(&phy0_ctrl->phy_con0); - val &= ~CTRL_ATGATE; - writel(val, &phy0_ctrl->phy_con0); - val = readl(&phy1_ctrl->phy_con0); - val &= ~CTRL_ATGATE; - writel(val, &phy1_ctrl->phy_con0); -} -#endif - -static void config_memory(struct exynos5_dmc *dmc) -{ - /* - * Memory Configuration Chip 0 - * Address Mapping: Interleaved - * Number of Column address Bits: 10 bits - * Number of Rows Address Bits: 14 - * Number of Banks: 8 - */ - writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0); - - /* - * Memory Configuration Chip 1 - * Address Mapping: Interleaved - * Number of Column address Bits: 10 bits - * Number of Rows Address Bits: 14 - * Number of Banks: 8 - */ - writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1); - - /* - * Chip0: AXI - * AXI Base Address: 0x40000000 - * AXI Base Address Mask: 0x780 - */ - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - - /* - * Chip1: AXI - * AXI Base Address: 0x80000000 - * AXI Base Address Mask: 0x780 - */ - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); -} - -void mem_ctrl_init() -{ - struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; - struct exynos5_dmc *dmc; - unsigned long val; - - phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; - phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; - dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - - /* Reset PHY Controllor: PHY_RESET[0] */ - reset_phy_ctrl(); - - /*set Read Latancy and Burst Length for PHY0 and PHY1 */ - writel(PHY_CON42_VAL, &phy0_ctrl->phy_con42); - writel(PHY_CON42_VAL, &phy1_ctrl->phy_con42); - - /* ZQ Cofiguration */ - config_zq(phy0_ctrl, phy1_ctrl); - - /* Operation Mode : LPDDR2 */ - val = PHY_CON0_RESET_VAL; - SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2); - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); - - /* DQS, DQ: Signal, for LPDDR2: Always Set */ - val = CTRL_PULLD_DQ | CTRL_PULLD_DQS; - writel(val, &phy0_ctrl->phy_con14); - writel(val, &phy1_ctrl->phy_con14); - - /* Init SEC SDRAM PHY */ - sec_sdram_phy_init(dmc); - sdelay(0x10000); - - update_reset_dll(dmc); - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 4 - * Number of chips: 2 - * Memory Bus width: 32 bit - * Memory Type: LPDDR2-S4 - * Additional Latancy for PLL: 1 Cycle - */ - writel(DMC_MEMCONTROL_VAL, &dmc->memcontrol); - - config_memory(dmc); - - /* Precharge Configuration */ - writel(DMC_PRECHCONFIG_VAL, &dmc->prechconfig); - - /* Power Down mode Configuration */ - writel(DMC_PWRDNCONFIG_VAL, &dmc->pwrdnconfig); - - /* Periodic Refrese Interval */ - writel(DMC_TIMINGREF_VAL, &dmc->timingref); - - /* - * TimingRow, TimingData, TimingPower Setting: - * Values as per Memory AC Parameters - */ - writel(DMC_TIMINGROW_VAL, &dmc->timingrow); - - writel(DMC_TIMINGDATA_VAL, &dmc->timingdata); - - writel(DMC_TIMINGPOWER_VAL, &dmc->timingpower); - - /* Memory Channel Inteleaving Size: 128 Bytes */ - writel(CONFIG_IV_SIZE, &dmc->ivcontrol); - - /* Set DQS, DQ and DEBUG offsets */ - config_offsets(SET, phy0_ctrl, phy1_ctrl); - - /* Disable CTRL_DLL_ON and set ctrl_force */ - config_ctrl_dll_on(RESET, 0x7F, phy0_ctrl, phy1_ctrl); - sdelay(0x10000); - - update_reset_dll(dmc); - - /* Config MRS(Mode Register Settingg) */ - config_mrs(dmc); - - config_cdrex(); - - /* Reset DQS DQ and DEBUG offsets */ - config_offsets(RESET, phy0_ctrl, phy1_ctrl); - - /* Enable CTRL_DLL_ON */ - config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl); - - /* Stop DLL Locking */ - config_ctrl_start(RESET, phy0_ctrl, phy1_ctrl); - sdelay(0x10000); - - /* Start DLL Locking */ - config_ctrl_start(SET, phy0_ctrl, phy1_ctrl); - sdelay(0x10000); - - update_reset_dll(dmc); - -#if defined(CONFIG_RD_LVL) - config_rdlvl(dmc, phy0_ctrl, phy1_ctrl); -#endif - config_prech(dmc); - - /* - * Dynamic Clock: Stops During Idle Period - * Dynamic Power Down: Enable - * Dynamic Self refresh: Enable - */ - val = readl(&dmc->memcontrol); - val |= CLK_STOP_EN | DPWRDN_EN | DSREF_EN; - writel(val, &dmc->memcontrol); - - /* Start Auto refresh */ - val = readl(&dmc->concontrol); - val |= AREF_EN; - writel(val, &dmc->concontrol); -} diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/board/samsung/smdk5250/dmc_init_ddr3.c new file mode 100644 index 0000000..e050790 --- /dev/null +++ b/board/samsung/smdk5250/dmc_init_ddr3.c @@ -0,0 +1,228 @@ +/* + * DDR3 mem setup file for SMDK5250 board based on EXYNOS5 + * + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/dmc.h> +#include "setup.h" +#include "clock_init.h" + +#define RDLVL_COMPLETE_TIMEOUT 10000 + +static void reset_phy_ctrl(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + + writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); + writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); +} + +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) +{ + unsigned int val; + struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; + struct exynos5_dmc *dmc; + int i; + + phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; + phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; + dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; + + reset_phy_ctrl(); + + /* Set Impedance Output Driver */ + val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | + (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | + (mem->impedance << CA_CS_DRVR_DS_OFFSET) | + (mem->impedance << CA_ADR_DRVR_DS_OFFSET); + writel(val, &phy0_ctrl->phy_con39); + writel(val, &phy1_ctrl->phy_con39); + + /* Set Read Latency and Burst Length for PHY0 and PHY1 */ + val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | + (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); + writel(val, &phy0_ctrl->phy_con42); + writel(val, &phy1_ctrl->phy_con42); + + /* ZQ Calibration */ + if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) + return SETUP_ERR_ZQ_CALIBRATION_FAILURE; + + /* DQ Signal */ + writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); + writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); + + writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) + | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), + &dmc->concontrol); + + update_reset_dll(dmc, DDR_MODE_DDR3); + + /* DQS Signal */ + writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); + writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); + + writel(mem->phy0_dq, &phy0_ctrl->phy_con6); + writel(mem->phy1_dq, &phy1_ctrl->phy_con6); + + writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); + writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); + + val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | + (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | + (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | + (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); + writel(val, &phy0_ctrl->phy_con12); + writel(val, &phy1_ctrl->phy_con12); + + /* Start DLL locking */ + writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), + &phy0_ctrl->phy_con12); + writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), + &phy1_ctrl->phy_con12); + + update_reset_dll(dmc, DDR_MODE_DDR3); + + writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &dmc->concontrol); + + /* Memory Channel Inteleaving Size */ + writel(mem->iv_size, &dmc->ivcontrol); + + writel(mem->memconfig, &dmc->memconfig0); + writel(mem->memconfig, &dmc->memconfig1); + writel(mem->membaseconfig0, &dmc->membaseconfig0); + writel(mem->membaseconfig1, &dmc->membaseconfig1); + + /* Precharge Configuration */ + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &dmc->prechconfig); + + /* Power Down mode Configuration */ + writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | + mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, + &dmc->pwrdnconfig); + + /* TimingRow, TimingData, TimingPower and Timingaref + * values as per Memory AC parameters + */ + writel(mem->timing_ref, &dmc->timingref); + writel(mem->timing_row, &dmc->timingrow); + writel(mem->timing_data, &dmc->timingdata); + writel(mem->timing_power, &dmc->timingpower); + + /* Send PALL command */ + dmc_config_prech(mem, dmc); + + /* Send NOP, MRS and ZQINIT commands */ + dmc_config_mrs(mem, dmc); + + if (mem->gate_leveling_enable) { + val = PHY_CON0_RESET_VAL; + val |= P0_CMD_EN; + writel(val, &phy0_ctrl->phy_con0); + writel(val, &phy1_ctrl->phy_con0); + + val = PHY_CON2_RESET_VAL; + val |= INIT_DESKEW_EN; + writel(val, &phy0_ctrl->phy_con2); + writel(val, &phy1_ctrl->phy_con2); + + val = PHY_CON0_RESET_VAL; + val |= P0_CMD_EN; + val |= BYTE_RDLVL_EN; + writel(val, &phy0_ctrl->phy_con0); + writel(val, &phy1_ctrl->phy_con0); + + val = (mem->ctrl_start_point << + PHY_CON12_CTRL_START_POINT_SHIFT) | + (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | + (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | + (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | + (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); + writel(val, &phy0_ctrl->phy_con12); + writel(val, &phy1_ctrl->phy_con12); + + val = PHY_CON2_RESET_VAL; + val |= INIT_DESKEW_EN; + val |= RDLVL_GATE_EN; + writel(val, &phy0_ctrl->phy_con2); + writel(val, &phy1_ctrl->phy_con2); + + val = PHY_CON0_RESET_VAL; + val |= P0_CMD_EN; + val |= BYTE_RDLVL_EN; + val |= CTRL_SHGATE; + writel(val, &phy0_ctrl->phy_con0); + writel(val, &phy1_ctrl->phy_con0); + + val = PHY_CON1_RESET_VAL; + val &= ~(CTRL_GATEDURADJ_MASK); + writel(val, &phy0_ctrl->phy_con1); + writel(val, &phy1_ctrl->phy_con1); + + writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); + i = RDLVL_COMPLETE_TIMEOUT; + while ((readl(&dmc->phystatus) & + (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != + (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config); + + writel(0, &phy0_ctrl->phy_con14); + writel(0, &phy1_ctrl->phy_con14); + + val = (mem->ctrl_start_point << + PHY_CON12_CTRL_START_POINT_SHIFT) | + (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | + (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | + (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | + (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | + (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); + writel(val, &phy0_ctrl->phy_con12); + writel(val, &phy1_ctrl->phy_con12); + + update_reset_dll(dmc, DDR_MODE_DDR3); + } + + /* Send PALL command */ + dmc_config_prech(mem, dmc); + + writel(mem->memcontrol, &dmc->memcontrol); + + /* Set DMC Concontrol and enable auto-refresh counter */ + writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) + | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); + return 0; +} diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index 1276fd3..a159601 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -1,5 +1,5 @@ /* - * Machine Specific Values for SMDK5250 board based on S5PC520 + * Machine Specific Values for SMDK5250 board based on EXYNOS5 * * Copyright (C) 2012 Samsung Electronics * @@ -26,12 +26,7 @@ #define _SMDK5250_SETUP_H #include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> - -/* GPIO Offsets for UART: GPIO Contol Register */ -#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0 -#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20 +#include <asm/arch/dmc.h> /* TZPC : Register Offsets */ #define TZPC0_BASE 0x10100000 @@ -45,295 +40,423 @@ #define TZPC8_BASE 0x10180000 #define TZPC9_BASE 0x10190000 -/* CLK_SRC_CPU */ -/* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ - | (MUX_CPU_SEL << 16) \ - | (MUX_APLL_SEL)) - -/* CLK_DIV_CPU0 */ -#define ARM2_RATIO 0x0 -#define APLL_RATIO 0x1 -#define PCLK_DBG_RATIO 0x1 -#define ATB_RATIO 0x4 -#define PERIPH_RATIO 0x7 -#define ACP_RATIO 0x7 -#define CPUD_RATIO 0x2 -#define ARM_RATIO 0x0 -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ - | (ARM_RATIO)) - -/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x4 -#define COPY_RATIO 0x0 -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ - | (COPY_RATIO)) - -#define APLL_MDIV 0x7D -#define APLL_PDIV 0x3 -#define APLL_SDIV 0x0 - -#define MPLL_MDIV 0x64 -#define MPLL_PDIV 0x3 -#define MPLL_SDIV 0x0 - -#define CPLL_MDIV 0x96 -#define CPLL_PDIV 0x4 -#define CPLL_SDIV 0x0 - -/* APLL_CON1 */ +/* APLL_CON1 */ #define APLL_CON1_VAL (0x00203800) -/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x00203800) -/* CPLL_CON1 */ +/* CPLL_CON1 */ #define CPLL_CON1_VAL (0x00203800) -#define EPLL_MDIV 0x60 -#define EPLL_PDIV 0x3 -#define EPLL_SDIV 0x3 +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (0x00203800) +/* EPLL_CON1, CON2 */ #define EPLL_CON1_VAL 0x00000000 #define EPLL_CON2_VAL 0x00000080 -#define VPLL_MDIV 0x96 -#define VPLL_PDIV 0x3 -#define VPLL_SDIV 0x2 - +/* VPLL_CON1, CON2 */ #define VPLL_CON1_VAL 0x00000000 #define VPLL_CON2_VAL 0x00000080 -#define BPLL_MDIV 0x215 -#define BPLL_PDIV 0xC -#define BPLL_SDIV 0x1 - +/* BPLL_CON1 */ #define BPLL_CON1_VAL 0x00203800 /* Set PLL */ #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) -#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV) -#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) -#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV) -#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) -#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) -#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV) +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 + +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) + +/* MEMCONTROL register bit fields */ +#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) +#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) +#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2) +#define DMC_MEMCONTROL_TP_DISABLE (0 << 4) +#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) +#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) +#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) + +#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8) + +#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) + +#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) + +#define DMC_MEMCONTROL_BL_8 (3 << 20) +#define DMC_MEMCONTROL_BL_4 (2 << 20) + +#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) + +#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) + +/* MEMCONFIG0 register bit fields */ +#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) + +#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMBASECONFIG_VAL(x) ( \ + DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ + DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ +) + +#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) +#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) + +#define DMC_PRECHCONFIG_VAL 0xFF000000 +#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF + +#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 +#define DFI_INIT_START (1 << 28) +#define EMPTY (1 << 8) +#define AREF_EN (1 << 5) + +#define DFI_INIT_COMPLETE_CHO (1 << 2) +#define DFI_INIT_COMPLETE_CH1 (1 << 3) + +#define RDLVL_COMPLETE_CHO (1 << 14) +#define RDLVL_COMPLETE_CH1 (1 << 15) + +#define CLK_STOP_EN (1 << 0) +#define DPWRDN_EN (1 << 1) +#define DSREF_EN (1 << 5) + +/* COJCONTROL register bit fields */ +#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) +#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) +#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) +#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) +#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) +#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) +#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ + | (APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (ACP_RATIO << 8) \ + | (CPUD_RATIO << 4) \ + | (ARM_RATIO)) + + +/* CLK_FSYS */ +#define CLK_SRC_FSYS0_VAL 0x66666 +#define CLK_DIV_FSYS0_VAL 0x0BB00000 + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0 + +/* CLK_DIV_CPU1 = 0x00000003 */ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ + | (COPY_RATIO)) /* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00060000 +#define CLK_SRC_CORE0_VAL 0x00000000 /* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 +#define CLK_SRC_CORE1_VAL 0x100 /* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x120000 +#define CLK_DIV_CORE0_VAL 0x00120000 /* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 +#define CLK_DIV_CORE1_VAL 0x07070700 + +/* CLK_DIV_SYSRGT */ +#define CLK_DIV_SYSRGT_VAL 0x00000111 + +/* CLK_DIV_ACP */ +#define CLK_DIV_ACP_VAL 0x12 + +/* CLK_DIV_SYSLFT */ +#define CLK_DIV_SYSLFT_VAL 0x00000311 /* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_INIT_VAL 0x1 -#define CLK_SRC_CDREX_VAL 0x111 +#define CLK_SRC_CDREX_VAL 0x1 /* CLK_DIV_CDREX */ -#define CLK_DIV_CDREX_INIT_VAL 0x71771111 - -#define MCLK_CDREX2_RATIO 0x0 -#define ACLK_EFCON_RATIO 0x1 -#define MCLK_DPHY_RATIO 0x0 -#define MCLK_CDREX_RATIO 0x0 +#define MCLK_CDREX2_RATIO 0x0 +#define ACLK_EFCON_RATIO 0x1 +#define MCLK_DPHY_RATIO 0x1 +#define MCLK_CDREX_RATIO 0x1 #define ACLK_C2C_200_RATIO 0x1 #define C2C_CLK_400_RATIO 0x1 -#define PCLK_CDREX_RATIO 0x3 +#define PCLK_CDREX_RATIO 0x1 #define ACLK_CDREX_RATIO 0x1 -#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \ - | (MCLK_CDREX_RATIO << 16) \ - | (ACLK_C2C_200_RATIO << 12) \ - | (C2C_CLK_400_RATIO << 8) \ - | (PCLK_CDREX_RATIO << 4) \ - | (ACLK_CDREX_RATIO)) -#define MCLK_EFPHY_RATIO 0x4 -#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO +#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ + | (C2C_CLK_400_RATIO << 6) \ + | (PCLK_CDREX_RATIO << 4) \ + | (ACLK_CDREX_RATIO)) -/* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 - -/* CLK_SRC_TOP0 */ -#define MUX_ACLK_300_GSCL_SEL 0x1 -#define MUX_ACLK_300_GSCL_MID_SEL 0x0 -#define MUX_ACLK_400_SEL 0x0 -#define MUX_ACLK_333_SEL 0x0 -#define MUX_ACLK_300_DISP1_SEL 0x1 -#define MUX_ACLK_300_DISP1_MID_SEL 0x0 -#define MUX_ACLK_200_SEL 0x0 -#define MUX_ACLK_166_SEL 0x0 -#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ - | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ - | (MUX_ACLK_400_SEL << 20) \ - | (MUX_ACLK_333_SEL << 16) \ - | (MUX_ACLK_300_DISP1_SEL << 15) \ +/* CLK_SRC_TOP0 */ +#define MUX_ACLK_300_GSCL_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID_SEL 0x0 +#define MUX_ACLK_400_G3D_MID_SEL 0x0 +#define MUX_ACLK_333_SEL 0x0 +#define MUX_ACLK_300_DISP1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_ACLK_166_SEL 0x0 +#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ + | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ + | (MUX_ACLK_400_G3D_MID_SEL << 20) \ + | (MUX_ACLK_333_SEL << 16) \ + | (MUX_ACLK_300_DISP1_SEL << 15) \ | (MUX_ACLK_300_DISP1_MID_SEL << 14) \ - | (MUX_ACLK_200_SEL << 12) \ + | (MUX_ACLK_200_SEL << 12) \ | (MUX_ACLK_166_SEL << 8)) -/* CLK_SRC_TOP1 */ -#define MUX_ACLK_400_ISP_SEL 0x0 -#define MUX_ACLK_400_IOP_SEL 0x0 -#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 -#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \ - |(MUX_ACLK_400_IOP_SEL << 20) \ - |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16)) +/* CLK_SRC_TOP1 */ +#define MUX_ACLK_400_G3D_SEL 0x1 +#define MUX_ACLK_400_ISP_SEL 0x0 +#define MUX_ACLK_400_IOP_SEL 0x0 +#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 +#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ + |(MUX_ACLK_400_ISP_SEL << 24) \ + |(MUX_ACLK_400_IOP_SEL << 20) \ + |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ + |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ + |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) /* CLK_SRC_TOP2 */ -#define MUX_BPLL_USER_SEL 0x1 -#define MUX_MPLL_USER_SEL 0x1 -#define MUX_VPLL_SEL 0x0 -#define MUX_EPLL_SEL 0x0 -#define MUX_CPLL_SEL 0x0 -#define VPLLSRC_SEL 0x0 -#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \ - | (MUX_MPLL_USER_SEL << 20) \ - | (MUX_VPLL_SEL << 16) \ - | (MUX_EPLL_SEL << 12) \ - | (MUX_CPLL_SEL << 8) \ +#define MUX_GPLL_SEL 0x1 +#define MUX_BPLL_USER_SEL 0x0 +#define MUX_MPLL_USER_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define MUX_CPLL_SEL 0x1 +#define VPLLSRC_SEL 0x0 +#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ + | (MUX_BPLL_USER_SEL << 24) \ + | (MUX_MPLL_USER_SEL << 20) \ + | (MUX_VPLL_SEL << 16) \ + | (MUX_EPLL_SEL << 12) \ + | (MUX_CPLL_SEL << 8) \ | (VPLLSRC_SEL)) /* CLK_SRC_TOP3 */ -#define MUX_ACLK_333_SUB_SEL 0x1 -#define MUX_ACLK_400_SUB_SEL 0x1 -#define MUX_ACLK_266_ISP_SUB_SEL 0x1 -#define MUX_ACLK_266_GPS_SUB_SEL 0x1 -#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 -#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 -#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ - | (MUX_ACLK_400_SUB_SEL << 20) \ - | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ - | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ - | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ - | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ - | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ - | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) - -/* CLK_DIV_TOP0 */ -#define ACLK_300_RATIO 0x0 -#define ACLK_400_RATIO 0x3 -#define ACLK_333_RATIO 0x2 +#define MUX_ACLK_333_SUB_SEL 0x1 +#define MUX_ACLK_400_SUB_SEL 0x1 +#define MUX_ACLK_266_ISP_SUB_SEL 0x1 +#define MUX_ACLK_266_GPS_SUB_SEL 0x0 +#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 +#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 +#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ + | (MUX_ACLK_400_SUB_SEL << 20) \ + | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ + | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ + | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ + | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ + | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ + | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) + +/* CLK_DIV_TOP0 */ +#define ACLK_300_DISP1_RATIO 0x2 +#define ACLK_400_G3D_RATIO 0x0 +#define ACLK_333_RATIO 0x0 #define ACLK_266_RATIO 0x2 #define ACLK_200_RATIO 0x3 -#define ACLK_166_RATIO 0x5 +#define ACLK_166_RATIO 0x1 #define ACLK_133_RATIO 0x1 #define ACLK_66_RATIO 0x5 -#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \ - | (ACLK_400_RATIO << 24) \ - | (ACLK_333_RATIO << 20) \ - | (ACLK_266_RATIO << 16) \ - | (ACLK_200_RATIO << 12) \ - | (ACLK_166_RATIO << 8) \ - | (ACLK_133_RATIO << 4) \ + +#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \ + | (ACLK_400_G3D_RATIO << 24) \ + | (ACLK_333_RATIO << 20) \ + | (ACLK_266_RATIO << 16) \ + | (ACLK_200_RATIO << 12) \ + | (ACLK_166_RATIO << 8) \ + | (ACLK_133_RATIO << 4) \ | (ACLK_66_RATIO)) -/* CLK_DIV_TOP1 */ -#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 -#define ACLK_66_PRE_RATIO 0x1 -#define ACLK_400_ISP_RATIO 0x1 -#define ACLK_400_IOP_RATIO 0x1 -#define ACLK_300_GSCL_RATIO 0x0 -#define ACLK_266_GPS_RATIO 0x7 - -#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ - | (ACLK_66_PRE_RATIO << 24) \ - | (ACLK_400_ISP_RATIO << 20) \ - | (ACLK_400_IOP_RATIO << 16) \ - | (ACLK_300_GSCL_RATIO << 12) \ - | (ACLK_266_GPS_RATIO << 8)) - -/* APLL_LOCK */ -#define APLL_LOCK_VAL (0x3E8) -/* MPLL_LOCK */ -#define MPLL_LOCK_VAL (0x2F1) -/* CPLL_LOCK */ -#define CPLL_LOCK_VAL (0x3E8) -/* EPLL_LOCK */ -#define EPLL_LOCK_VAL (0x2321) -/* VPLL_LOCK */ -#define VPLL_LOCK_VAL (0x2321) -/* BPLL_LOCK */ -#define BPLL_LOCK_VAL (0x3E8) +/* CLK_DIV_TOP1 */ +#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 +#define ACLK_66_PRE_RATIO 0x1 +#define ACLK_400_ISP_RATIO 0x1 +#define ACLK_400_IOP_RATIO 0x1 +#define ACLK_300_GSCL_RATIO 0x2 + +#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ + | (ACLK_66_PRE_RATIO << 24) \ + | (ACLK_400_ISP_RATIO << 20) \ + | (ACLK_400_IOP_RATIO << 16) \ + | (ACLK_300_GSCL_RATIO << 12)) + +/* APLL_LOCK */ +#define APLL_LOCK_VAL (0x546) +/* MPLL_LOCK */ +#define MPLL_LOCK_VAL (0x546) +/* CPLL_LOCK */ +#define CPLL_LOCK_VAL (0x546) +/* GPLL_LOCK */ +#define GPLL_LOCK_VAL (0x546) +/* EPLL_LOCK */ +#define EPLL_LOCK_VAL (0x3A98) +/* VPLL_LOCK */ +#define VPLL_LOCK_VAL (0x3A98) +/* BPLL_LOCK */ +#define BPLL_LOCK_VAL (0x546) + +#define MUX_APLL_SEL_MASK (1 << 0) +#define MUX_MPLL_SEL_MASK (1 << 8) +#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) +#define MUX_CPLL_SEL_MASK (1 << 8) +#define MUX_EPLL_SEL_MASK (1 << 12) +#define MUX_VPLL_SEL_MASK (1 << 16) +#define MUX_GPLL_SEL_MASK (1 << 28) +#define MUX_BPLL_SEL_MASK (1 << 0) +#define MUX_HPM_SEL_MASK (1 << 20) +#define HPM_SEL_SCLK_MPLL (1 << 21) +#define APLL_CON0_LOCKED (1 << 29) +#define MPLL_CON0_LOCKED (1 << 29) +#define BPLL_CON0_LOCKED (1 << 29) +#define CPLL_CON0_LOCKED (1 << 29) +#define EPLL_CON0_LOCKED (1 << 29) +#define GPLL_CON0_LOCKED (1 << 29) +#define VPLL_CON0_LOCKED (1 << 29) +#define CLK_REG_DISABLE 0x0 +#define TOP2_VAL 0x0110000 /* CLK_SRC_PERIC0 */ +#define PWM_SEL 0 +#define UART3_SEL 6 +#define UART2_SEL 6 +#define UART1_SEL 6 +#define UART0_SEL 6 +/* SRC_CLOCK = SCLK_MPLL */ +#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL)) + +/* CLK_SRC_PERIC1 */ /* SRC_CLOCK = SCLK_MPLL */ -#define PWM_SEL 0 -#define UART4_SEL 6 -#define UART3_SEL 6 -#define UART2_SEL 6 -#define UART1_SEL 6 -#define UART0_SEL 6 -#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ - | (UART4_SEL << 16) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ - | (UART0_SEL << 0)) - -#define CLK_SRC_FSYS_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 -#define CLK_DIV_FSYS1_VAL 0x000f000f -#define CLK_DIV_FSYS2_VAL 0x020f020f -#define CLK_DIV_FSYS3_VAL 0x000f - -/* CLK_DIV_PERIC0 */ -#define UART5_RATIO 8 -#define UART4_RATIO 8 -#define UART3_RATIO 8 -#define UART2_RATIO 8 -#define UART1_RATIO 8 -#define UART0_RATIO 8 -#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \ - | (UART3_RATIO << 12) \ - | (UART2_RATIO << 8) \ - | (UART1_RATIO << 4) \ - | (UART0_RATIO << 0)) +#define SPI0_SEL 6 +#define SPI1_SEL 6 +#define SPI2_SEL 6 +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \ + | (SPI1_SEL << 20) \ + | (SPI0_SEL << 16)) + +/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ +#define SPI0_ISP_SEL 6 +#define SPI1_ISP_SEL 6 +#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ + | (SPI0_ISP_SEL << 0) + +/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ +#define SPI0_ISP_RATIO 0xf +#define SPI1_ISP_RATIO 0xf +#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ + | (SPI0_ISP_RATIO << 0) + +/* CLK_DIV_PERIL0 */ +#define UART5_RATIO 7 +#define UART4_RATIO 7 +#define UART3_RATIO 7 +#define UART2_RATIO 7 +#define UART1_RATIO 7 +#define UART0_RATIO 7 + +#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO)) +/* CLK_DIV_PERIC1 */ +#define SPI1_RATIO 0x7 +#define SPI0_RATIO 0xf +#define SPI1_SUB_RATIO 0x0 +#define SPI0_SUB_RATIO 0x0 +#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ + | ((SPI1_RATIO << 16) \ + | (SPI0_SUB_RATIO << 8) \ + | (SPI0_RATIO << 0))) + +/* CLK_DIV_PERIC2 */ +#define SPI2_RATIO 0xf +#define SPI2_SUB_RATIO 0x0 +#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \ + | (SPI2_RATIO << 0)) /* CLK_DIV_PERIC3 */ #define PWM_RATIO 8 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO_MASK 0xf +#define MMC2_RATIO_VAL 0x3 +#define MMC2_RATIO_OFFSET 0 + +#define MMC2_PRE_RATIO_MASK 0xff +#define MMC2_PRE_RATIO_VAL 0x9 +#define MMC2_PRE_RATIO_OFFSET 8 + +#define MMC3_RATIO_MASK 0xf +#define MMC3_RATIO_VAL 0x1 +#define MMC3_RATIO_OFFSET 16 + +#define MMC3_PRE_RATIO_MASK 0xff +#define MMC3_PRE_RATIO_VAL 0x0 +#define MMC3_PRE_RATIO_OFFSET 24 + /* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0 /* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10 /* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10 /* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10 -/* SCLK_SRC_ISP */ -#define SCLK_SRC_ISP_VAL 0x600 /* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 +#define CLK_DIV_ISP0_VAL 0x31 /* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 +#define CLK_DIV_ISP1_VAL 0x0 /* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1 + +/* CLK_SRC_DISP1_0 */ +#define CLK_SRC_DISP1_0_VAL 0x6 + +/* + * DIV_DISP1_0 + * For DP, divisor should be 2 + */ +#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) -#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1))) +/* CLK_GATE_IP_DISP1 */ +#define CLK_GATE_DP1_ALLOW (1 << 4) /* * TZPC Register Value : @@ -347,105 +470,125 @@ */ #define DECPROTXSET 0xFF -/* DMC Init */ -#define SET 1 -#define RESET 0 -/* (Memory Interleaving Size = 1 << IV_SIZE) */ -#define CONFIG_IV_SIZE 0x07 +#define DDR3PHY_CTRL_PHY_RESET (1 << 0) +#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) -#define PHY_RESET_VAL (0 << 0) +#define PHY_CON0_RESET_VAL 0x17020a40 +#define P0_CMD_EN (1 << 14) +#define BYTE_RDLVL_EN (1 << 13) +#define CTRL_SHGATE (1 << 8) + +#define PHY_CON1_RESET_VAL 0x09210100 +#define CTRL_GATEDURADJ_MASK (0xf << 20) + +#define PHY_CON2_RESET_VAL 0x00010004 +#define INIT_DESKEW_EN (1 << 6) +#define RDLVL_GATE_EN (1 << 24) /*ZQ Configurations */ #define PHY_CON16_RESET_VAL 0x08000304 -#define ZQ_MODE_DDS_VAL (0x5 << 24) -#define ZQ_MODE_TERM_VAL (0x5 << 21) -#define SET_ZQ_MODE_DDS_VAL(x) (x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL) -#define SET_ZQ_MODE_TERM_VAL(x) (x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL) - -#define ZQ_MODE_NOTERM (1 << 19) #define ZQ_CLK_DIV_EN (1 << 18) #define ZQ_MANUAL_STR (1 << 1) +#define ZQ_DONE (1 << 0) + +#define CTRL_RDLVL_GATE_ENABLE 1 +#define CTRL_RDLVL_GATE_DISABLE 1 + +/* Direct Command */ +#define DIRECT_CMD_NOP 0x07000000 +#define DIRECT_CMD_PALL 0x01000000 +#define DIRECT_CMD_ZQINIT 0x0a000000 +#define DIRECT_CMD_CHANNEL_SHIFT 28 +#define DIRECT_CMD_CHIP_SHIFT 20 + +/* DMC PHY Control0 register */ +#define PHY_CONTROL0_RESET_VAL 0x0 +#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ +#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ +#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ +#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ + +/* Driver strength for CK, CKE, CS & CA */ +#define IMP_OUTPUT_DRV_40_OHM 0x5 +#define IMP_OUTPUT_DRV_30_OHM 0x7 +#define CA_CK_DRVR_DS_OFFSET 9 +#define CA_CKE_DRVR_DS_OFFSET 6 +#define CA_CS_DRVR_DS_OFFSET 3 +#define CA_ADR_DRVR_DS_OFFSET 0 + +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 + +struct mem_timings; + +/* Errors that we can encourter in low-level setup */ +enum { + SETUP_ERR_OK, + SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1, + SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2, +}; -/* Channel and Chip Selection */ -#define CONFIG_DMC_CHANNELS 2 -#define CONFIG_CHIPS_PER_CHANNEL 2 - -#define SET_CMD_CHANNEL(x, y) (x = (x & ~(1 << 28)) | y << 28) -#define SET_CMD_CHIP(x, y) (x = (x & ~(1 << 20)) | y << 20) - -/* Diret Command */ -#define DIRECT_CMD_NOP 0x07000000 -#define DIRECT_CMD_MRS1 0x00071C00 -#define DIRECT_CMD_MRS2 0x00010BFC -#define DIRECT_CMD_MRS3 0x00000708 -#define DIRECT_CMD_MRS4 0x00000818 -#define DIRECT_CMD_PALL 0x01000000 - -/* DLL Resync */ -#define FP_RSYNC (1 << 3) - -#define CONFIG_CTRL_DLL_ON(x, y) (x = (x & ~(1 << 5)) | y << 5) -#define CONFIG_CTRL_START(x, y) (x = (x & ~(1 << 6)) | y << 6) -#define SET_CTRL_FORCE_VAL(x, y) (x = (x & ~(0x7F << 8)) | y << 8) +/* + * Memory variant specific initialization code + * + * @param mem Memory timings for this memory type. + * @param mem_iv_size Memory interleaving size is a configurable parameter + * which the DMC uses to decide how to split a memory + * chunk into smaller chunks to support concurrent + * accesses; may vary across boards. + * @return 0 if ok, SETUP_ERR_... if there is a problem + */ +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); -/* RDLVL */ -#define PHY_CON0_RESET_VAL 0x17023240 -#define DDR_MODE_LPDDR2 0x2 -#define BYTE_RDLVL_EN (1 << 13) -#define CTRL_ATGATE (1 << 6) -#define SET_CTRL_DDR_MODE(x, y) (x = (x & ~(0x3 << 11)) | y << 11) +/* + * Configure ZQ I/O interface + * + * @param mem Memory timings for this memory type. + * @param phy0_ctrl Pointer to struct containing PHY0 control reg + * @param phy1_ctrl Pointer to struct containing PHY1 control reg + * @return 0 if ok, -1 on error + */ +int dmc_config_zq(struct mem_timings *mem, + struct exynos5_phy_control *phy0_ctrl, + struct exynos5_phy_control *phy1_ctrl); -#define PHY_CON1_RESET_VAL 0x9210100 -#define RDLVL_RDDATAPADJ 0x1 -#define SET_RDLVL_RDDATAPADJ ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\ - | RDLVL_RDDATAPADJ << 0) +/* + * Send NOP and MRS/EMRS Direct commands + * + * @param mem Memory timings for this memory type. + * @param dmc Pointer to struct of DMC registers + */ +void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc); -#define PHY_CON2_RESET_VAL 0x00010004 -#define RDLVL_EN (1 << 25) -#define RDDSKEW_CLEAR (1 << 13) - -#define CTRL_RDLVL_DATA_EN (1 << 1) -#define LPDDR2_ADDR 0x00000208 - -#define DMC_MEMCONFIG0_VAL 0x00001323 -#define DMC_MEMCONFIG1_VAL 0x00001323 -#define DMC_MEMBASECONFIG0_VAL 0x00400780 -#define DMC_MEMBASECONFIG1_VAL 0x00800780 -#define DMC_MEMCONTROL_VAL 0x00212500 -#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF -#define DMC_TIMINGREF_VAL 0x0000005D -#define DMC_TIMINGROW_VAL 0x2336544C -#define DMC_TIMINGDATA_VAL 0x24202408 -#define DMC_TIMINGPOWER_VAL 0x38260235 - -#define CTRL_BSTLEN 0x04 -#define CTRL_RDLAT 0x08 -#define PHY_CON42_VAL (CTRL_BSTLEN << 8 | CTRL_RDLAT << 0) - -/* DQS, DQ, DEBUG offsets */ -#define SET_DQS_OFFSET_VAL 0x7F7F7F7F -#define SET_DQ_OFFSET_VAL 0x7F7F7F7F -#define SET_DEBUG_OFFSET_VAL 0x7F - -#define RESET_DQS_OFFSET_VAL 0x08080808 -#define RESET_DQ_OFFSET_VAL 0x08080808 -#define RESET_DEBUG_OFFSET_VAL 0x8 - -#define CTRL_PULLD_DQ (0x0F << 8) -#define CTRL_PULLD_DQS (0x0F << 0) +/* + * Send PALL Direct commands + * + * @param mem Memory timings for this memory type. + * @param dmc Pointer to struct of DMC registers + */ +void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc); -#define DFI_INIT_START (1 << 28) +/* + * Configure the memconfig and membaseconfig registers + * + * @param mem Memory timings for this memory type. + * @param exynos5_dmc Pointer to struct of DMC registers + */ +void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc); -#define CLK_STOP_EN (1 << 0) -#define DPWRDN_EN (1 << 1) -#define DSREF_EN (1 << 5) +/* + * Reset the DLL. This function is common between DDR3 and LPDDR2. + * However, the reset value is different. So we are passing a flag + * ddr_mode to distinguish between LPDDR2 and DDR3. + * + * @param exynos5_dmc Pointer to struct of DMC registers + * @param ddr_mode Type of DDR memory + */ +void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); -#define AREF_EN (1 << 5) void sdelay(unsigned long); void mem_ctrl_init(void); void system_clock_init(void); void tzpc_init(void); - #endif diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds new file mode 100644 index 0000000..d78dd77 --- /dev/null +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * Copyright (C) 2012 Samsung Electronics + * + * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) + +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + . = ALIGN(4); + + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + . = ALIGN(4); + + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + + /* Align .machine_param on 256 byte boundary for easier searching */ + .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram + . = ALIGN(4); + + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram +} diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index fae7d6f..a5816e4 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -131,13 +131,13 @@ int board_mmc_init(bd_t *bis) { int err; - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); if (err) { - debug("SDMMC2 not configured\n"); + debug("SDMMC0 not configured\n"); return err; } - err = s5p_mmc_init(2, 4); + err = s5p_mmc_init(0, 8); return err; } #endif diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c new file mode 100644 index 0000000..1d453ca --- /dev/null +++ b/board/samsung/smdk5250/smdk5250_spl.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/spl.h> +#include <asm/arch/clk.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirM", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .mem_manuf = MEM_MANUF_SAMSUNG, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* Will hang if SIGNATURE dont match */ + while (1) + ; + } + + return &machine_param; +} diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 6d18835..6f9a554 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -50,12 +50,10 @@ lowlevel_init: orr r0, r0, #0x0 str r5, [r0] -#ifndef CONFIG_ONENAND_IPL /* setting SRAM */ ldr r0, =S5PC100_SROMC_BASE ldr r1, =0x9 str r1, [r0] -#endif /* S5PC100 has 3 groups of interrupt sources */ ldr r0, =S5PC100_VIC0_BASE @0xE4000000 @@ -68,7 +66,6 @@ lowlevel_init: str r3, [r1, #0x14] @INTENCLEAR str r3, [r2, #0x14] @INTENCLEAR -#ifndef CONFIG_ONENAND_IPL /* Set all interrupts as IRQ */ str r5, [r0, #0xc] @INTSELECT str r5, [r1, #0xc] @INTSELECT @@ -78,54 +75,17 @@ lowlevel_init: str r5, [r0, #0xf00] @INTADDRESS str r5, [r1, #0xf00] @INTADDRESS str r5, [r2, #0xf00] @INTADDRESS -#endif -#ifndef CONFIG_ONENAND_IPL /* for UART */ bl uart_asm_init /* for TZPC */ bl tzpc_asm_init -#endif - -#ifdef CONFIG_ONENAND_IPL - /* init system clock */ - bl system_clock_init - - bl mem_ctrl_asm_init - - /* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =S5PC100_RST_STAT - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset -#endif 1: mov lr, r9 mov pc, lr -#ifdef CONFIG_ONENAND_IPL -wakeup_reset: - - /* Clear wakeup status register */ - ldr r0, =S5PC100_WAKEUP_STAT - ldr r1, [r0] - str r1, [r0] - - /* Load return address and jump to kernel */ - ldr r0, =S5PC100_INFORM0 - - /* r1 = physical address of s5pc100_cpu_resume function */ - ldr r1, [r0] - - /* Jump to kernel (sleep.S) */ - mov pc, r1 - nop - nop -#endif - /* * system_clock_init: Initialize core clock and bus clock. * void system_clock_init(void) @@ -178,7 +138,6 @@ system_clock_init: mov pc, lr -#ifndef CONFIG_ONENAND_IPL /* * uart_asm_init: Initialize UART's pins */ @@ -212,4 +171,3 @@ tzpc_asm_init: str r1, [r0, #0x810] mov pc, lr -#endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a8b2b11..e11a892 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -59,6 +59,8 @@ static int hwrevision(int rev) return (board_rev & 0xf) == rev; } +struct s3c_plat_otg_data s5pc210_otg_data; + int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -73,6 +75,21 @@ int board_init(void) return 0; } +void i2c_init_board(void) +{ + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + + /* I2C_5 -> PMIC */ + s5p_gpio_direction_output(&gpio1->b, 7, 1); + s5p_gpio_direction_output(&gpio1->b, 6, 1); + /* I2C_9 -> FG */ + s5p_gpio_direction_output(&gpio2->y4, 0, 1); + s5p_gpio_direction_output(&gpio2->y4, 1, 1); +} + int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + @@ -259,6 +276,12 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, .usb_flags = PHY0_SLEEP, }; + +void board_usb_init(void) +{ + debug("USB_udc_probe\n"); + s3c_udc_probe(&s5pc210_otg_data); +} #endif static void pmic_reset(void) diff --git a/board/apollon/Makefile b/board/schulercontrol/sc_sps_1/Makefile index 1bf1a32..24a1003 100644 --- a/board/apollon/Makefile +++ b/board/schulercontrol/sc_sps_1/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000, 2001, 2002 +# (C) Copyright 2000-2012 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,19 +25,23 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-y := apollon.o mem.o sys_info.o -SOBJS := lowlevel_init.o +ifndef CONFIG_SPL_BUILD +COBJS := sc_sps_1.o +else +COBJS := spl_boot.o +endif -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### +# defines $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend + +######################################################################### diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c new file mode 100644 index 0000000..fda191a --- /dev/null +++ b/board/schulercontrol/sc_sps_1/sc_sps_1.c @@ -0,0 +1,113 @@ +/* + * SchulerControl GmbH, SC_SPS_1 module + * + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | + MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); + gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1); +#endif + + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + return mxsmmc_initialize(bis, 0, NULL); +} +#endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + int ret; + + ret = cpu_eth_init(bis); + + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK, + CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC1\n"); + return ret; + } + + return ret; +} + +#endif diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c new file mode 100644 index 0000000..7fcbc18 --- /dev/null +++ b/board/schulercontrol/sc_sps_1/spl_boot.c @@ -0,0 +1,165 @@ +/* + * SchulerControl GmbH, SC_SPS_1 module setup + * + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* -- Strick 3 -- */ + + /* FEC Ethernet */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */ + + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* -- Strick 4 -- */ + + /* EMI */ + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + + /* -- Strick 5 -- */ + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + + /* SPI2 (for flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + + /* -- Strick 6 -- */ + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* AUART0 */ + MX28_PAD_AUART0_TX__AUART0_TX, + MX28_PAD_AUART0_RX__AUART0_RX, + + /* MEGA interface */ + + /* Debug UART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* LED */ + MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED, + MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED, + MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED, +}; + +void board_init_ll(void) +{ + mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); +} + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[0x74 >> 2] = 0x0f02010a; +} diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile new file mode 100644 index 0000000..a26dadc --- /dev/null +++ b/board/st-ericsson/snowball/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) ST-Ericsson SA 2009 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +CFLAGS += -D__RELEASE -D__STN_8500 +LIB = $(obj)lib$(BOARD).o + +COBJS := snowball.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h new file mode 100644 index 0000000..e339cb8 --- /dev/null +++ b/board/st-ericsson/snowball/db8500_pins.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + ** + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __DB8500_PINS_H +#define __DB8500_PINS_H + +#include <asm/arch/db8500_pincfg.h> + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c new file mode 100644 index 0000000..8c743c0 --- /dev/null +++ b/board/st-ericsson/snowball/snowball.c @@ -0,0 +1,348 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <i2c.h> +#include <mmc.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/db8500_pincfg.h> +#include <asm/arch/prcmu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_MMC +#include "../../../drivers/mmc/arm_pl180_mmci.h" +#endif +#include "db8500_pins.h" + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* + * Memory controller register + */ +#define DMC_BASE_ADDR 0x80156000 +#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) + +/* + * GPIO pin config common for MOP500/HREF boards + */ +unsigned long gpio_cfg_common[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, + + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* UART2, console */ + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, + + /* + * USB, pin 256-267 USB, Is probably already setup correctly from + * BootROM/boot stages, but we don't trust that and set it up anyway + */ + GPIO256_USB_NXT, + GPIO257_USB_STP, + GPIO258_USB_XCLK, + GPIO259_USB_DIR, + GPIO260_USB_DAT7, + GPIO261_USB_DAT6, + GPIO262_USB_DAT5, + GPIO263_USB_DAT4, + GPIO264_USB_DAT3, + GPIO265_USB_DAT2, + GPIO266_USB_DAT1, + GPIO267_USB_DAT0, +}; + +unsigned long gpio_cfg_snowball[] = { + /* MMC0 (MicroSD card) */ + GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ + GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ + GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ + + /* eMMC */ + GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ + + /* LAN */ + GPIO131_SM_ADQ8, + GPIO132_SM_ADQ9, + GPIO133_SM_ADQ10, + GPIO134_SM_ADQ11, + GPIO135_SM_ADQ12, + GPIO136_SM_ADQ13, + GPIO137_SM_ADQ14, + GPIO138_SM_ADQ15, + + /* RSTn_LAN */ + GPIO141_GPIO | PIN_OUTPUT_HIGH, +}; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* + * Setup board (bd) and board-info (bi). + * bi_arch_number: Unique id for this board. It will passed in r1 to + * Linux startup code and is the machine_id. + * bi_boot_params: Where this board expects params. + */ + gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; + gd->bd->bi_boot_params = 0x00000100; + + /* Configure GPIO pins needed by U-boot */ + db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); + + db8500_gpio_config_pins(gpio_cfg_snowball, + ARRAY_SIZE(gpio_cfg_snowball)); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = gd->bd->bi_dram[0].size = + get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); + + return 0; +} + +static int raise_ab8500_gpio16(void) +{ + int ret; + + /* selection */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret); + if (ret < 0) + goto out; + + /* direction */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret); + if (ret < 0) + goto out; + + /* out */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret); + +out: + return ret; +} + +static int raise_ab8500_gpio26(void) +{ + int ret; + + /* selection */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG); + if (ret < 0) + goto out; + + ret |= 0x2; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret); + if (ret < 0) + goto out; + + /* out */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG); + if (ret < 0) + goto out; + + ret |= 0x2; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret); + +out: + return ret; +} + +int board_late_init(void) +{ + /* enable 3V3 for LAN controller */ + if (raise_ab8500_gpio26() >= 0) { + /* Turn on FSMC device */ + writel(0x1, 0x8000f000); + writel(0x1, 0x8000f008); + + /* setup FSMC for LAN controler */ + writel(0x305b, 0x80000000); + + /* run at the highest possible speed */ + writel(0x01010210, 0x80000004); + } else + printf("error: can't raise GPIO26\n"); + + /* enable 3v6 for GBF chip */ + if ((raise_ab8500_gpio16() < 0)) + printf("error: cant' raise GPIO16\n"); + + return 0; +} + +#ifdef CONFIG_MMC +/* + * emmc_host_init - initialize the emmc controller. + * Configure GPIO settings, set initial clock and power for emmc slot. + * Initialize mmc struct and register with mmc framework. + */ +static int emmc_host_init(void) +{ + struct pl180_mmc_host *host; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + host->base = (struct sdi_registers *)CFG_EMMC_BASE; + host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | + SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; + strcpy(host->name, "EMMC"); + host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; + host->voltages = VOLTAGE_WINDOW_MMC; + host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); + host->clock_max = ARM_MCLK / 2; + host->clock_in = ARM_MCLK; + host->version2 = 1; + + return arm_pl180_mmci_init(host); +} + +/* + * mmc_host_init - initialize the external mmc controller. + * Configure GPIO settings, set initial clock and power for mmc slot. + * Initialize mmc struct and register with mmc framework. + */ +static int mmc_host_init(void) +{ + struct pl180_mmc_host *host; + u32 sdi_u32; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + host->base = (struct sdi_registers *)CFG_MMC_BASE; + sdi_u32 = 0xBF; + writel(sdi_u32, &host->base->power); + host->pwr_init = 0xBF; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | + SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; + strcpy(host->name, "MMC"); + host->caps = MMC_MODE_8BIT; + host->b_max = 0; + host->voltages = VOLTAGE_WINDOW_SD; + host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); + host->clock_max = ARM_MCLK / 2; + host->clock_in = ARM_MCLK; + host->version2 = 1; + + return arm_pl180_mmci_init(host); +} + +/* + * board_mmc_init - initialize all the mmc/sd host controllers. + * Called by generic mmc framework. + */ +int board_mmc_init(bd_t *bis) +{ + int error; + + (void) bis; + + error = emmc_host_init(); + if (error) { + printf("emmc_host_init() %d\n", error); + return -1; + } + + u8500_mmc_power_init(); + + error = mmc_host_init(); + if (error) { + printf("mmc_host_init() %d\n", error); + return -1; + } + + return 0; +} +#endif /* CONFIG_MMC */ diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile index 4091a42..4ea2212 100644 --- a/board/st-ericsson/u8500/Makefile +++ b/board/st-ericsson/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk CFLAGS += -D__RELEASE -D__STN_8500 LIB = $(obj)lib$(BOARD).o -COBJS := u8500_href.o gpio.o prcmu.o +COBJS := u8500_href.o gpio.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/st-ericsson/u8500/prcmu-fw.h b/board/st-ericsson/u8500/prcmu-fw.h deleted file mode 100644 index 0836983..0000000 --- a/board/st-ericsson/u8500/prcmu-fw.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Copied from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __MACH_PRCMU_FW_V1_H -#define __MACH_PRCMU_FW_V1_H - -#define AP_EXECUTE 2 -#define I2CREAD 1 -#define I2C_WR_OK 1 -#define I2C_RD_OK 2 -#define I2CWRITE 0 - -#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ - -/* Mailbox 5 Requests */ -#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) -#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) -#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) - -/* Mailbox 5 ACKs */ -#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) -#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) -#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) - -#define LOW_POWER_WAKEUP 1 -#define EXE_WAKEUP 0 - -#define REQ_MB5 5 - -extern int prcmu_i2c_read(u8 reg, u16 slave); -extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); - -#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/prcmu.c b/board/st-ericsson/u8500/prcmu.c deleted file mode 100644 index 6f9302f..0000000 --- a/board/st-ericsson/u8500/prcmu.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Adapted from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - */ - -/* - * NOTE: This currently does not support the I2C workaround access method. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> - -#include "prcmu-fw.h" - -/* CPU mailbox registers */ -#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc) -#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) -#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) - -static int prcmu_is_ready(void) -{ - int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; - if (!ready) - printf("PRCMU firmware not ready\n"); - return ready; -} - -static int _wait_for_req_complete(int num) -{ - int timeout = 1000; - - /* checking any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - timeout = 1000; - - /* Set an interrupt to XP70 */ - writel(1 << num, PRCM_MBOX_CPU_SET); - - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - if (!timeout) { - printf("PRCMU operation timed out\n"); - return -1; - } - - return 0; -} - -/** - * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db8500 register to be accessed - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_read(u8 reg, u16 slave) -{ - uint8_t i2c_status; - uint8_t i2c_val; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(0, PRCM_REQ_MB5_I2CVAL); - - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - i2c_val = readb(PRCM_ACK_MB5_VAL); - - if (i2c_status == I2C_RD_OK) - return i2c_val; - else { - - printf("prcmu_i2c_read:read return status= %d\n", - i2c_status); - return -1; - } - -} - -/** - * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db800 register to be written to - * @reg_data: - the data to write - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) -{ - uint8_t i2c_status; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - - debug("\ncpu_is_u8500v11\n"); - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - debug("\ni2c_status = %x\n", i2c_status); - if (i2c_status == I2C_WR_OK) - return 0; - else { - printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); - return -1; - } -} diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 5f85fdc..ec559e3 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -18,6 +18,7 @@ #include <config.h> #include <common.h> +#include <malloc.h> #include <i2c.h> #include <asm/types.h> #include <asm/io.h> @@ -26,8 +27,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/prcmu.h> #ifdef CONFIG_MMC -#include "prcmu-fw.h" #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif @@ -42,7 +43,6 @@ * SGA: Smart Graphic accelerator * B2R2: Graphic blitter */ -#define PRCMU_BASE CFG_PRCMU_BASE /* 0x80157000 for U8500 */ #define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000) #define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004) #define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008) @@ -139,18 +139,6 @@ void show_boot_progress(int progress) } #endif -static unsigned int read_asicid(void) -{ - unsigned int *address = (void *)U8500_BOOTROM_BASE - + U8500_BOOTROM_ASIC_ID_OFFSET; - return readl(address); -} - -int cpu_is_u8500v11(void) -{ - return read_asicid() == 0x008500A1; -} - /* * Miscellaneous platform dependent initialisations */ @@ -227,67 +215,6 @@ unsigned int addr_vall_arr[] = { }; #ifdef CONFIG_BOARD_LATE_INIT -#ifdef CONFIG_MMC - -#define LDO_VAUX3_MASK 0x3 -#define LDO_VAUX3_ENABLE 0x1 -#define VAUX3_VOLTAGE_2_9V 0xd - -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 - -static int hrefplus_mmc_power_init(void) -{ - int ret; - int val; - - if (!cpu_is_u8500v11()) - return 0; - - /* - * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD - * card to work. This is done by enabling the regulators in the AB8500 - * via PRCMU I2C transactions. - * - * This code is derived from the handling of AB8500_LDO_VAUX3 in - * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. - * - * Turn off and delay is required to have it work across soft reboots. - */ - - ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); - if (ret < 0) - goto out; - - val = ret; - - /* Turn off */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, - val & ~LDO_VAUX3_MASK); - if (ret < 0) - goto out; - - udelay(10 * 1000); - - /* Set the voltage to 2.9V */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, - VAUX3_VOLTAGE_2_9V); - if (ret < 0) - goto out; - - val = val & ~LDO_VAUX3_MASK; - val = val | LDO_VAUX3_ENABLE; - - /* Turn on the supply */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, val); - -out: - return ret; -} -#endif /* * called after all initialisation were done, but before the generic * mmc_initialize(). @@ -314,7 +241,7 @@ int board_late_init(void) setenv("board_id", "1"); } #ifdef CONFIG_MMC - hrefplus_mmc_power_init(); + u8500_mmc_power_init(); /* * config extended GPIO pins for level shifter and @@ -448,12 +375,27 @@ static int u8500_mmci_board_init(void) int board_mmc_init(bd_t *bd) { + struct pl180_mmc_host *host; + if (u8500_mmci_board_init()) return -ENODEV; - if (arm_pl180_mmci_init()) - return -ENODEV; - return 0; + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + strcpy(host->name, "MMC"); + host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; + host->voltages = VOLTAGE_WINDOW_MMC; + host->caps = 0; + host->clock_in = ARM_MCLK; + host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; + + return arm_pl180_mmci_init(host); } #endif diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index c56b195..fe5589d 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -56,7 +56,7 @@ int board_init() /* Setup of core volatage selection pin to run at 1.4V */ writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + gpio_direction_output(IMX_GPIO_NR(3, 15), 1); /* Setup of input daisy chains for SD card pins*/ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); @@ -68,10 +68,10 @@ int board_init() /* Setup of digital output for USB power and OC */ writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + gpio_direction_output(IMX_GPIO_NR(1, 28), 1); writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ - gpio_direction_input(MXC_GPIO_PORT_TO_NUM(1, 18)); + gpio_direction_input(IMX_GPIO_NR(1, 18)); /* Setup of digital output control pins */ writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ @@ -83,21 +83,21 @@ int board_init() writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ /* Switch both output drivers off */ - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 7), 0); - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 6), 0); + gpio_direction_output(IMX_GPIO_NR(1, 7), 0); + gpio_direction_output(IMX_GPIO_NR(1, 6), 0); /* Setup of key input pin GPIO2[29]*/ writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ - gpio_direction_input(MXC_GPIO_PORT_TO_NUM(2, 29)); + gpio_direction_input(IMX_GPIO_NR(2, 29)); /* Setup of status LED outputs */ writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ /* Switch both LEDs off */ - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(4, 21), 0); - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + gpio_direction_output(IMX_GPIO_NR(4, 21), 0); + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); /* Setup of CAN1 and CAN2 signals */ writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ @@ -148,12 +148,12 @@ int board_late_init(void) writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); /* assert PHY reset (low) */ - gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0); + gpio_direction_output(IMX_GPIO_NR(3, 16), 0); udelay(5000); /* deassert PHY reset */ - gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + gpio_set_value(IMX_GPIO_NR(3, 16), 1); udelay(5000); #endif @@ -161,12 +161,12 @@ int board_late_init(void) e = getenv("gs_base_board"); if (e != NULL) { if (strcmp(e, "G283") == 0) { - int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29)); + int key = gpio_get_value(IMX_GPIO_NR(2, 29)); if (key) { /* Switch on both LEDs to inidcate boot mode */ - gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0); - gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + gpio_set_value(IMX_GPIO_NR(1, 29), 0); + gpio_set_value(IMX_GPIO_NR(4, 21), 0); setenv("preboot", "run gs_slow_boot"); } else diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile new file mode 100644 index 0000000..4f17a27 --- /dev/null +++ b/board/taskit/stamp9g20/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2012 +# Markus Hubig <mhubig@imko.de> +# IMKO GmbH <www.imko.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += stamp9g20.o +COBJS-y += led.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/taskit/stamp9g20/led.c b/board/taskit/stamp9g20/led.c new file mode 100644 index 0000000..197b4da --- /dev/null +++ b/board/taskit/stamp9g20/led.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * (C) Copyright 2009 + * Eric Benard <eric@eukrea.com> + * + * (C) Copyright 2012 + * Markus Hubig <mhubig@imko.de> + * IMKO GmbH <www.imko.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pmc.h> +#include <status_led.h> + +static unsigned int saved_state[3] = {STATUS_LED_OFF, + STATUS_LED_OFF, STATUS_LED_OFF}; + +void coloured_LED_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable the clock */ + writel(ATMEL_ID_PIOC, &pmc->pcer); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 0); +} + +void red_led_on(void) +{ + at91_set_gpio_value(CONFIG_RED_LED, 1); + saved_state[STATUS_LED_RED] = STATUS_LED_ON; +} + +void red_led_off(void) +{ + at91_set_gpio_value(CONFIG_RED_LED, 0); + saved_state[STATUS_LED_RED] = STATUS_LED_OFF; +} + +void green_led_on(void) +{ + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + saved_state[STATUS_LED_GREEN] = STATUS_LED_ON; +} + +void green_led_off(void) +{ + at91_set_gpio_value(CONFIG_GREEN_LED, 0); + saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF; +} + +void yellow_led_on(void) +{ + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON; +} + +void yellow_led_off(void) +{ + at91_set_gpio_value(CONFIG_YELLOW_LED, 0); + saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF; +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_led_off(); + else + red_led_on(); + + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) + green_led_off(); + else + green_led_on(); + + } else if (STATUS_LED_YELLOW == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW]) + yellow_led_off(); + else + yellow_led_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_led_on(); + else + red_led_off(); + + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == state) + green_led_on(); + else + green_led_off(); + + } else if (STATUS_LED_YELLOW == mask) { + if (STATUS_LED_ON == state) + yellow_led_on(); + else + yellow_led_off(); + } +} diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c new file mode 100644 index 0000000..06df0af --- /dev/null +++ b/board/taskit/stamp9g20/stamp9g20.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * Achim Ehrlich <aehrlich@taskit.de> + * taskit GmbH <www.taskit.de> + * + * (C) Copyright 2012- + * Markus Hubig <mhubig@imko.de> + * IMKO GmbH <www.imko.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <watchdog.h> + +#ifdef CONFIG_MACB +# include <net.h> +# include <netdev.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void stamp9G20_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +#ifdef CONFIG_MACB +static void stamp9G20_macb_hw_init(void) +{ + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ + at91_set_gpio_output(AT91_PIN_PA26, 0); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA18) | + pin_to_mask(AT91_PIN_PA28), + &pioa->pudr); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) & + ~AT91_RSTC_MR_URSTEN), &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end of hardware reset */ + unsigned long start = get_timer(0); + unsigned long timeout = 1000; /* 1000ms */ + + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { + + /* avoid shutdown by watchdog */ + WATCHDOG_RESET(); + mdelay(10); + + /* timeout for not getting stuck in an endless loop */ + if (get_timer(start) >= timeout) { + puts("*** ERROR: Timeout waiting for PHY reset!\n"); + break; + }; + }; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA18) | + pin_to_mask(AT91_PIN_PA28), + &pioa->puer); + + /* Initialize EMAC=MACB hardware */ + at91_macb_hw_init(); +} +#endif /* CONFIG_MACB */ + +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), &pmc->pcer); + + return 0; +} + +int board_postclk_init(void) +{ + /* + * Initialize the serial interface here, because be need a running + * timer to set PC9 to high and wait for some time to enable the + * level converter of the RS232 interface on the PortuxG20 board. + */ + +#ifdef CONFIG_PORTUXG20 + at91_set_gpio_output(AT91_PIN_PC9, 1); + mdelay(1); +#endif + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + stamp9G20_nand_hw_init(); +#ifdef CONFIG_MACB + stamp9G20_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_MACB +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); +} +#endif /* CONFIG_MACB */ diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index c2b10ac..7429e93 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -100,8 +100,18 @@ int board_init(void) int misc_init_r(void) { + char *eth_addr; + dieid_num_r(); + eth_addr = getenv("ethaddr"); + if (eth_addr) + return 0; + +#ifndef CONFIG_SPL_BUILD + TAM3517_READ_MAC_FROM_EEPROM; +#endif + return 0; } diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 9fbaedd..b8ad447 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -21,13 +21,17 @@ #include <common.h> #include <netdev.h> +#include <malloc.h> #include <fpga.h> +#include <video_fb.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/omap_gpio.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/dss.h> +#include <asm/arch/clocks.h> #include <i2c.h> #include <spartan3.h> #include <asm/gpio.h> @@ -39,6 +43,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BUZZER 140 +#define SPEAKER 141 + #ifndef CONFIG_FPGA #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" #endif @@ -50,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_INIT 119 #define FPGA_DONE 154 +#define LCD_PWR 138 +#define LCD_PON_PIN 139 + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct { + u32 xres; + u32 yres; +} panel_resolution[] = { + { 480, 272 }, + { 800, 480 } +}; + +static struct panel_config lcd_cfg[] = { + { + .timing_h = PANEL_TIMING_H(4, 8, 41), + .timing_v = PANEL_TIMING_V(2, 4, 10), + .pol_freq = 0x00000000, /* Pol Freq */ + .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + }, + { + .timing_h = PANEL_TIMING_H(20, 192, 4), + .timing_v = PANEL_TIMING_V(2, 20, 10), + .pol_freq = 0x00004000, /* Pol Freq */ + .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + } +}; +#endif + /* Timing definitions for FPGA */ static const u32 gpmc_fpga[] = { FPGA_GPMC_CONFIG1, @@ -193,6 +236,33 @@ int board_init(void) mt_ventoux_init_fpga(); + /* GPIO_140: speaker #mute */ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) + /* GPIO_141: Buzz Hi */ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) + + /* Turning off the buzzer */ + gpio_request(BUZZER, "BUZZER_MUTE"); + gpio_request(SPEAKER, "SPEAKER"); + gpio_direction_output(BUZZER, 0); + gpio_direction_output(SPEAKER, 0); + + return 0; +} + +int misc_init_r(void) +{ + char *eth_addr; + + dieid_num_r(); + + eth_addr = getenv("ethaddr"); + if (eth_addr) + return 0; + +#ifndef CONFIG_SPL_BUILD + TAM3517_READ_MAC_FROM_EEPROM; +#endif return 0; } @@ -224,3 +294,46 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0); } #endif + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +int board_video_init(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct panel_config *panel = &lcd_cfg[0]; + char *s; + u32 index = 0; + + void *fb; + + fb = (void *)0x88000000; + + s = getenv("panel"); + if (s) { + index = simple_strtoul(s, NULL, 10); + if (index < ARRAY_SIZE(lcd_cfg)) + panel = &lcd_cfg[index]; + else + return 0; + } + + panel->frame_buffer = fb; + printf("Panel: %dx%d\n", panel_resolution[index].xres, + panel_resolution[index].yres); + panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | + (panel_resolution[index].xres - 1); + + gpio_request(LCD_PWR, "LCD Power"); + gpio_request(LCD_PON_PIN, "LCD Pon"); + gpio_direction_output(LCD_PWR, 0); + gpio_direction_output(LCD_PON_PIN, 1); + + + setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); + + omap3_dss_panel_config(panel); + omap3_dss_enable(); + + return 0; +} +#endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index 9b2e43e..1cd7ec2 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -142,7 +142,8 @@ const omap3_sysinfo sysinfo = { /*GPIO_62: FPGA_RESET */ \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/ \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ + /* GPIO_64*/ \ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ /* DSS */\ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ @@ -174,26 +175,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ @@ -209,6 +190,7 @@ const omap3_sysinfo sysinfo = { /* GPIO_126: CardDetect */\ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + /*GPIO_128 */ \ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ \ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ @@ -221,7 +203,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ /* GPIO_138: LCD_ENVD */\ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ /* GPIO_139: LCD_PON */\ /* McBSP */\ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ @@ -241,16 +223,12 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ /* GPIO_119: FPGA_INIT */ \ \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ - /* GPIO_140: speaker #mute */\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ - /* GPIO_141: Buzz Hi */\ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ \ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ /*GPIO_152: Ignition Sense */ \ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) \ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ /*GPIO_153: Power Button Sense */ \ MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ /* GPIO_154: FPGA_DONE */ \ @@ -264,10 +242,14 @@ const omap3_sysinfo sysinfo = { /* GPIO_150: USB status 1 */\ \ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ + /* gpt9_pwm */\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ + /* gpt10_pwm */\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ + /* gpt8_pwm */\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ + /* gpt11_pwm */\ \ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ /*GPIO_163 : TS_PENIRQ*/ \ @@ -299,22 +281,24 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ + /* GPIO94 */\ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ /* GPIO95: #Enable Output */\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ /* GPIO 99: #SOM_PWR_OFF */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ /* GPIO_100: #power out */\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ + /* GPIO_102 */\ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ /* RMII */\ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ @@ -363,7 +347,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ \ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ + /* gpio_10 */\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ @@ -387,12 +372,15 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ + /* gpio_24 */\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + /* gpio_26 */\ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* gpio_29 */\ /* Die to Die */\ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index d58b185..ca50eef 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -18,7 +18,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := evm.o mux.o +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c deleted file mode 100644 index 5e2d53a..0000000 --- a/board/ti/am335x/evm.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * evm.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/common_def.h> -#include <serial.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -/* - * Basic board specific setup - */ -int board_init(void) -{ - enable_uart0_pin_mux(); - -#ifdef CONFIG_I2C - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; - - return 0; -} diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 9ccb436..80becd5 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ -#include <config.h> -#include <asm/arch/common_def.h> +#include <common.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/io.h> +#include <i2c.h> #define MUX_CFG(value, offset) \ __raw_writel(value, (CTRL_BASE + offset)); @@ -258,7 +259,6 @@ static struct module_pin_mux uart0_pin_mux[] = { {-1}, }; -#ifdef CONFIG_MMC static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ @@ -270,7 +270,29 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; -#endif + +static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ + {-1}, +}; static struct module_pin_mux i2c0_pin_mux[] = { {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | @@ -280,6 +302,66 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + /* * Configure the pin mux for the module */ @@ -299,14 +381,75 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } -#ifdef CONFIG_MMC -void enable_mmc0_pin_mux(void) -{ - configure_module_pin_mux(mmc0_pin_mux); -} -#endif void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } + +/* + * The AM335x GP EVM, if daughter card(s) are connected, can have 8 + * different profiles. These profiles determine what peripherals are + * valid and need pinmux to be configured. + */ +#define PROFILE_NONE 0x0 +#define PROFILE_0 (1 << 0) +#define PROFILE_1 (1 << 1) +#define PROFILE_2 (1 << 2) +#define PROFILE_3 (1 << 3) +#define PROFILE_4 (1 << 4) +#define PROFILE_5 (1 << 5) +#define PROFILE_6 (1 << 6) +#define PROFILE_7 (1 << 7) +#define PROFILE_MASK 0x7 +#define PROFILE_ALL 0xFF + +/* CPLD registers */ +#define I2C_CPLD_ADDR 0x35 +#define CFG_REG 0x10 + +static unsigned short detect_daughter_board_profile(void) +{ + unsigned short val; + + if (i2c_probe(I2C_CPLD_ADDR)) + return PROFILE_NONE; + + if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) + return PROFILE_NONE; + + return (1 << (val & PROFILE_MASK)); +} + +void enable_board_pin_mux(struct am335x_baseboard_id *header) +{ + /* Do board-specific muxes. */ + if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { + /* Beaglebone pinmux */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + } else if (!strncmp(header->config, "SKU#01", 6)) { + /* General Purpose EVM */ + unsigned short profile = detect_daughter_board_profile(); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + /* In profile #2 i2c1 and spi0 conflict. */ + if (profile & ~PROFILE_2) + configure_module_pin_mux(i2c1_pin_mux); + else if (profile == PROFILE_2) { + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + } + } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { + /* Starter Kit EVM */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux_sk_evm); + } else { + puts("Unknown board, cannot configure pinmux."); + hang(); + } +} diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 2ef2290..99f833f 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -50,8 +50,6 @@ #include <asm/ehci-omap.h> #endif -#define pr_debug(fmt, args...) debug(fmt, ##args) - #define TWL4030_I2C_BUS 0 #define EXPANSION_EEPROM_I2C_BUS 1 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 @@ -112,7 +110,7 @@ int board_init(void) * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 * GPIO173, GPIO172, GPIO171: 0 0 0 => xM */ -int get_board_revision(void) +static int get_board_revision(void) { int revision; @@ -211,7 +209,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, * bus 1 for the availability of an AT24C01B serial EEPROM. * returns the device_vendor field from the EEPROM */ -unsigned int get_expansion_id(void) +static unsigned int get_expansion_id(void) { i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); @@ -230,11 +228,12 @@ unsigned int get_expansion_id(void) return expansion_config.device_vendor; } +#ifdef CONFIG_VIDEO_OMAP3 /* * Configure DSS to display background color on DVID * Configure VENC to display color bar on S-Video */ -void beagle_display_init(void) +static void beagle_display_init(void) { omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); switch (get_board_revision()) { @@ -284,6 +283,7 @@ static void beagle_dvi_pup(void) break; } } +#endif /* * Routine: misc_init_r @@ -460,9 +460,11 @@ int misc_init_r(void) dieid_num_r(); +#ifdef CONFIG_VIDEO_OMAP3 beagle_dvi_pup(); beagle_display_init(); omap3_dss_enable(); +#endif return 0; } diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index d68bef7..f28eab0 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -521,7 +521,7 @@ static void setup_fec(void) } struct fsl_esdhc_cfg esdhc_cfg[1] = { - {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, }; int get_mmc_getcd(u8 *cd, struct mmc *mmc) @@ -674,11 +674,18 @@ int board_late_init(void) udelay(2000); #endif - setenv("stdout", "serial"); - return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int checkboard(void) { puts("Board: TTControl Vision II CPU V\n"); diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index a1e2bfe..b75e62c 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -28,6 +28,7 @@ #include <common.h> #include <config.h> #include <netdev.h> +#include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -69,6 +70,14 @@ int fsl_init2 (void) { } #endif +void board_init(void) +{ + gpio_init(); +#ifdef CONFIG_SYS_FSL_2 + fsl_init2(); +#endif +} + int board_eth_init(bd_t *bis) { int ret = 0; |