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-rw-r--r--board/adder/Makefile46
-rw-r--r--board/adder/adder.c107
-rw-r--r--board/adder/config.mk27
-rw-r--r--board/adder/u-boot.lds122
-rw-r--r--board/mx1ads/Makefile50
-rw-r--r--board/mx1ads/config.mk28
-rw-r--r--board/mx1ads/memsetup.S82
-rw-r--r--board/mx1ads/mx1ads.c183
-rw-r--r--board/mx1ads/syncflash.c334
-rw-r--r--board/mx1ads/u-boot.lds58
10 files changed, 1037 insertions, 0 deletions
diff --git a/board/adder/Makefile b/board/adder/Makefile
new file mode 100644
index 0000000..9123a80
--- /dev/null
+++ b/board/adder/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/adder/adder.c b/board/adder/adder.c
new file mode 100644
index 0000000..cab6e2f
--- /dev/null
+++ b/board/adder/adder.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+ /* Single read (offset 0x00 in UPM RAM) */
+ 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+ 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+ /* Burst read (offset 0x08 in UPM RAM) */
+ 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+ 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+ 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+ /* Single write (offset 0x18 in UPM RAM) */
+ 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+ 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Burst write (offset 0x20 in UPM RAM) */
+ 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+ 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Refresh (offset 0x30 in UPM RAM) */
+ 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Exception (offset 0x3C in UPM RAM) */
+ 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+ long int msize = CFG_SDRAM_SIZE;
+ volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+ /* Configure SDRAM refresh */
+ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+ memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+ memctl->memc_mar = 0x0;
+ udelay(200);
+
+ /* Run precharge from location 0x15 */
+ memctl->memc_mcr = 0x80002115;
+ udelay(200);
+
+ /* Run 8 refresh cycles */
+ memctl->memc_mcr = 0x80002830;
+ udelay(200);
+
+ memctl->memc_mar = 0x88;
+ udelay(200);
+
+ /* Run MRS pattern from location 0x16 */
+ memctl->memc_mcr = 0x80002116;
+ udelay(200);
+
+ return msize;
+}
+
+int checkboard( void )
+{
+ puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+ puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+ puts("II\n");
+#endif
+
+ return 0;
+}
diff --git a/board/adder/config.mk b/board/adder/config.mk
new file mode 100644
index 0000000..4691a69
--- /dev/null
+++ b/board/adder/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
new file mode 100644
index 0000000..1d2a7d7
--- /dev/null
+++ b/board/adder/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile
new file mode 100644
index 0000000..8a17702
--- /dev/null
+++ b/board/mx1ads/Makefile
@@ -0,0 +1,50 @@
+#/*
+#* board/mx1ads/Makefile
+#*
+#* (c) Copyright 2004
+#* Techware Information Technology, Inc.
+#* http://www.techware.com.tw/
+#*
+#* Ming-Len Wu <minglen_wu@techware.com.tw>
+#*
+#* This program is free software; you can redistribute it and/or
+#* modify it under the terms of the GNU General Public License as
+#* published by the Free Software Foundation; either version 2 of
+#* the License, or (at your option) any later version.
+#*
+#* This program is distributed in the hope that it will be useful,
+#* but WITHOUT ANY WARRANTY; without even the implied warranty of
+#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+#* GNU General Public License for more details.
+#*
+#* You should have received a copy of the GNU General Public License
+#* along with this program; if not, write to the Free Software
+#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#* MA 02111-1307 USA
+#*/
+
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mx1ads.o syncflash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk
new file mode 100644
index 0000000..16a0b84
--- /dev/null
+++ b/board/mx1ads/config.mk
@@ -0,0 +1,28 @@
+#/*
+#* board/mx1ads/config.mk
+#*
+#* (c) Copyright 2004
+#* Techware Information Technology, Inc.
+#* http://www.techware.com.tw/
+#*
+#* Ming-Len Wu <minglen_wu@techware.com.tw>
+#*
+#* This program is free software; you can redistribute it and/or
+#* modify it under the terms of the GNU General Public License as
+#* published by the Free Software Foundation; either version 2 of
+#* the License, or (at your option) any later version.
+#*
+#* This program is distributed in the hope that it will be useful,
+#* but WITHOUT ANY WARRANTY; without even the implied warranty of
+#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+#* GNU General Public License for more details.
+#*
+#* You should have received a copy of the GNU General Public License
+#* along with this program; if not, write to the Free Software
+#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#* MA 02111-1307 USA
+#*/
+
+
+TEXT_BASE = 0x08400000
+
diff --git a/board/mx1ads/memsetup.S b/board/mx1ads/memsetup.S
new file mode 100644
index 0000000..39b71fe
--- /dev/null
+++ b/board/mx1ads/memsetup.S
@@ -0,0 +1,82 @@
+/*
+ * board/mx1ads/memsetup.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0 0x221000
+#define SDCTL1 0x221004
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl memsetup
+memsetup:
+/* memory controller init */
+
+ ldr r1, =SDCTL0
+
+/* Set Precharge Command */
+
+ ldr r3, =0x92120200
+/* ldr r3, =0x92120251
+*/
+ str r3, [r1]
+
+/* Issue Precharge All Commad */
+ ldr r3, =0x8200000
+ ldr r2, [r3]
+
+/* Set AutoRefresh Command */
+ ldr r3, =0xA2120200
+ str r3, [r1]
+
+/* Issue AutoRefresh Command */
+ ldr r3, =0x8000000
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+
+/* Set Mode Register */
+ ldr r3, =0xB2120200
+ str r3, [r1]
+
+/* Issue Mode Register Command */
+ ldr r3, =0x08111800 /* Mode Register Value */
+ ldr r2, [r3]
+
+/* Set Normal Mode */
+ ldr r3, =0x82124200
+ str r3, [r1]
+
+/* everything is fine now */
+ mov pc, lr
+
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
new file mode 100644
index 0000000..567f88a
--- /dev/null
+++ b/board/mx1ads/mx1ads.c
@@ -0,0 +1,183 @@
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mc9328.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
+#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+#if 0
+
+static inline void delay (unsigned long loops) {
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+
+void SetAsynchMode(void) {
+ __asm__ (
+ "mrc p15,0,r0,c1,c0,0 \n"
+ "mov r2, #0xC0000000 \n"
+ "orr r0,r2,r0 \n"
+ "mcr p15,0,r0,c1,c0,0 \n"
+ );
+}
+
+static u32 mc9328sid;
+
+int board_init (void) {
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile unsigned int tmp;
+
+ mc9328sid = MX1_SIDR;
+
+ MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
+
+/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
+/* MX1_CS1L = 0x11110601; */
+
+
+ MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
+
+/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
+
+
+
+/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
+ * BCLK divider to 2 (i.e. BCLK to 48 MHz)
+ */
+ MX1_CSCR = 0xAF000403;
+
+ MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
+ MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+
+/* setup cs4 for cs8900 ethernet */
+
+ MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
+ MX1_CS4L = 0x00001501;
+
+ MX1_GIUS_A &= 0xFF3FFFFF;
+ MX1_GPR_A &= 0xFF3FFFFF;
+
+ tmp = *(unsigned int *)(0x1500000C);
+ tmp = *(unsigned int *)(0x1500000C);
+
+/* setup timer 1 as system timer */
+
+ MX1_TPRER1 = 0x1f; /* divide by 32 */
+ MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
+
+
+ SetAsynchMode();
+
+ gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
+
+ gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
+
+ icache_enable();
+ dcache_enable();
+
+/* set PERCLKs */
+ MX1_PCDR = 0x00000055; /* set PERCLKS */
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+ * all sources selected as normal interrupt
+ */
+ MX1_INTTYPEH = 0;
+ MX1_INTTYPEL = 0;
+
+ return 0;
+}
+
+
+int board_late_init(void) {
+
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+
+ switch (mc9328sid) {
+ case 0x0005901d :
+ printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+ case 0x04d4c01d :
+ printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+ case 0x00d4c01d :
+ printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+
+ default :
+ printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
+ break;
+
+ }
+
+ return 0;
+}
+
+
+int dram_init (void) {
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
new file mode 100644
index 0000000..afbe786
--- /dev/null
+++ b/board/mx1ads/syncflash.c
@@ -0,0 +1,334 @@
+/*
+ * board/mx1ads/syncflash.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mc9328.h>
+
+typedef unsigned long * p_u32;
+
+/* 4Mx16x2 IAM=0 CSD1 */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Following Setting is for CSD1 */
+#define SFCTL 0x00221004
+#define reg_SFCTL __REG(SFCTL)
+
+#define SYNCFLASH_A10 (0x00100000)
+
+#define CMD_NORMAL (0x81020300) /* Normal Mode */
+#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
+#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
+#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
+#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
+#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
+
+#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
+
+/* LCR Command */
+#define LCR_READSTATUS (0x0001C000) /* 0x70 */
+#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
+#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
+#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
+#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
+
+
+/* Get Status register */
+u32 SF_SR(void) {
+ u32 tmp,tmp1;
+
+ reg_SFCTL = CMD_PROGRAM;
+ tmp = __REG(CFG_FLASH_BASE);
+
+ reg_SFCTL = CMD_NORMAL;
+
+ reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
+ tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+
+ return tmp;
+}
+
+/* check if SyncFlash is ready */
+u8 SF_Ready(void) {
+ u32 tmp;
+
+ tmp = SF_SR();
+
+ if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
+ printf ("SyncFlash Error code %08x\n",tmp);
+ };
+
+ if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
+ printf ("SyncFlash Error code %08x\n",tmp);
+
+ };
+
+ if (tmp == 0x00800080) /* Test Bit 7 of SR */
+ return 1;
+ else
+ return 0;
+}
+
+/* Issue the precharge all command */
+void SF_PrechargeAll(void) {
+
+ u32 tmp;
+
+ reg_SFCTL = CMD_PREC; /* Set Precharge Command */
+ tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+
+}
+
+/* set SyncFlash to normal mode */
+void SF_Normal(void) {
+
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_NORMAL;
+}
+
+/* Erase SyncFlash */
+void SF_Erase(u32 RowAddress) {
+ u32 tmp;
+
+ reg_SFCTL = CMD_NORMAL;
+ tmp = __REG(RowAddress);
+
+ reg_SFCTL = CMD_PREC;
+ tmp = __REG(RowAddress);
+
+ reg_SFCTL = CMD_LCR; /* Set LCR mode */
+ __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
+
+ reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
+ __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
+
+ while(!SF_Ready());
+}
+
+
+void SF_NvmodeErase(void) {
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_LCR; /* Set to LCR mode */
+ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
+
+ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
+ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
+
+ while(!SF_Ready());
+}
+
+void SF_NvmodeWrite(void) {
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_LCR; /* Set to LCR mode */
+ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
+
+ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
+ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
+
+}
+
+
+/****************************************************************************************/
+
+ulong flash_init(void) {
+ int i, j;
+ u32 tmp;
+
+/* Turn on CSD1 for negating RESETSF of SyncFLash */
+
+ reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
+ udelay(200);
+
+ reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
+ tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
+
+ SF_Normal();
+
+ i = 0;
+
+ flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
+
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
+ }
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+
+ return FLASH_BANK_SIZE;
+}
+
+
+void flash_print_info (flash_info_t *info) {
+
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (FLASH_MAN_MT & FLASH_VENDMASK):
+ printf("Micron: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
+ printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ return;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses: ");
+
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+
+ printf ("\n");
+}
+
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+
+/* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last))
+ return ERR_INVAL;
+
+ if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+ return ERR_UNKNOWN_FLASH_VENDOR;
+
+ prot = 0;
+
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf("protected!\n");
+ return ERR_PROTECTED;
+ }
+/*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+/* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
+
+ printf("Erasing sector %2d ... ", sect);
+
+/* arm simple, non interrupt dependent timer */
+
+ reset_timer_masked();
+
+ SF_NvmodeErase();
+ SF_NvmodeWrite();
+
+ SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
+ SF_Normal();
+
+ printf("ok.\n");
+ }
+
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+ int i;
+
+ for(i = 0; i < cnt; i += 4) {
+
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
+ __REG(addr + i) = __REG((u32)src + i);
+
+ while(!SF_Ready());
+ }
+
+ SF_Normal();
+
+ return ERR_OK;
+}
+
+
diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds
new file mode 100644
index 0000000..946994d
--- /dev/null
+++ b/board/mx1ads/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * board/mx1ads/u-boot.lds
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/mc9328/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
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