diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 | ||||
| -rw-r--r-- | board/freescale/mx28evk/mx28evk.c | 25 | ||||
| -rw-r--r-- | board/freescale/mx51evk/mx51evk.c | 8 | ||||
| -rw-r--r-- | board/karo/tx25/lowlevel_init.S | 8 |
4 files changed, 20 insertions, 25 deletions
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index ae408bc..06028aa 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void) csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; /* NAND flash on D16 */ csa |= AT91_MATRIX_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index d782aea..6e719ff 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_NET -#define MII_OPMODE_STRAP_OVERRIDE 0x16 -#define MII_PHY_CTRL1 0x1e -#define MII_PHY_CTRL2 0x1f - -int fecmxc_mii_postcall(int phy) -{ - miiphy_write("FEC1", phy, MII_BMCR, 0x9000); - miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); - if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); - return 0; -} - int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis) return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC0 mii postcall\n"); - return ret; - } - dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC1 mii postcall\n"); - return ret; - } - return ret; } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 7a0682a..a94701c 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -60,6 +60,14 @@ int dram_init(void) return 0; } +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} + static void setup_iomux_uart(void) { unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 823df10..eb3f187 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -67,6 +67,14 @@ write32 0x53f80008, 0x20034000 /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + + /* * enable all implemented clocks in all three * clock control registers */ |