diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/lwmon5/sdram.c | 13 | ||||
| -rw-r--r-- | board/netstal/hcu5/sdram.c | 6 |
2 files changed, 13 insertions, 6 deletions
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 7c3cf49..36b5100 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -34,6 +34,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/io.h> +#include <asm/cache.h> #include <ppc440.h> #include <watchdog.h> @@ -59,7 +60,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); static u32 is_ecc_enabled(void) { @@ -106,6 +106,7 @@ static void program_ecc(u32 start_address, { u32 val; u32 current_addr = start_address; + u32 size; int bytes_remaining; sync(); @@ -123,12 +124,18 @@ static void program_ecc(u32 start_address, * watchdog. */ while (bytes_remaining > 0) { - dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + size = min((64 << 20), bytes_remaining); + + /* Write zero's to SDRAM */ + dcbz_area(current_addr, size); + + /* Write modified dcache lines back to memory */ + clean_dcache_range(current_addr, current_addr + size); + current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } - dflush(); sync(); wait_ddr_idle(); diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0b16b505..6b1b53a 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -34,11 +34,11 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <ppc440.h> void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); #define DDR_DCR_BASE 0x10 #define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ @@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) #endif sync(); - eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ |