diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 14 | ||||
| -rw-r--r-- | board/esd/pmc440/cmd_pmc440.c | 4 | ||||
| -rw-r--r-- | board/inka4x0/Makefile | 2 | ||||
| -rw-r--r-- | board/inka4x0/flash.c | 432 | ||||
| -rw-r--r-- | board/inka4x0/hyb25d512160bf-5.h | 32 | ||||
| -rw-r--r-- | board/inka4x0/inka4x0.c | 20 | ||||
| -rw-r--r-- | board/inka4x0/k4h511638c.h | 32 | ||||
| -rw-r--r-- | board/inka4x0/mt46v16m16-75.h | 7 | ||||
| -rw-r--r-- | board/inka4x0/mt46v32m16-75.h | 32 | ||||
| -rw-r--r-- | board/inka4x0/mt48lc16m16a2-75.h | 19 | ||||
| -rw-r--r-- | board/lwmon5/init.S | 2 |
11 files changed, 130 insertions, 466 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 2268bc0..e46efef 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -29,6 +29,7 @@ #include <asm/gpio.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/ppc4xx-intvec.h> DECLARE_GLOBAL_DATA_PTR; @@ -387,6 +388,16 @@ int testdram(void) } #endif +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. + */ +void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); +} +#endif + /************************************************************************* * pci_pre_init * @@ -438,6 +449,9 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#ifdef CONFIG_PCI_PNP + hose->fixup_irq = sequoia_pci_fixup_irq; +#endif return 1; } #endif /* defined(CONFIG_PCI) */ diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index d588d8c..350af48 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -280,10 +280,10 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] if (argc > 1) { if (!strcmp(argv[1], "400")) { - /* PLB=133MHz, PLB/PCI=4 */ + /* PLB=133MHz, PLB/PCI=3 */ printf("Bootstrapping for 400MHz\n"); sdsdp[0]=0x8678624e; - sdsdp[1]=0x0947a030; + sdsdp[1]=0x095fa030; sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; } else if (!strcmp(argv[1], "533")) { diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile index 8aa7e7c..ddfd2ef 100644 --- a/board/inka4x0/Makefile +++ b/board/inka4x0/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c deleted file mode 100644 index b138655..0000000 --- a/board/inka4x0/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CPU to flash interface is 8-bit, so make declaration accordingly - */ -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - extern void flash_preinit(void); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = - flash_get_size((FPW *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM116DB: - printf ("AM29LV116DB (16Mbit, bottom boot sect)\n"); - break; - case FLASH_AMLV128U: - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (uchar)AMD_ID_LV116DB: - debug ("Chip: AM29LV116DB\n"); - info->flash_id += FLASH_AM116DB; - info->sector_count = 35; - info->size = 0x00200000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * (64 << 10)) - 0x00030000; - break; /* => 2 MB */ - - case (FPW)AMD_ID_LV160B: - debug ("Chip: AM29LV160MB\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * 2 * (64 << 10)) - 0x00060000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr = (FPWV*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - addr[0x0555] = (FPW)0x00800080; - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FPWV*)(info->start[sect]); - addr[0] = (FPW)0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FPWV*)(info->start[l_sect]); - while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FPWV*)info->start[0]; - addr[0] = (FPW)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int i, rc = 0; - - for (i = 0; i < cnt; i++) - if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) { - return (rc); - } - - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h new file mode 100644 index 0000000..7eb1f50 --- /dev/null +++ b/board/inka4x0/hyb25d512160bf-5.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 478a331..5157f7d 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -31,10 +31,18 @@ #include <mpc5xxx.h> #include <pci.h> -#if defined(CONFIG_MPC5200_DDR) +#if defined(CONFIG_DDR_MT46V16M16) #include "mt46v16m16-75.h" -#else +#elif defined(CONFIG_SDR_MT48LC16M16A2) #include "mt48lc16m16a2-75.h" +#elif defined(CONFIG_DDR_MT46V32M16) +#include "mt46v32m16.h" +#elif defined(CONFIG_DDR_HYB25D512160BF) +#include "hyb25d512160bf.h" +#elif defined(CONFIG_DDR_K4H511638C) +#include "k4h511638c.h" +#else +#error "INKA4x0 SDRAM: invalid chip type specified!" #endif #ifndef CFG_RAMBOOT @@ -88,7 +96,7 @@ long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT - ulong test1, test2; + long test1, test2; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -108,9 +116,9 @@ long int initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -175,7 +183,7 @@ void flash_preinit(void) int misc_init_f (void) { - uchar tmp[10]; + char tmp[10]; int i, br; i = getenv_r("brightness", tmp, sizeof(tmp)); diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h new file mode 100644 index 0000000..70cc405 --- /dev/null +++ b/board/inka4x0/k4h511638c.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h index f650faa..a78e50e 100644 --- a/board/inka4x0/mt46v16m16-75.h +++ b/board/inka4x0/mt46v16m16-75.h @@ -23,15 +23,10 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONTROL 0x714F0F00 #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h new file mode 100644 index 0000000..7eb1f50 --- /dev/null +++ b/board/inka4x0/mt46v32m16-75.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h index 13a97ac..1547725 100644 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ b/board/inka4x0/mt48lc16m16a2-75.h @@ -21,27 +21,10 @@ * MA 02111-1307 USA */ -#define SDRAM_DDR 1 /* is SDR */ +#define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S index 6798e80..5aade72 100644 --- a/board/lwmon5/init.S +++ b/board/lwmon5/init.S @@ -57,7 +57,7 @@ tlbtab: #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #endif /* TLB-entry for PCI Memory */ |