diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/esd/cpci405/cpci405.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 2ed0fc2..58f792e 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -54,8 +54,6 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" - - #include "../common/auto_update.h" #ifdef CONFIG_CPCI405AB @@ -88,13 +86,11 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - /* Prototypes */ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); - int board_early_init_f (void) { #ifndef CONFIG_CPCI405_VER2 @@ -197,7 +193,6 @@ int board_early_init_f (void) return 0; } - /* ------------------------------------------------------------------------- */ int ctermm2(void) @@ -213,7 +208,6 @@ int ctermm2(void) #endif } - int cpci405_host(void) { if (mfdcr(strap) & PSR_PCI_ARBIT_EN) @@ -222,7 +216,6 @@ int cpci405_host(void) return 0; /* no, board is cpci405 adapter */ } - int cpci405_version(void) { unsigned long cntrl0Reg; @@ -262,13 +255,11 @@ int cpci405_version(void) } } - int misc_init_f (void) { return 0; /* dummy implementation */ } - int misc_init_r (void) { unsigned long cntrl0Reg; @@ -432,7 +423,6 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ @@ -515,7 +505,6 @@ long int initdram (int board_type) return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP @@ -527,7 +516,6 @@ void reset_phy(void) #endif } - /* ------------------------------------------------------------------------- */ #ifdef CONFIG_CPCI405_VER2 @@ -550,7 +538,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CPCI405_VER2 */ - #if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { @@ -585,7 +572,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ - #ifdef CONFIG_CPCI405AB #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ @@ -615,7 +601,6 @@ int OWTouchReset(void) return result; } - /* * Send 1 a 1-wire write bit. * Provide 10us recovery time. @@ -641,7 +626,6 @@ void OWWriteBit(int bit) } } - /* * Read a bit from the 1-wire bus and return it. * Provide 10us recovery time. @@ -661,7 +645,6 @@ int OWReadBit(void) return result; } - void OWWriteByte(int data) { int loop; @@ -672,7 +655,6 @@ void OWWriteByte(int data) } } - int OWReadByte(void) { int loop, result = 0; @@ -687,7 +669,6 @@ int OWReadByte(void) return result; } - int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { volatile unsigned short val; @@ -728,7 +709,6 @@ U_BOOT_CMD( NULL ); - #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ |