diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/csb226/memsetup.S | 36 | ||||
| -rw-r--r-- | board/innokom/flash.c | 3 | ||||
| -rw-r--r-- | board/innokom/innokom.c | 7 | ||||
| -rw-r--r-- | board/innokom/memsetup.S | 27 | ||||
| -rw-r--r-- | board/mpl/common/pci.c | 40 | ||||
| -rw-r--r-- | board/mpl/mip405/mip405.c | 15 | ||||
| -rw-r--r-- | board/svm_sc8xx/ppcboot.lds | 133 | ||||
| -rw-r--r-- | board/svm_sc8xx/ppcboot.lds.debug | 131 | ||||
| -rw-r--r-- | board/wepep250/Makefile | 47 | ||||
| -rw-r--r-- | board/wepep250/config.mk | 11 | ||||
| -rw-r--r-- | board/wepep250/flash.c | 321 | ||||
| -rw-r--r-- | board/wepep250/intel.h | 100 | ||||
| -rw-r--r-- | board/wepep250/memsetup.S | 147 | ||||
| -rw-r--r-- | board/wepep250/u-boot.lds | 55 | ||||
| -rw-r--r-- | board/wepep250/wepep250.c | 77 |
15 files changed, 841 insertions, 309 deletions
diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S index 6567184..60f9d50 100644 --- a/board/csb226/memsetup.S +++ b/board/csb226/memsetup.S @@ -38,6 +38,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE sub pc,pc,#4 .endm +_TEXT_BASE: + .word TEXT_BASE + /* * Memory setup @@ -222,23 +225,28 @@ mem_init: /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + /* ---------------------------------------------------------------- */ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ /* ---------------------------------------------------------------- */ /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DIR field. */ + /* this to power on defaults + DRI field. */ - ldr r4, =0x03ca4fff - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 - ldr r4, =0x03ca4030 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ + ldr r4, [r1, #MDREFR_OFFSET] /* ---------------------------------------------------------------- */ @@ -258,18 +266,16 @@ mem_init: /* Step 4: Initialize SDRAM */ /* ---------------------------------------------------------------- */ - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ + /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_SLFRSH) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 32c57d8..b7c2072 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -10,7 +10,8 @@ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> * * (C) Copyright 2002 - * Kai-Uwe Bloem, GDS, <kai-uwe.bloem@auerswald.de> + * Auerswald GmbH & Co KG, Germany + * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index 5ee5117..da238da 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -48,7 +48,7 @@ int i2c_init_board(void) icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); /* set gpio pin low _before_ we change direction to output */ - GPCR(70) = GPIO_bit(70); + GPCR(70) = GPIO_bit(70); /* now toggle between output=low and high-impedance */ for (i = 0; i < 20; i++) { @@ -100,13 +100,8 @@ int board_init (void) /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ - /* arch number of Innokom board */ gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; - - /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; - - /* baud rate */ gd->bd->bi_baudrate = CONFIG_BAUDRATE; return 0; diff --git a/board/innokom/memsetup.S b/board/innokom/memsetup.S index a2bc99d..60f9d50 100644 --- a/board/innokom/memsetup.S +++ b/board/innokom/memsetup.S @@ -237,17 +237,16 @@ mem_init: /* ---------------------------------------------------------------- */ /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DIR field. */ + /* this to power on defaults + DRI field. */ - ldr r4, =0x03ca4fff - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 - ldr r4, =0x03ca4030 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ + ldr r4, [r1, #MDREFR_OFFSET] /* ---------------------------------------------------------------- */ @@ -267,18 +266,16 @@ mem_init: /* Step 4: Initialize SDRAM */ /* ---------------------------------------------------------------- */ - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ + /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_SLFRSH) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index a26f542..692930b 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -65,21 +65,22 @@ void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line = 0xff; + unsigned char pin; /* * Write pci interrupt line register */ if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ return; - if(PCI_FUNC(dev)==0) - { - /* assuming all function 0 are using their INTA# Pin*/ - int_line=PCI_IRQ_VECTOR(dev); - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); + if ((pin == 0) || (pin > 4)) + return; + + int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); #ifdef DEBUG - printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev),dev,int_line,int_line); + printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", + PCI_DEV(dev),dev,int_line,int_line); #endif - } } extern void pci_405gp_init(struct pci_controller *hose); @@ -90,11 +91,34 @@ static struct pci_controller hose = { fixup_irq: pci_pip405_fixup_irq, }; + +static void reloc_pci_cfg_table(struct pci_config_table *table) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + + for (; table && table->vendor; table++) { + addr = (ulong) (table->config_device) + gd->reloc_off; +#ifdef DEBUG + printf ("device \"%d\": 0x%08lx => 0x%08lx\n", + table->device, (ulong) (table->config_device), addr); +#endif + table->config_device = + (void (*)(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *))addr; + table->priv[0]+=gd->reloc_off; + } +} + void pci_init_board(void) { /*we want the ptrs to RAM not flash (ie don't use init list)*/ hose.fixup_irq = pci_pip405_fixup_irq; hose.config_table = pci_pip405_config_table; + reloc_pci_cfg_table(hose.config_table); +#ifdef DEBUG + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); +#endif pci_405gp_init(&hose); } diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 8bab47c..95ad97c 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -128,6 +128,15 @@ const sdram_t sdram_table[] = { 2, /* Address Mode = 2 */ 4, /* size value */ 1}, /* ECC enabled */ + { 0x03, /* Rev A, 128MByte -4 Board */ + 3, /* Case Latenty = 3 */ + 3, /* trp 20ns / 7.5 ns datain[27] */ + 3, /* trcd 20ns /7.5 ns (datain[29]) */ + 6, /* tras 44ns /7.5 ns (datain[30]) */ + 4, /* tcpt 44 - 20ns = 24ns */ + 3, /* Address Mode = 3 */ + 5, /* size value */ + 1}, /* ECC enabled */ { 0xff, /* terminator */ 0xff, 0xff, @@ -616,9 +625,15 @@ void print_mip405_rev (void) int last_stage_init (void) { + /* write correct LED configuration */ if (miiphy_write (0x1, 0x14, 0x2402) != 0) { printf ("Error writing to the PHY\n"); } + /* since LED/CFG2 is not connected on the -2, + * write to correct capability information */ + if (miiphy_write (0x1, 0x4, 0x01E1) != 0) { + printf ("Error writing to the PHY\n"); + } print_mip405_rev (); show_stdio_dev (); check_env (); diff --git a/board/svm_sc8xx/ppcboot.lds b/board/svm_sc8xx/ppcboot.lds deleted file mode 100644 index 5f5e2e4..0000000 --- a/board/svm_sc8xx/ppcboot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/ppcstring.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/svm_sc8xx/ppcboot.lds.debug b/board/svm_sc8xx/ppcboot.lds.debug deleted file mode 100644 index f230a6b..0000000 --- a/board/svm_sc8xx/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile new file mode 100644 index 0000000..d4314d7 --- /dev/null +++ b/board/wepep250/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := wepep250.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk new file mode 100644 index 0000000..792f0ee --- /dev/null +++ b/board/wepep250/config.mk @@ -0,0 +1,11 @@ +# +# This is config used for compilation of WEP EP250 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xa1fe0000 +#TEXT_BASE = 0xa1001000
\ No newline at end of file diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c new file mode 100644 index 0000000..319dddc --- /dev/null +++ b/board/wepep250/flash.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + */ + +#include <common.h> +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( WEP_FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( WEP_FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + +#if ( CFG_MAX_FLASH_BANKS != 1 ) +# error "WEP platform has only one flash bank!" +#endif + + +ulong flash_init (void) +{ + int i; + FLASH_BUS address = WEP_FLASH_BASE; + + flash_info[0].size = WEP_FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; +#ifdef WEP_FLASH_UNLOCK + /* Some devices are hw locked after start. */ + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); + flash_ready (0); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); +#endif + address += WEP_FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _armboot_end_data - _armboot_start, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return WEP_FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h new file mode 100644 index 0000000..f622590 --- /dev/null +++ b/board/wepep250/intel.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka <marcel@telka.sk>, 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include <common.h> + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ + diff --git a/board/wepep250/memsetup.S b/board/wepep250/memsetup.S new file mode 100644 index 0000000..8a5d42f --- /dev/null +++ b/board/wepep250/memsetup.S @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2001, 2002 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002. + * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003. + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + * Documentation: + * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors + * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", + * Revision 1.0, February 2002 + * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", + * Revision 1.0, February 2002 + * +*/ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +.globl memsetup +memsetup: + + mov r10, lr + +/* setup memory - see 6.12 in [1] + * Step 1 - wait 200 us + */ + mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r0, r0, #1 + bne 1b +/* TODO: complete step 1 for Synchronous Static memory*/ + + ldr r0, =0x48000000 /* MC_BASE */ + + + +/* step 1.a - setup MSCx + */ + ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ + str r1, [r0, #0x8] /* MSC0_OFFSET */ + +/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI + * see AUTO REFRESH chapter in section D. in [2] and in [3] + * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 + * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 + * TODO: complete for Synchronous Static memory + */ + ldr r1, [r0, #4] /* MDREFR_OFFSET */ + ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ + bic r1, r1, r2 +#if defined( WEP_SDRAM_K4S281633 ) + orr r1, r1, #48 /* MDREFR_DRI(48) */ +#elif defined( WEP_SDRAM_K4S561633 ) + orr r1, r1, #24 /* MDREFR_DRI(24) */ +#else +#error SDRAM chip is not defined +#endif + + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 2 - only for Synchronous Static memory (TODO) + * + * Step 3 - same as step 4 + * + * Step 4 + * + * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 + */ + orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ + bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.b - clear MDREFR:SLFRSH */ + bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.c - set MDREFR:E1PIN */ + orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.d - automatically done + * + * Steps 4.e and 4.f - configure SDRAM + */ +#if defined( WEP_SDRAM_K4S281633 ) + ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ +#elif defined( WEP_SDRAM_K4S561633 ) + ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ +#else +#error SDRAM chip is not defined +#endif + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 5 - wait at least 200 us for SDRAM + * see section B. in [2] + */ + mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r2, r2, #1 + bne 1b + +/* Step 6 - after reset dcache is disabled, so automatically done + * + * Step 7 - eight refresh cycles + */ + mov r2, #0xA0000000 + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + +/* Step 8 - we don't need dcache now + * + * Step 9 - enable SDRAM partition 0 + */ + orr r1, r1, #1 /* MDCNFG_DE0 */ + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 10 - write MDMRS */ + mov r1, #0 + str r1, [r0, #0x40] /* MDMRS_OFFSET */ + +/* Step 11 - optional (TODO) */ + + mov pc,r10 + diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds new file mode 100644 index 0000000..280fc48 --- /dev/null +++ b/board/wepep250/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/xscale/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + armboot_end_data = .; + + . = ALIGN(4); + bss_start = .; + .bss : { *(.bss) } + bss_end = .; + + armboot_end = .; +} diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c new file mode 100644 index 0000000..ebf75d7 --- /dev/null +++ b/board/wepep250/wepep250.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + */ + +#include <common.h> +#include <asm/arch/pxa-regs.h> + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = 288; + gd->bd->bi_boot_params = 0xa0000000; +/* + * Setup GPIO stuff to get serial working + */ +#if defined( CONFIG_FFUART ) + GPDR1 = 0x80; + GAFR1_L = 0x8010; +#elif defined( CONFIG_BTUART ) + GPDR1 = 0x800; + GAFR1_L = 0x900000; +#endif + PSSR = 0x20; + +/* + * Following code is just bug workaround, remove it if not neccessary + */ + + /* cpu/xscale/cpu.c do not set armboot_real_end that is used for + malloc pool.*/ + if( _armboot_real_end == 0xbadc0de ){ + _armboot_real_end = _armboot_end; + } + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = WEP_SDRAM_1; + gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = WEP_SDRAM_2; + gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 2 ) + gd->bd->bi_dram[2].start = WEP_SDRAM_3; + gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 3 ) + gd->bd->bi_dram[3].start = WEP_SDRAM_4; + gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; +#endif + + return 0; +} + |