diff options
Diffstat (limited to 'board')
55 files changed, 2833 insertions, 1894 deletions
diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c index afe124a..267c476 100644 --- a/board/AtmarkTechno/suzaku/suzaku.c +++ b/board/AtmarkTechno/suzaku/suzaku.c @@ -24,7 +24,7 @@ /* This is a board specific file. It's OK to include board specific * header files */ -#include <asm/suzaku.h> +#include <config.h> void do_reset(void) { diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds index 00a8ef7..cb90854 100644 --- a/board/AtmarkTechno/suzaku/u-boot.lds +++ b/board/AtmarkTechno/suzaku/u-boot.lds @@ -61,6 +61,7 @@ SECTIONS { __bss_start = .; *(.bss) - __bss_start = .; + __bss_end = .; } + __end = . ; } diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index 183f694..abcbf3e 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -23,25 +23,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS = $(BOARD).o cpr.o memory.o +COBJS = $(BOARD).o cpr.o memory.o SOBJS = -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak .depend *~ ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index c8aaad2..baf598c 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -26,10 +26,7 @@ extern void board_pll_init_f(void); -/* Some specific Acadia Defines */ -#define CPLD_BASE 0x80000000 - -void liveoak_gpio_init(void) +static void acadia_gpio_init(void) { /* * GPIO0 setup (select GPIO or alternate function) @@ -54,62 +51,16 @@ void liveoak_gpio_init(void) out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ } -#if 0 /* test-only: not called at all??? */ -void ext_bus_cntlr_init(void) -{ -#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, EBC_PB4AP); - mtebc(pb4cr, EBC_PB4CR); -#endif -} -#endif - int board_early_init_f(void) { unsigned int reg; -#if 0 /* test-only */ - /* - * If CRAM memory and SPI/NAND boot, and if the CRAM memory is - * already initialized by the pre-loader then we can't reinitialize - * CPR registers, GPIO registers and EBC registers as this will - * have the effect of un-initializing CRAM. - */ - spr_reg = (volatile unsigned long) mfspr(SPRG7); - if (spr_reg != LOAK_CRAM) { /* != CRAM */ + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) board_pll_init_f(); - liveoak_gpio_init(); - ext_bus_cntlr_init(); - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); - - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); - } -#else - board_pll_init_f(); - liveoak_gpio_init(); -/* ext_bus_cntlr_init(); */ -#endif - -#if 0 /* test-only (orig) */ - /* - * If we boot from NAND Flash, we are running in - * RAM, so disable the EBC_CS0 so that it goes back - * to the NOR Flash. It will be enabled later - * for the NAND Flash on EBC_CS1 - */ - mfsdr(sdrultra0, reg); - mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); -#endif -#if 0 /* test-only */ - /* configure for NAND */ - mfsdr(sdrultra0, reg); - reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS; - mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); -#endif + acadia_gpio_init(); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); @@ -128,7 +79,7 @@ int board_early_init_f(void) int misc_init_f(void) { /* Set EPLD to take PHY out of reset */ - out8(CPLD_BASE + 0x05, 0x00); + out8(CFG_CPLD_BASE + 0x05, 0x00); udelay(100000); return 0; diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index ce21374..c8566ec 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,21 +21,10 @@ # MA 02111-1307 USA # -sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp - ifndef TEXT_BASE TEXT_BASE = 0xFFFC0000 endif -ifeq ($(CONFIG_NAND_U_BOOT),y) -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds -endif - -ifeq ($(CONFIG_SPI_U_BOOT),y) -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds -PAD_TO = 0x00840000 -endif - ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c index 23b9e12..9dcce35 100644 --- a/board/amcc/acadia/cpr.c +++ b/board/amcc/acadia/cpr.c @@ -76,19 +76,19 @@ void board_pll_init_f(void) * | UART0 | 28.57 | 7 (0x07)| * | UART1 | 28.57 | 7 (0x07)| * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| + * | ADC | 4 | 50 (0x32)| * | PWM | 28.57 | 7 (0x07)| * | EMAC | 4 | 50 (0x32)| * ----------------------------------- */ /* Initialize PLL */ - mtcpr(cprpllc, 0x20000238); - mtcpr(cprplld, 0x03010400); + mtcpr(cprpllc, 0x20000238); + mtcpr(cprplld, 0x03010400); mtcpr(cprprimad, 0x03050a0a); - mtcpr(cprperc0, 0x00000000); - mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0x07323200); + mtcpr(cprperc0, 0x00000000); + mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0x07323200); mtcpr(cprclkupd, 0x40000000); } @@ -117,11 +117,11 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033C); - mtcpr(cprplld, 0x0a010000); + mtcpr(cprpllc, 0x0000033C); + mtcpr(cprplld, 0x0a010000); mtcpr(cprprimad, 0x02040808); - mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xA6A60300); + mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xA6A60300); mtcpr(cprclkupd, 0x40000000); } @@ -143,20 +143,20 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x000003BC); - mtcpr(cprplld, 0x06060600); + mtcpr(cprpllc, 0x000003BC); + mtcpr(cprplld, 0x06060600); mtcpr(cprprimad, 0x02020004); - mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xC8C81600); + mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xC8C81600); mtcpr(cprclkupd, 0x40000000); } -#endif /* CPU_<speed>_405EZ */ +#endif /* CPU_<speed>_405EZ */ #if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) /* * Get timebase clock frequency */ -unsigned long get_tbclk (void) +unsigned long get_tbclk(void) { unsigned long cpr_plld; unsigned long cpr_primad; @@ -192,4 +192,4 @@ unsigned long get_tbclk (void) return (freqProcessor); } -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ +#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c deleted file mode 100644 index 0626aba..0000000 --- a/board/amcc/acadia/flash.c +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { - {0xffc00001}, /* 0:boot from big flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf("MIXC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) { - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV - -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - -#if 0 /* TODO: remove ifdef when Flash responds correctly */ - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#endif /* TODO: remove ifdef when Flash responds correctly */ - - /* - * TODO: Start - * uncomment block above when Flash responds correctly. - * also remove the lines below: - */ - info->flash_id = FLASH_MAN_AMD; - DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n"); - /* TODO: End */ - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - -#if 0 /* TODO: remove ifdef when Flash responds correctly */ - switch (value) { - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } -#endif /* TODO: remove ifdef when Flash responds correctly */ - - /* - * TODO: Start - * uncomment block above when Flash responds correctly. - * also remove the lines below: - */ - DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; /* => 4 MB */ - /* TODO: End */ - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - else { - if (info->flash_id & FLASH_BTYPE){ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address,(A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -/* - * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command - * never was accepted (i.e. didn't start) - why???? - */ -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last, counter = 0; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - DEBUGF("DQ7_2: start = 0x%08lx\n", start); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now); - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - udelay(1000000); /* 1 sec */ - putc('.'); - counter++; - if (counter > 5) { - return -1; - } - DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last); - } - return 0; -} - -static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value) -{ - int fw_size; - - fw_size = sizeof(value); - switch (fw_size) - { - case 1: - out8((ulong)(sector + addr), value); - break; - case 2: - out16((ulong)(sector + (addr << 1)), value); - break; - default: - printf("flash_erase: error incorrect chip programing size.\n"); - } - return; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect, count = 0; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first, count = 0; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - /* - * TODO: fix code - */ - wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); - wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030); - udelay(2000000); /* 2 sec */ - wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); - -#if 0 - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ -#endif - } - l_sect = sect; - printf(".."); - printf(".."); - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - count++; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - - if (count > 0) { - return 0; - } else { - return 1; - } -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CFG_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - index = 0; - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index a1b0155..5375d36 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -21,529 +21,80 @@ * MA 02111-1307 USA */ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + #include <common.h> #include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> -#define CRAM_BANK0_BASE 0x0 -#define CRAM_DIDR 0x00100000 -#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43 -#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343 -#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */ -#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */ -#define CRAM_DEVID_NOT_SUPPORTED 0x00000000 - -#define PSRAM_PASS 0x50415353 /* "PASS" */ -#define PSRAM_FAIL 0x4641494C /* "FAIL" */ - -static u32 is_cram_inited(void); -static u32 is_cram(void); -static long int cram_init(u32); -static void cram_bcr_write(u32); -void udelay (unsigned long); - +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ void sdram_init(void) { - volatile unsigned long spr_reg; - - /* - * If CRAM not initialized or CRAM looks initialized because this - * is after a warm reboot then set SPRG7 to indicate CRAM needs - * initialization. Note that CRAM is initialized by the SPI and - * NAND preloader. - */ - spr_reg = (volatile unsigned long) mfspr(SPRG6); - if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) { - mtspr(SPRG7, LOAK_NONE); /* "NONE" */ - } -#if 1 - /* - * When running the NAND SPL, the normal EBC configuration is not - * done, so We need to enable EPLD access on EBC_CS_2 and the memory - * on EBC_CS_3 - */ - - /* Enable CPLD - Needed for PSRAM Access */ - - - /* Init SDRAM by setting EBC Bank 3 for PSRAM */ - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); - - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); - - /* pre-boot loader code: we are in OCM */ - mtspr(SPRG6, LOAK_SPL); /* "SPL " */ - mtspr(SPRG7, LOAK_OCM); /* "OCM " */ -#endif return; } static void cram_bcr_write(u32 wr_val) { - u32 tmp_reg; - u32 val; - volatile u32 gpio_reg; - - /* # Program CRAM write */ - - /* - * set CRAM_CRE = 0x1 - * set wr_val = wr_val << 2 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - wr_val = wr_val << 2; - /* wr_val = 0x1c048; */ + wr_val <<= 2; - /* - * # stop PLL clock before programming CRAM - * set EPLD0_MUX_CTL.OESPR3 = 1 - * delay 2 - */ + /* set CRAM_CRE to 1 */ + gpio_write_bit(CFG_GPIO_CRAM_CRE, 1); - /* - * # CS1 - * read 0x00200000 - * #shift 2 bit left before write - * set val = wr_val + 0x00200000 - * write dmem val 0 - * read 0x00200000 val - * print val/8x - */ - tmp_reg = in32(0x00200000); - val = wr_val + 0x00200000; - /* val = 0x0021c048; */ - out32(val, 0x0000); - udelay(100000); - val = in32(0x00200000); + /* Write BCR to CRAM on CS1 */ + out32(wr_val + 0x00200000, 0); + debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); - debug("CRAM VAL: %x for CS1 ", val); + /* Write BCR to CRAM on CS2 */ + out32(wr_val + 0x02200000, 0); + debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); - /* - * # CS2 - * read 0x02200000 - * #shift 2 bit left before write - * set val = wr_val + 0x02200000 - * write dmem val 0 - * read 0x02200000 val - * print val/8x - */ - tmp_reg = in32(0x02200000); - val = wr_val + 0x02200000; - /* val = 0x0221c048; */ - out32(val, 0x0000); - udelay(100000); - val = in32(0x02200000); + sync(); + eieio(); - debug("CRAM VAL: %x for CS2 ", val); + /* set CRAM_CRE back to 0 (normal operation) */ + gpio_write_bit(CFG_GPIO_CRAM_CRE, 0); - /* - * # Start PLL clock before programming CRAM - * set EPLD0_MUX_CTL.OESPR3 = 0 - */ - - /* - * set CRAMCR = 0x1 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - - /* - * # read CRAM config BCR ( bit19:18 = 10b ) - * #read 0x00200000 - * # 1001_1001_0001_1111 ( 991f ) => - * #10_0110_0100_0111_1100 => 2647c => 0022647c - * #0011_0010_0011_1110 (323e) - * # - */ - - /* - * set EPLD0_MUX_CTL.CRAMCR = 0x0 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF); return; } -static u32 is_cram_inited() -{ - volatile unsigned long spr_reg; - - /* - * If CRAM is initialized already, then don't reinitialize it again. - * In the case of NAND boot and SPI boot, CRAM will already be - * initialized by the pre-loader - */ - spr_reg = (volatile unsigned long) mfspr(SPRG7); - if (spr_reg == LOAK_CRAM) { - return 1; - } else { - return 0; - } -} - -/****** - * return 0 if not CRAM - * return 1 if CRAM and it's already inited by preloader - * else return cram_id (CRAM Device Identification Register) - ******/ -static u32 is_cram(void) -{ - u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L; - volatile u32 gpio_reg; - volatile u32 cram_id = 0; - - if (is_cram_inited() == 1) { - /* this is CRAM and it is already inited (by preloader) */ - cram_id = 1; - } else { - /* - * # CRAM CLOCK - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 0 - * set GPIO0_OR.G8 = 0 - */ - gpio_reg = in32(GPIO0_TCR); - gpio_TCR = gpio_reg; - out32(GPIO0_TCR, gpio_reg | 0x00800000); - gpio_reg = in32(GPIO0_OSRL); - gpio_OSRL = gpio_reg; - out32(GPIO0_OSRL, gpio_reg & 0xffffbfff); - gpio_reg = in32(GPIO0_OR); - gpio_OR = gpio_reg; - out32(GPIO0_OR, gpio_reg & 0xff7fffff); - - /* - * # CRAM Addreaa Valid - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 0 - * set GPIO0_OR.G10 = 0 - */ - gpio_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, gpio_reg | 0x00200000); - gpio_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, gpio_reg & 0xfffffbff); - gpio_reg = in32(GPIO0_OR); - out32(GPIO0_OR, gpio_reg & 0xffdfffff); - - /* - * # config input (EBC_WAIT) - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - gpio_reg = in32(GPIO0_ISR1L); - gpio_ISR1L = gpio_reg; - out32(GPIO0_ISR1L, gpio_reg | 0x00001000); - gpio_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, gpio_reg & 0xffbfffff); - - /* - * Enable CRE to read Registers - * set GPIO0_TCR.21 = 1 - * set GPIO1_OR.21 = 1 - */ - gpio_reg = in32(GPIO1_TCR); - out32(GPIO1_TCR, gpio_reg | 0x00000400); - - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - - /* Read Version ID */ - cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR); - udelay(100000); - - asm volatile(" sync"); - asm volatile(" eieio"); - - debug("Cram ID: %X ", cram_id); - - switch (cram_id) { - case MICRON_MT45W8MW16BGX_CRAM_ID: - case MICRON_MT45W8MW16BGX_CRAM_ID2: - /* supported CRAM vendor/part */ - break; - case CRAM_DEVID_NOT_SUPPORTED: - default: - /* check for DIDR Vendor ID of Micron */ - if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) == - MICRON_DIDR_VENDOR_ID) - { - /* supported CRAM vendor */ - break; - } - /* this is not CRAM or not supported CRAM vendor/part */ - cram_id = 0; - /* - * reset the GPIO registers to the values that were - * there before this routine - */ - out32(GPIO0_TCR, gpio_TCR); - out32(GPIO0_OSRL, gpio_OSRL); - out32(GPIO0_OR, gpio_OR); - out32(GPIO0_ISR1L, gpio_ISR1L); - break; - } - } - - return cram_id; -} - -static long int cram_init(u32 already_inited) -{ - volatile u32 tmp_reg; - u32 cram_wr_val; - - if (already_inited == 0) return 0; - - /* - * If CRAM is initialized already, then don't reinitialize it again. - * In the case of NAND boot and SPI boot, CRAM will already be - * initialized by the pre-loader - */ - if (already_inited != 1) { - /* - * #o CRAM Card - * # - CRAMCRE @reg16 = 1; for CRAM to use - * # - CRAMCRE @reg16 = 0; for CRAM to program - * - * # enable CRAM SEL, move from setEPLD.cmd - * set EPLD0_MUX_CTL.OECRAM = 0 - * set EPLD0_MUX_CTL.CRAMCR = 1 - * set EPLD0_ETHRSTBOOT.SLCRAM = 0 - * #end - */ - - /* - * #1. EBC need to program READY, CLK, ADV for ASync mode - * # config output - */ - - /* - * # CRAM CLOCK - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 0 - * set GPIO0_OR.G8 = 0 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00800000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg & 0xffffbfff); - tmp_reg = in32(GPIO0_OR); - out32(GPIO0_OR, tmp_reg & 0xff7fffff); - - /* - * # CRAM Addreaa Valid - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 0 - * set GPIO0_OR.G10 = 0 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00200000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg & 0xfffffbff); - tmp_reg = in32(GPIO0_OR); - out32(GPIO0_OR, tmp_reg & 0xffdfffff); - - /* - * # config input (EBC_WAIT) - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - tmp_reg = in32(GPIO0_ISR1L); - out32(GPIO0_ISR1L, tmp_reg | 0x00001000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg & 0xffbfffff); - - /* - * # config CS4 from GPIO - * set GPIO0_TCR.G0 = 1 - * set GPIO0_OSRL.G0 = 1 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x80000000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x40000000); - - /* - * #2. EBC in Async mode - * # set EBC0_PB1AP = 0x078f0ec0 - * set EBC0_PB1AP = 0x078f1ec0 - * set EBC0_PB2AP = 0x078f1ec0 - */ - mtebc(pb1ap, 0x078F1EC0); - mtebc(pb2ap, 0x078F1EC0); - - /* - * #set EBC0_PB1CR = 0x000bc000 - * #enable CS2 for CRAM - * set EBC0_PB2CR = 0x020bc000 - */ - mtebc(pb1cr, 0x000BC000); - mtebc(pb2cr, 0x020BC000); - - /* - * #3. set CRAM in Sync mode - * #exec cm_bcr_write.cmd { 0x701f } - * #3. set CRAM in Sync mode (full drv strength) - * exec cm_bcr_write.cmd { 0x701F } - */ - cram_wr_val = 0x7012; /* CRAM burst setting */ - cram_bcr_write(cram_wr_val); - - /* - * #4. EBC in Sync mode - * #set EBC0_PB1AP = 0x9f800fc0 - * #set EBC0_PB1AP = 0x900001c0 - * set EBC0_PB2AP = 0x9C0201c0 - * set EBC0_PB2AP = 0x9C0201c0 - */ - mtebc(pb1ap, 0x9C0201C0); - mtebc(pb2ap, 0x9C0201C0); - - /* - * #5. EBC need to program READY, CLK, ADV for Sync mode - * # config output - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 1 - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 1 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00800000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x00004000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00200000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x00000400); - - /* - * # config input - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - tmp_reg = in32(GPIO0_ISR1L); - out32(GPIO0_ISR1L, tmp_reg | 0x00001000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg & 0xffbfffff); - - /* - * # config EBC to use RDY - * set SDR0_ULTRA0.EBCREN = 1 - */ - mfsdr(sdrultra0, tmp_reg); - mtsdr(sdrultra0, tmp_reg | 0x04000000); - - /* - * set EPLD0_MUX_CTL.OESPR3 = 0 - */ - mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */ - } /* if (already_inited != 1) */ - - return (64 * 1024 * 1024); -} - -/****** - * return 0 if not PSRAM - * return 1 if is PSRAM - ******/ -static int is_psram(u32 addr) -{ - u32 test_pattern = 0xdeadbeef; - volatile u32 readback; - - if (addr == CFG_SDRAM_BASE) { - /* This is to temp enable OE for PSRAM */ - out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); - udelay(10000); - } - - out32(addr, test_pattern); - asm volatile(" sync"); - asm volatile(" eieio"); - - readback = (volatile u32) in32(addr); - asm volatile(" sync"); - asm volatile(" eieio"); - if (readback == test_pattern) { - return 1; - } else { - return 0; - } -} - -static long int psram_init(void) +long int initdram(int board_type) { - u32 readback; - long psramsize = 0; - int i; - - /* This is to temp enable OE for PSRAM */ - out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); - udelay(10000); + u32 val; - /* - * PSRAM bank 1: read then write to address 0x00000000 - */ - for (i = 0; i < 100; i++) { - if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) { - readback = PSRAM_PASS; - } else { - readback = PSRAM_FAIL; - break; - } - } - if (readback == PSRAM_PASS) { - debug("psram_init(bank0): pass\n"); - psramsize = (16 * 1024 * 1024); - } else { - debug("psram_init(bank0): fail\n"); - return 0; - } + /* 1. EBC need to program READY, CLK, ADV for ASync mode */ + gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); -#if 0 - /* - * PSRAM bank 1: read then write to address 0x01000000 - */ - for (i = 0; i < 100; i++) { - if (is_psram((1 << 24) + (i*256)) == 1) { - readback = PSRAM_PASS; - } else { - readback = PSRAM_FAIL; - break; - } - } - if (readback == PSRAM_PASS) { - debug("psram_init(bank1): pass\n"); - psramsize = psramsize + (16 * 1024 * 1024); - } -#endif + /* 2. EBC in Async mode */ + mtebc(pb1ap, 0x078F1EC0); + mtebc(pb2ap, 0x078F1EC0); + mtebc(pb1cr, 0x000BC000); + mtebc(pb2cr, 0x020BC000); - mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */ + /* 3. Set CRAM in Sync mode */ + cram_bcr_write(0x7012); /* CRAM burst setting */ - return psramsize; -} + /* 4. EBC in Sync mode */ + mtebc(pb1ap, 0x9C0201C0); + mtebc(pb2ap, 0x9C0201C0); -long int initdram(int board_type) -{ - long int sram_size; - u32 cram_inited; + /* Set GPIO pins back to alternate function */ + gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - /* Determine Attached Memory Expansion Card*/ - cram_inited = is_cram(); - if (cram_inited != 0) { /* CRAM */ - debug("CRAM Expansion Card attached\n"); - sram_size = cram_init(cram_inited); - } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */ - debug("PSRAM Expansion Card attached\n"); - sram_size = psram_init(); - } else { /* no SRAM */ - debug("No Memory Card Attached!!\n"); - sram_size = 0; - } + /* Config EBC to use RDY */ + mfsdr(sdrultra0, val); + mtsdr(sdrultra0, val | 0x04000000); - return sram_size; + return (CFG_MBYTES_RAM << 20); } int testdram(void) diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds index be03092..b08c999 100644 --- a/board/amcc/acadia/u-boot.lds +++ b/board/amcc/acadia/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index c93ba6e..b5bb145 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/gpio.h> #include <spd_sdram.h> #include <ppc440.h> #include "bamboo.h" diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 1ce6366..4474862 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -264,19 +264,9 @@ #define TRUE 1 #define FALSE 0 -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - #define GPIO0 0 #define GPIO1 1 - /*#define MAX_SELECTION_NB CORE_NB */ #define MAX_CORE_SELECT_NB 22 diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index 684f6a5..439be4f 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -27,6 +27,9 @@ #include <i2c.h> #include <asm/byteorder.h> +#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */ +#define DEBUG + static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; @@ -49,55 +52,28 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else chip = IIC0_ALT_BOOTPROM_ADDR; - do { - printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); - nbytes = readline (" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0)) - nbytes=0; - - strcpy(sysClock, console_buffer); - - } while (nbytes == 0); + /* on Katmai SysClk is always 33MHz */ + strcpy(sysClock, "33"); do { - if (strcmp(sysClock, "66") == 0) { - printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); - } else { #ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); #else - printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); #endif - } nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "533") != 0) -#ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) -#endif - ) { - nbytes = 0; - } - } else { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "500") != 0) & - (strcmp(console_buffer, "533") != 0) + if ((strcmp(console_buffer, "400") != 0) && + (strcmp(console_buffer, "500") != 0) && + (strcmp(console_buffer, "533") != 0) #ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) + && (strcmp(console_buffer, "667") != 0) #endif - ) { - nbytes = 0; - } + ) { + nbytes = 0; } strcpy(cpuClock, console_buffer); @@ -124,13 +100,13 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; if (strcmp(cpuClock, "400") == 0) { - if ((strcmp(console_buffer, "100") != 0) & + if ((strcmp(console_buffer, "100") != 0) && (strcmp(console_buffer, "133") != 0)) nbytes = 0; } #ifdef CONFIG_STRESS if (strcmp(cpuClock, "667") == 0) { - if ((strcmp(console_buffer, "133") != 0) & + if ((strcmp(console_buffer, "133") != 0) && (strcmp(console_buffer, "166") != 0)) nbytes = 0; } @@ -147,9 +123,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strcmp(console_buffer, "quit") == 0) return 0; - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0) & - (strcmp(console_buffer, "100") != 0) & + if ((strcmp(console_buffer, "33") != 0) && + (strcmp(console_buffer, "66") != 0) && + (strcmp(console_buffer, "100") != 0) && (strcmp(console_buffer, "133") != 0)) { nbytes = 0; } @@ -176,11 +152,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } while (nbytes == 0); if (strcmp(sysClock, "33") == 0) { - if ((strcmp(cpuClock, "400") == 0) & + if ((strcmp(cpuClock, "400") == 0) && (strcmp(plbClock, "100") == 0)) data = 0x8678c206; - if ((strcmp(cpuClock, "400") == 0) & + if ((strcmp(cpuClock, "400") == 0) && (strcmp(plbClock, "133") == 0)) data = 0x8678c2c6; @@ -189,42 +165,16 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if ((strcmp(cpuClock, "533") == 0)) data = 0x87790252; - #ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & + if ((strcmp(cpuClock, "667") == 0) && (strcmp(plbClock, "133") == 0)) data = 0x87794256; - if ((strcmp(cpuClock, "667") == 0) & + if ((strcmp(cpuClock, "667") == 0) && (strcmp(plbClock, "166") == 0)) data = 0x87794206; - -#endif - } - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "100") == 0)) - data = 0x84706206; - - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x847062c6; - - if ((strcmp(cpuClock, "533") == 0)) - data = 0x85708206; - -#ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x8570a256; - - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "166") == 0)) - data = 0x8570a206; - #endif } - #ifdef DEBUG printf(" pin strap0 to write in i2c = %x\n", data); #endif /* DEBUG */ @@ -233,19 +183,20 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("Error writing strap0 in %s\n", argv[2]); if (strcmp(pcixClock, "33") == 0) - data = 0x00000701; + data = 0x000007E1; if (strcmp(pcixClock, "66") == 0) - data = 0x00000601; + data = 0x000006E1; if (strcmp(pcixClock, "100") == 0) - data = 0x00000501; + data = 0x000005E1; if (strcmp(pcixClock, "133") == 0) - data = 0x00000401; + data = 0x000004E1; if (strcmp(plbClock, "166") == 0) - data |= 0x05950000; +/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */ + data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */ else data |= 0x05A50000; diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 6b024ee..5202ae6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -103,7 +103,7 @@ tlbtabB: tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index fbf1a98..286bdc1 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <i2c.h> #include <asm-ppc/io.h> +#include <asm-ppc/gpio.h> #include "../cpu/ppc4xx/440spe_pcie.h" diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index daaffe0..930fa71 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -363,8 +363,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = *(u8 *)(CFG_CPLD + 0); - val = *(u8 *)(CFG_CPLD + 5) & 0x01; + rev = *(u8 *)(CFG_BCSR_BASE + 0); + val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile index 155d46a..8a15713 100644 --- a/board/atmel/atstk1000/Makefile +++ b/board/atmel/atstk1000/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS := $(BOARD).o flash.o eth.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 4d737d2..6618963 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -23,6 +23,8 @@ #include <asm/io.h> #include <asm/sdram.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix2.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,9 +42,27 @@ static const struct sdram_info sdram = { .txsr = 5, }; -void board_init_memories(void) +int board_early_init_f(void) { - gd->sdram_size = sdram_init(&sdram); + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(SFR4, 1 << 1); + + gpio_enable_ebi(); + gpio_enable_usart1(); +#if defined(CONFIG_MACB) + gpio_enable_macb0(); + gpio_enable_macb1(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + return 0; +} + +long int initdram(int board_type) +{ + return sdram_init(&sdram); } void board_init_info(void) diff --git a/board/atmel/atstk1000/eth.c b/board/atmel/atstk1000/eth.c new file mode 100644 index 0000000..3a7916e --- /dev/null +++ b/board/atmel/atstk1000/eth.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Ethernet initialization for the ATSTK1000 starterkit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/arch/memory-map.h> + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET) +void atstk1000_eth_initialize(bd_t *bi) +{ + int id = 0; + + macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]); +} +#endif diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 3aebf66..958f4dc 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init(void) gd->bd->bi_flashstart = CFG_FLASH_BASE; gd->bd->bi_flashsize = CFG_FLASH_SIZE; - gd->bd->bi_flashoffset = __edata_lma - _text; + gd->bd->bi_flashoffset = _edata - _text; flash_info[0].size = CFG_FLASH_SIZE; flash_info[0].sector_count = 135; diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds index ef89ea4..34e347a 100644 --- a/board/atmel/atstk1000/u-boot.lds +++ b/board/atmel/atstk1000/u-boot.lds @@ -40,35 +40,38 @@ SECTIONS } . = ALIGN(32); __flashprog_end = .; + _etext = .; - . = ALIGN(8); .rodata : { *(.rodata) *(.rodata.*) } - _etext = .; - __data_lma = ALIGN(8); - . = 0x24000000; + . = ALIGN(8); _data = .; - .data : AT(__data_lma) { + .data : { *(.data) *(.data.*) } . = ALIGN(4); __u_boot_cmd_start = .; - __u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data); - .u_boot_cmd : AT(__u_boot_cmd_lma) { + .u_boot_cmd : { KEEP(*(.u_boot_cmd)) } __u_boot_cmd_end = .; + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + . = ALIGN(8); _edata = .; - __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start); - .bss : AT(__edata_lma) { + .bss : { *(.bss) *(.bss.*) } diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 4fe7d78..e55c1a7 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -1,7 +1,7 @@ # # U-boot - Makefile # -# Copyright (c) 2007 Analog Device Inc. +# Copyright (c) 2005-2007 Analog Device Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index feaeb00..1dd4a3f 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -1,7 +1,7 @@ /* * U-boot - ezkit533.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index e211918..bd9e859 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -1,7 +1,7 @@ /* * U-boot - flash-defines.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __FLASHDEFINES_H__ @@ -60,7 +60,7 @@ void reset_flash(void); int erase_flash(void); int erase_block_flash(int, unsigned long); void unlock_flash(long lOffset); -int write_data(long lStart, long lCount, long lStride, int *pnData); +int write_data(long lStart, long lCount, uchar *pnData); int FillData(long lStart, long lCount, long lStride, int *pnData); int read_data(long lStart, long lCount, long lStride, int *pnData); int read_flash(long nOffset, int *pnValue); diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index 067a260..299cdba 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -1,7 +1,7 @@ /* * U-boot - flash.c Flash driver for PSD4256GV * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. * * (C) Copyright 2000-2004 @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <asm/io.h> @@ -178,63 +178,66 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { int ret; - - ret = write_data(addr, cnt, 1, (int *)src); + int d; + if (addr % 2) { + read_flash(addr - 1 - CFG_FLASH_BASE, &d); + d = (int)((d & 0x00FF) | (*src++ << 8)); + ret = write_data(addr - 1, 2, (uchar *) & d); + if (ret == FLASH_FAIL) + return ERR_NOT_ERASED; + ret = write_data(addr + 1, cnt - 1, src); + } else + ret = write_data(addr, cnt, src); if (ret == FLASH_FAIL) return ERR_NOT_ERASED; return FLASH_SUCCESS; } -int write_data(long lStart, long lCount, long lStride, int *pnData) +int write_data(long lStart, long lCount, uchar * pnData) { long i = 0; - int j = 0; unsigned long ulOffset = lStart - CFG_FLASH_BASE; int d; - int iShift = 0; - int iNumWords = 2; - int nLeftover = lCount % 4; int nSector = 0; + int flag = 0; - for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { - for (iShift = 0, j = 0; (j < iNumWords); - j++, ulOffset += (lStride * 2)) { - if ((ulOffset >= INVALIDLOCNSTART) - && (ulOffset < INVALIDLOCNEND)) { - printf - ("Invalid locations, Try writing to another location \n"); - return FLASH_FAIL; - } - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - iShift += 16; - } + if (lCount % 2) { + flag = 1; + lCount = lCount - 1; } - if (nLeftover > 0) { - if ((ulOffset >= INVALIDLOCNSTART) - && (ulOffset < INVALIDLOCNEND)) + + for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) { + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &d); + if (d != 0xffff) { + printf + ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ulOffset); return FLASH_FAIL; + } + unlock_flash(ulOffset); + d = (int)(pnData[i] | pnData[i + 1] << 8); + write_flash(ulOffset, d); + if (poll_toggle_bit(ulOffset) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + if ((i > 0) && (!(i % AFP_SectorSize2))) + printf("."); + } + if (flag) { get_sector_number(ulOffset, &nSector); read_flash(ulOffset, &d); if (d != 0xffff) { printf - ("Flash already programmed. Please erase to reprogram \n"); - printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d); + ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ulOffset); return FLASH_FAIL; } unlock_flash(ulOffset); - if (write_flash(ulOffset, pnData[i]) < 0) { + d = (int)(pnData[i] | (d & 0xFF00)); + write_flash(ulOffset, d); + if (poll_toggle_bit(ulOffset) < 0) { printf("Error programming the flash \n"); return FLASH_FAIL; } diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h index 9776516..cc654b8 100644 --- a/board/bf533-ezkit/psd4256.h +++ b/board/bf533-ezkit/psd4256.h @@ -1,7 +1,7 @@ /* * U-boot - psd4256.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 8223d59..02c941b 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -1,7 +1,7 @@ # # U-boot - Makefile # -# Copyright (c) 2007 Analog Device Inc. +# Copyright (c) 2005-2007 Analog Device Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 2f6e751..b9dff99 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -1,7 +1,7 @@ /* * U-boot - stamp.c STAMP board specific routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h index b2b51aa..1e58e47 100644 --- a/board/bf533-stamp/bf533-stamp.h +++ b/board/bf533-stamp/bf533-stamp.h @@ -1,7 +1,7 @@ /* * U-boot - stamp.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __STAMP_H__ diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index cc4e998..47f7c9e 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -1,7 +1,7 @@ /* * U-boot - BF537.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h index f19e171..acc1e86 100644 --- a/board/bf537-stamp/flash-defines.h +++ b/board/bf537-stamp/flash-defines.h @@ -1,7 +1,7 @@ /* * U-boot - flash-defines.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __FLASHDEFINES_H__ diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c index 42dcf06..ed85841 100644 --- a/board/bf537-stamp/flash.c +++ b/board/bf537-stamp/flash.c @@ -1,7 +1,7 @@ /* * U-boot - flash.c Flash driver for PSD4256GV * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. * * (C) Copyright 2000-2004 @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <malloc.h> diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 71281c0..989b019 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -2,7 +2,7 @@ * U-boot - ezkit561.c * * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 700c9d9..2960998 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -42,6 +42,53 @@ #include "mt48lc16m16a2-75.h" # endif #endif + +#ifdef CONFIG_LITE5200B_PM +/* u-boot part of low-power mode implementation */ +#define SAVED_ADDR (*(void **)0x00000000) +#define PSC2_4 0x02 + +void lite5200b_wakeup(void) +{ + unsigned char wakeup_pin; + void (*linux_wakeup)(void); + + /* check PSC2_4, if it's down "QT" is signaling we have a wakeup + * from low power mode */ + *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; + __asm__ volatile ("sync"); + + wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; + if (wakeup_pin & PSC2_4) + return; + + /* acknowledge to "QT" + * by holding pin at 1 for 10 uS */ + *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; + __asm__ volatile ("sync"); + *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; + __asm__ volatile ("sync"); + udelay(10); + + /* put ram out of self-refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ + __asm__ volatile ("sync"); + udelay(10); /* wait a bit */ + + /* jump back to linux kernel code */ + linux_wakeup = SAVED_ADDR; + printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", + linux_wakeup); + linux_wakeup(); +} +#else +#define lite5200b_wakeup() +#endif + #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -208,6 +255,8 @@ long int initdram (int board_type) __asm__ volatile ("sync"); } + lite5200b_wakeup(); + return dramsize + dramsize2; } diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c index 98b86d1..726366d 100644 --- a/board/mcc200/lcd.c +++ b/board/mcc200/lcd.c @@ -180,10 +180,6 @@ void lcd_enable (void) break; udelay (PSOC_WAIT_TIME); } - if (!retries) { - printf ("%s Warning: PSoC doesn't respond on " - "RTS NEGATE\n", __FUNCTION__); - } return; } diff --git a/board/mpc7448hpc2/Makefile b/board/mpc7448hpc2/Makefile new file mode 100644 index 0000000..e3d757d --- /dev/null +++ b/board/mpc7448hpc2/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o tsi108_init.o +SOBJS := asm_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S new file mode 100644 index 0000000..a7a40a1 --- /dev/null +++ b/board/mpc7448hpc2/asm_init.S @@ -0,0 +1,918 @@ +/* + * (C) Copyright 2004-05; Tundra Semiconductor Corp. + * + * Added automatic detect of SDC settings + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * Maintainer tie-fei.zang@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * FILENAME: asm_init.s + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + * + */ + +#include <config.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> + +#include <tsi108.h> + +/* + * Build Configuration Options + */ + +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ + +/* + * Hardcoded SDC settings + */ + +#ifdef SDC_HARDCODED_INIT + +/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ + +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ + +#endif /* SDC_HARDCODED_INIT */ + +/* + CPU Configuration: + + CPU Address and Data Parity enables. + +#define CPU_AP +#define CPU_DP +*/ + +/* + * Macros + * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + * expected to work correctly for the CSR space within 32KB range. + * + * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + * These macros are absolutely identical except their names. This difference + * is provided intentionally for better readable code. + */ + +#define LOAD_PTR(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +#define LOAD_U32(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +/* LOADMEM initializes a register with the contents of a specified 32-bit + * memory location, usually a CSR value. + */ + +#define LOAD_MEM(reg,addr32) \ + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + +#ifndef SDC_HARDCODED_INIT +sdc_clk_sync: + /* MHz: 0,0,183,100,133,167,200,233 */ + .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ +#endif + +/* + * board_asm_init() - early initialization function. Coded to be portable to + * dual-CPU configuration. + * Checks CPU number and performs board HW initialization if called for CPU0. + * Registers used: r3,r4,r5,r6,r19,r29 + * + * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + * and the rest of the board. Current implementation demonstrates two + * possible ways to identify CPU number: + * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. + */ + + .globl board_asm_init +board_asm_init: + mflr r19 /* Save LR to be able return later. */ + bl icache_enable /* Enable icache to reduce reads from flash. */ + +/* Initialize pointer to Tsi108 register space */ + + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET + +/* Check Processor Version Number */ + + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init + + /* + * For MPC744x/5x enable extended BATs[4-7] + * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + * to disable prefetch + */ + + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync + + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync + + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync + + /* def CONFIG_DUAL_CPU + * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ +#if(1) + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init + +cont_brd_init: + + /* An alternative method of checking the processor number (in addition + * to configuration using MSSCR0[ID] bit on MPC74xx). + * Good for IBM PPC750FX/GX. + */ + + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + bne init_done +#else + +cont_brd_init: + +#endif /* CONFIG_DUAL_CPU */ + + /* Initialize Tsi108 chip */ + +do_tsi108_init: + + /* + * Adjust HLP/Flash parameters. By default after reset the HLP port is + * set to support slow devices. Better performance can be achived when + * an optimal parameters are used for specific EPROM device. + * NOTE: This should be performed ASAP for the emulation platform + * because it has 5MHz HLP clocking. + */ + +#ifdef CONFIG_TSI108EMU + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync +#endif + + /* Initialize PB interface. */ + + ori r4,r29,TSI108_PB_REG_OFFSET + +#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) + /* Relocate (if required) Tsi108 registers. Set new value for + * PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + ori r4,r29,TSI108_PB_REG_OFFSET +#endif + + /* Set PB Slave configuration register */ + + LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync + + /* Configure PB Arbiter */ + + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ +#ifdef DISABLE_PBM + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ +#endif + andc r5,r5,r3 /* Clear the masked bit fields */ + ori r5,r5,0x0001 /* Set pipeline depth */ + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync +#endif + + /* Disable or enable PVT based on processor bus frequency + * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + * 2. See if the value is < or > 133mhz (18:16 = 100) + * 3. If > enable PVT + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 + + cmpi 0,0,r3,0x0004 + bgt sdc_init + +#ifndef CONFIG_TSI108EMU + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync +#endif + + /* Initialize SDRAM controller. */ + +sdc_init: + +#ifndef SDC_HARDCODED_INIT + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 + +get_nsec: + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ +#endif /* !SDC_HARDCODED_INIT */ + + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ +#ifdef ENABLE_SDRAM_ECC + li r5, 0x01 +#endif /* ENABLE_SDRAM_ECC */ + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync + +#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ + + /* First read the CG_PWRUP_STATUS register to get the + * memory speed from bits 22,21,20 + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 + + /* Now first check for 166, then 200, or default */ + + cmpi 0,0,r3,0x0005 + bne check_for_200mhz + + /* set values for 166 Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +check_for_200mhz: + + cmpi 0,0,r3,0x0006 + bne set_default_values + + /* set values for 200Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +set_default_values: + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync +#else /* !SDC_HARDCODED_INIT */ + bl tsi108_sdram_spd /* automatically detect SDC settings */ +#endif /* SDC_HARDCODED_INIT */ + +sdc_init_done: + +#ifdef DISABLE_PBM + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ +#else + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_TSI108EMU + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ +#endif + + stw r5,SD_CTRL(r4) + eieio + sync + + /* Enable SDRAM access */ + + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync + +wait_init_complete: + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + /* wait until SDRAM initialization is complete */ + beq wait_init_complete + + /* Map SDRAM into the processor bus address space */ + + ori r4,r29,TSI108_PB_REG_OFFSET + + /* Setup BARs associated with direct path PB<->SDRAM */ + + /* PB_SDRAM_BAR1: + * provides a direct path to the main system memory (cacheable SDRAM) + */ + + /* BA=0,Size=512MB, ENable, No Addr.Translation */ + LOAD_U32(r5, 0x00000011) + stw r5,PB_SDRAM_BAR1(r4) + sync + + /* Make sure that PB_SDRAM_BAR1 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR1(r4) + sync + + /* PB_SDRAM_BAR2: + * provides non-cacheable alias (via the direct path) to main + * system memory. + * Size = 512MB, ENable, Addr.Translation - ON, + * BA = 0x0_40000000, TA = 0x0_00000000 + */ + + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + + /* Make sure that PB_SDRAM_BAR2 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR2(r4) + sync + +init_done: + + /* All done. Restore LR and return. */ + mtlr r19 + blr + +#if (0) + /* + * init_cpu1 + * This routine enables CPU1 on the dual-processor system. + * Now there is only one processor in the system + */ + + .global enable_cpu1 +enable_cpu1: + + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) + + blr +#endif + + /* + * enable_EI + * Enable CPU core external interrupt + */ + + .global enable_EI +enable_EI: + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr + + /* + * disable_EI + * Disable CPU core external interrupt + */ + + .global disable_EI +disable_EI: + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr + +#ifdef ENABLE_SDRAM_ECC + /* enables SDRAM ECC */ + + .global enable_ECC +enable_ECC: + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr + + /* + * clear_ECC_err + * Clears all pending SDRAM ECC errors + * (normally after SDRAM scrubbing/initialization) + */ + + .global clear_ECC_err +clear_ECC_err: + ori r4,r29,TSI108_SD_REG_OFFSET + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr + +#endif /* ENABLE_SDRAM_ECC */ + +#ifndef SDC_HARDCODED_INIT + + /* SDRAM SPD Support */ +#define SD_I2C_CTRL1 (0x400) +#define SD_I2C_CTRL2 (0x404) +#define SD_I2C_RD_DATA (0x408) +#define SD_I2C_WR_DATA (0x40C) + + /* + * SDRAM SPD Support Macros + */ + +#define SPD_DIMM0 (0x00000100) +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ + +#define SPD_RDIMM (0x01) +#define SPD_UDIMM (0x02) + +#define SPD_CAS_3 0x8 +#define SPD_CAS_4 0x10 +#define SPD_CAS_5 0x20 + +#define ERR_NO_DIMM_FOUND (0xdb0) +#define ERR_TRAS_FAIL (0xdb1) +#define ERR_TRCD_FAIL (0xdb2) +#define ERR_TRP_FAIL (0xdb3) +#define ERR_TWR_FAIL (0xdb4) +#define ERR_UNKNOWN_PART (0xdb5) +#define ERR_NRANK_INVALID (0xdb6) +#define ERR_DIMM_SIZE (0xdb7) +#define ERR_ADDR_MODE (0xdb8) +#define ERR_RFRSH_RATE (0xdb9) +#define ERR_DIMM_TYPE (0xdba) +#define ERR_CL_VALUE (0xdbb) +#define ERR_TRFC_FAIL (0xdbc) + +/* READ_SPD requirements: + * byte - byte address in SPD device (0 - 255) + * r3 = will return data read from I2C Byte location + * r4 - unchanged (SDC base addr) + * r5 - clobbered in routine (I2C status) + * r10 - number of DDR slot where first SPD device is detected + */ + +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l; \ + or r3, r3, r10; \ + ori r3, r3, 0x0A; \ + stw r3, SD_I2C_CTRL1(r4); \ + li r3, I2C_CNTRL2_START; \ + stw r3, SD_I2C_CTRL2(r4); \ + eieio; \ + sync; \ + li r3, 0x100; \ +1:; \ + addic. r3, r3, -1; \ + bne 1b; \ +2:; \ + lwz r5, SD_I2C_CTRL2(r4); \ + rlwinm. r3,r5,0,23,23; \ + bne 2b; \ + rlwinm. r3,r5,0,3,3; \ + lwz r3,SD_I2C_RD_DATA(r4) + +#define SPD_MIN_RFRSH (0x80) +#define SPD_MAX_RFRSH (0x85) + +refresh_rates: /* in nSec */ + .long 15625 /* Normal (0x80) */ + .long 3900 /* Reduced 0.25x (0x81) */ + .long 7800 /* Reduced 0.5x (0x82) */ + .long 31300 /* Extended 2x (0x83) */ + .long 62500 /* Extended 4x (0x84) */ + .long 125000 /* Extended 8x (0x85) */ + +/* + * tsi108_sdram_spd + * + * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data + * Uses registers: r4 - SDC base address (not changed) + * r9 - SDC clocking period in nSec + * Changes registers: r3,r5,r6,r7,r8,r10,r11 + */ + +tsi108_sdram_spd: + + li r10,SPD_DIMM0 + xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ + +do_first_dimm: + + /* Program Refresh Rate Register */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync + + /* Program SD Timing Register */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + beq spd_read_fail + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + +do_cl: + READ_SPD(18) /* Get CAS Latency */ + beq spd_read_fail + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl +cl_4: + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl +cl_5: + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 +set_cl: + rlwimi r7,r6,24,5,7 + + READ_SPD(30) /* Get tRAS */ + beq spd_read_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_tras + addi r6,r6,1 +set_tras: + li r5,ERR_TRAS_FAIL + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 + + READ_SPD(29) /* Get tRCD */ + beq spd_read_fail + /* right shift tRCD by 2 bits as per DDR2 spec */ + rlwinm r3,r3,30,2,31 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trcd + addi r6,r6,1 +set_trcd: + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 + + READ_SPD(27) /* Get tRP value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trp + addi r6,r6,1 +set_trp: + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 + + READ_SPD(36) /* Get tWR value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_twr + addi r6,r6,1 +set_twr: + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 + + READ_SPD(42) /* Get tRFC */ + beq spd_read_fail + li r5, ERR_TRFC_FAIL + /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trfc + addi r6,r6,1 +set_trfc: + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 + + stw r7,SD_TIMING(r4) + sync + + /* + * The following two registers are set on per-DIMM basis. + * The SD_REFRESH and SD_TIMING settings are common for both DIMMS + */ + +do_each_dimm: + + /* Program SDRAM DIMM Control Register */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(13) /* Get Primary SDRAM Width */ + beq spd_read_fail + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + +do_nbank: + READ_SPD(17) /* Get Number of banks on SDRAM device */ + beq spd_read_fail + /* Grendel only distinguish betw. 4 or 8-bank memory parts */ + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 + +do_nrank: + READ_SPD(5) /* Get # of Ranks */ + beq spd_read_fail + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 + +do_addr_mode: + READ_SPD(4) /* Get # of Column Addresses */ + beq spd_read_fail + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + +set_dimm_ctrl: +#ifdef SDC_AUTOPRECH_EN + oris r7,r7,0x0001 /* set auto precharge EN bit */ +#endif + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) + sync + b set_dimm_bar +1: + stw r7,SD_D1_CTRL(r4) + sync + + + /* Program SDRAM DIMMx Base Address Register */ + +set_dimm_bar: + READ_SPD(5) /* get # of Ranks */ + beq spd_read_fail + andi. r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ + beq spd_read_fail + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 + READ_SPD(0) + bne do_each_dimm + b spd_done + +set_dimm1_size: + stw r7,SD_D1_BAR(r4) + sync +spd_done: + blr + +check_next_slot: + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm +spd_read_fail: + ori r3,r0,0xdead + b err_hung +spd_fail: + li r3,0x0bad + sync +err_hung: /* hang here for debugging */ + nop + nop + b err_hung + +#endif /* !SDC_HARDCODED_INIT */ diff --git a/board/mpc7448hpc2/config.mk b/board/mpc7448hpc2/config.mk new file mode 100644 index 0000000..2e58858 --- /dev/null +++ b/board/mpc7448hpc2/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (c) 2005 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Flash address +TEXT_BASE = 0xFF000000 +# RAM address +#TEXT_BASE = 0x00400000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c new file mode 100644 index 0000000..63c99de --- /dev/null +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2005 Freescale Semiconductor, Inc. + * + * Roy Zang <tie-fei.zang@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the Tsi108 Emul Board by avb@Tundra + */ + +/* + * board support/init functions for the + * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). + */ + +#include <common.h> +#include <74xx_7xx.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +extern void ft_cpu_setup (void *blob, bd_t *bd); +#endif + +#undef DEBUG + +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); +extern void tsi108_init_f (void); + +int display_mem_map (void); + +void after_reloc (ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Jump to the main U-Boot board init code + */ + board_init_r ((gd_t *) gd, dest_addr); + /* NOTREACHED */ +} + +/* + * Check Board Identity: + * report board type + */ + +int checkboard (void) +{ + int l_type = 0; + + printf ("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* + * Read Processor ID: + * + * report calling processor number + */ + +int read_pid (void) +{ + return 0; /* we are on single CPU platform for a while */ +} + +long int dram_size (int board_type) +{ + return 0x20000000; /* 256M bytes */ +} + +long int initdram (int board_type) +{ + return dram_size (board_type); +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup (void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup (blob, bd); + + p = ft_get_prop (blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); + } +} +#endif diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c new file mode 100644 index 0000000..8a7efef --- /dev/null +++ b/board/mpc7448hpc2/tsi108_init.c @@ -0,0 +1,665 @@ +/***************************************************************************** + * (C) Copyright 2003; Tundra Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + *****************************************************************************/ + +/*---------------------------------------------------------------------------- + * FILENAME: tsi108_init.c + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + *---------------------------------------------------------------------------*/ + +#include <common.h> +#include <74xx_7xx.h> +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <tsi108.h> + +extern void mpicInit (int verbose); + +/* + * Configuration Options + */ + +typedef struct { + ulong upper; + ulong lower; +} PB2OCN_LUT_ENTRY; + +PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { + /* 0 - 7 */ + {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */ + + /* 8 - 15 */ + {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */ + + /* 16 - 23 */ + {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */ + /* 24 - 31 */ + {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */ + + {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */ + {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */ + {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */ + {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ +}; + +#ifdef CFG_CLK_SPREAD +typedef struct { + ulong ctrl0; + ulong ctrl1; +} PLL_CTRL_SET; + +/* + * Clock Generator SPLL0 initialization values + * PLL0 configuration table for various PB_CLKO freq. + * Uses pre-calculated values for Fs = 30 kHz, D = 0.5% + * Fout depends on required PB_CLKO. Based on Fref = 33 MHz + */ + +static PLL_CTRL_SET pll0_config[8] = { + {0x00000000, 0x00000000}, /* 0: bypass */ + {0x00000000, 0x00000000}, /* 1: reserved */ + {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */ + {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */ + {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */ + {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */ + {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ + {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ +}; +#endif /* CFG_CLK_SPREAD */ + +/* + * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT + * (based on recommended Tsi108 reference clock 33MHz) + */ +static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; + +/* + * get_board_bus_clk () + * + * returns the bus clock in Hz. + */ +unsigned long get_board_bus_clk (void) +{ + ulong i; + + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + return pb_clk_sel[i] * 1000000; +} + +/* + * board_early_init_f () + * + * board-specific initialization executed from flash + */ + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong i; + + gd->mem_clk = 0; + i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + + CG_PWRUP_STATUS); + i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ + switch (i) { + case 0: /* external clock */ + printf ("Using external clock\n"); + break; + case 1: /* system clock */ + gd->mem_clk = gd->bus_clk; + break; + case 4: /* 133 MHz */ + case 5: /* 166 MHz */ + case 6: /* 200 MHz */ + gd->mem_clk = pb_clk_sel[i] * 1000000; + break; + default: + printf ("Invalid DDR2 clock setting\n"); + return -1; + } + printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); + return 0; +} + +/* + * board_early_init_r() - Tsi108 initialization function executed right after + * relocation. Contains code that cannot be executed from flash. + */ + +int board_early_init_r (void) +{ + ulong temp, i; + ulong reg_val; + volatile ulong *reg_ptr; + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ + *reg_ptr++ = 0x00; + } + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + 0x80000001); + __asm__ __volatile__ ("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following immediate + * read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); + __asm__ __volatile__ ("sync"); + + /* + * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the + * processor bus address space. Immediately after reset LUT and address + * translation are disabled for this BAR. Now we have to initialize LUT + * and switch from the BOOT mode to the normal operation mode. + * + * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 + * and covers 512MB of address space. To allow larger aperture we also + * have to relocate register window of Tsi108 + * + * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT + * mode. + * + * initialize pointer to LUT associated with PB_OCN_BAR1 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = pb2ocn_lut1[i].lower; + *reg_ptr++ = pb2ocn_lut1[i].upper; + } + + __asm__ __volatile__ ("sync"); + + /* Base addresses for CS0, CS1, CS2, CS3 */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + 0x00000000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + 0x00100000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + 0x00200000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + 0x00300000); + __asm__ __volatile__ ("sync"); + + /* Masks for HLP banks */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + /* Set CTRL0 values for banks */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); + + /* Set banks to latched mode, enabled, and other default settings */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + /* + * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. + * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) + */ + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + 0xE0000011); + __asm__ __volatile__ ("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following + * immediate read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); + __asm__ __volatile__ ("sync"); + + /* + * SRI: At this point we have enabled the HLP banks. That means we can + * now read from the NVRAM and initialize the environment variables. + * We will over-ride the env_init called in board_init_f + * This is really a work-around because, the HLP bank 1 + * where NVRAM resides is not visible during board_init_f + * (lib_ppc/board.c) + * Alternatively, we could use the I2C EEPROM at start-up to configure + * and enable all HLP banks and not just HLP 0 as is being done for + * Taiga Rev. 2. + */ + + env_init (); + +#ifndef DISABLE_PBM + + /* + * For IBM processors we have to set Address-Only commands generated + * by PBM that are different from ones set after reset. + */ + + temp = get_cpu_type (); + + if ((CPU_750FX == temp) || (CPU_750GX == temp)) + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + 0x00009955); +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_PCI + /* + * Initialize PCI/X block + */ + + /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_PFAB_BAR0_UPPER, 0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + 0xFB000001); + __asm__ __volatile__ ("sync"); + + /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ + + temp = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); + + temp &= ~0xFF00; /* Clear the BUS_NUM field */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + temp); + + /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + 0); + __asm__ __volatile__ ("sync"); + + /* This register is on the PCI side to interpret the address it receives + * and maps it as a IO address. + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + 0xFA000001); + __asm__ __volatile__ ("sync"); + + /* + * Map PCI/X Memory Space + * + * Transactions directed from OCM to PCI Memory Space are directed + * from PB to PCI + * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). + * If address remapping is required the corresponding PCI_PFAB_MEM32 + * and PCI_PFAB_PFMx register groups have to be configured. + * + * Map the path from the PCI/X bus into the system memory + * + * The memory mapped window assotiated with PCI P2O_BAR2 provides + * access to the system memory without address remapping. + * All system memory is opened for accesses initiated by PCI/X bus + * masters. + * + * Initialize LUT associated with PCI P2O_BAR2 + * + * set pointer to LUT associated with PCI P2O_BAR2 + */ + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + +#ifdef DISABLE_PBM + + /* In case when PBM is disabled (no HW supported cache snoopng on PB) + * P2O_BAR2 is directly mapped into the system memory without address + * translation. + */ + + reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ + *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */ + } + + /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */ + reg_val = 0x00007500; +#else + + reg_val = 0x00000002; /* Destination port = PBM */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ +/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0x40000000; +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + +/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */ + reg_val = 0x00007100; +#endif + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); + + /* Set 64-bit PCI bus address for system memory + * ( 0 is the best choice for easy mapping) + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + 0x00000000); + __asm__ __volatile__ ("sync"); + +#ifndef DISABLE_PBM + /* + * The memory mapped window assotiated with PCI P2O_BAR3 provides + * access to the system memory using SDRAM OCN port and address + * translation. This is alternative way to access SDRAM from PCI + * required for Tsi108 emulation testing. + * All system memory is opened for accesses initiated by + * PCI/X bus masters. + * + * Initialize LUT associated with PCI P2O_BAR3 + * + * set pointer to LUT associated with PCI P2O_BAR3 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + + reg_val = 0x00000004; /* Destination port = SDC */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ + +/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0; + +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ + + reg_val = + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_P2O_PAGE_SIZES); + reg_val &= ~0x00FF; + reg_val |= 0x0071; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); + + /* Set 64-bit base PCI bus address for window (0x20000000) */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + 0x20000000); + __asm__ __volatile__ ("sync"); + +#endif /* !DISABLE_PBM */ + +#ifdef ENABLE_PCI_CSR_BAR + /* open if required access to Tsi108 CSRs from the PCI/X bus */ + /* enable BAR0 on the PCI/X bus */ + reg_val = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); + reg_val |= 0x02; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + reg_val); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CFG_TSI108_CSR_BASE); + __asm__ __volatile__ ("sync"); + +#endif + + /* + * Finally enable PCI/X Bus Master and Memory Space access + */ + + reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); + reg_val |= 0x06; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + __asm__ __volatile__ ("sync"); + +#endif /* CONFIG_PCI */ + + /* + * Initialize MPIC outputs (interrupt pins): + * Interrupt routing on the Grendel Emul. Board: + * PB_INT[0] -> INT (CPU0) + * PB_INT[1] -> INT (CPU1) + * PB_INT[2] -> MCP (CPU0) + * PB_INT[3] -> MCP (CPU1) + * Set interrupt controller outputs as Level_Sensitive/Active_Low + */ + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + __asm__ __volatile__ ("sync"); + + /* + * Ensure that Machine Check exception is enabled + * We need it to support PCI Bus probing (configuration reads) + */ + + reg_val = mfmsr (); + mtmsr(reg_val | MSR_ME); + + return 0; +} + +/* + * Needed to print out L2 cache info + * used in the misc_init_r function + */ + +unsigned long get_l2cr (void) +{ + unsigned long l2controlreg; + asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); + return l2controlreg; +} + +/* + * misc_init_r() + * + * various things to do after relocation + * + */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ + ulong i; + + /* Ensure that Spread-Spectrum is disabled */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + + /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK + * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x002e0044); /* D = 0.25% */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, + 0x00000039); /* BWADJ */ + + /* Initialize PLL0: CG_PB_CLKO */ + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); + + /* Wait and set SSEN for both PLL0 and 1 */ + udelay (1000); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x802e0044); /* D=0.25% */ + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, + 0x80000000 | pll0_config[i].ctrl0); +#endif /* CFG_CLK_SPREAD */ + +#ifdef CFG_L2 + l2cache_enable (); +#endif + printf ("BUS: %d MHz\n", gd->bus_clk / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); + + /* + * All the information needed to print the cache details is avaiblable + * at this point i.e. above call to l2cache_enable is the very last + * thing done with regards to enabling diabling the cache. + * So this seems like a good place to print all this information + */ + + printf ("CACHE: "); + switch (get_cpu_type()) { + case CPU_7447A: + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 512KB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("\n"); + break; + + case CPU_7448: + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 1MB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + break; + default: + break; + } + return 0; +} diff --git a/board/mpc7448hpc2/u-boot.lds b/board/mpc7448hpc2/u-boot.lds new file mode 100644 index 0000000..8f24213 --- /dev/null +++ b/board/mpc7448hpc2/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk index 9ace886..5801a5f 100644 --- a/board/mpc8360emds/config.mk +++ b/board/mpc8360emds/config.mk @@ -26,3 +26,8 @@ # TEXT_BASE = 0xFE000000 + +# +# Additional board-specific libraries +# +BOARDLIBS = libfdt/libfdt.a diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 535884c..deadb5f 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -31,6 +31,10 @@ #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> #endif +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -658,22 +662,36 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc, " - disables injects\n" " - re-inits memory"); #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ + && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_LIBFDT) + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_path_offset (fdt, "/memory"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(bd->bi_memstart); + tmp[1] = cpu_to_be32(bd->bi_memsize); + err = fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp)); + } +#else u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); } #endif diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 67cd709..158effe 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -21,6 +21,10 @@ #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> #endif +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> +#endif #include <asm/fsl_i2c.h> @@ -299,6 +303,22 @@ void pci_init_board(void) } #endif /* CONFIG_PCISLAVE */ +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp)); + } +} +#endif /* CONFIG_OF_LIBFDT */ #ifdef CONFIG_OF_FLAT_TREE void ft_pci_setup(void *blob, bd_t *bd) diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c index 7a6b3be..f726513 100644 --- a/board/uc101/uc101.c +++ b/board/uc101/uc101.c @@ -221,6 +221,8 @@ long int initdram (int board_type) int checkboard (void) { puts ("Board: MAN UC101\n"); + /* clear the Display */ + *(char *)(CFG_DISP_CWORD) = 0x80; return 0; } diff --git a/board/xilinx/ml401/Makefile b/board/xilinx/ml401/Makefile new file mode 100644 index 0000000..9ab5633 --- /dev/null +++ b/board/xilinx/ml401/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../xilinx_enet) +endif + +INCS := -I../common -I../xilinx_enet +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o \ + ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ + ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ + ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ + ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \ + ../common/xbasic_types.o ../common/xdma_channel.o \ + ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ + ../common/xversion.o \ + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/ml401/config.mk new file mode 100644 index 0000000..807f169 --- /dev/null +++ b/board/xilinx/ml401/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK <monstr@monstr.eu> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# CAUTION: This file is automatically generated by libgen. +# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 +# + +TEXT_BASE = 0x12000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c new file mode 100644 index 0000000..b48103f --- /dev/null +++ b/board/xilinx/ml401/ml401.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ + +#include <common.h> +#include <config.h> + +void do_reset (void) +{ +#ifdef CFG_GPIO_0 + *((unsigned long *)(CFG_GPIO_0_ADDR)) = + ++(*((unsigned long *)(CFG_GPIO_0_ADDR))); +#endif +#ifdef CFG_RESET_ADDRESS + puts ("Reseting board\n"); + asm ("bra r0"); +#endif +} + +int gpio_init (void) +{ +#ifdef CFG_GPIO_0 + *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0; +#endif + return 0; +} diff --git a/board/xilinx/ml401/u-boot.lds b/board/xilinx/ml401/u-boot.lds new file mode 100644 index 0000000..cb90854 --- /dev/null +++ b/board/xilinx/ml401/u-boot.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI <yashi@atmark-techno.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + cpu/microblaze/start.o (.text) + *(.text) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(.rodata) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + __data_end = .; + } + + .u_boot_cmd ALIGN(0x4): + { + . = .; + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.bss) + __bss_end = .; + } + __end = . ; +} diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h new file mode 100644 index 0000000..18d24f9 --- /dev/null +++ b/board/xilinx/ml401/xparameters.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 6.3 EDK_Gmm.12.3 + */ + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 66666667 + +/* Interrupt controller is intc_0 */ +#define XILINX_INTC_BASEADDR 0xd1000fc0 +#define XILINX_INTC_NUM_INTR_INPUTS 12 + +/* Timer pheriphery is opb_timer_0 */ +#define XILINX_TIMER_BASEADDR 0xa2000000 +#define XILINX_TIMER_IRQ 0 + +/* Uart pheriphery is console_uart */ +#define XILINX_UART_BASEADDR 0xa0000000 +#define XILINX_UART_BAUDRATE 115200 + +/* GPIO is opb_gpio_0*/ +#define XILINX_GPIO_BASEADDR 0x90000000 + +/* Flash Memory is opb_emc_0 */ +#define XILINX_FLASH_START 0x28000000 +#define XILINX_FLASH_SIZE 0x00800000 + +/* Main Memory is plb_ddr_0 */ +#define XILINX_RAM_START 0x10000000 +#define XILINX_RAM_SIZE 0x10000000 + +/* Sysace Controller is opb_sysace_0 */ +#define XILINX_SYSACE_BASEADDR 0xCF000000 +#define XILINX_SYSACE_HIGHADDR 0xCF0001FF +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is opb_ethernet_0 */ +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index f159cb6..d340303 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -147,7 +147,11 @@ eth_rx(void) RecvFrameLength = PKTSIZE; Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); if (Result == XST_SUCCESS) { +#ifndef CONFIG_EMACLITE NetReceive((uchar *)etherrxbuff, RecvFrameLength); +#else + NetReceive(etherrxbuff, RecvFrameLength); +#endif return (1); } else { return (0); diff --git a/board/xilinx/xupv2p/Makefile b/board/xilinx/xupv2p/Makefile new file mode 100644 index 0000000..9ab5633 --- /dev/null +++ b/board/xilinx/xupv2p/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../xilinx_enet) +endif + +INCS := -I../common -I../xilinx_enet +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o \ + ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ + ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ + ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ + ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \ + ../common/xbasic_types.o ../common/xdma_channel.o \ + ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ + ../common/xversion.o \ + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/xupv2p/config.mk b/board/xilinx/xupv2p/config.mk new file mode 100644 index 0000000..c07b0b3 --- /dev/null +++ b/board/xilinx/xupv2p/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK <monstr@monstr.eu> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# CAUTION: This file is automatically generated by libgen. +# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 +# + +TEXT_BASE = 0x38000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/xupv2p/u-boot.lds b/board/xilinx/xupv2p/u-boot.lds new file mode 100644 index 0000000..cb90854 --- /dev/null +++ b/board/xilinx/xupv2p/u-boot.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI <yashi@atmark-techno.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + cpu/microblaze/start.o (.text) + *(.text) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(.rodata) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + __data_end = .; + } + + .u_boot_cmd ALIGN(0x4): + { + . = .; + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.bss) + __bss_end = .; + } + __end = . ; +} diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h new file mode 100644 index 0000000..a96c693 --- /dev/null +++ b/board/xilinx/xupv2p/xparameters.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 + */ + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 11 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 1 + +/* Uart pheriphery is RS232_Uart_1 */ +#define XILINX_UART_BASEADDR 0x40600000 +#define XILINX_UART_BAUDRATE 115200 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* FLASH doesn't exist none */ + +/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */ +#define XILINX_RAM_START 0x30000000 +#define XILINX_RAM_SIZE 0x10000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 diff --git a/board/xilinx/xupv2p/xupv2p.c b/board/xilinx/xupv2p/xupv2p.c new file mode 100644 index 0000000..b48103f --- /dev/null +++ b/board/xilinx/xupv2p/xupv2p.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ + +#include <common.h> +#include <config.h> + +void do_reset (void) +{ +#ifdef CFG_GPIO_0 + *((unsigned long *)(CFG_GPIO_0_ADDR)) = + ++(*((unsigned long *)(CFG_GPIO_0_ADDR))); +#endif +#ifdef CFG_RESET_ADDRESS + puts ("Reseting board\n"); + asm ("bra r0"); +#endif +} + +int gpio_init (void) +{ +#ifdef CFG_GPIO_0 + *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0; +#endif + return 0; +} |