diff options
Diffstat (limited to 'board')
33 files changed, 2902 insertions, 3184 deletions
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 25c9a22..e41caaf 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -246,6 +246,18 @@ int checkboard (void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +u32 ddr_wrdtr(u32 default_val) { + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); +} + +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_90_DEG_ADV); +} + #if defined(CFG_DRAM_TEST) int testdram (void) { diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 78e2cb4..5e93f6c 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -33,343 +33,11 @@ #include <asm/io.h> #include <ppc440.h> -#include "sdram.h" - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_DDR_DATA_EYE) -/*-----------------------------------------------------------------------------+ - * wait_for_dlllock. - +----------------------------------------------------------------------------*/ -static int wait_for_dlllock(void) -{ - unsigned long val; - int wait = 0; - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); - val = DDR0_17_DLLLOCKREG_UNLOCKED; - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) - /* dlllockreg bit on */ - return 0; - else - wait++; - } - debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); - debug("Waiting for dlllockreg bit to raise\n"); - - return -1; -} -#endif - -#if defined(CONFIG_DDR_DATA_EYE) /*-----------------------------------------------------------------------------+ - * wait_for_dram_init_complete. - +----------------------------------------------------------------------------*/ -int wait_for_dram_init_complete(void) -{ - unsigned long val; - int wait = 0; - - /* --------------------------------------------------------------+ - * Wait for 'DRAM initialization complete' bit in status register - * -------------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_00); - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) - /* 'DRAM initialization complete' bit */ - return 0; - else - wait++; - } - - debug("DRAM initialization complete bit in status register did not rise\n"); - - return -1; -} - -#define NUM_TRIES 64 -#define NUM_READS 10 - -/*-----------------------------------------------------------------------------+ - * denali_core_search_data_eye. - +----------------------------------------------------------------------------*/ -void denali_core_search_data_eye(unsigned long memory_size) -{ - int k, j; - u32 val; - u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; - u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; - u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; - u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; - volatile u32 *ram_pointer; - u32 test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); - - for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { - /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - - passing_cases = 0; - - for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { - /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ - - /* write values */ - for (j=0; j<NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - } - - /* read values back */ - for (j=0; j<NUM_TRIES; j++) { - for (k=0; k<NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) - break; - } - - /* See if the dll_dqs_delay_X value passed.*/ - if (j < NUM_TRIES) { - /* Failed */ - passing_cases = 0; - /* break; */ - } else { - /* Passed */ - if (passing_cases == 0) - dll_dqs_delay_X_sw_val = dll_dqs_delay_X; - passing_cases++; - if (passing_cases >= max_passing_cases) { - max_passing_cases = passing_cases; - wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; - dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; - dll_dqs_delay_X_end_window = dll_dqs_delay_X; - } - } - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ - - } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ - - /* -----------------------------------------------------------+ - * Largest passing window is now detected. - * ----------------------------------------------------------*/ - - /* Compute dll_dqs_delay_X value */ - dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; - wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; - - debug("DQS calibration - Window detected:\n"); - debug("max_passing_cases = %d\n", max_passing_cases); - debug("wr_dqs_shift = %d\n", wr_dqs_shift); - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); - debug("dll_dqs_delay_X window = %d - %d\n", - dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_09=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_22=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_17=0x%08lx\n", val); - - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_18=0x%08lx\n", val); - - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_19=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ -} -#endif /* CONFIG_DDR_DATA_EYE */ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); #if defined(CONFIG_NAND_SPL) /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big @@ -428,14 +96,14 @@ long int initdram (int board_type) mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); - wait_for_dlllock(); + denali_wait_for_dlllock(); #endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ - denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20); + denali_core_search_data_eye(); #endif return (CFG_MBYTES_SDRAM << 20); diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h deleted file mode 100644 index 6a7bf01..0000000 --- a/board/amcc/sequoia/sdram.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPD_SDRAM_DENALI_H_ -#define _SPD_SDRAM_DENALI_H_ - -#define ppcMsync sync -#define ppcMbar eieio - -/* General definitions */ -#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ -#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ -#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ -#define SDRAM_NONE 0 /* No DIMM detected in Slot */ -#define MAXRANKS 2 /* 2 ranks maximum */ - -/* Supported PLB Frequencies */ -#define PLB_FREQ_133MHZ 133333333 -#define PLB_FREQ_152MHZ 152000000 -#define PLB_FREQ_160MHZ 160000000 -#define PLB_FREQ_166MHZ 166666666 - -/* Denali Core Registers */ -#define SDRAM_DCR_BASE 0x10 - -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -/*-----------------------------------------------------------------------------+ - | Values for ddrcfga register - indirect addressing of these regs - +-----------------------------------------------------------------------------*/ - -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) - -#define DDR0_13 0x0D - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) - -#define DDR0_15 0x0F - -#define DDR0_16 0x10 - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) - -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_29 0x1D - -#define DDR0_30 0x1E - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 37b4f31..e46efef 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -26,8 +26,10 @@ #include <libfdt.h> #include <fdt_support.h> #include <ppc440.h> +#include <asm/gpio.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/ppc4xx-intvec.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,36 +47,6 @@ int board_early_init_f(void) mtdcr(ebccfgd, 0xb8400000); /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - /* test-only: take GPIO init from pcs440ep ???? in config file */ - out_be32((u32 *) GPIO0_OR, 0x00000000); - out_be32((u32 *) GPIO0_TCR, 0x0000000f); - out_be32((u32 *) GPIO0_OSRL, 0x50015400); - out_be32((u32 *) GPIO0_OSRH, 0x550050aa); - out_be32((u32 *) GPIO0_TSRL, 0x50015400); - out_be32((u32 *) GPIO0_TSRH, 0x55005000); - out_be32((u32 *) GPIO0_ISR1L, 0x50000000); - out_be32((u32 *) GPIO0_ISR1H, 0x00000000); - out_be32((u32 *) GPIO0_ISR2L, 0x00000000); - out_be32((u32 *) GPIO0_ISR2H, 0x00000100); - out_be32((u32 *) GPIO0_ISR3L, 0x00000000); - out_be32((u32 *) GPIO0_ISR3H, 0x00000000); - - out_be32((u32 *) GPIO1_OR, 0x00000000); - out_be32((u32 *) GPIO1_TCR, 0xc2000000); - out_be32((u32 *) GPIO1_OSRL, 0x5c280000); - out_be32((u32 *) GPIO1_OSRH, 0x00000000); - out_be32((u32 *) GPIO1_TSRL, 0x0c000000); - out_be32((u32 *) GPIO1_TSRH, 0x00000000); - out_be32((u32 *) GPIO1_ISR1L, 0x00005550); - out_be32((u32 *) GPIO1_ISR1H, 0x00000000); - out_be32((u32 *) GPIO1_ISR2L, 0x00050000); - out_be32((u32 *) GPIO1_ISR2H, 0x00000000); - out_be32((u32 *) GPIO1_ISR3L, 0x01400000); - out_be32((u32 *) GPIO1_ISR3H, 0x00000000); - - /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(uic0sr, 0xffffffff); /* clear all */ @@ -416,6 +388,16 @@ int testdram(void) } #endif +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. + */ +void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); +} +#endif + /************************************************************************* * pci_pre_init * @@ -467,6 +449,9 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#ifdef CONFIG_PCI_PNP + hose->fixup_irq = sequoia_pci_fixup_irq; +#endif return 1; } #endif /* defined(CONFIG_PCI) */ diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 4116838..ed50def 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -37,41 +37,41 @@ int lcd_depth; unsigned char *glob_lcd_reg; unsigned char *glob_lcd_mem; -#ifdef CFG_LCD_ENDIAN +#if defined(CFG_LCD_ENDIAN) void lcd_setup(int lcd, int config) { if (lcd == 0) { /* * Set endianess and reset lcd controller 0 (small) */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ udelay(10); /* wait 10us */ if (config == 1) - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ else - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ } else { /* * Set endianess and reset lcd controller 1 (big) */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ udelay(10); /* wait 10us */ if (config == 1) - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ else - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ } /* * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ } -#endif /* #ifdef CFG_LCD_ENDIAN */ +#endif /* CFG_LCD_ENDIAN */ void lcd_bmp(uchar *logo_bmp) @@ -93,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp) * Check for bmp mark 'BM' */ if (*(ushort *)logo_bmp != 0x424d) { - /* * Decompress bmp image */ @@ -160,7 +159,7 @@ void lcd_bmp(uchar *logo_bmp) */ if ((colors <= 256) && (lcd_depth <= 8)) { ptr = (unsigned char *)(dst + 14 + 40); - for (i=0; i<colors; i++) { + for (i = 0; i < colors; i++) { b = *ptr++; g = *ptr++; r = *ptr++; @@ -175,11 +174,11 @@ void lcd_bmp(uchar *logo_bmp) ptr = glob_lcd_mem; ptr2 = (ushort *)glob_lcd_mem; header_size = 14 + 40 + 4*colors; /* skip bmp header */ - for (y=0; y<height; y++) { + for (y = 0; y < height; y++) { bmp = &dst[(height-1-y)*line_size + header_size]; if (lcd_depth == 16) { if (bpp == 24) { - for (x=0; x<width; x++) { + for (x = 0; x < width; x++) { /* * Generate epson 16bpp fb-format from 24bpp image */ @@ -190,7 +189,7 @@ void lcd_bmp(uchar *logo_bmp) *ptr2++ = val; } } else if (bpp == 8) { - for (x=0; x<line_size; x++) { + for (x = 0; x < line_size; x++) { /* query rgb value from palette */ ptr = (unsigned char *)(dst + 14 + 40) ; ptr += (*bmp++) << 2; @@ -202,9 +201,8 @@ void lcd_bmp(uchar *logo_bmp) } } } else { - for (x=0; x<line_size; x++) { + for (x = 0; x < line_size; x++) *ptr++ = *bmp++; - } } } @@ -254,7 +252,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, palette_value = 0x17; lcd_depth = 8; puts("LCD: S1D13704"); - } else if (in_8(&lcd_reg[0x10000]) == 0x24) { + } else if (in_8(&lcd_reg[0x10000]) == 0x24) { /* * Small epson detected (705) */ @@ -296,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, lcd_bmp(logo_bmp); } -#ifdef CONFIG_VIDEO_SM501 +#if defined(CONFIG_VIDEO_SM501) int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr; diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index d588d8c..350af48 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -280,10 +280,10 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] if (argc > 1) { if (!strcmp(argv[1], "400")) { - /* PLB=133MHz, PLB/PCI=4 */ + /* PLB=133MHz, PLB/PCI=3 */ printf("Bootstrapping for 400MHz\n"); sdsdp[0]=0x8678624e; - sdsdp[1]=0x0947a030; + sdsdp[1]=0x095fa030; sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; } else if (!strcmp(argv[1], "533")) { diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index 78e2cb4..7f92d37 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -33,343 +33,9 @@ #include <asm/io.h> #include <ppc440.h> -#include "sdram.h" +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_DDR_DATA_EYE) -/*-----------------------------------------------------------------------------+ - * wait_for_dlllock. - +----------------------------------------------------------------------------*/ -static int wait_for_dlllock(void) -{ - unsigned long val; - int wait = 0; - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); - val = DDR0_17_DLLLOCKREG_UNLOCKED; - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) - /* dlllockreg bit on */ - return 0; - else - wait++; - } - debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); - debug("Waiting for dlllockreg bit to raise\n"); - - return -1; -} -#endif - -#if defined(CONFIG_DDR_DATA_EYE) -/*-----------------------------------------------------------------------------+ - * wait_for_dram_init_complete. - +----------------------------------------------------------------------------*/ -int wait_for_dram_init_complete(void) -{ - unsigned long val; - int wait = 0; - - /* --------------------------------------------------------------+ - * Wait for 'DRAM initialization complete' bit in status register - * -------------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_00); - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) - /* 'DRAM initialization complete' bit */ - return 0; - else - wait++; - } - - debug("DRAM initialization complete bit in status register did not rise\n"); - - return -1; -} - -#define NUM_TRIES 64 -#define NUM_READS 10 - -/*-----------------------------------------------------------------------------+ - * denali_core_search_data_eye. - +----------------------------------------------------------------------------*/ -void denali_core_search_data_eye(unsigned long memory_size) -{ - int k, j; - u32 val; - u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; - u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; - u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; - u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; - volatile u32 *ram_pointer; - u32 test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); - - for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { - /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - - passing_cases = 0; - - for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { - /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ - - /* write values */ - for (j=0; j<NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - } - - /* read values back */ - for (j=0; j<NUM_TRIES; j++) { - for (k=0; k<NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) - break; - } - - /* See if the dll_dqs_delay_X value passed.*/ - if (j < NUM_TRIES) { - /* Failed */ - passing_cases = 0; - /* break; */ - } else { - /* Passed */ - if (passing_cases == 0) - dll_dqs_delay_X_sw_val = dll_dqs_delay_X; - passing_cases++; - if (passing_cases >= max_passing_cases) { - max_passing_cases = passing_cases; - wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; - dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; - dll_dqs_delay_X_end_window = dll_dqs_delay_X; - } - } - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ - - } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ - - /* -----------------------------------------------------------+ - * Largest passing window is now detected. - * ----------------------------------------------------------*/ - - /* Compute dll_dqs_delay_X value */ - dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; - wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; - - debug("DQS calibration - Window detected:\n"); - debug("max_passing_cases = %d\n", max_passing_cases); - debug("wr_dqs_shift = %d\n", wr_dqs_shift); - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); - debug("dll_dqs_delay_X window = %d - %d\n", - dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_09=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_22=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_17=0x%08lx\n", val); - - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_18=0x%08lx\n", val); - - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_19=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ -} -#endif /* CONFIG_DDR_DATA_EYE */ #if defined(CONFIG_NAND_SPL) /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big @@ -428,14 +94,14 @@ long int initdram (int board_type) mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); - wait_for_dlllock(); + denali_wait_for_dlllock(); #endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ - denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20); + denali_core_search_data_eye(); #endif return (CFG_MBYTES_SDRAM << 20); diff --git a/board/esd/pmc440/sdram.h b/board/esd/pmc440/sdram.h deleted file mode 100644 index 7f847aa..0000000 --- a/board/esd/pmc440/sdram.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPD_SDRAM_DENALI_H_ -#define _SPD_SDRAM_DENALI_H_ - -#define ppcMsync sync -#define ppcMbar eieio - -/* General definitions */ -#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ -#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ -#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ -#define SDRAM_NONE 0 /* No DIMM detected in Slot */ -#define MAXRANKS 2 /* 2 ranks maximum */ - -/* Supported PLB Frequencies */ -#define PLB_FREQ_133MHZ 133333333 -#define PLB_FREQ_152MHZ 152000000 -#define PLB_FREQ_160MHZ 160000000 -#define PLB_FREQ_166MHZ 166666666 - -/* Denali Core Registers */ -#define SDRAM_DCR_BASE 0x10 - -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -/*-----------------------------------------------------------------------------+ - | Values for ddrcfga register - indirect addressing of these regs - +-----------------------------------------------------------------------------*/ - -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) - -#define DDR0_13 0x0D - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) - -#define DDR0_15 0x0F - -#define DDR0_16 0x10 - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) - -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_29 0x1D - -#define DDR0_30 0x1E - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 44f613e..9cee9f1 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -31,7 +31,9 @@ LIB = $(obj)lib$(VENDOR).a COBJS := sys_eeprom.o \ pixis.o \ - pq-mds-pib.o + pq-mds-pib.o \ + fsl_logo_bmp.o \ + fsl_diu_fb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c new file mode 100644 index 0000000..c1dc48c --- /dev/null +++ b/board/freescale/common/fsl_diu_fb.c @@ -0,0 +1,624 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <i2c.h> +#include <malloc.h> + +#ifdef CONFIG_FSL_DIU_FB + +#include "fsl_diu_fb.h" + + +#ifdef DEBUG +#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args) +#else +#define DPRINTF(fmt, args...) +#endif + + +struct fb_videomode { + const char *name; /* optional */ + unsigned int refresh; /* optional */ + unsigned int xres; + unsigned int yres; + unsigned int pixclock; + unsigned int left_margin; + unsigned int right_margin; + unsigned int upper_margin; + unsigned int lower_margin; + unsigned int hsync_len; + unsigned int vsync_len; + unsigned int sync; + unsigned int vmode; + unsigned int flag; +}; + +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ + +/* + * These parameters give default parameters + * for video output 1024x768, + * FIXME - change timing to proper amounts + * hsync 31.5kHz, vsync 60Hz + */ +static struct fb_videomode fsl_diu_mode_1024 = { + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_1280 = { + .name = "1280x1024-60", + .refresh = 60, + .xres = 1280, + .yres = 1024, + .pixclock = 9375, + .left_margin = 38, + .right_margin = 128, + .upper_margin = 2, + .lower_margin = 7, + .hsync_len = 216, + .vsync_len = 37, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* + * These are the fields of area descriptor(in DDR memory) for every plane + */ +struct diu_ad { + /* Word 0(32-bit) in DDR memory */ + unsigned int pix_fmt; /* hard coding pixel format */ + /* Word 1(32-bit) in DDR memory */ + unsigned int addr; + /* Word 2(32-bit) in DDR memory */ + unsigned int src_size_g_alpha; + /* Word 3(32-bit) in DDR memory */ + unsigned int aoi_size; + /* Word 4(32-bit) in DDR memory */ + unsigned int offset_xyi; + /* Word 5(32-bit) in DDR memory */ + unsigned int offset_xyd; + /* Word 6(32-bit) in DDR memory */ + unsigned int ckmax_r:8; + unsigned int ckmax_g:8; + unsigned int ckmax_b:8; + unsigned int res9:8; + /* Word 7(32-bit) in DDR memory */ + unsigned int ckmin_r:8; + unsigned int ckmin_g:8; + unsigned int ckmin_b:8; + unsigned int res10:8; + /* Word 8(32-bit) in DDR memory */ + unsigned int next_ad; + /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */ + unsigned int res1; + unsigned int res2; + unsigned int res3; +}__attribute__ ((packed)); + +/* + * DIU register map + */ +struct diu { + unsigned int desc[3]; + unsigned int gamma; + unsigned int pallete; + unsigned int cursor; + unsigned int curs_pos; + unsigned int diu_mode; + unsigned int bgnd; + unsigned int bgnd_wb; + unsigned int disp_size; + unsigned int wb_size; + unsigned int wb_mem_addr; + unsigned int hsyn_para; + unsigned int vsyn_para; + unsigned int syn_pol; + unsigned int thresholds; + unsigned int int_status; + unsigned int int_mask; + unsigned int colorbar[8]; + unsigned int filling; + unsigned int plut; +} __attribute__ ((packed)); + +struct diu_hw { + struct diu *diu_reg; + volatile unsigned int mode; /* DIU operation mode */ +}; + +struct diu_addr { + unsigned char * paddr; /* Virtual address */ + unsigned int offset; +}; + +#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */ + +/* + * Modes of operation of DIU + */ +#define MFB_MODE0 0 /* DIU off */ +#define MFB_MODE1 1 /* All three planes output to display */ +#define MFB_MODE2 2 /* Plane 1 to display, + * planes 2+3 written back to memory */ +#define MFB_MODE3 3 /* All three planes written back to memory */ +#define MFB_MODE4 4 /* Color bar generation */ + +#define MAX_CURS 32 + + + +static struct fb_info fsl_fb_info; +static struct diu_addr gamma, cursor; +static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32))); +static struct diu_ad dummy_ad __attribute__ ((aligned(32))); +static unsigned char *dummy_fb; +static struct diu_hw dr = { + .mode = MFB_MODE1, +}; + +int fb_enabled = 0; +int fb_initialized = 0; +const int default_xres = 1280; +const int default_pixel_format = 0x88882317; + +static int map_video_memory(struct fb_info *info, unsigned long bytes_align); +static void enable_lcdc(void); +static void disable_lcdc(void); +static int fsl_diu_enable_panel(struct fb_info *info); +static int fsl_diu_disable_panel(struct fb_info *info); +static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); +static u32 get_busfreq(void); + + +int fsl_diu_init(int xres, + unsigned int pixel_format, + int gamma_fix, + unsigned char *splash_bmp) +{ + struct fb_videomode *fsl_diu_mode_db; + struct diu_ad *ad = &fsl_diu_fb_ad; + struct diu *hw; + struct fb_info *info = &fsl_fb_info; + struct fb_var_screeninfo *var = &info->var; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; + unsigned char *gamma_table_base; + unsigned int i, j; + unsigned long speed_ccb, temp, pixval; + + DPRINTF("Enter fsl_diu_init\n"); + dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET); + hw = (struct diu *) dr.diu_reg; + + disable_lcdc(); + + if (xres == 1280) { + fsl_diu_mode_db = &fsl_diu_mode_1280; + } else { + fsl_diu_mode_db = &fsl_diu_mode_1024; + } + + if (0 == fb_initialized) { + allocate_buf(&gamma, 768, 32); + DPRINTF("gamma is allocated @ 0x%x\n", + (unsigned int)gamma.paddr); + allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32); + DPRINTF("curosr is allocated @ 0x%x\n", + (unsigned int)cursor.paddr); + + /* create a dummy fb and dummy ad */ + dummy_fb = malloc(64); + if (NULL == dummy_fb) { + printf("Cannot allocate dummy fb\n"); + return -1; + } + dummy_ad.addr = cpu_to_le32((unsigned int)dummy_fb); + dummy_ad.pix_fmt = 0x88882317; + dummy_ad.src_size_g_alpha = 0x04400000; /* alpha = 0 */ + dummy_ad.aoi_size = 0x02000400; + dummy_ad.offset_xyi = 0; + dummy_ad.offset_xyd = 0; + dummy_ad.next_ad = 0; + /* Memory allocation for framebuffer */ + if (map_video_memory(info, 32)) { + printf("Unable to allocate fb memory 1\n"); + return -1; + } + } else { + memset(info->screen_base, 0, info->smem_len); + } + + dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; + dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; + dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; + DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); + DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]); + + /* read mode info */ + var->xres = fsl_diu_mode_db->xres; + var->yres = fsl_diu_mode_db->yres; + var->bits_per_pixel = 32; + var->pixclock = fsl_diu_mode_db->pixclock; + var->left_margin = fsl_diu_mode_db->left_margin; + var->right_margin = fsl_diu_mode_db->right_margin; + var->upper_margin = fsl_diu_mode_db->upper_margin; + var->lower_margin = fsl_diu_mode_db->lower_margin; + var->hsync_len = fsl_diu_mode_db->hsync_len; + var->vsync_len = fsl_diu_mode_db->vsync_len; + var->sync = fsl_diu_mode_db->sync; + var->vmode = fsl_diu_mode_db->vmode; + info->line_length = var->xres * var->bits_per_pixel / 8; + info->logo_size = 0; + info->logo_height = 0; + + ad->pix_fmt = pixel_format; + ad->addr = cpu_to_le32((unsigned int)info->screen_base); + ad->src_size_g_alpha + = cpu_to_le32((var->yres << 12) | var->xres); + /* fix me. AOI should not be greater than display size */ + ad->aoi_size = cpu_to_le32(( var->yres << 16) | var->xres); + ad->offset_xyi = 0; + ad->offset_xyd = 0; + + /* Disable chroma keying function */ + ad->ckmax_r = 0; + ad->ckmax_g = 0; + ad->ckmax_b = 0; + + ad->ckmin_r = 255; + ad->ckmin_g = 255; + ad->ckmin_b = 255; + + gamma_table_base = gamma.paddr; + DPRINTF("gamma_table_base is allocated @ 0x%x\n", + (unsigned int)gamma_table_base); + + /* Prep for DIU init - gamma table */ + + for (i = 0; i <= 2; i++) + for (j = 0; j <= 255; j++) + *gamma_table_base++ = j; + + if (gamma_fix == 1) { /* fix the gamma */ + DPRINTF("Fix gamma table\n"); + gamma_table_base = gamma.paddr; + for (i = 0; i < 256*3; i++) { + gamma_table_base[i] = (gamma_table_base[i] << 2) + | ((gamma_table_base[i] >> 6) & 0x03); + } + } + + DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw); + + /* Program DIU registers */ + + hw->gamma = (unsigned int) gamma.paddr; + hw->cursor= (unsigned int) cursor.paddr; + hw->bgnd = 0x007F7F7F; /* BGND */ + hw->bgnd_wb = 0; /* BGND_WB */ + hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */ + hw->wb_size = 0; /* WB SIZE */ + hw->wb_mem_addr = 0; /* WB MEM ADDR */ + hw->hsyn_para = var->left_margin << 22 | /* BP_H */ + var->hsync_len << 11 | /* PW_H */ + var->right_margin; /* FP_H */ + hw->vsyn_para = var->upper_margin << 22 | /* BP_V */ + var->vsync_len << 11 | /* PW_V */ + var->lower_margin; /* FP_V */ + + /* Pixel Clock configuration */ + DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq()); + speed_ccb = get_busfreq(); + + DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); + temp = 1; + temp *= 1000000000; + temp /= var->pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + DPRINTF("DIU pixval = %lu\n", pixval); + + hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ + hw->thresholds = 0x00037800; /* The Thresholds */ + hw->int_status = 0; /* INTERRUPT STATUS */ + hw->int_mask = 0; /* INT MASK */ + hw->plut = 0x01F5F666; + + /* Modify PXCLK in GUTS CLKDVDR */ + DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + temp = *guts_clkdvdr & 0x2000FFFF; + *guts_clkdvdr = temp; /* turn off clock */ + *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); + DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + + fb_initialized = 1; + + if (splash_bmp) { + info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0); + info->logo_size = info->logo_height * info->line_length; + DPRINTF("logo height %d, logo_size 0x%x\n", + info->logo_height,info->logo_size); + } + + /* Enable the DIU */ + fsl_diu_enable_panel(info); + enable_lcdc(); + + return 0; +} + +char *fsl_fb_open(struct fb_info **info) +{ + *info = &fsl_fb_info; + return (char *) ((unsigned int)(*info)->screen_base + + (*info)->logo_size); +} + +void fsl_diu_close(void) +{ + struct fb_info *info = &fsl_fb_info; + fsl_diu_disable_panel(info); +} + +static int fsl_diu_enable_panel(struct fb_info *info) +{ + struct diu *hw = dr.diu_reg; + struct diu_ad *ad = &fsl_diu_fb_ad; + + DPRINTF("Entered: enable_panel\n"); + if (hw->desc[0] != (unsigned int)ad) + hw->desc[0] = (unsigned int)ad; + DPRINTF("desc[0] = 0x%x\n", hw->desc[0]); + return 0; +} + +static int fsl_diu_disable_panel(struct fb_info *info) +{ + struct diu *hw = dr.diu_reg; + + DPRINTF("Entered: disable_panel\n"); + if (hw->desc[0] != (unsigned int)&dummy_ad) + hw->desc[0] = (unsigned int)&dummy_ad; + return 0; +} + +static int map_video_memory(struct fb_info *info, unsigned long bytes_align) +{ + unsigned long offset; + unsigned long mask; + + DPRINTF("Entered: map_video_memory\n"); + /* allocate maximum 1280*1024 with 32bpp */ + info->smem_len = 1280 * 4 *1024 + bytes_align; + DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len); + info->screen_base = malloc(info->smem_len); + if (info->screen_base == NULL) { + printf("Unable to allocate fb memory\n"); + return -1; + } + info->smem_start = (unsigned int) info->screen_base; + mask = bytes_align - 1; + offset = (unsigned long)info->screen_base & mask; + if (offset) { + info->screen_base += offset; + info->smem_len = info->smem_len - (bytes_align - offset); + } else + info->smem_len = info->smem_len - bytes_align; + + info->screen_size = info->smem_len; + + DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n", + info->smem_start, info->smem_len); + + return 0; +} + +static void enable_lcdc(void) +{ + struct diu *hw = dr.diu_reg; + + DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); + if (!fb_enabled) { + hw->diu_mode = dr.mode; + fb_enabled++; + } + DPRINTF("diu_mode = %d\n", hw->diu_mode); +} + +static void disable_lcdc(void) +{ + struct diu *hw = dr.diu_reg; + + DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); + if (fb_enabled) { + hw->diu_mode = 0; + fb_enabled = 0; + } +} + +static u32 get_busfreq(void) +{ + u32 fs_busfreq = 0; + + fs_busfreq = get_bus_freq(0); + return fs_busfreq; +} + +/* + * Align to 64-bit(8-byte), 32-byte, etc. + */ +static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) +{ + u32 offset, ssize; + u32 mask; + + DPRINTF("Entered: allocate_buf\n"); + ssize = size + bytes_align; + buf->paddr = malloc(ssize); + if (!buf->paddr) + return -1; + + memset(buf->paddr, 0, ssize); + mask = bytes_align - 1; + offset = (u32)buf->paddr & mask; + if (offset) { + buf->offset = bytes_align - offset; + buf->paddr = (unsigned char *) ((u32)buf->paddr + offset); + } else + buf->offset = 0; + return 0; +} + +int fsl_diu_display_bmp(unsigned char *bmp, + int xoffset, + int yoffset, + int transpar) +{ + struct fb_info *info = &fsl_fb_info; + unsigned char r, g, b; + unsigned int *fb_t, val; + unsigned char *bitmap; + unsigned int palette[256]; + int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp; + + if (!bmp) { + printf("Must supply a bitmap address\n"); + return 0; + } + + raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24); + width = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18]; + height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22]; + bpp = (bmp[29] << 8) | (bmp[28]); + ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24); + bitmap = bmp + raster; + cpp = info->var.bits_per_pixel / 8; + + DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp); + DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap); + DPRINTF("width = %d\n", width); + DPRINTF("height = %d\n", height); + DPRINTF("bpp = %d\n", bpp); + DPRINTF("ncolors = %d\n", ncolors); + + DPRINTF("xres = %d\n", info->var.xres); + DPRINTF("yres = %d\n", info->var.yres); + DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base); + + if (((width+xoffset) > info->var.xres) || + ((height+yoffset) > info->var.yres)) { + printf("bitmap is out of range, image too large or too much offset\n"); + return 0; + } + if (bpp < 24) { + for (i = 0, offset = 54; i < ncolors; i++, offset += 4) + palette[i] = (bmp[offset+2] << 16) + + (bmp[offset+1] << 8) + bmp[offset]; + } + + switch (bpp) { + case 1: + for (y = height - 1; y >= 0; y--) { + fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); + for (x = 0; x < width; x += 8) { + b = *bitmap++; + for (k = 0; k < 8; k++) { + if (b & 0x80) + *fb_t = palette[1]; + else + *fb_t = palette[0]; + b = b << 1; + } + } + for (i = (width / 2) % 4; i > 0; i--) + bitmap++; + } + break; + case 4: + for (y = height - 1; y >= 0; y--) { + fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); + for (x = 0; x < width; x += 2) { + b = *bitmap++; + r = (b >> 4) & 0x0F; + g = b & 0x0F; + *fb_t++ = palette[r]; + *fb_t++ = palette[g]; + } + for (i = (width / 2) % 4; i > 0; i--) + bitmap++; + } + break; + case 8: + for (y = height - 1; y >= 0; y--) { + fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); + for (x = 0; x < width; x++) { + *fb_t++ = palette[ *bitmap++ ]; + } + for (i = (width / 2) % 4; i > 0; i--) + bitmap++; + } + break; + case 24: + for (y = height - 1; y >= 0; y--) { + fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); + for (x = 0; x < width; x++) { + b = *bitmap++; + g = *bitmap++; + r = *bitmap++; + val = (r << 16) + (g << 8) + b; + *fb_t++ = val; + } + for (; (x % 4) != 0; x++) /* 4-byte alignment */ + bitmap++; + } + break; + } + + return height; +} + +void fsl_diu_clear_screen(void) +{ + struct fb_info *info = &fsl_fb_info; + + memset(info->screen_base, 0, info->smem_len); +} +#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h new file mode 100644 index 0000000..6deba32 --- /dev/null +++ b/board/freescale/common/fsl_diu_fb.h @@ -0,0 +1,69 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +struct fb_var_screeninfo { + unsigned int xres; /* visible resolution */ + unsigned int yres; + + unsigned int bits_per_pixel; /* guess what */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + unsigned int pixclock; /* pixel clock in ps (pico seconds) */ + unsigned int left_margin; /* time from sync to picture */ + unsigned int right_margin; /* time from picture to sync */ + unsigned int upper_margin; /* time from sync to picture */ + unsigned int lower_margin; + unsigned int hsync_len; /* length of horizontal sync */ + unsigned int vsync_len; /* length of vertical sync */ + unsigned int sync; /* see FB_SYNC_* */ + unsigned int vmode; /* see FB_VMODE_* */ + unsigned int rotate; /* angle we rotate counter clockwise */ +}; + +struct fb_info { + struct fb_var_screeninfo var; /* Current var */ + unsigned long smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + unsigned int smem_len; /* Length of frame buffer mem */ + unsigned int type; /* see FB_TYPE_* */ + unsigned int line_length; /* length of a line in bytes */ + + char *screen_base; + unsigned long screen_size; + int logo_height; + unsigned int logo_size; +}; + + +extern char *fsl_fb_open(struct fb_info **info); +extern int fsl_diu_init(int xres, + unsigned int pixel_format, + int gamma_fix, + unsigned char *splash_bmp); +extern void fsl_diu_clear_screen(void); +extern int fsl_diu_display_bmp(unsigned char *bmp, + int xoffset, + int yoffset, + int transpar); diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c new file mode 100644 index 0000000..956dbee --- /dev/null +++ b/board/freescale/common/fsl_logo_bmp.c @@ -0,0 +1,878 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*--------------------------------------------------------------------------- + * FSL_Logo_BMP -- + * + * A 340x128x4bpp BMP logo. + *--------------------------------------------------------------------------- + */ +unsigned int FSL_Logo_BMP[] = { +0x424d765c, +0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000, +0x0000005c,0x0000130b,0x0000130b,0x00001000,0x00000000,0x00000402,0x04000d91, +0xbc000b51,0x67001536,0x9a000f2a,0x4b005050,0x50009090,0x90000c70,0x92002e2f, +0x2e00cfcf,0xcf007c82,0x7c00fbfd,0xfb006f70,0x6f00b0b0,0xb00004bd,0xfa000542, +0xf9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, 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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, 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a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile new file mode 100644 index 0000000..76087c1 --- /dev/null +++ b/board/freescale/mpc8610hpcd/Makefile @@ -0,0 +1,59 @@ +# Copyright 2007 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o \ + ../common/sys_eeprom.o \ + ../common/pixis.o \ + mpc8610hpcd_diu.o \ + ../common/fsl_diu_fb.o + +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk new file mode 100644 index 0000000..64ac4dc --- /dev/null +++ b/board/freescale/mpc8610hpcd/config.mk @@ -0,0 +1,25 @@ +# Copyright 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2 diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S new file mode 100644 index 0000000..4d811e1 --- /dev/null +++ b/board/freescale/mpc8610hpcd/init.S @@ -0,0 +1,147 @@ +/* + * Copyright 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <config.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <mpc86xx.h> + +#define LAWAR_TRGT_PCI1 0x00000000 +#define LAWAR_TRGT_PCIE1 0x00200000 +#define LAWAR_TRGT_PCIE2 0x00100000 +#define LAWAR_TRGT_LBC 0x00400000 +#define LAWAR_TRGT_DDR 0x00f00000 + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#else +#define LAWBAR1 0 +#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) + +#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) + +#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + + blr diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c new file mode 100644 index 0000000..617881a --- /dev/null +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -0,0 +1,546 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define DEBUG +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_86xx.h> +#include <asm/immap_fsl_pci.h> +#include <spd.h> +#include <asm/io.h> + + +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#include "../common/pixis.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif + +void sdram_init(void); +long int fixed_sdram(void); + +/* called before any console output */ +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ + + return 0; +} + +int misc_init_r(void) +{ + u8 tmp_val, version; + + /*Do not use 8259PIC*/ + tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); + out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); + + /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ + version = in8(PIXIS_BASE + PIXIS_PVER); + if(version >= 0x07) { + tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); + out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); + } + + /* Using this for DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n",tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n",tmp_val); + +#ifdef CONFIG_FSL_DIU_FB + mpc8610hpcd_diu_init(); +#endif + + return 0; +} + +int checkboard(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + + puts("Board: MPC8610HPCD\n"); + + mcm->abcr |= 0x00010000; /* 0 */ + mcm->hpmr3 = 0x80000008; /* 4c */ + mcm->hpmr0 = 0; + mcm->hpmr1 = 0; + mcm->hpmr2 = 0; + mcm->hpmr4 = 0; + mcm->hpmr5 = 0; + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram(); +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + puts(" DDR: "); + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + puts("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +long int fixed_sdram(void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + uint d_init; + + ddr->cs0_bnds = 0x0000001f; + ddr->cs0_config = 0x80010202; + + ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_0 = 0x00260802; + ddr->timing_cfg_1 = 0x3935d322; + ddr->timing_cfg_2 = 0x14904cc8; + ddr->sdram_mode_1 = 0x00480432; + ddr->sdram_mode_2 = 0x00000000; + ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ + ddr->sdram_data_init = 0xDEADBEEF; + ddr->sdram_clk_cntl = 0x03800000; + ddr->sdram_cfg_2 = 0x04400010; + +#if defined(CONFIG_DDR_ECC) + ddr->err_int_en = 0x0000000d; + ddr->err_disable = 0x00000000; + ddr->err_sbe = 0x00010000; +#endif + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) + udelay(1000); + + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + return 512 * 1024 * 1024; +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} + +#endif + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, + {} +}; +#endif + + +static struct pci_controller pci1_hose = { +#ifndef CONFIG_PCI_PNP +config_table:pci_mpc86xxcts_config_table +#endif +}; +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +int first_free_busno = 0; + +void pci_init_board(void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_configured = (io_sel == 1) || (io_sel == 4); + int pcie_ep = (host_agent == 0) || (host_agent == 2) || + (host_agent == 5); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { + printf(" PCIe 1 connected to Uli as %s (base address %x)\n", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) + pci->pme_msg_det = 0xffffffff; + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCI-Express 1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + } else + puts(" PCI-Express 1: Disabled\n"); + } +#else + puts("PCI-Express 1: Disabled\n"); +#endif /* CONFIG_PCIE1 */ + + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + + int pcie_configured = (io_sel == 0) || (io_sel == 4); + int pcie_ep = (host_agent == 0) || (host_agent == 1) || + (host_agent == 4); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { + printf(" PCI-Express 2 connected to slot as %s" \ + " (base address %x)\n", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) + pci->pme_msg_det = 0xffffffff; + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCI-Express 2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } else + puts(" PCI-Express 2: Disabled\n"); + } +#else + puts("PCI-Express 2: Disabled\n"); +#endif /* CONFIG_PCIE2 */ + + +#ifdef CONFIG_PCI1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + int pci_agent = (host_agent >= 4) && (host_agent <= 6); + + if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { + printf(" PCI connected to PCI slots as %s" \ + " (base address %x)\n", + pci_agent ? "Agent" : "Host", + (uint)pci); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, + (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCI on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + + } else + puts(" PCI: Disabled\n"); + } +#endif /* CONFIG_PCI1 */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } + +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + +} +#endif + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long +get_board_sys_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + ulong a; + + a = PIXIS_BASE + PIXIS_SPD; + i = in8(a); + i &= 0x07; + + switch (i) { + case 0: + val = 33333000; + break; + case 1: + val = 39999600; + break; + case 2: + val = 49999500; + break; + case 3: + val = 66666000; + break; + case 4: + val = 83332500; + break; + case 5: + val = 99999000; + break; + case 6: + val = 133332000; + break; + case 7: + val = 166665000; + break; + } + + return val; +} diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c new file mode 100644 index 0000000..b70637f --- /dev/null +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -0,0 +1,177 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_FSL_DIU_FB + +#include "../common/pixis.h" +#include "../common/fsl_diu_fb.h" + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <devices.h> +#include <video_fb.h> +#endif + +extern unsigned int FSL_Logo_BMP[]; + +static int xres, yres; + + +void mpc8610hpcd_diu_init(void) +{ + char *monitor_port; + int gamma_fix; + unsigned int pixel_format; + unsigned char tmp_val; + unsigned char pixis_arch; + + tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); + pixis_arch = in8(PIXIS_BASE + PIXIS_VER); + + monitor_port = getenv("monitor"); + if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */ + xres = 1280; + yres = 1024; + if (pixis_arch == 0x01) + pixel_format = 0x88882317; + else + pixel_format = 0x88883316; + gamma_fix = 0; + out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08); + + } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + gamma_fix = 0; + out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); + + } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */ + xres = 1280; + yres = 1024; + pixel_format = 0x88883316; + gamma_fix = 1; + out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7); + + } else { /* DVI */ + xres = 1280; + yres = 1024; + pixel_format = 0x88882317; + gamma_fix = 0; + out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08); + } + + fsl_diu_init(xres, pixel_format, gamma_fix, + (unsigned char *)FSL_Logo_BMP); +} + +int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + unsigned int addr; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!strncmp(argv[1],"init",4)) { +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + fsl_diu_clear_screen(); + drv_video_init(); +#else + mpc8610hpcd_diu_init(); +#endif + } else { + addr = simple_strtoul(argv[1], NULL, 16); + fsl_diu_clear_screen(); + fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); + } + + return 0; +} + +U_BOOT_CMD( + diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp, + "diufb init | addr - Init or Display BMP file\n", + "init\n - initialize DIU\n" + "addr\n - display bmp at address 'addr'\n" + ); + + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + +/* + * The Graphic Device + */ +GraphicDevice ctfb; +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) &ctfb; + struct fb_info *info; + + mpc8610hpcd_diu_init(); + + /* fill in Graphic device struct */ + sprintf(pGD->modeIdent, + "%dx%dx%d %ldkHz %ldHz", + xres, yres, 32, 64, 60); + + pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); + pGD->winSizeX = xres; + pGD->winSizeY = yres - info->logo_height; + pGD->plnSizeX = pGD->winSizeX; + pGD->plnSizeY = pGD->winSizeY; + + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + + pGD->isaBase = 0; + pGD->pciBase = 0; + pGD->memSize = info->screen_size - info->logo_size; + + /* Cursor Start Address */ + pGD->dprBase = 0; + pGD->vprBase = 0; + pGD->cprBase = 0; + + return (void *)pGD; +} + +void video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + return; +} + +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ + +#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds new file mode 100644 index 0000000..ae9c6c4 --- /dev/null +++ b/board/freescale/mpc8610hpcd/u-boot.lds @@ -0,0 +1,135 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/freescale/mpc8610hpcd/init.o (.bootpg) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 931be9f..8278789 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -27,11 +27,8 @@ #include <asm/immap_fsl_pci.h> #include <spd.h> #include <asm/io.h> - -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif +#include <libfdt.h> +#include <fdt_support.h> #include "../common/pixis.h" @@ -324,36 +321,47 @@ void pci_init_board(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + int node, tmp[2]; + const char *path; - ft_cpu_setup(blob, bd); + fdt_fixup_ethernet(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 4, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); + + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); + + fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { #ifdef CONFIG_PCI1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pci1_hose.last_busno - pci1_hose.first_busno; - debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif #ifdef CONFIG_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pci2_hose.last_busno - pci2_hose.first_busno; - debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif + } } #endif diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile index 8aa7e7c..ddfd2ef 100644 --- a/board/inka4x0/Makefile +++ b/board/inka4x0/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c deleted file mode 100644 index b138655..0000000 --- a/board/inka4x0/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CPU to flash interface is 8-bit, so make declaration accordingly - */ -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - extern void flash_preinit(void); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = - flash_get_size((FPW *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM116DB: - printf ("AM29LV116DB (16Mbit, bottom boot sect)\n"); - break; - case FLASH_AMLV128U: - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (uchar)AMD_ID_LV116DB: - debug ("Chip: AM29LV116DB\n"); - info->flash_id += FLASH_AM116DB; - info->sector_count = 35; - info->size = 0x00200000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * (64 << 10)) - 0x00030000; - break; /* => 2 MB */ - - case (FPW)AMD_ID_LV160B: - debug ("Chip: AM29LV160MB\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * 2 * (64 << 10)) - 0x00060000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr = (FPWV*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - addr[0x0555] = (FPW)0x00800080; - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FPWV*)(info->start[sect]); - addr[0] = (FPW)0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FPWV*)(info->start[l_sect]); - while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FPWV*)info->start[0]; - addr[0] = (FPW)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int i, rc = 0; - - for (i = 0; i < cnt; i++) - if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) { - return (rc); - } - - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h new file mode 100644 index 0000000..7eb1f50 --- /dev/null +++ b/board/inka4x0/hyb25d512160bf-5.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 478a331..5157f7d 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -31,10 +31,18 @@ #include <mpc5xxx.h> #include <pci.h> -#if defined(CONFIG_MPC5200_DDR) +#if defined(CONFIG_DDR_MT46V16M16) #include "mt46v16m16-75.h" -#else +#elif defined(CONFIG_SDR_MT48LC16M16A2) #include "mt48lc16m16a2-75.h" +#elif defined(CONFIG_DDR_MT46V32M16) +#include "mt46v32m16.h" +#elif defined(CONFIG_DDR_HYB25D512160BF) +#include "hyb25d512160bf.h" +#elif defined(CONFIG_DDR_K4H511638C) +#include "k4h511638c.h" +#else +#error "INKA4x0 SDRAM: invalid chip type specified!" #endif #ifndef CFG_RAMBOOT @@ -88,7 +96,7 @@ long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT - ulong test1, test2; + long test1, test2; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -108,9 +116,9 @@ long int initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -175,7 +183,7 @@ void flash_preinit(void) int misc_init_f (void) { - uchar tmp[10]; + char tmp[10]; int i, br; i = getenv_r("brightness", tmp, sizeof(tmp)); diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h new file mode 100644 index 0000000..70cc405 --- /dev/null +++ b/board/inka4x0/k4h511638c.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h index f650faa..a78e50e 100644 --- a/board/inka4x0/mt46v16m16-75.h +++ b/board/inka4x0/mt46v16m16-75.h @@ -23,15 +23,10 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONTROL 0x714F0F00 #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h new file mode 100644 index 0000000..7eb1f50 --- /dev/null +++ b/board/inka4x0/mt46v32m16-75.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h index 13a97ac..1547725 100644 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ b/board/inka4x0/mt48lc16m16a2-75.h @@ -21,27 +21,10 @@ * MA 02111-1307 USA */ -#define SDRAM_DDR 1 /* is SDR */ +#define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh index 53b0d1e..4b94d8f 100755 --- a/board/integratorap/split_by_variant.sh +++ b/board/integratorap/split_by_variant.sh @@ -14,7 +14,7 @@ echo " 1 /* Integrator/AP */" >> tmp.fil cpu="arm_intcm" variant="unknown core module" -if [ "$1" == "" ] +if [ "$1" = "" ] then echo "$0:: No parameters - using arm_intcm" else @@ -84,7 +84,7 @@ else esac fi -if [ "$cpu" == "arm_intcm" ] +if [ "$cpu" = "arm_intcm" ] then echo "/* Core module undefined/not ported */" >> tmp.fil echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh index 37ae517..79a6a9d 100755 --- a/board/integratorcp/split_by_variant.sh +++ b/board/integratorcp/split_by_variant.sh @@ -12,7 +12,7 @@ echo " 1 /* Integrator/CP */" >> tmp.fil cpu="arm_intcm" variant="unknown core module" -if [ "$1" == "" ] +if [ "$1" = "" ] then echo "$0:: No parameters - using arm_intcm" else @@ -79,7 +79,7 @@ else fi -if [ "$cpu" == "arm_intcm" ] +if [ "$cpu" = "arm_intcm" ] then echo "/* Core module undefined/not ported */" >> tmp.fil echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil diff --git a/board/korat/korat.c b/board/korat/korat.c index 7cb9ee1..199c1ff 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006 @@ -26,6 +26,7 @@ */ #include <common.h> +#include <asm/gpio.h> #include <asm/processor.h> #include <asm-ppc/io.h> #include <i2c.h> @@ -40,7 +41,6 @@ ulong flash_get_size(ulong base, int banknum); int board_early_init_f(void) { u32 sdr0_pfc1, sdr0_pfc2; - u32 gpio0_ir; u32 reg; int eth; @@ -48,102 +48,6 @@ int board_early_init_f(void) mtdcr(ebccfgd, 0xb8400000); /*-------------------------------------------------------------------- - * Setup the GPIO pins - * - * Korat GPIO usage: - * - * Init. - * Pin Source I/O value Function - * ------ ------ --- ----- --------------------------------- - * GPIO00 Alt1 I/O x PerAddr07 - * GPIO01 Alt1 I/O x PerAddr06 - * GPIO02 Alt1 I/O x PerAddr05 - * GPIO03 GPIO x x GPIO03 to expansion bus connector - * GPIO04 GPIO x x GPIO04 to expansion bus connector - * GPIO05 GPIO x x GPIO05 to expansion bus connector - * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) - * GPIO07 Alt1 O x PerCS2 (CPLD) - * GPIO08 Alt1 O x PerCS3 to expansion bus connector - * GPIO09 Alt1 O x PerCS4 to expansion bus connector - * GPIO10 Alt1 O x PerCS5 to expansion bus connector - * GPIO11 Alt1 I x PerErr - * GPIO12 GPIO O 0 ATMega !Reset - * GPIO13 GPIO O 1 SPI Atmega !SS - * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) - * GPIO15 GPIO O 0 CPU Run LED !On - * GPIO16 Alt1 O x GMC1TxD0 - * GPIO17 Alt1 O x GMC1TxD1 - * GPIO18 Alt1 O x GMC1TxD2 - * GPIO19 Alt1 O x GMC1TxD3 - * GPIO20 Alt1 O x RejectPkt0 - * GPIO21 Alt1 O x RejectPkt1 - * GPIO22 GPIO I x PGOOD_DDR - * GPIO23 Alt1 O x SCPD0 - * GPIO24 Alt1 O x GMC0TxD2 - * GPIO25 Alt1 O x GMC0TxD3 - * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) - * GPIO27 GPIO O 0 PHY #0 1000BASE-X - * GPIO28 GPIO O 0 PHY #1 1000BASE-X - * GPIO29 GPIO I x Test jumper !Present - * GPIO30 GPIO I x SFP module #0 !Present - * GPIO31 GPIO I x SFP module #1 !Present - * - * GPIO32 GPIO O 1 SFP module #0 Tx !Enable - * GPIO33 GPIO O 1 SFP module #1 Tx !Enable - * GPIO34 Alt2 I x !UART1_CTS - * GPIO35 Alt2 O x !UART1_RTS - * GPIO36 Alt1 I x !UART0_CTS - * GPIO37 Alt1 O x !UART0_RTS - * GPIO38 Alt2 O x UART1_Tx - * GPIO39 Alt2 I x UART1_Rx - * GPIO40 Alt1 I x IRQ0 (Ethernet 0) - * GPIO41 Alt1 I x IRQ1 (Ethernet 1) - * GPIO42 Alt1 I x IRQ2 (PCI interrupt) - * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) - * GPIO44 xxxx x x (grounded through pulldown) - * GPIO45 GPIO O 0 PHY #0 Enable - * GPIO46 GPIO O 0 PHY #1 Enable - * GPIO47 GPIO I x Reset switch !Pressed - * GPIO48 GPIO I x Shutdown switch !Pressed - * GPIO49 xxxx x x (reserved for trace port) - * . . . . . - * . . . . . - * . . . . . - * GPIO63 xxxx x x (reserved for trace port) - *-------------------------------------------------------------------*/ - - out_be32((u32 *) GPIO0_OR, 0x00060000); - out_be32((u32 *) GPIO1_OR, 0xC0000000); - - out_be32((u32 *) GPIO0_OSRL, 0x54055400); - out_be32((u32 *) GPIO0_OSRH, 0x55015000); - out_be32((u32 *) GPIO1_OSRL, 0x02180000); - out_be32((u32 *) GPIO1_OSRH, 0x00000000); - - out_be32((u32 *) GPIO0_TSRL, 0x54055500); - out_be32((u32 *) GPIO0_TSRH, 0x00015000); - out_be32((u32 *) GPIO1_TSRL, 0x00000000); - out_be32((u32 *) GPIO1_TSRH, 0x00000000); - - out_be32((u32 *) GPIO0_TCR, 0x000FF0D8); - out_be32((u32 *) GPIO1_TCR, 0xD6060000); - - out_be32((u32 *) GPIO0_ISR1L, 0x54000100); - out_be32((u32 *) GPIO0_ISR1H, 0x00500000); - out_be32((u32 *) GPIO1_ISR1L, 0x00405500); - out_be32((u32 *) GPIO1_ISR1H, 0x00000000); - - out_be32((u32 *) GPIO0_ISR2L, 0x00000000); - out_be32((u32 *) GPIO0_ISR2H, 0x00000000); - out_be32((u32 *) GPIO1_ISR2L, 0x04010000); - out_be32((u32 *) GPIO1_ISR2H, 0x00000000); - - out_be32((u32 *) GPIO0_ISR3L, 0x00000000); - out_be32((u32 *) GPIO0_ISR3H, 0x00000000); - out_be32((u32 *) GPIO1_ISR3L, 0x00000000); - out_be32((u32 *) GPIO1_ISR3H, 0x00000000); - - /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(uic0sr, 0xffffffff); /* clear all */ @@ -176,9 +80,8 @@ int board_early_init_f(void) /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. */ - gpio0_ir = in_be32((u32 *) GPIO0_IR); for (eth = 0; eth < 2; ++eth) { - if (gpio0_ir & (0x00000001 << (1 - eth))) { + if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ out_8((u8 *) CFG_CPLD_BASE + 0x06, @@ -187,14 +90,13 @@ int board_early_init_f(void) } else { /* SFP module present: configure PHY for fiber and enable output */ - out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) | - (0x00000001 << (4 - eth))); - out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) & - ~(0x00000001 << (31 - eth))); + gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1); + gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0); } } /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ - out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000); + gpio_write_bit(CFG_GPIO_PHY0_EN, 1); + gpio_write_bit(CFG_GPIO_PHY1_EN, 1); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -525,20 +427,19 @@ int checkboard(void) { char const *const s = getenv("serial#"); u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); - u32 const gpio0_or = in_be32((u32 *) GPIO0_OR); printf("Board: Korat, Rev. %X", rev); if (s != NULL) printf(", serial# %s", s); printf(", Ethernet PHY 0: "); - if (gpio0_or & 0x00000010) + if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL)) printf("fiber"); else printf("copper"); printf(", PHY 1: "); - if (gpio0_or & 0x00000008) + if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL)) printf("fiber"); else printf("copper"); diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 399da8a..affaeff 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -36,8 +36,6 @@ #include <asm/io.h> #include <ppc440.h> -#include "sdram.h" - /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory * region. Right now the cache should still be disabled in U-Boot because of the @@ -54,8 +52,13 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); +extern void dflush(void); static u32 is_ecc_enabled(void) { @@ -87,330 +90,6 @@ void board_add_ram_info(int use_default) printf(", CL%d)", val); } -static int wait_for_dlllock(void) -{ - u32 val; - int wait = 0; - - /* - * Wait for the DCC master delay line to finish calibration - */ - mtdcr(ddrcfga, DDR0_17); - val = DDR0_17_DLLLOCKREG_UNLOCKED; - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) - /* dlllockreg bit on */ - return 0; - else - wait++; - } - debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); - debug("Waiting for dlllockreg bit to raise\n"); - - return -1; -} - -#if defined(CONFIG_DDR_DATA_EYE) -int wait_for_dram_init_complete(void) -{ - u32 val; - int wait = 0; - - /* - * Wait for 'DRAM initialization complete' bit in status register - */ - mtdcr(ddrcfga, DDR0_00); - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) - /* 'DRAM initialization complete' bit */ - return 0; - else - wait++; - } - - debug("DRAM initialization complete bit in status register did not rise\n"); - - return -1; -} - -#define NUM_TRIES 64 -#define NUM_READS 10 - -void denali_core_search_data_eye(u32 start_addr, u32 memory_size) -{ - int k, j; - u32 val; - u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; - u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; - u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; - u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; - volatile u32 *ram_pointer; - u32 test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - ram_pointer = (volatile u32 *)start_addr; - - for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { - /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ - - /* - * De-assert 'start' parameter. - */ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* - * Set 'wr_dqs_shift' - */ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - - /* - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - */ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - - passing_cases = 0; - - for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { - /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ - /* - * Set 'dll_dqs_delay_X'. - */ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* - * Assert 'start' parameter. - */ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* - * Wait for the DCC master delay line to finish calibration - */ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", - wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ - - /* write values */ - for (j=0; j<NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - } - - /* read values back */ - for (j=0; j<NUM_TRIES; j++) { - for (k=0; k<NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) - break; - } - - /* See if the dll_dqs_delay_X value passed.*/ - if (j < NUM_TRIES) { - /* Failed */ - passing_cases = 0; - /* break; */ - } else { - /* Passed */ - if (passing_cases == 0) - dll_dqs_delay_X_sw_val = dll_dqs_delay_X; - passing_cases++; - if (passing_cases >= max_passing_cases) { - max_passing_cases = passing_cases; - wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; - dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; - dll_dqs_delay_X_end_window = dll_dqs_delay_X; - } - } - - /* - * De-assert 'start' parameter. - */ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ - - } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ - - /* - * Largest passing window is now detected. - */ - - /* Compute dll_dqs_delay_X value */ - dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; - wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; - - debug("DQS calibration - Window detected:\n"); - debug("max_passing_cases = %d\n", max_passing_cases); - debug("wr_dqs_shift = %d\n", wr_dqs_shift); - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); - debug("dll_dqs_delay_X window = %d - %d\n", - dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); - - /* - * De-assert 'start' parameter. - */ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* - * Set 'wr_dqs_shift' - */ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_09=0x%08lx\n", val); - - /* - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - */ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_22=0x%08lx\n", val); - - /* - * Set 'dll_dqs_delay_X'. - */ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_17=0x%08lx\n", val); - - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_18=0x%08lx\n", val); - - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_19=0x%08lx\n", val); - - /* - * Assert 'start' parameter. - */ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - ppcMsync(); - ppcMbar(); - - /* - * Wait for the DCC master delay line to finish calibration - */ - if (wait_for_dlllock() != 0) { - printf("dlllock did not occur !!!\n"); - hang(); - } - ppcMsync(); - ppcMbar(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ -} -#endif /* CONFIG_DDR_DATA_EYE */ - #ifdef CONFIG_DDR_ECC static void wait_ddr_idle(void) { @@ -610,12 +289,23 @@ long int initdram (int board_type) mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ #endif - wait_for_dlllock(); + denali_wait_for_dlllock(); + +#if defined(CONFIG_DDR_DATA_EYE) + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20, + TLB_WORD2_I_ENABLE); + denali_core_search_data_eye(); + remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); +#endif /* * Program tlb entries for this size (dynamic) */ - program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20, + MY_TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual address @@ -623,13 +313,6 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); -#ifdef CONFIG_DDR_DATA_EYE - /* - * Perform data eye search if requested. - */ - denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); -#endif - #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h deleted file mode 100644 index 6a7bf01..0000000 --- a/board/lwmon5/sdram.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPD_SDRAM_DENALI_H_ -#define _SPD_SDRAM_DENALI_H_ - -#define ppcMsync sync -#define ppcMbar eieio - -/* General definitions */ -#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ -#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ -#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ -#define SDRAM_NONE 0 /* No DIMM detected in Slot */ -#define MAXRANKS 2 /* 2 ranks maximum */ - -/* Supported PLB Frequencies */ -#define PLB_FREQ_133MHZ 133333333 -#define PLB_FREQ_152MHZ 152000000 -#define PLB_FREQ_160MHZ 160000000 -#define PLB_FREQ_166MHZ 166666666 - -/* Denali Core Registers */ -#define SDRAM_DCR_BASE 0x10 - -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -/*-----------------------------------------------------------------------------+ - | Values for ddrcfga register - indirect addressing of these regs - +-----------------------------------------------------------------------------*/ - -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) - -#define DDR0_13 0x0D - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) - -#define DDR0_15 0x0F - -#define DDR0_16 0x10 - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) - -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_29 0x1D - -#define DDR0_30 0x1E - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh index 25461c2..ccded7e 100755 --- a/board/versatile/split_by_variant.sh +++ b/board/versatile/split_by_variant.sh @@ -8,7 +8,7 @@ mkdir -p ${obj}include variant=PB926EJ-S -if [ "$1" == "" ] +if [ "$1" = "" ] then echo "$0:: No parameters - using versatilepb_config" echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h |