diff options
Diffstat (limited to 'board')
122 files changed, 3047 insertions, 2669 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 709d41e..3dec315 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -33,14 +33,6 @@ extern void board_pll_init_f(void); -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { @@ -116,10 +108,3 @@ long int initdram(int board_type) return (CFG_MBYTES_RAM << 20); } - -#ifndef CONFIG_NAND_SPL -int testdram(void) -{ - return (0); -} -#endif diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 5077187..0c7d69e 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -466,73 +466,6 @@ long int initdram (int board_type) #endif } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n, *p32, ctr; - const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM*1024; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - - /* - * Perform a sequence test to ensure that all - * memory locations are uniquely addressable - */ - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Writing %3d MB\r", (unsigned long)p32 >> 20); - *p32++ = ctr++; - } - - ctr = 0; - p32 = 0; - while ((unsigned long)p32 != bend) { - if (0 == ((unsigned long)p32 & ((1<<20)-1))) - printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); - - if (*p32 != ctr) { - printf("SDRAM test fails at: %08x\n", p32); - return 1; - } - - ctr++; - p32++; - } - - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 66e7509..9d508b8 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -66,14 +66,6 @@ int checkboard(void) return (0); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - /* ------------------------------------------------------------------------- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration @@ -85,11 +77,3 @@ long int initdram(int board_type) ret = spd_sdram(); return ret; } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 0f66061..4e3b349 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -211,44 +211,6 @@ long int initdram(int board_type) } #endif -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /* * pci_target_init * diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index ededb3e..c6375ac 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -116,36 +116,6 @@ long int initdram(int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 193083f..3a0b18f 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) { return (SDRAM_CLKTR_CLKP_90_DEG_ADV); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile index 39328c2..981ef3a 100644 --- a/board/amcc/kilauea/Makefile +++ b/board/amcc/kilauea/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o -SOBJS = init.o +COBJS = $(BOARD).o cmd_pll.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S deleted file mode 100644 index 8cd534c..0000000 --- a/board/amcc/kilauea/init.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on code provided from UDTech and AMCC - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - - /* - * DDR2 setup - */ - - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */ - mtsdram_as(SDRAM_MB0CF, 0x00006701); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram_as(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram_as(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram_as(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); - mtsdram_as(SDRAM_MODT1, 0x00000000); - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ - - blr diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c deleted file mode 100644 index 1d7a3fa..0000000 --- a/board/amcc/kilauea/memory.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> - -void sdram_init(void) -{ - return; -} - -long int initdram(int board_type) -{ - return (CFG_MBYTES_SDRAM << 20); -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index f964511..b14b6e1 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -126,50 +126,6 @@ u32 ddr_clktr(u32 default_val) { } /************************************************************************* - * int testdram() - * - ************************************************************************/ -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *) 0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - - return 0; -} -#endif - - -/************************************************************************* * pci_pre_init * * This routine is called just prior to registering the hose and gives diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile index 39328c2..4def0d4 100644 --- a/board/amcc/makalu/Makefile +++ b/board/amcc/makalu/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o +COBJS = $(BOARD).o cmd_pll.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 11c5b19..4d0f460 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,8 +1,11 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * Based on code provided from Senao and AMCC + * Originally based on code provided from Senao and AMCC * * See file CREDITS for list of people who contributed to this * project. @@ -23,126 +26,6 @@ * MA 02111-1307 USA */ -#include <config.h> -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - .globl ext_bus_cntlr_init ext_bus_cntlr_init: - - /* - * DDR2 setup - */ - - /* Following the DDR Core Manual, here is the initialization */ - - /* Step 1 */ - - /* Step 2 */ - - /* Step 3 */ - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB0CF, 0x00005201); - - /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - - /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ - mtsdram_as(SDRAM_CLKTR,0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram_as(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram_as(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram_as(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram_as(SDRAM_MMODE, 0x00000442); - mtsdram_as(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram_as(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram_as(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram_as(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram_as(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram_as(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram_as(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram_as(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram_as(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram_as(SDRAM_INITPLR11, 0x81000442); - mtsdram_as(SDRAM_INITPLR12, 0x81010780); - mtsdram_as(SDRAM_INITPLR13, 0x81010400); - mtsdram_as(SDRAM_INITPLR14, 0x00000000); - mtsdram_as(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram_as(SDRAM_CODT, 0x0080f837); - mtsdram_as(SDRAM_MODT0, 0x01800000); -#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */ - mtsdram_as(SDRAM_MODT1, 0x00000000); -#endif - - mtsdram_as(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram_as(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - lis r3,0x1 /* 400000 = wait 100ms */ - mtctr r3 - -pll_wait: - bdnz pll_wait - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram_as(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram_as(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram_as(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram_as(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mtsdram_as(SDRAM_MCOPT2, 0x28000000); - blr diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c deleted file mode 100644 index b03b60b..0000000 --- a/board/amcc/makalu/memory.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -void sdram_init(void) -{ - return; -} - -long int initdram(int board_type) -{ - /* - * Same as on Kilauea, Makalu generates exception 0x200 - * (machine check) after trap_init() in board_init_f, - * when SDRAM is initialized here (late) and d-cache is - * used earlier as INIT_RAM. - * So for now, initialize DDR2 in init.S very early and - * also use it for INIT_RAM. Then this exception doesn't - * occur. - */ -#if 0 - u32 val; - - /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ - mtsdram(SDRAM_MB0CF, 0x00005201); - - /* SET SDRAM_MB1CF - Not enabled */ - mtsdram(SDRAM_MB1CF, 0x00000000); - - /* SET SDRAM_MB2CF - Not enabled */ - mtsdram(SDRAM_MB2CF, 0x00000000); - - /* SET SDRAM_MB3CF - Not enabled */ - mtsdram(SDRAM_MB3CF, 0x00000000); - - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ - mtsdram(SDRAM_CLKTR, 0x80000000); - - /* Refresh Time register (0x30) Refresh every 7.8125uS */ - mtsdram(SDRAM_RTR, 0x06180000); - - /* SDRAM_SDTR1 */ - mtsdram(SDRAM_SDTR1, 0x80201000); - - /* SDRAM_SDTR2 */ - mtsdram(SDRAM_SDTR2, 0x32204232); - - /* SDRAM_SDTR3 */ - mtsdram(SDRAM_SDTR3, 0x080b0d1a); - - mtsdram(SDRAM_MMODE, 0x00000442); - mtsdram(SDRAM_MEMODE, 0x00000404); - - /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ - mtsdram(SDRAM_MCOPT1, 0x04322000); - - /* NOP */ - mtsdram(SDRAM_INITPLR0, 0xa8380000); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR1, 0x81900400); - /* EMR2 twr = 2tck */ - mtsdram(SDRAM_INITPLR2, 0x81020000); - /* EMR3 twr = 2tck */ - mtsdram(SDRAM_INITPLR3, 0x81030000); - /* EMR DLL ENABLE twr = 2tck */ - mtsdram(SDRAM_INITPLR4, 0x81010404); - /* MR w/ DLL reset - * Note: 5 is CL. May need to be changed - */ - mtsdram(SDRAM_INITPLR5, 0x81000542); - /* precharge 3 DDR clock cycle */ - mtsdram(SDRAM_INITPLR6, 0x81900400); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR7, 0x8D080000); - /* Auto-refresh trfc = 26tck */ - mtsdram(SDRAM_INITPLR8, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR9, 0x8D080000); - /* Auto-refresh */ - mtsdram(SDRAM_INITPLR10, 0x8D080000); - /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ - mtsdram(SDRAM_INITPLR11, 0x81000442); - mtsdram(SDRAM_INITPLR12, 0x81010780); - mtsdram(SDRAM_INITPLR13, 0x81010400); - mtsdram(SDRAM_INITPLR14, 0x00000000); - mtsdram(SDRAM_INITPLR15, 0x00000000); - - /* SET MCIF0_CODT Die Termination On */ - mtsdram(SDRAM_CODT, 0x0080f837); - mtsdram(SDRAM_MODT0, 0x01800000); - mtsdram(SDRAM_MODT1, 0x00000000); - - mtsdram(SDRAM_WRDTR, 0x00000000); - - /* SDRAM0_MCOPT2 (0X21) Start initialization */ - mtsdram(SDRAM_MCOPT2, 0x20000000); - - /* Step 5 */ - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP); - - /* Step 6 */ - - /* SDRAM_DLCR */ - mtsdram(SDRAM_DLCR, 0x030000a5); - - /* SDRAM_RDCC */ - mtsdram(SDRAM_RDCC, 0x40000000); - - /* SDRAM_RQDC */ - mtsdram(SDRAM_RQDC, 0x80000038); - - /* SDRAM_RFDC */ - mtsdram(SDRAM_RFDC, 0x00000209); - - /* Enable memory controller */ - mfsdram(SDRAM_MCOPT2, val); - val |= SDRAM_MCOPT2_DCEN_ENABLE; - mtsdram(SDRAM_MCOPT2, val); -#endif - return (CFG_MBYTES_SDRAM << 20); -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 3bd1b81..79c1a1b 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -214,36 +214,6 @@ long int initdram (int board_type) } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk index e62b8d3..5e04ee4 100644 --- a/board/amcc/sequoia/config.mk +++ b/board/amcc/sequoia/config.mk @@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE TEXT_BASE = 0xFFFA0000 +# +# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000 +# TEXT_BASE = 0xFFF80000 +# endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 6bcb3ab..5ff9787 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -329,44 +329,6 @@ int checkboard(void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) /* * Assign interrupts to PCI devices. diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 891b4d9..e4fdf4a 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -200,45 +200,3 @@ int pci_pre_init(struct pci_controller *hose) return 1; } #endif /* CONFIG_PCI */ - -#ifdef CFG_DRAM_TEST -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - unsigned long msr; - unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024; - - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE)); - - for (k = 0; k < total_kbytes ; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) - printf("%3d MB\r", k / 1024); - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - mtmsr(msr); - - return 0; -} -#endif /* CFG_DRAM_TEST */ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index f00397e..b6c3065 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -196,36 +196,6 @@ int checkboard (void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x04000000; - uint *pend = (uint *) 0x0fc00000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 292e026..641987e 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -86,14 +86,6 @@ int checkboard(void) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - -/* * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of * the necessary info for SDRAM controller configuration */ @@ -101,11 +93,3 @@ long int initdram(int board_type) { return spd_sdram(); } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 212fab8..8345537 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -200,7 +200,7 @@ int checkboard(void) } /************************************************************************* - * sdram_init -- doesn't use serial presence detect. + * initdram -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz @@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -void sdram_init(void) +long int initdram(int board) { register uint reg; int tr1_bank1, tr1_bank2; @@ -327,57 +327,11 @@ void sdram_init(void) sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) ); -} + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); -/************************************************************************* - * long int initdram - * - ************************************************************************/ -long int initdram(int board) -{ - sdram_init(); return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 11d1743..6608893 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) { return default_val; } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S index 3aaa5c2..65f13e1 100644 --- a/board/amirix/ap1000/init.S +++ b/board/amirix/ap1000/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/atum8548/law.c b/board/atum8548/law.c index 3606cbb..b66fd7b 100644 --- a/board/atum8548/law.c +++ b/board/atum8548/law.c @@ -48,14 +48,14 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 72a10d3..4b6b3f4 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -134,14 +134,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/* NOTE: for CrayL1 we have ECC memory, so enable it. */ -/*....now done in C in L1.c:init_sdram for readability. */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - blr diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 24c6f0d..640412d 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -27,6 +27,8 @@ #include <miiphy.h> #include <ppc4xx_enet.h> +void sdram_init(void); + /* * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator * @@ -124,6 +126,13 @@ long initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 833bbce..1fbf17f 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -27,6 +27,8 @@ #include <miiphy.h> #include <ppc4xx_enet.h> +void sdram_init(void); + /* * board_early_init_f: do early board initialization * @@ -92,6 +94,13 @@ long initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/eric/eric.c b/board/eric/eric.c index 5413ae1..14ba9b0 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -31,6 +31,8 @@ #define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ #define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ +void sdram_init(void); + int board_early_init_f (void) { @@ -127,6 +129,12 @@ long int initdram (int board_type) int TotalSize; #endif + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); #ifdef CONFIG_ERIC /* diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index dfead33..3abcfe6 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -190,28 +190,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - #if 1 /* test-only: some internal test routines... */ /* diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 055a397..30fa605 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -181,22 +181,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 39a9722..49031cf 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -3,6 +3,8 @@ #include <common.h> #include "exbitgen.h" +void sdram_init(void); + /* ************************************************************************ */ int board_early_init_f (void) /* ------------------------------------------------------------------------ -- @@ -83,6 +85,13 @@ long int initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index 785576a..3b8bd05 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a951b9e..051f985 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -41,12 +41,6 @@ void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); - -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { puts("Board: ADS\n"); @@ -230,42 +224,6 @@ sdram_init(void) udelay(100); } - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c index 0ac223c..fbf2bdc 100644 --- a/board/freescale/mpc8541cds/law.c +++ b/board/freescale/mpc8541cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 62c8d63..420a89a 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -196,11 +196,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -425,45 +420,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 433e509..a82dede 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -28,15 +28,15 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), /* contains both PCIE3 MEM & IO space */ - SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index dd10af8..5041426 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -40,11 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); void sdram_init(void); -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -83,45 +78,6 @@ initdram(int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 0ee53e2..34b9d1c 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -52,21 +52,21 @@ struct law_entry law_table[] = { #ifdef CFG_PCI1_MEM_PHYS - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), #endif #ifdef CFG_PCI2_MEM_PHYS - SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), #endif #ifdef CFG_PCIE1_MEM_PHYS - SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), #ifdef CFG_RIO_MEM_PHYS - SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif }; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index efe2a3a..ad29734 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -45,11 +45,6 @@ DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); void sdram_init(void); -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -250,45 +245,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c index 0ac223c..fbf2bdc 100644 --- a/board/freescale/mpc8555cds/law.c +++ b/board/freescale/mpc8555cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 8acbba4..74e20cb 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -194,11 +194,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -int board_early_init_f (void) -{ - return 0; -} - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -422,45 +417,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #ifdef CONFIG_PCI /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 785576a..3b8bd05 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 8d4b8a8..144b584 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -212,12 +212,6 @@ typedef struct bcsr_ { volatile unsigned char bcsr5; } bcsr_t; - -int board_early_init_f (void) -{ - return 0; -} - void reset_phy (void) { #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ @@ -433,42 +427,6 @@ sdram_init(void) udelay(100); } - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index 5e96ea7..3bc24c5 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -50,13 +50,13 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 4568aa1..f1928ab 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -292,45 +292,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8568mds_config_table[] = { diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index b4d222d..91b922b 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -29,16 +29,16 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), - SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) + SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 3a855b5..ce563dc 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -141,42 +141,6 @@ initdram(int board_type) } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - puts("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 245f420..2d6c3c1 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -47,18 +47,18 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), #if !defined(CONFIG_SPD_EEPROM) - SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), #endif - SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index bb1f927..915fb58 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -81,42 +81,6 @@ initdram(int board_type) } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - puts("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test passed.\n"); - return 0; -} -#endif - - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 2dfd87c..9fcab74 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -149,41 +149,6 @@ long int initdram (int board_type) } -#if 1 /* test-only */ -void sdram_init(void) -{ - init_sdram_static_settings(); -} -#endif - - -#if 0 /* test-only */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} -#endif - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/jse/init.S b/board/jse/init.S index 231cd1c..c564ed3 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -93,13 +93,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - - -/*----------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: This function is called by cpu/ppc4xx/start.S code */ -/* to get the SDRAM initialized. */ -/*----------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b63fbdc..85795b7 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -275,44 +275,6 @@ int checkboard(void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/ml2/init.S b/board/ml2/init.S index 80f98c5..9064d3b 100644 --- a/board/ml2/init.S +++ b/board/ml2/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c index 273ec5c..cfcd73e 100644 --- a/board/mpc8540eval/law.c +++ b/board/mpc8540eval/law.c @@ -43,11 +43,11 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), #ifndef CONFIG_RAM_AS_FLASH - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 3351b5b..f00a871 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -178,19 +178,6 @@ ext_bus_cntlr_init: nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 39f2ea5..8384325 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -175,19 +175,6 @@ nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile new file mode 100644 index 0000000..84cd14a --- /dev/null +++ b/board/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk new file mode 100644 index 0000000..1d85f4f --- /dev/null +++ b/board/mvblm7/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF00000 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c new file mode 100644 index 0000000..a60af01 --- /dev/null +++ b/board/mvblm7/fpga.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include "fpga.h" +#include "mvblm7.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, + 0 +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_init_fpga(void) +{ + fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", + gd->reloc_off); + fpga_init(gd->reloc_off); + fpga_add(fpga_altera, &cyclone2); + fpga_config_fn(0, 1, 0); + udelay(60); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("SET config : %s\n", assert ? "low" : "high"); + if (assert) + dvo |= FPGA_CONFIG; + else + dvo &= ~FPGA_CONFIG; + + if (flush) + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + fpga_debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + fpga_debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + fpga_debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + fpga_debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + fpga_debug("\n"); + + return 0; +} + +int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + fpga_debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/board/mvblm7/fpga.h b/board/mvblm7/fpga.h new file mode 100644 index 0000000..19277eb --- /dev/null +++ b/board/mvblm7/fpga.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvblm7_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/mvblm7/mvblm7.c b/board/mvblm7/mvblm7.c new file mode 100644 index 0000000..c02c59c --- /dev/null +++ b/board/mvblm7/mvblm7.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mpc8349_pci.h> +#include <pci.h> +#include <spi.h> +#include <asm/mmu.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +#include "mvblm7.h" + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & + LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + + udelay(300); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return CFG_DDR_SIZE; +} + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram(); + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n"); + + return 0; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + ptr = getenv("dhcp_vendor-class-identifier"); + if (ptr) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + ptr = getenv("dhcp_client_id"); + if (ptr) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} + +#ifdef CONFIG_HARD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat &= ~MVBLM7_MMC_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat |= ~MVBLM7_MMC_CS; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} + +#endif diff --git a/board/mvblm7/mvblm7.h b/board/mvblm7/mvblm7.h new file mode 100644 index 0000000..03e9f41 --- /dev/null +++ b/board/mvblm7/mvblm7.h @@ -0,0 +1,21 @@ +#ifndef __MVBC_H__ +#define __MVBC_H__ + +#define MV_GPIO + +#define FPGA_CONFIG 0x80000000 +#define FPGA_CCLK 0x40000000 +#define FPGA_DIN 0x20000000 +#define FPGA_STATUS 0x10000000 +#define FPGA_CONF_DONE 0x08000000 +#define MMC_CS 0x04000000 + +#define WD_WDI 0x00400000 +#define WD_TS 0x00200000 +#define MAN_RST 0x00100000 + +#define MV_GPIO_DAT (WD_TS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) +#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) + +#endif diff --git a/board/mvblm7/mvblm7_autoscript b/board/mvblm7/mvblm7_autoscript new file mode 100644 index 0000000..ec6e34e --- /dev/null +++ b/board/mvblm7/mvblm7_autoscript @@ -0,0 +1,37 @@ +echo +echo "==== running autoscript ====" +echo +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} +setenv ramkernel setenv kernel_boot \${loadaddr} +setenv flashkernel setenv kernel_boot \${mv_kernel_addr} +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} +setenv bootfromflash run flashkernel cpird ramparam bootdtb +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +setenv set_static_ip setenv ipaddr \${static_ipaddr} +setenv set_static_nm setenv netmask \${static_netmask} +setenv set_static_gw setenv gatewayip \${static_gateway} +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${autoscr_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip + run getdtb rundtb bootfromnet ramparam bootdtb + else + echo "=== netboot failed ===" + fi + fi + run set_static_ip set_static_nm set_static_gw set_ip + echo "=== bootfromflash ===" + run cpdtb rundtb bootfromflash +else + echo "=== boot stopped with autoscr_boot no ===" +fi diff --git a/board/mvblm7/pci.c b/board/mvblm7/pci.c new file mode 100644 index 0000000..ef34a6b --- /dev/null +++ b/board/mvblm7/pci.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#include <pci.h> +#include <mpc83xx.h> +#include <fpga.h> +#include "mvblm7.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_load_fpga(void) +{ + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + + return fpga_load(0, fpga_data, data_size); +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + char *s; + int i; + int warmboot; + int load_fpga; + volatile immap_t *immr; + volatile pcictrl83xx_t *pci_ctrl; + volatile gpio83xx_t *gpio; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + struct pci_region *reg[] = { pci_regions }; + + load_fpga = 1; + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) &immr->clk; + pci_ctrl = immr->pci_ctrl; + pci_law = immr->sysconf.pcilaw; + gpio = (volatile gpio83xx_t *)&immr->gpio[0]; + + s = getenv("skip_fpga"); + if (s) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + load_fpga = 0; + } + + gpio->dat = MV_GPIO_DAT; + gpio->odr = MV_GPIO_ODE; + if (load_fpga) + gpio->dir = MV_GPIO_OUT; + else + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + mvblm7_init_fpga(); + if (load_fpga) + mvblm7_load_fpga(); + + /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ + clk->occr = 0xc0000000; + + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + + for (i = 0; i < 1000; ++i) + udelay(1000); + + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index dc526fc..42c7c16 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -121,15 +121,6 @@ void hcu_led_set(u32 value) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - -/* * hcu_get_slot */ u32 hcu_get_slot(void) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 6b1b53a..d8817b8 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -40,28 +40,6 @@ void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) - #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -111,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(memcfga, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(memcfgd); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 2b21444..07891f6 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -128,15 +128,6 @@ void hcu_led_set(u32 value) } /* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - -/* * hcu_get_slot */ u32 hcu_get_slot(void) diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 620000a..2b8992e 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -553,44 +553,6 @@ long int initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/pm854/law.c b/board/pm854/law.c index cb6b37f..d74d17a 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/law.c b/board/pm856/law.c index cb6b37f..d74d17a 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 287f32e..8d60936 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -132,36 +132,6 @@ int checkboard (void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index bcf3468..ab54260 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -46,12 +46,12 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c index e370853..10dedb4 100644 --- a/board/sbc8560/law.c +++ b/board/sbc8560/law.c @@ -51,10 +51,10 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index d403873..801c5b7 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -44,15 +44,15 @@ struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), - SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW(CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/Makefile b/board/socrates/Makefile index 6453f24..11503eb 100644 --- a/board/socrates/Makefile +++ b/board/socrates/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a # -COBJS := $(BOARD).o law.o tlb.o sdram.o +COBJS := $(BOARD).o law.o tlb.o sdram.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/socrates/config.mk b/board/socrates/config.mk index 1cf5d38..4f17294 100644 --- a/board/socrates/config.mk +++ b/board/socrates/config.mk @@ -25,6 +25,5 @@ # # socrates board # default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256k # -TEXT_BASE = 0xfffc0000 +TEXT_BASE = 0xfffa0000 diff --git a/board/socrates/law.c b/board/socrates/law.c index 5f4b8ca..35c4a90 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -33,13 +33,12 @@ /* * LAW(Local Access Window) configuration: * - * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * 0xfc00_0000 0xffff_ffff FLASH 64M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. @@ -47,11 +46,13 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#if defined(CFG_FPGA_BASE) + SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c new file mode 100644 index 0000000..fc82ecb --- /dev/null +++ b/board/socrates/nand.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CFG_NAND_BASE) +#include <nand.h> +#include <asm/errno.h> +#include <asm/io.h> + +static int state; +static void nand_write_byte(struct mtd_info *mtd, u_char byte); +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static void nand_write_word(struct mtd_info *mtd, u16 word); +static u_char nand_read_byte(struct mtd_info *mtd); +static u16 nand_read_word(struct mtd_info *mtd); +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); +static int nand_device_ready(struct mtd_info *mtdinfo); +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd); + +#define FPGA_NAND_CMD_MASK (0x7 << 28) +#define FPGA_NAND_CMD_COMMAND (0x0 << 28) +#define FPGA_NAND_CMD_ADDR (0x1 << 28) +#define FPGA_NAND_CMD_READ (0x2 << 28) +#define FPGA_NAND_CMD_WRITE (0x3 << 28) +#define FPGA_NAND_BUSY (0x1 << 15) +#define FPGA_NAND_ENABLE (0x1 << 31) +#define FPGA_NAND_DATA_SHIFT 16 + +/** + * nand_write_byte - write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + */ +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); +} + +/** + * nand_write_word - write one word to the chip + * @mtd: MTD device structure + * @word: data word to write + */ +static void nand_write_word(struct mtd_info *mtd, u16 word) +{ + nand_write_buf(mtd, (const uchar *)&word, sizeof(word)); +} + +/** + * nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + long val; + + if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) { + /* Write data */ + val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE; + } else { + /* Write address or command */ + val = state; + } + + for (i = 0; i < len; i++) { + out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT)); + } +} + + +/** + * nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 nand_read_word(struct mtd_info *mtd) +{ + u16 word; + nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + int val; + + val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; + + out_be32(this->IO_ADDR_W, val); + for (i = 0; i < len; i++) { + buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; + } +} + +/** + * nand_verify_buf - Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (buf[i] != nand_read_byte(mtd)); + return -EFAULT; + } + return 0; +} + +/** + * nand_device_ready - Check the NAND device is ready for next command. + * @mtd: MTD device structure + */ +static int nand_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + + if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) + return 0; /* busy */ + return 1; +} + +/** + * nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + + switch(cmd) { + case NAND_CTL_CLRALE: + state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ + break; + case NAND_CTL_CLRCLE: + state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */ + break; + case NAND_CTL_SETCLE: + state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND; + break; + case NAND_CTL_SETALE: + state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR; + break; + case NAND_CTL_SETNCE: + state |= FPGA_NAND_ENABLE; + break; + case NAND_CTL_CLRNCE: + state &= ~FPGA_NAND_ENABLE; + break; + default: + printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd); + break; + } +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->hwcontrol = nand_hwcontrol; + nand->eccmode = NAND_ECC_SOFT; + nand->dev_ready = nand_device_ready; + nand->write_byte = nand_write_byte; + nand->read_byte = nand_read_byte; + nand->write_word = nand_write_word; + nand->read_word = nand_read_word; + nand->write_buf = nand_write_buf; + nand->read_buf = nand_read_buf; + nand->verify_buf = nand_verify_buf; + + return 0; +} + +#endif diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 15c6478..d791f11 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -35,7 +35,11 @@ #include <flash.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/io.h> +#if defined(CFG_FPGA_BASE) +#include "upm_table.h" +#endif DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ @@ -58,7 +62,8 @@ int checkboard (void) putc('\n'); #ifdef CONFIG_PCI - if (gur->porpllsr & (1<<15)) { + /* Check the PCI_clk sel bit */ + if (in_be32(&gur->porpllsr) & (1<<15)) { src = "SYSCLK"; f = CONFIG_SYS_CLK_FREQ; } else { @@ -74,7 +79,10 @@ int checkboard (void) * Initialize local bus. */ local_bus_init (); - +#if defined(CFG_FPGA_BASE) + /* Init UPMA for FPGA access */ + upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); +#endif return 0; } @@ -216,5 +224,15 @@ ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + +#if defined (CFG_FPGA_BASE) + memset(val, 0, sizeof(val)); + val[0] = CFG_FPGA_BASE; + rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property \"fpga\", err=%s\n", + fdt_strerror(rc)); +#endif } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index b80caea..aea99ad 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = { /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 2: 256M Non-cacheable, guarded @@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), +#if defined(CFG_FPGA_BASE) /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 4: 1M Non-cacheable, guarded + * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), + 0, 4, BOOKE_PAGESZ_1M, 1), +#endif /* * TLB 6: 64M Non-cacheable, guarded diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h new file mode 100644 index 0000000..f26d8a7 --- /dev/null +++ b/board/socrates/upm_table.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UPM_TABLE_H +#define __UPM_TABLE_H + +/* UPM Table Configuration Code for FPGA access */ +static const unsigned int UPMTableA[] = +{ + 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, //Words 0 to 3 + 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, //Words 4 to 7 + 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, //Words 8 to 11 + 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, //Words 12 to 15 + 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, //Words 16 to 19 + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23 + 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, //Words 24 to 27 + 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, //Words 28 to 31 + 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 32 to 35 + 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 36 to 39 + 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43 + 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47 + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51 + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55 + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59 + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63 +}; + +#endif diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c index 312b3c5..a7e9ceb 100644 --- a/board/stxgp3/law.c +++ b/board/stxgp3/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/law.c b/board/stxssa/law.c index 2b25292..8730cdf 100644 --- a/board/stxssa/law.c +++ b/board/stxssa/law.c @@ -47,14 +47,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ - SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index a5ce7bd..a5ce7bd 100644 --- a/board/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile diff --git a/board/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index b3f095d..b3f095d 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 7472ca9..7472ca9 100644 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c index 214dca6..214dca6 100644 --- a/board/tqm5200/cmd_tb5200.c +++ b/board/tqc/tqm5200/cmd_tb5200.c diff --git a/board/tqm5200/config.mk b/board/tqc/tqm5200/config.mk index d72dfe7..d72dfe7 100644 --- a/board/tqm5200/config.mk +++ b/board/tqc/tqm5200/config.mk diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h index 3f1e169..3f1e169 100644 --- a/board/tqm5200/mt48lc16m16a2-75.h +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h diff --git a/board/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index f9891db..f9891db 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c diff --git a/board/tqm8260/Makefile b/board/tqc/tqm8260/Makefile index 61221fd..61221fd 100644 --- a/board/tqm8260/Makefile +++ b/board/tqc/tqm8260/Makefile diff --git a/board/tqm8260/config.mk b/board/tqc/tqm8260/config.mk index 1fe9952..1fe9952 100644 --- a/board/tqm8260/config.mk +++ b/board/tqc/tqm8260/config.mk diff --git a/board/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 056fe81..056fe81 100644 --- a/board/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c diff --git a/board/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c index 736c410..736c410 100644 --- a/board/tqm8260/tqm8260.c +++ b/board/tqc/tqm8260/tqm8260.c diff --git a/board/tqm8272/Makefile b/board/tqc/tqm8272/Makefile index 6730263..6730263 100644 --- a/board/tqm8272/Makefile +++ b/board/tqc/tqm8272/Makefile diff --git a/board/tqm8272/config.mk b/board/tqc/tqm8272/config.mk index af7a81e..af7a81e 100644 --- a/board/tqm8272/config.mk +++ b/board/tqc/tqm8272/config.mk diff --git a/board/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index ec1a37c..ec1a37c 100644 --- a/board/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c diff --git a/board/tqm834x/Makefile b/board/tqc/tqm834x/Makefile index 4c0d204..4c0d204 100644 --- a/board/tqm834x/Makefile +++ b/board/tqc/tqm834x/Makefile diff --git a/board/tqm834x/config.mk b/board/tqc/tqm834x/config.mk index f172c4e..f172c4e 100644 --- a/board/tqm834x/config.mk +++ b/board/tqc/tqm834x/config.mk diff --git a/board/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index e3d0309..e3d0309 100644 --- a/board/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c diff --git a/board/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index aea985c..aea985c 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c diff --git a/board/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile index 52f5ef9..8ea07f2 100644 --- a/board/tqm85xx/Makefile +++ b/board/tqc/tqm85xx/Makefile @@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sdram.o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += sdram.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_NAND) += nand.o + +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/tqm85xx/config.mk b/board/tqc/tqm85xx/config.mk index 52e84ad..52e84ad 100644 --- a/board/tqm85xx/config.mk +++ b/board/tqc/tqm85xx/config.mk diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c new file mode 100644 index 0000000..de3ea00 --- /dev/null +++ b/board/tqc/tqm85xx/law.c @@ -0,0 +1,86 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * Standard mapping: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M + * 0xef00_0000 0xefff_ffff PCI express IO 16M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M + * + * Big FLASH mapping: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xa000_ffff CCSR 1M + * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M + * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M + * 0xaf00_0000 0xafff_ffff PCI express IO 16M + * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M + * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#ifdef CONFIG_TQM_BIGFLASH +#define LAW_3_SIZE LAW_SIZE_1G +#define LAW_5_SIZE LAW_SIZE_256M +#else +#define LAW_3_SIZE LAW_SIZE_128M +#define LAW_5_SIZE LAW_SIZE_512M +#endif + +struct law_entry law_table[] = { + SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#ifdef CONFIG_PCIE1 + SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), +#else /* !CONFIG_PCIE1 */ + SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), +#endif /* CONFIG_PCIE1 */ +#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) + SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), +#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ +#ifdef CONFIG_PCIE1 + SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), +#endif /* CONFIG_PCIE */ +}; + +int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c new file mode 100644 index 0000000..fe3b31f --- /dev/null +++ b/board/tqc/tqm85xx/nand.c @@ -0,0 +1,469 @@ +/* + * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <ioports.h> + +#include <nand.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern uint get_lbc_clock (void); + +/* index of UPM RAM array run pattern for NAND command cycle */ +#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08 + +/* index of UPM RAM array run pattern for NAND address cycle */ +#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 + +/* Structure for table with supported UPM timings */ +struct upm_freq { + ulong freq; + const u32 *upm_patt; + uchar gpl4_disable; + uchar ehtr; + uchar ead; +}; + +/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ + +/* UPM pattern for bus clock = 25 MHz */ +static const u32 upm_patt_25[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 33.3 MHz */ +static const u32 upm_patt_33[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 41.7 MHz */ +static const u32 upm_patt_42[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 50 MHz */ +static const u32 upm_patt_50[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 66.7 MHz */ +static const u32 upm_patt_67[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 83.3 MHz */ +static const u32 upm_patt_83[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const u32 upm_patt_100[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const u32 upm_patt_133[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 166.7 MHz */ +static const u32 upm_patt_167[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* Supported UPM timings */ +struct upm_freq upm_freq_table[] = { + /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ + {25000000, upm_patt_25, 1, 0, 0}, + {33333333, upm_patt_33, 1, 0, 0}, + {41666666, upm_patt_42, 1, 0, 0}, + {50000000, upm_patt_50, 0, 0, 0}, + {66666666, upm_patt_67, 0, 0, 0}, + {83333333, upm_patt_83, 0, 0, 0}, + {100000000, upm_patt_100, 0, 1, 1}, + {133333333, upm_patt_133, 0, 1, 1}, + {166666666, upm_patt_167, 0, 1, 1}, +}; + +#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) + +volatile const u32 *nand_upm_patt; + +/* + * write into UPMB ram + */ +static void upmb_write (u_char addr, ulong val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, + MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); + + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_NAND0_BASE, 0); + + clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); +} + +/* + * Initialize UPM for NAND flash access. + */ +static void nand_upm_setup (volatile ccsr_lbc_t *lbc) +{ + uint i; + uint or3 = CFG_OR3_PRELIM; + uint clock = get_lbc_clock (); + + out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ + out_be32 (&lbc->br3, CFG_BR3_PRELIM); + + /* + * Search appropriate UPM table for bus clock. + * If the bus clock exceeds a tolerated value, take the UPM timing for + * the next higher supported frequency to ensure that access works + * (even the access may be slower then). + */ + for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) + ; + + if (i >= UPM_FREQS) + /* no valid entry found */ + /* take last entry with configuration for max. bus clock */ + i--; + + if (upm_freq_table[i].ehtr) { + /* EHTR must be set due to TQM8548 timing specification */ + or3 |= OR_UPM_EHTR; + } + if (upm_freq_table[i].ead) + /* EAD must be set due to TQM8548 timing specification */ + or3 |= OR_UPM_EAD; + + out_be32 (&lbc->or3, or3); + + /* Assign address of table */ + nand_upm_patt = upm_freq_table[i].upm_patt; + + for (i = 0; i < 64; i++) { + upmb_write (i, *nand_upm_patt); + nand_upm_patt++; + } + + /* Put UPM back to normal operation mode */ + if (upm_freq_table[i].gpl4_disable) + /* GPL4 must be disabled according to timing specification */ + out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); + + return; +} + +static struct fsl_upm_nand fun = { + .width = 8, + .upm_cmd_offset = 0x08, + .upm_addr_offset = 0x10, + .chip_delay = NAND_BIG_DELAY_US, +}; + +void board_nand_select_device (struct nand_chip *nand, int chip) +{ +} + +int board_nand_init (struct nand_chip *nand) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + if (!nand_upm_patt) + nand_upm_setup (lbc); + + fun.upm.io_addr = nand->IO_ADDR_R; + fun.upm.mxmr = (void __iomem *)&lbc->mbmr; + fun.upm.mdr = (void __iomem *)&lbc->mdr; + fun.upm.mar = (void __iomem *)&lbc->mar; + + return fsl_upm_nand_init (nand, &fun); +} diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c new file mode 100644 index 0000000..442ff66 --- /dev/null +++ b/board/tqc/tqm85xx/sdram.c @@ -0,0 +1,371 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> + +struct sdram_conf_s { + unsigned long size; + unsigned long reg; +#ifdef CONFIG_TQM8548 + unsigned long refresh; +#endif /* CONFIG_TQM8548 */ +}; + +typedef struct sdram_conf_s sdram_conf_t; + +#ifdef CONFIG_TQM8548 +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ + {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ +}; +#else /* !CONFIG_TQM8548 */ +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ + {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ + {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ +}; +#endif /* CONFIG_TQM8548 */ + +#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) + +int cas_latency (void); + +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int sdram_setup (int casl) +{ + int i; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); +#ifdef CONFIG_TQM8548 + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#else /* !CONFIG_TQM8548 */ + unsigned long cfg_ddr_timing1; + unsigned long cfg_ddr_mode; +#endif /* CONFIG_TQM8548 */ + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + +#ifdef CONFIG_TQM8548 + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_3 = 0x00010000; + + /* TIMING CFG 1, 533MHz + * PRETOACT: 4 Clocks + * ACTTOPRE: 12 Clocks + * ACTTORW: 4 Clocks + * CASLAT: 4 Clocks + * REFREC: 34 Clocks + * WRREC: 4 Clocks + * ACTTOACT: 3 Clocks + * WRTORD: 2 Clocks + */ + ddr->timing_cfg_1 = 0x4C47A432; + + /* TIMING CFG 2, 533MHz + * ADD_LAT: 3 Clocks + * CPO: READLAT + 1 + * WR_LAT: 3 Clocks + * RD_TO_PRE: 2 Clocks + * WR_DATA_DELAY: 1/2 Clock + * CKE_PLS: 1 Clock + * FOUR_ACT: 13 Clocks + */ + ddr->timing_cfg_2 = 0x3318484D; + + /* DDR SDRAM Mode, 533MHz + * MRS: Extended Mode Register + * OUT: Outputs enabled + * RDQS: no + * DQS: enabled + * OCD: default state + * RTT: 75 Ohms + * Posted CAS: 3 Clocks + * ODS: reduced strength + * DLL: enabled + * MR: Mode Register + * PD: fast exit + * WR: 4 Clocks + * DLL: no DLL reset + * TM: normal + * CAS latency: 4 Clocks + * BT: sequential + * Burst length: 4 + */ + ddr->sdram_mode = 0x439E0642; + + /* DDR SDRAM Interval, 533MHz + * REFINT: 1040 Clocks + * BSTOPRE: 256 + */ + ddr->sdram_interval = (1040 << 16) | 0x100; + + /* + * workaround for erratum DD10 of MPC8458 family below rev. 2.0: + * DDR IO receiver must be set to an acceptable bias point by modifying + * a hidden register. + */ + if (SVR_REV (get_svr ()) < 0x20) { + gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ + } + + /* DDR SDRAM CFG 2 + * FRC_SR: normal mode + * SR_IE: no self-refresh interrupt + * DLL_RST_DIS: don't care, leave at reset value + * DQS_CFG: differential DQS signals + * ODT_CFG: assert ODT to internal IOs only during reads to DRAM + * LVWx_CFG: don't care, leave at reset value + * NUM_PR: 1 refresh will be issued at a time + * DM_CFG: don't care, leave at reset value + * D_INIT: no data initialization + */ + ddr->sdram_cfg_2 = 0x04401000; + + /* DDR SDRAM MODE 2 + * MRS: Extended Mode Register 2 + */ + ddr->sdram_mode_2 = 0x8000C000; + + /* DDR SDRAM CLK CNTL + * CLK_ADJUST: 1/2 Clock 0x02000000 + * CLK_ADJUST: 5/8 Clock 0x02800000 + */ + ddr->sdram_clk_cntl = 0x02800000; + + /* wait for clock stabilization */ + asm ("sync;isync;msync"); + udelay(1000); + + /* DDR SDRAM CLK CNTL + * MEM_EN: enabled + * SREN: don't care, leave at reset value + * ECC_EN: no error report + * RD_EN: no register DIMMs + * SDRAM_TYPE: DDR2 + * DYN_PWR: no power management + * 32_BE: don't care, leave at reset value + * 8_BE: 4 beat burst + * NCAP: don't care, leave at reset value + * 2T_EN: 1T Timing + * BA_INTLV_CTL: no interleaving + * x32_EN: x16 organization + * PCHB8: MA[10] for auto-precharge + * HSE: half strength for single and 2-layer stacks + * (full strength for 3- and 4-layer stacks no yet considered) + * MEM_HALT: no halt + * BI: automatic initialization + */ + ddr->sdram_cfg = 0x83000008; + asm ("sync; isync; msync"); + udelay(1000); + +#else /* !CONFIG_TQM8548 */ + switch (casl) { + case 20: + cfg_ddr_timing1 = 0x47405331 | (3 << 16); + cfg_ddr_mode = 0x40020002 | (2 << 4); + break; + + case 25: + cfg_ddr_timing1 = 0x47405331 | (4 << 16); + cfg_ddr_mode = 0x40020002 | (6 << 4); + break; + + case 30: + default: + cfg_ddr_timing1 = 0x47405331 | (5 << 16); + cfg_ddr_mode = 0x40020002 | (3 << 4); + break; + } + + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_1 = cfg_ddr_timing1; + ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ + ddr->sdram_mode = cfg_ddr_mode; + ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ + ddr->err_disable = 0x0000000D; + + asm ("sync; isync; msync"); + udelay (1000); + + ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ + asm ("sync; isync; msync"); + udelay (1000); +#endif /* CONFIG_TQM8548 */ + + for (i = 0; i < N_DDR_CS_CONF; i++) { + ddr->cs0_config = ddr_cs_conf[i].reg; + + if (get_ram_size (0, ddr_cs_conf[i].size) == + ddr_cs_conf[i].size) { + /* + * size detected -> set Chip Select Bounds Register + */ + ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; + + break; + } + } + +#ifdef CONFIG_TQM8548 + if (i < N_DDR_CS_CONF) { + /* Adjust refresh rate for DDR2 */ + + ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; + + ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | + (ddr_cs_conf[i].refresh & 0x0000F000); + + return ddr_cs_conf[i].size; + } +#endif /* CONFIG_TQM8548 */ + + /* return size if detected, else return 0 */ + return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; +} + +void board_add_ram_info (int use_default) +{ + int casl; + + if (use_default) + casl = CONFIG_DDR_DEFAULT_CL; + else + casl = cas_latency (); + + puts (" (CL="); + switch (casl) { + case 20: + puts ("2)"); + break; + + case 25: + puts ("2.5)"); + break; + + case 30: + puts ("3)"); + break; + } +} + +long int initdram (int board_type) +{ + long dram_size = 0; + int casl; + +#if defined(CONFIG_DDR_DLL) + /* + * This DLL-Override only used on TQM8540 and TQM8560 + */ + { + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + int i, x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm ("sync; isync; msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) { + gur->devdisr = gur->devdisr | 0x00010000; + asm ("sync; isync; msync"); + for (i = 0; i < x; i++) + ; + gur->devdisr = gur->devdisr & 0xfff7ffff; + asm ("sync; isync; msync"); + x++; + } + } +#endif + + casl = cas_latency (); + dram_size = sdram_setup (casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + puts ("Problem with CAS lantency"); + board_add_ram_info (1); + puts (", using default CL!\n"); + casl = CONFIG_DDR_DEFAULT_CL; + dram_size = sdram_setup (casl); + puts (" "); + } + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c new file mode 100644 index 0000000..380448a --- /dev/null +++ b/board/tqc/tqm85xx/tlb.c @@ -0,0 +1,248 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, + CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, + CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, + CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + +#ifndef CONFIG_TQM_BIGFLASH + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, + CFG_FLASH_BASE + 0x4000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M PCI express MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, + CFG_PCIE1_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, + CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif /* CONFIG_PCIE */ + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + * 0xe3000000 16M CAN and NAND Flash + */ + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 9: 16M Non-cacheable, guarded + * 0xef000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + +#else /* CONFIG_TQM_BIGFLASH */ + + /* + * TLB 0,1,2,3: 1G Non-cacheable, guarded + * 0xc0000000 1G FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, + CFG_FLASH_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, + CFG_FLASH_BASE + 0x20000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, + CFG_FLASH_BASE + 0x30000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xb0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + +#endif /* CONFIG_PCIE */ + + /* + * TLB 7: 64M Non-cacheable, guarded + * 0xa0000000 1M CCSRBAR + * 0xa2000000 16M PCI1 IO + * 0xa3000000 16M CAN and NAND Flash + */ + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 8+9: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 10: 16M Non-cacheable, guarded + * 0xaf000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + +#endif /* CONFIG_TQM_BIGFLASH */ +}; + +int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c new file mode 100644 index 0000000..f1c2e58 --- /dev/null +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -0,0 +1,744 @@ +/* + * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <ioports.h> +#include <flash.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +ulong flash_get_size (ulong base, int banknum); + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init (void); +#endif + +#ifdef CONFIG_CPM2 +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ + {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ + {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ + {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ + {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ + {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ + {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ + {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ + {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ + {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ + {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ + {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ + {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ + {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ + {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ + {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ + {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ + {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ + {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ + {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ + {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ + }, + + /* Port B: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ + {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ + {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ + {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ + {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ + {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ + {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ + {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ + {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ + {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ + }, + + /* Port C: conf, ppar, psor, pdir, podr, pdat */ + { + {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ + {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ + {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ + {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ + {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ + {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ + {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ + {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ + {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ + {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ + {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ + {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ + {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ + {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ + {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ + {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ + {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ + {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ + {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ + {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ + {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ + {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ + {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ + {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ + {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ + {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ + {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ + {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ + {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ + {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ + }, + + /* Port D: conf, ppar, psor, pdir, podr, pdat */ + { +#ifdef CONFIG_TQM8560 + {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ + {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ + {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ +#else /* !CONFIG_TQM8560 */ + {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ + {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ + {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ +#endif /* CONFIG_TQM8560 */ + {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ + {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ + {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ + {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ + {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ + {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ + {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ + {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ + {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ + {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ + {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ + {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ + {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ + {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ + {0, 0, 0, 1, 0, 0}, /* PD14: LED */ + {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ + {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ + {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ + {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ + {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ + {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ + {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ + {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ + {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ + {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ + {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ + } +}; +#endif /* CONFIG_CPM2 */ + +#define CASL_STRING1 "casl=xx" +#define CASL_STRING2 "casl=" + +static const int casl_table[] = { 20, 25, 30 }; +#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) + +int cas_latency (void) +{ + char *s = getenv ("serial#"); + int casl; + int val; + int i; + + casl = CONFIG_DDR_DEFAULT_CL; + + if (s != NULL) { + if (strncmp(s + strlen (s) - strlen (CASL_STRING1), + CASL_STRING2, strlen (CASL_STRING2)) == 0) { + val = simple_strtoul (s + strlen (s) - 2, NULL, 10); + + for (i = 0; i < N_CASL; ++i) { + if (val == casl_table[i]) { + return val; + } + } + } + } + + return casl; +} + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + printf ("Board: %s", CONFIG_BOARDNAME); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +int misc_init_r (void) +{ + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Recalculate CS configuration if second FLASH bank is available + */ + if (flash_info[0].size > 0) { + memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | + (CFG_OR1_PRELIM & 0x00007fff); + memctl->br1 = gd->bd->bi_flashstart | + (CFG_BR1_PRELIM & 0x00007fff); + /* + * Re-check to get correct base address for bank 1 + */ + flash_get_size (gd->bd->bi_flashstart, 0); + } else { + memctl->or1 = 0; + memctl->br1 = 0; + } + + /* + * If bank 1 is equipped, bank 0 is mapped after bank 1 + */ + memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | + (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | + (CFG_BR0_PRELIM & 0x00007fff); + /* + * Re-check to get correct base address for bank 0 + */ + flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + +#ifdef CFG_ENV_ADDR_REDUND + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); +#endif + + return 0; +} + +#ifdef CONFIG_CAN_DRIVER +/* + * Initialize UPMC RAM + */ +static void upmc_write (u_char addr, uint val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, + MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); + + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_CAN_BASE, 0); + + /* normal operation */ + clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); +} +#endif /* CONFIG_CAN_DRIVER */ + +uint get_lbc_clock (void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + sys_info_t sys_info; + ulong clkdiv = lbc->lcrr & 0x0f; + + get_sys_info (&sys_info); + + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { +#ifdef CONFIG_MPC8548 + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider value. + */ + clkdiv *= 2; +#endif + return sys_info.freqSystemBus / clkdiv; + } + + puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + uint lbc_mhz = get_lbc_clock () / 1000000; + +#ifdef CONFIG_MPC8548 + uint svr = get_svr (); + uint lcrr; + + /* + * MPC revision < 2.0 + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0x0000_FFFF + * 3. OR result with 0x0000_0004 + * 4. Write result back to offset 0xE_0F20." + * + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0xFFFF_FFDF + * 3. Write result back to offset 0xE_0F20." + * + * Since it is the same register, we do the modification in one step. + */ + if (SVR_MAJ (svr) < 2) { + uint dummy = gur->lbiuiplldcr1; + dummy &= 0x0000FFDF; + dummy |= 0x00000004; + gur->lbiuiplldcr1 = dummy; + } + + lcrr = CFG_LBC_LCRR; + + /* + * Local Bus Clock > 83.3 MHz. According to timing + * specifications set LCRR[EADC] to 2 delay cycles. + */ + if (lbc_mhz > 83) { + lcrr &= ~LCRR_EADC; + lcrr |= LCRR_EADC_2; + } + + /* + * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 + * disable PLL bypass for Local Bus Clock > 83 MHz. + */ + if (lbc_mhz >= 66) + lcrr &= (~LCRR_DBYP); /* DLL Enabled */ + + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + lbc->lcrr = lcrr; + asm ("sync;isync;msync"); + + /* + * According to MPC8548ERMAD Rev.1.3 read back LCRR + * and terminate with isync + */ + lcrr = lbc->lcrr; + asm ("isync;"); + + /* let DLL stabilize */ + udelay (500); + +#else /* !CONFIG_MPC8548 */ + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + if (lbc_mhz < 66) { + lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ + lbc->ltedr = 0xa4c80000; /* DK: !!! */ + + } else if (lbc_mhz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr (); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + udelay (200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm ("sync;isync;msync"); + } +#endif /* !CONFIG_MPC8548 */ + +#ifdef CONFIG_CAN_DRIVER + /* + * According to timing specifications EAD must be + * set if Local Bus Clock is > 83 MHz. + */ + if (lbc_mhz > 83) + out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); + else + out_be32 (&lbc->or2, CFG_OR2_CAN); + out_be32 (&lbc->br2, CFG_BR2_CAN); + + /* LGPL4 is UPWAIT */ + out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); + + /* Initialize UPMC for CAN: single read */ + upmc_write (0x00, 0xFFFFED00); + upmc_write (0x01, 0xCCFFCC00); + upmc_write (0x02, 0x00FFCF00); + upmc_write (0x03, 0x00FFCF00); + upmc_write (0x04, 0x00FFDC00); + upmc_write (0x05, 0x00FFCF00); + upmc_write (0x06, 0x00FFED00); + upmc_write (0x07, 0x3FFFCC07); + + /* Initialize UPMC for CAN: single write */ + upmc_write (0x18, 0xFFFFED00); + upmc_write (0x19, 0xCCFFEC00); + upmc_write (0x1A, 0x00FFED80); + upmc_write (0x1B, 0x00FFED80); + upmc_write (0x1C, 0x00FFFC00); + upmc_write (0x1D, 0x0FFFEC00); + upmc_write (0x1E, 0x0FFFEF00); + upmc_write (0x1F, 0x3FFFEC05); +#endif /* CONFIG_CAN_DRIVER */ +} + +/* + * Initialize PCI Devices, report devices found. + */ +static int first_free_busno; + +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI || CONFIG_PCI1 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +static inline void init_pci1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + /* PORDEVSR[15] */ + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + /* PORDEVSR[14] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + /* PORPLLSR[16] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || + (host_agent == 6); + + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333333) ? "33" : + (pci_speed == 66666666) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter"); + + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect (hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + + printf (" PCI on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + ushort reg16 = + PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | + PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + uint dev = PCI_BDF(hose->first_busno, 0, 0); + + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + puts ("PCI-X will only work at 66 MHz\n"); + + pci_hose_write_config_word (hose, dev, PCIX_COMMAND, + reg16); + } +#endif + } else { + puts ("PCI1: disabled\n"); + } +#else /* !(CONFIG_PCI || CONFIG_PCI1) */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif /* CONFIG_PCI || CONFIG_PCI1) */ +} + +static inline void init_pcie1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_PCIE1 + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || + (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("PCIe: %s, base address %x", + pcie_ep ? "End point" : "Root complex", (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (", with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + puts ("\n"); + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + printf (" PCIe on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; + + } else { + printf ("PCIe: disabled\n"); + } +#else /* !CONFIG_PCIE1 */ + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ +} + +void pci_init_board (void) +{ + init_pci1(); + init_pcie1(); +} + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup (void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + ft_cpu_setup (blob, bd); + + node = fdt_path_offset (blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + path = fdt_getprop (blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#ifdef CONFIG_PCIE1 + path = fdt_getprop (blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif /* CONFIG_PCIE1 */ + } +} +#endif /* CONFIG_OF_BOARD_SETUP */ + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_PS2MULT + ps2mult_early_init (); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ diff --git a/board/tqm85xx/u-boot.lds b/board/tqc/tqm85xx/u-boot.lds index 8cb551a..8cb551a 100644 --- a/board/tqm85xx/u-boot.lds +++ b/board/tqc/tqm85xx/u-boot.lds diff --git a/board/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile index b48934b..b48934b 100644 --- a/board/tqm8xx/Makefile +++ b/board/tqc/tqm8xx/Makefile diff --git a/board/tqm8xx/config.mk b/board/tqc/tqm8xx/config.mk index 9d6080b..9d6080b 100644 --- a/board/tqm8xx/config.mk +++ b/board/tqc/tqm8xx/config.mk diff --git a/board/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c index 4342ebc..4342ebc 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqc/tqm8xx/flash.c diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c index 143f368..143f368 100644 --- a/board/tqm8xx/load_sernum_ethaddr.c +++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c diff --git a/board/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 18bf2a8..18bf2a8 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c diff --git a/board/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 8c46e46..8c46e46 100644 --- a/board/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index c33581d..c33581d 100644 --- a/board/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c deleted file mode 100644 index 224af6c..0000000 --- a/board/tqm85xx/law.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c deleted file mode 100644 index 788a48c..0000000 --- a/board/tqm85xx/sdram.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -}; - -typedef struct sdram_conf_s sdram_conf_t; - -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ - {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ -}; - -#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) - -int cas_latency(void); - -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -long int sdram_setup(int casl) -{ - int i; - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); - unsigned long cfg_ddr_timing1; - unsigned long cfg_ddr_mode; - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - - switch (casl) { - case 20: - cfg_ddr_timing1 = 0x47405331 | (3 << 16); - cfg_ddr_mode = 0x40020002 | (2 << 4); - break; - - case 25: - cfg_ddr_timing1 = 0x47405331 | (4 << 16); - cfg_ddr_mode = 0x40020002 | (6 << 4); - break; - - case 30: - default: - cfg_ddr_timing1 = 0x47405331 | (5 << 16); - cfg_ddr_mode = 0x40020002 | (3 << 4); - break; - } - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_1 = cfg_ddr_timing1; - ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ - ddr->sdram_mode = cfg_ddr_mode; - ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ - ddr->err_disable = 0x0000000D; - - asm ("sync;isync;msync"); - udelay(1000); - - ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ - asm ("sync; isync; msync"); - udelay(1000); - - for (i=0; i<N_DDR_CS_CONF; i++) { - ddr->cs0_config = ddr_cs_conf[i].reg; - - if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { - /* - * OK, size detected -> all done - */ - return ddr_cs_conf[i].size; - } - } - - return 0; /* nothing found ! */ -} - -void board_add_ram_info(int use_default) -{ - int casl; - - if (use_default) - casl = CONFIG_DDR_DEFAULT_CL; - else - casl = cas_latency(); - - puts(" (CL="); - switch (casl) { - case 20: - puts("2)"); - break; - - case 25: - puts("2.5)"); - break; - - case 30: - puts("3)"); - break; - } -} - -long int initdram (int board_type) -{ - long dram_size = 0; - int casl; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - - casl = cas_latency(); - dram_size = sdram_setup(casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - puts("Problem with CAS lantency"); - board_add_ram_info(1); - puts(", using default CL!\n"); - casl = CONFIG_DDR_DEFAULT_CL; - dram_size = sdram_setup(casl); - puts(" "); - } - - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c deleted file mode 100644 index ad26cae..0000000 --- a/board/tqm85xx/tlb.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c deleted file mode 100644 index 8fa0162..0000000 --- a/board/tqm85xx/tqm85xx.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <ioports.h> -#include <flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#ifdef CONFIG_CPM2 -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; -#endif /* CONFIG_CPM2 */ - -#define CASL_STRING1 "casl=xx" -#define CASL_STRING2 "casl=" - -static const int casl_table[] = { 20, 25, 30 }; -#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) - -int cas_latency(void) -{ - char *s = getenv("serial#"); - int casl; - int val; - int i; - - casl = CONFIG_DDR_DEFAULT_CL; - - if (s != NULL) { - if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, - strlen(CASL_STRING2)) == 0) { - val = simple_strtoul(s + strlen(s) - 2, NULL, 10); - - for (i=0; i<N_CASL; ++i) { - if (val == casl_table[i]) { - return val; - } - } - } - } - - return casl; -} - -int checkboard (void) -{ - char *s = getenv("serial#"); - - printf("Board: %s", CONFIG_BOARDNAME); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - -#ifdef CONFIG_PCI - printf ("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf ("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -int misc_init_r (void) -{ - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); - } - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - } - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - lbc->ltedr = 0xa4c80000; /* DK: !!! */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr (); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay (200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm ("sync;isync;msync"); - } -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ -} - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index c56c269..7a3d63a 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -31,6 +31,7 @@ #include <watchdog.h> unsigned long get_dram_size (void); +void sdram_init(void); /* * Macros to transform values @@ -153,6 +154,13 @@ int checkboard (void) long int initdram (int board_type) { + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + return get_dram_size (); } diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S index f753df8..a282c9a 100644 --- a/board/xilinx/ml300/init.S +++ b/board/xilinx/ml300/init.S @@ -42,7 +42,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 4ab853f..1239ea0 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -213,51 +213,6 @@ long int initdram (int board_type) return detect_sdram_size(); } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - unsigned long msr; - unsigned long total_kbytes; - - total_kbytes = detect_sdram_size(); - - msr = mfmsr(); - mtmsr(msr & ~(MSR_EE)); - - for (k = 0; k < total_kbytes ; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - mtmsr(msr); - - return 0; -} -#endif - static int default_env_var(char *buf, char *var) { char *ptr; |