diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx25_3stack/mx25_3stack.c | 167 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/mx35_3stack.c | 133 | ||||
| -rw-r--r-- | board/freescale/mx51_bbg/mx51_bbg.c | 192 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/mx53_evk.c | 131 |
4 files changed, 330 insertions, 293 deletions
diff --git a/board/freescale/mx25_3stack/mx25_3stack.c b/board/freescale/mx25_3stack/mx25_3stack.c index ced6599..e5624c1 100644 --- a/board/freescale/mx25_3stack/mx25_3stack.c +++ b/board/freescale/mx25_3stack/mx25_3stack.c @@ -74,88 +74,105 @@ int dram_init(void) #ifdef CONFIG_CMD_MMC -u32 *imx_esdhc_base_addr; +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE, 1, 1}, + {MMC_SDHC2_BASE, 1, 1}, +}; -int esdhc_gpio_init(void) +int esdhc_gpio_init(bd_t *bis) { - u32 interface_esdhc = 0, val = 0; - - interface_esdhc = (readl(CCM_RCSR) & (0x00300000)) >> 20; - - switch (interface_esdhc) { - case 0: - imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE; - /* Pins */ - writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */ - writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */ - writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */ - writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */ - writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */ - writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */ - writel(0x06, IOMUXC_BASE + 0x094); /* D12 (SD1_DATA4) */ - writel(0x06, IOMUXC_BASE + 0x090); /* D13 (SD1_DATA5) */ - writel(0x06, IOMUXC_BASE + 0x08c); /* D14 (SD1_DATA6) */ - writel(0x06, IOMUXC_BASE + 0x088); /* D15 (SD1_DATA7) */ - writel(0x05, IOMUXC_BASE + 0x010); /* A14 (SD1_WP) */ - writel(0x05, IOMUXC_BASE + 0x014); /* A15 (SD1_DET) */ - - /* Pads */ - writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */ - writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */ - writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */ - writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */ - writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */ - writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */ - writel(0xD1, IOMUXC_BASE + 0x28c); /* D12 (SD1_DATA4) */ - writel(0xD1, IOMUXC_BASE + 0x288); /* D13 (SD1_DATA5) */ - writel(0xD1, IOMUXC_BASE + 0x284); /* D14 (SD1_DATA6) */ - writel(0xD1, IOMUXC_BASE + 0x280); /* D15 (SD1_DATA7) */ - writel(0xD1, IOMUXC_BASE + 0x230); /* A14 (SD1_WP) */ - writel(0xD1, IOMUXC_BASE + 0x234); /* A15 (SD1_DET) */ - - /* - * Set write protect and card detect gpio as inputs - * A14 (SD1_WP) and A15 (SD1_DET) - */ - val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR); - writel(val, GPIO1_BASE + GPIO_GDIR); - break; - case 1: - imx_esdhc_base_addr = (u32 *)MMC_SDHC2_BASE; - /* Pins */ - writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */ - writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */ - writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0) */ - writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1) */ - writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2) */ - writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3) */ - writel(0x02, IOMUXC_BASE + 0x120); /* CSI_D2 (SD1_DATA4) */ - writel(0x02, IOMUXC_BASE + 0x124); /* CSI_D3 (SD1_DATA5) */ - writel(0x02, IOMUXC_BASE + 0x128); /* CSI_D4 (SD1_DATA6) */ - writel(0x02, IOMUXC_BASE + 0x12c); /* CSI_D5 (SD1_DATA7) */ - - /* Pads */ - writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */ - writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */ - writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0) */ - writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1) */ - writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2) */ - writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3) */ - writel(0xD1, IOMUXC_BASE + 0x318); /* CSI_D2 (SD1_DATA4) */ - writel(0xD1, IOMUXC_BASE + 0x31c); /* CSI_D3 (SD1_DATA5) */ - writel(0xD1, IOMUXC_BASE + 0x320); /* CSI_D4 (SD1_DATA6) */ - writel(0xD1, IOMUXC_BASE + 0x324); /* CSI_D5 (SD1_DATA7) */ - break; - default: - break; + s32 status = 0; + u32 index = 0; + u32 val = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + /* Pins */ + writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */ + writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */ + writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */ + writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */ + writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */ + writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */ + writel(0x06, IOMUXC_BASE + 0x094); /* D12 (SD1_DATA4) */ + writel(0x06, IOMUXC_BASE + 0x090); /* D13 (SD1_DATA5) */ + writel(0x06, IOMUXC_BASE + 0x08c); /* D14 (SD1_DATA6) */ + writel(0x06, IOMUXC_BASE + 0x088); /* D15 (SD1_DATA7) */ + writel(0x05, IOMUXC_BASE + 0x010); /* A14 (SD1_WP) */ + writel(0x05, IOMUXC_BASE + 0x014); /* A15 (SD1_DET) */ + + /* Pads */ + writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */ + writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */ + writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */ + writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */ + writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */ + writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */ + writel(0xD1, IOMUXC_BASE + 0x28c); /* D12 (SD1_DATA4) */ + writel(0xD1, IOMUXC_BASE + 0x288); /* D13 (SD1_DATA5) */ + writel(0xD1, IOMUXC_BASE + 0x284); /* D14 (SD1_DATA6) */ + writel(0xD1, IOMUXC_BASE + 0x280); /* D15 (SD1_DATA7) */ + writel(0xD1, IOMUXC_BASE + 0x230); /* A14 (SD1_WP) */ + writel(0xD1, IOMUXC_BASE + 0x234); /* A15 (SD1_DET) */ + + /* + * Set write protect and card detect gpio as inputs + * A14 (SD1_WP) and A15 (SD1_DET) + */ + val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR); + writel(val, GPIO1_BASE + GPIO_GDIR); + break; + case 1: + /* Pins */ + writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */ + writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */ + writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0)*/ + writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1)*/ + writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2)*/ + writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3)*/ + /* CSI_D2 (SD1_DATA4) */ + writel(0x02, IOMUXC_BASE + 0x120); + /* CSI_D3 (SD1_DATA5) */ + writel(0x02, IOMUXC_BASE + 0x124); + /* CSI_D4 (SD1_DATA6) */ + writel(0x02, IOMUXC_BASE + 0x128); + /* CSI_D5 (SD1_DATA7) */ + writel(0x02, IOMUXC_BASE + 0x12c); + + /* Pads */ + writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */ + writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */ + writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0)*/ + writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1)*/ + writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2)*/ + writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3)*/ + /* CSI_D2 (SD1_DATA4) */ + writel(0xD1, IOMUXC_BASE + 0x318); + /* CSI_D3 (SD1_DATA5) */ + writel(0xD1, IOMUXC_BASE + 0x31c); + /* CSI_D4 (SD1_DATA6) */ + writel(0xD1, IOMUXC_BASE + 0x320); + /* CSI_D5 (SD1_DATA7) */ + writel(0xD1, IOMUXC_BASE + 0x324); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); } return 0; } -int board_mmc_init(void) +int board_mmc_init(bd_t *bis) { - if (!esdhc_gpio_init()) - return fsl_esdhc_mmc_init(gd->bd); + if (!esdhc_gpio_init(bis)) + return 0; else return -1; } diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c index 6480c16..4da8f25 100644 --- a/board/freescale/mx35_3stack/mx35_3stack.c +++ b/board/freescale/mx35_3stack/mx35_3stack.c @@ -370,85 +370,82 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_CMD_MMC -u32 *imx_esdhc_base_addr; +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; -int esdhc_gpio_init(void) +int esdhc_gpio_init(bd_t *bis) { - u32 interface_esdhc = 0; - u32 pad_val = 0; - - interface_esdhc = (readl(IIM_BASE_ADDR + 0x80c)) & (0x000000C0) >> 6; + u32 pad_val = 0, index = 0; + s32 status = 0; /* IOMUX PROGRAMMING */ - switch (interface_esdhc) { - case 0: - imx_esdhc_base_addr = \ - (u32 *)MMC_SDHC1_BASE_ADDR; - - pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; - mxc_request_iomux(MX35_PIN_SD1_CMD, - MUX_CONFIG_FUNC | MUX_CONFIG_SION); - mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val); - - pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; - mxc_request_iomux(MX35_PIN_SD1_CLK, + PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC | MUX_CONFIG_SION); - mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val); - mxc_request_iomux(MX35_PIN_SD1_DATA0, - MUX_CONFIG_FUNC); - mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val); - mxc_request_iomux(MX35_PIN_SD1_DATA3, - MUX_CONFIG_FUNC); - mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val); - - break; - case 1: - imx_esdhc_base_addr = \ - (u32 *)MMC_SDHC2_BASE_ADDR; - - mxc_request_iomux(MX35_PIN_SD2_CLK, - MUX_CONFIG_FUNC | MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_SD2_CMD, - MUX_CONFIG_FUNC | MUX_CONFIG_SION); - mxc_request_iomux(MX35_PIN_SD2_DATA0, - MUX_CONFIG_FUNC); - mxc_request_iomux(MX35_PIN_SD2_DATA3, - MUX_CONFIG_FUNC); - - pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | - PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; - mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); - - pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | - PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | - PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; - mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val); - mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); - mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val); - - break; - case 2: - imx_esdhc_base_addr = \ - (u32 *)MMC_SDHC3_BASE_ADDR; - - printf("TO2 ESDHC3 not supported!"); - break; - default: - break; + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + mxc_request_iomux(MX35_PIN_SD1_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val); + mxc_request_iomux(MX35_PIN_SD1_DATA0, + MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val); + mxc_request_iomux(MX35_PIN_SD1_DATA3, + MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val); + + break; + case 1: + mxc_request_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD2_DATA3, + MUX_CONFIG_FUNC); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_100K_PD | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); } - return 0; + return status; } -int board_mmc_init(void) +int board_mmc_init(bd_t *bis) { - if (!esdhc_gpio_init()) - return fsl_esdhc_mmc_init(gd->bd); + if (!esdhc_gpio_init(bis)) + return 0; else return -1; } diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c index 4446a63..1d553c1 100644 --- a/board/freescale/mx51_bbg/mx51_bbg.c +++ b/board/freescale/mx51_bbg/mx51_bbg.c @@ -567,108 +567,114 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_CMD_MMC -u32 *imx_esdhc_base_addr; +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; -int esdhc_gpio_init(void) +int esdhc_gpio_init(bd_t *bis) { - u32 interface_esdhc = 0; s32 status = 0; - u32 pad = 0; - uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); - - interface_esdhc = (soc_sbmr & (0x00180000)) >> 19; - - switch (interface_esdhc) { - case 0: - imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE_ADDR; - - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - break; - case 1: - imx_esdhc_base_addr = (u32 *)MMC_SDHC2_BASE_ADDR; - - pad = PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST; - - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_DATA1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_DATA2, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD2_DATA3, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, pad); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, pad); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, pad); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, pad); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, pad); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, pad); - break; - case 2: - status = -1; - break; - case 3: - status = -1; - break; - default: - status = -1; - break; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + break; + case 1: + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); } return status; } -int board_mmc_init(void) +int board_mmc_init(bd_t *bis) { - if (!esdhc_gpio_init()) - return fsl_esdhc_mmc_init(gd->bd); + if (!esdhc_gpio_init(bis)) + return 0; else return -1; } diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c index 4804b02..9661df6 100644 --- a/board/freescale/mx53_evk/mx53_evk.c +++ b/board/freescale/mx53_evk/mx53_evk.c @@ -402,72 +402,89 @@ static void setup_fec(void) #ifdef CONFIG_CMD_MMC -u32 *imx_esdhc_base_addr; +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; -int esdhc_gpio_init(void) +int esdhc_gpio_init(bd_t *bis) { - u32 interface_esdhc = 0; s32 status = 0; - uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); - - interface_esdhc = (soc_sbmr & (0x00300000)) >> 20; - - switch (interface_esdhc) { - case 0: - imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE_ADDR; - - mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - - mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); - mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); - break; - case 2: - imx_esdhc_base_addr = (u32 *)MMC_SDHC3_BASE_ADDR; - - mxc_request_iomux(MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4); - mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4); - - mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4); - mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); - - break; - default: - status = -1; - break; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_ATA_RESET_B, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_IORDY, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA8, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA9, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA10, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA11, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA0, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA1, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA2, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA3, + IOMUX_CONFIG_ALT4); + + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); } return status; } -int board_mmc_init(void) +int board_mmc_init(bd_t *bis) { - if (!esdhc_gpio_init()) - return fsl_esdhc_mmc_init(gd->bd); + if (!esdhc_gpio_init(bis)) + return 0; else return -1; } |