diff options
Diffstat (limited to 'board')
339 files changed, 22370 insertions, 5528 deletions
diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c new file mode 100644 index 0000000..f18313d --- /dev/null +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include "asm/m5282.h" +#include "VCxK.h" + +int checkboard (void) +{ + puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n"); +#if (TEXT_BASE == CFG_INT_FLASH_BASE) + puts (" Boot from Internal FLASH\n"); +#endif + + return 0; +} + +long int initdram (int board_type) +{ + int size,i; + + size = 0; + MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4); + #ifdef CFG_SDRAM_BASE0 + + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16); + + MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; + + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + *(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5; + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + for (i=0; i < 2000; i++) + asm(" nop"); + mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0) + | MCFSDRAMC_DACR_IMRS); + *(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5; + size += CFG_SDRAM_SIZE * 1024 * 1024; + #endif + #ifdef CFG_SDRAM_BASE1 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16; + + MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; + + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; + + *(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5; + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; + for (i=0; i < 2000; i++) + asm(" nop"); + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; + *(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SDRAM_SIZE1 * 1024 * 1024; + #endif + return size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + +int misc_init_r(void) +{ + init_vcxk(); + return 1; +} + +/*---------------------------------------------------------------------------*/ + +int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + ulong source; + + switch (argc) { + case 2: + source = simple_strtoul(argv[1],NULL,16); + vcxk_loadimage(source); + rcode = 0; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + break; + } + return rcode; +} + +/***************************************************/ + +U_BOOT_CMD( + vcimage, 2, 0, do_vcimage, + "vcimage - loads an image to Display\n", + "vcimage addr\n" +); + +/* EOF EB+MCF-EV123c */ diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile new file mode 100644 index 0000000..0596572 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c new file mode 100644 index 0000000..4938817 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/m5282.h> +#include "VCxK.h" + +vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE); +#define VCXK_BWS vcxk_bws + +static ulong vcxk_driver; + + +ulong search_vcxk_driver(void); +void vcxk_cls(void); +void vcxk_setbrightness(short brightness); +int vcxk_request(void); +int vcxk_acknowledge_wait(void); +void vcxk_clear(void); + +int init_vcxk(void) +{ + VIDEO_Invert_CFG &= ~VIDEO_Invert_IO; + VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN; + VIDEO_INVERT_DDR |= VIDEO_INVERT_PIN; + + VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN; + VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN; + + VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN; + + vcxk_driver = search_vcxk_driver(); + if (vcxk_driver) + { + /* use flash resist driver */ + } + else + { + vcxk_cls(); + vcxk_cls(); + vcxk_setbrightness(1000); + } + VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN; + VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN; + VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN; + return 1; +} + +void vcxk_loadimage(ulong source) +{ + int cnt; + vcxk_acknowledge_wait(); + for (cnt=0; cnt<16384; cnt++) + { + VCXK_BWS[cnt*2] = (*(vu_char*) source); + source++; + } + vcxk_request(); +} + +void vcxk_cls(void) +{ + vcxk_acknowledge_wait(); + vcxk_clear(); + vcxk_request(); +} + +void vcxk_clear(void) +{ + int cnt; + for (cnt=0; cnt<16384; cnt++) + { + VCXK_BWS[cnt*2] = 0x00; + } +} + +void vcxk_setbrightness(short brightness) +{ + VCXK_BWS[0x8000]=(brightness >> 4) +2; + VCXK_BWS[0xC000]= (brightness + 23) >> 8; + VCXK_BWS[0xC001]= (brightness + 23) & 0xFF; +} + +int vcxk_request(void) +{ + if (vcxk_driver) + { + /* use flash resist driver */ + } + else + { + VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN; + VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN; + } + return 1; +} + +int vcxk_acknowledge_wait(void) +{ + if (vcxk_driver) + { + /* use flash resist driver */ + } + else + { + while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN)); + } + return 1; +} + +ulong search_vcxk_driver(void) +{ + return 0; +} + +/* eof */ diff --git a/board/BuS/EB+MCF-EV123/VCxK.h b/board/BuS/EB+MCF-EV123/VCxK.h new file mode 100644 index 0000000..74467ba --- /dev/null +++ b/board/BuS/EB+MCF-EV123/VCxK.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VCXK_H_ +#define __VCXK_H_ + +extern int init_vcxk(void); +void vcxk_loadimage(ulong source); + +#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT +#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR +#define VIDEO_ACKNOWLEDGE_PIN 0x0001 + +#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT +#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR +#define VIDEO_ENABLE_PIN 0x0002 + +#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT +#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR +#define VIDEO_REQUEST_PIN 0x0004 + +#define VIDEO_Invert_CFG MCFGPIO_PEPAR +#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2 +#define VIDEO_INVERT_PORT MCFGPIO_PORTE +#define VIDEO_INVERT_DDR MCFGPIO_DDRE +#define VIDEO_INVERT_PIN MCFGPIO_PORT2 + +#endif diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c new file mode 100644 index 0000000..6ecf0d1 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -0,0 +1,212 @@ +/* + * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH + * + * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/m5282.h> +#include "cfm_flash.h" + +#if defined(CONFIG_M5281) || defined(CONFIG_M5282) + +#if (CFG_CLK>20000000) + #define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40) +#else + #define CFM_CLK ((long) CFG_CLK / 400000 + 1) +#endif + +#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \ + (CFG_MBAR & 0xC0000000)) + +void cfm_flash_print_info (flash_info_t * info) +{ + printf ("Freescale: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK: + printf ("MCF5281 internal FLASH\n"); + break; + case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK: + printf ("MCF5282 internal FLASH\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } +} + +void cfm_flash_init (flash_info_t * info) +{ + int sector; + ulong protection; + MCFCFM_MCR = 0; + MCFCFM_CLKD = CFM_CLK; + debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ + CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CFG_CLK); + MCFCFM_SACC = 0; + MCFCFM_DACC = 0; + + if (MCFCFM_SEC & MCFCFM_SEC_KEYEN) + puts("CFM backdoor access is enabled\n"); + if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT) + puts("CFM securety is enabled\n"); + + #ifdef CONFIG_M5281 + info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) | + (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK); + info->size = 256*1024; + info->sector_count = 16; + #else + info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) | + (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK); + info->size = 512*1024; + info->sector_count = 32; + #endif + protection = MCFCFM_PROT; + for (sector = 0; sector < info->sector_count; sector++) + { + if (sector == 0) + { + info->start[sector] = CFG_INT_FLASH_BASE; + } + else + { + info->start[sector] = info->start[sector-1] + 0x04000; + } + info->protect[sector] = protection & 1; + protection >>= 1; + } +} + +int cfm_flash_readycheck(int checkblank) +{ + int rc; + unsigned char state; + + rc = ERR_OK; + while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF)); + state = MCFCFM_USTAT; + if (state & MCFCFM_USTAT_ACCERR) + { + debug ("%s(): CFM access error",__FUNCTION__); + rc = ERR_PROG_ERROR; + } + if (state & MCFCFM_USTAT_PVIOL) + { + debug ("%s(): CFM protection violation",__FUNCTION__); + rc = ERR_PROTECTED; + } + if (checkblank) + { + if (!(state & MCFCFM_USTAT_BLANK)) + { + debug ("%s(): CFM erras error",__FUNCTION__); + rc = ERR_NOT_ERASED; + } + } + MCFCFM_USTAT = state & 0x34; /* reset state */ + return rc; +} + +/* Erase 16KiB = 8 2KiB pages */ + +int cfm_flash_erase_sector (flash_info_t * info, int sector) +{ + ulong address; + int page; + int rc; + rc= ERR_OK; + address = cmf_backdoor_address(info->start[sector]); + for (page=0; (page<8) && (rc==ERR_OK); page++) + { + *(volatile __u32*) address = 0; + MCFCFM_CMD = MCFCFM_CMD_PGERS; + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; + rc = cfm_flash_readycheck(0); + if (rc==ERR_OK) + { + *(volatile __u32*) address = 0; + MCFCFM_CMD = MCFCFM_CMD_PGERSVER; + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; + rc = cfm_flash_readycheck(1); + } + address += 0x800; + } + return rc; +} + +int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + ulong dest, data; + + rc = ERR_OK; + if (addr & 3) + { + debug ("Byte and Word alignment not supported\n"); + rc = ERR_ALIGN; + } + if (cnt & 3) + { + debug ("Byte and Word transfer not supported\n"); + rc = ERR_ALIGN; + } + dest = cmf_backdoor_address(addr); + while ((cnt>=4) && (rc == ERR_OK)) + { + data =*((volatile u32 *) src); + *(volatile u32*) dest = data; + MCFCFM_CMD = MCFCFM_CMD_PGM; + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; + rc = cfm_flash_readycheck(0); + if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR; + src +=4; + dest +=4; + addr +=4; + cnt -=4; + } + return rc; +} + +#ifdef CFG_FLASH_PROTECTION + +int cfm_flash_protect(flash_info_t * info,long sector,int prot) +{ + int rc; + + rc= ERR_OK; + if (prot) + { + MCFCFM_PROT |= (1<<sector); + info->protect[sector]=1; + } + else + { + MCFCFM_PROT &= ~(1<<sector); + info->protect[sector]=0; + } + return rc; +} + +#endif + +#endif diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.h b/board/BuS/EB+MCF-EV123/cfm_flash.h new file mode 100644 index 0000000..cc8cdbd --- /dev/null +++ b/board/BuS/EB+MCF-EV123/cfm_flash.h @@ -0,0 +1,40 @@ +/* + * Basic Flash Driver for Freescale MCF 5282 internal FLASH + * + * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CFM_FLASH_H_ +#define __CFM_FLASH_H_ + +#define FREESCALE_MANUFACT 0xFACFFACF +#define FREESCALE_ID_MCF5281 0x5281 +#define FREESCALE_ID_MCF5282 0x5282 + +extern void cfm_flash_print_info (flash_info_t * info); +extern int cfm_flash_erase_sector (flash_info_t * info, int sector); +extern void cfm_flash_init (flash_info_t * info); +extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +#ifdef CFG_FLASH_PROTECTION +extern int cfm_flash_protect(flash_info_t * info,long sector,int prot); +#endif + +#endif diff --git a/board/BuS/EB+MCF-EV123/config.mk b/board/BuS/EB+MCF-EV123/config.mk new file mode 100644 index 0000000..9fe2fc5 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk +ifndef TEXT_BASE +TEXT_BASE = 0xFE000000 +endif diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c new file mode 100644 index 0000000..ba76bef --- /dev/null +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> + * + * Based On + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include "cfm_flash.h" + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV160B & FLASH_TYPEMASK): + printf ("AM29LV160B (16Bit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + break; + case FREESCALE_MANUFACT & FLASH_VENDMASK: + cfm_flash_print_info (info); + break; + default: + printf ("Unknown Vendor "); + break; + } + + puts (" Size: "); + if ((info->size >> 20) > 0) + { + printf ("%ld MiB",info->size >> 20); + } + else + { + printf ("%ld KiB",info->size >> 10); + } + printf (" in %d Sectors\n", info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) { + printf ("\n "); + } + printf ("%02d: %08lX%s ", i,info->start[i], + info->protect[i] ? " P" : " "); + } + printf ("\n\n"); +} + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + switch (i) + { + case 1: + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV160B & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flashbase = PHYS_FLASH_1; + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 32 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 34)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x10000 + 0x10000 * (j - 4); + } + } + break; + case 0: + cfm_flash_init (&flash_info[i]); + break; + default: + panic ("configured to many flash banks!\n"); + } + + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0xffff, &flash_info[0]); + + return size; +} + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1))) + + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define ERR_READY -1 + +int amd_flash_erase_sector(flash_info_t * info, int sector) +{ + int state; + ulong result; + + volatile u16 *addr = + (volatile u16 *) (info->start[sector]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + state = 0; + set_timer (0); + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + state = ERR_TIMOUT; + } + + if (!state && (result & 0xFFFF) & BIT_ERASE_DONE) + state = ERR_READY; + } + while (!state); + if (state == ERR_READY) + state = ERR_OK; + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + return state; +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int iflag, cflag; + int sector; + int rc; + + rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + { + rc = ERR_UNKNOWN_FLASH_TYPE; + } /* (info->flash_id == FLASH_UNKNOWN) */ + + if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count) + { + rc = ERR_INVAL; + } + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) { + + if (info->protect[sector]) + { + putc('P'); /* protected sector will not erase */ + } + else + { + /* erase on unprotected sector */ + puts("E\b"); + switch (info->flash_id & FLASH_VENDMASK) + { + case (AMD_MANUFACT & FLASH_VENDMASK): + rc = amd_flash_erase_sector(info,sector); + break; + case (FREESCALE_MANUFACT & FLASH_VENDMASK): + rc = cfm_flash_erase_sector(info,sector); + break; + default: + return ERR_UNKNOWN_FLASH_VENDOR; + } + putc('.'); + } + } + if (rc!=ERR_OK) + { + printf ("\n "); + flash_perror (rc); + } + else + { + printf (" done\n"); + } + + udelay (10000); /* allow flash to settle - wait 10 ms */ + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) +{ + volatile u16 *addr; + ulong result; + int cflag, iflag; + int state; + + /* + * Check if Flash is (sufficiently) erased + */ + addr = (volatile u16 *) dest; + + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + state = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + state = ERR_TIMOUT; + } + if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK))) + state = ERR_READY; + + } while (!state); + + *addr = CMD_READ_ARRAY; + + if (state == ERR_READY) + state = ERR_OK; + if ((*addr != data) && (state != ERR_TIMOUT)) + state = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return state; +} + +int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + ulong dest; + u16 data; + + rc = ERR_OK; + if (addr & 1) + { + debug ("Byte alignment not supported\n"); + rc = ERR_ALIGN; + } + if (cnt & 1) + { + debug ("Byte transfer not supported\n"); + rc = ERR_ALIGN; + } + + dest = addr; + while ((cnt>=2) && (rc == ERR_OK)) + { + data =*((volatile u16 *) src); + rc=amd_write_word (info,dest,data); + src +=2; + dest +=2; + cnt -=2; + } + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (AMD_MANUFACT & FLASH_VENDMASK): + rc = amd_flash_write_buff(info,src,addr,cnt); + break; + case (FREESCALE_MANUFACT & FLASH_VENDMASK): + rc = cfm_flash_write_buff(info,src,addr,cnt); + break; + default: + rc = ERR_UNKNOWN_FLASH_VENDOR; + } + return rc; + +} +int amd_flash_protect(flash_info_t * info,long sector,int prot) +{ + int rc; + rc= ERR_OK; + if (prot) + { + info->protect[sector]=1; + } + else + { + info->protect[sector]=0; + } + return rc; +} + +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect(flash_info_t * info,long sector,int prot) +{ + int rc; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (AMD_MANUFACT & FLASH_VENDMASK): + rc = amd_flash_protect(info,sector,prot); + break; + case (FREESCALE_MANUFACT & FLASH_VENDMASK): + rc = cfm_flash_protect(info,sector,prot); + break; + default: + rc = ERR_UNKNOWN_FLASH_VENDOR; + } + return rc; +} + +#endif diff --git a/board/BuS/EB+MCF-EV123/textbase.mk b/board/BuS/EB+MCF-EV123/textbase.mk new file mode 100644 index 0000000..10106f4 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/textbase.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xF0000000 diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds new file mode 100644 index 0000000..d790018 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset; */ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c index 0934e1b..40f41c7 100644 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -1,6 +1,7 @@ /* * (C) Copyright 2002 * Hyperion Entertainment, ThomasF@hyperion-entertainment.com + * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -88,8 +89,6 @@ long initdram (int board_type) void after_reloc (ulong dest_addr, gd_t *gd) { -/* HJF: DECLARE_GLOBAL_DATA_PTR; */ - board_init_r (gd, dest_addr); } diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c index a4dad64..3901b80 100644 --- a/board/MAI/AmigaOneG3SE/articiaS.c +++ b/board/MAI/AmigaOneG3SE/articiaS.c @@ -29,6 +29,8 @@ #include "smbus.h" #include "via686.h" +DECLARE_GLOBAL_DATA_PTR; + #undef DEBUG struct dimm_bank { @@ -82,7 +84,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte) long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks) { - DECLARE_GLOBAL_DATA_PTR; int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR; uint32 busclock = gd->bus_clk; uint32 memclock = busclock; @@ -394,8 +395,6 @@ uint32 burst_to_len (uint32 support) long articiaS_ram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - register uint32 i; register uint32 value1; register uint32 value2; diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c index d2e9f29..480dae5 100644 --- a/board/MAI/AmigaOneG3SE/articiaS_pci.c +++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c @@ -26,6 +26,8 @@ #include "memio.h" #include "articiaS.h" +DECLARE_GLOBAL_DATA_PTR; + #undef ARTICIA_PCI_DEBUG #ifdef ARTICIA_PCI_DEBUG @@ -493,8 +495,6 @@ pci_dev_t video_dev; int articiaS_init_vga (void) { - DECLARE_GLOBAL_DATA_PTR; - extern void shutdown_bios(void); pci_dev_t dev = ~0; int busnr = 0; diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c index 3e2835a..143bba2 100644 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -3,6 +3,7 @@ #include "../disk/part_amiga.h" #include <asm/cache.h> +DECLARE_GLOBAL_DATA_PTR; #undef BOOTA_DEBUG @@ -108,8 +109,6 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) s = getenv ("autostart"); if (s && strcmp (s, "yes") == 0) { - DECLARE_GLOBAL_DATA_PTR; - void (*boot) (bd_t *, char *, block_dev_desc_t *); char *args; diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c index e83fb46..b6f57c7 100644 --- a/board/MAI/AmigaOneG3SE/serial.c +++ b/board/MAI/AmigaOneG3SE/serial.c @@ -4,6 +4,8 @@ #include "memio.h" #include "articiaS.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_NS16550 static uint32 ComPort1; @@ -150,8 +152,6 @@ const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2; int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - uint32 clock_divisor = 115200 / gd->baudrate; NS16550_init (Com0, clock_divisor); @@ -239,8 +239,6 @@ void serial_puts (const char *string) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - uint32 clock_divisor = 115200 / gd->baudrate; NS16550_init (Com0, clock_divisor); diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c index c797e47..3606db8 100644 --- a/board/MAI/AmigaOneG3SE/via686.c +++ b/board/MAI/AmigaOneG3SE/via686.c @@ -28,6 +28,8 @@ #include "via686.h" #include "i8259.h" +DECLARE_GLOBAL_DATA_PTR; + #undef VIA_DEBUG #ifdef VIA_DEBUG @@ -226,33 +228,31 @@ __asm (" .globl via_calibrate_time_base \n" extern unsigned long via_calibrate_time_base(void); -void via_calibrate_bus_freq(void) +void via_calibrate_bus_freq (void) { - DECLARE_GLOBAL_DATA_PTR; - - unsigned long tb; + unsigned long tb; - /* This is 20 microseconds */ - #define CALIBRATE_TIME 28636 + /* This is 20 microseconds */ +#define CALIBRATE_TIME 28636 + /* Enable the timer (and disable speaker) */ + unsigned char c; - /* Enable the timer (and disable speaker) */ - unsigned char c; - c = in_byte(0x61); - out_byte(0x61, ((c & ~0x02) | 0x01)); + c = in_byte (0x61); + out_byte (0x61, ((c & ~0x02) | 0x01)); - /* Set timer 2 to low/high writing */ - out_byte(0x43, 0xb0); - out_byte(0x42, CALIBRATE_TIME & 0xff); - out_byte(0x42, CALIBRATE_TIME >>8); + /* Set timer 2 to low/high writing */ + out_byte (0x43, 0xb0); + out_byte (0x42, CALIBRATE_TIME & 0xff); + out_byte (0x42, CALIBRATE_TIME >> 8); - /* Read the time base */ - tb = via_calibrate_time_base(); + /* Read the time base */ + tb = via_calibrate_time_base (); - if (tb >= 700000) - gd->bus_clk = 133333333; - else - gd->bus_clk = 100000000; + if (tb >= 700000) + gd->bus_clk = 133333333; + else + gd->bus_clk = 100000000; } diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c index 36e3c62..f6327f7 100644 --- a/board/MAI/AmigaOneG3SE/video.c +++ b/board/MAI/AmigaOneG3SE/video.c @@ -26,6 +26,8 @@ #include "memio.h" #include <part.h> +DECLARE_GLOBAL_DATA_PTR; + unsigned char *cursor_position; unsigned int cursor_row; unsigned int cursor_col; @@ -480,7 +482,6 @@ extern char version_string[]; void video_banner(void) { block_dev_desc_t *ide; - DECLARE_GLOBAL_DATA_PTR; int i; char *s; int maxdev; diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 9d0d213..6a1d4d7 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -45,13 +45,13 @@ #include "ns16550.h" +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_MPSC int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) int clock_divisor = 230400 / gd->baudrate; #endif @@ -88,8 +88,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } @@ -97,8 +95,6 @@ void serial_setbrg (void) int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = 230400 / gd->baudrate; #ifdef CFG_INIT_CHAN1 @@ -130,8 +126,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = 230400 / gd->baudrate; #ifdef CFG_INIT_CHAN1 diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index ccb3adc..d8acd31 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -42,6 +42,8 @@ #include "../include/memory.h" +DECLARE_GLOBAL_DATA_PTR; + /* Define this if you wish to use the MPSC as a register based UART. * This will force the serial port to not use the SDMA engine at all. */ @@ -114,9 +116,7 @@ static void mpsc_debug_init (void) /* Clear the CFR (CHR4) */ /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" - -REG_GAP)); + temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); temp &= 0xffffff00; temp |= BIT29; GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), @@ -158,7 +158,6 @@ char mpsc_getchar_debug (void) * global variables [josh] */ int mpsc_putchar_early (char ch) { - DECLARE_GLOBAL_DATA_PTR; int mpsc = CHANNEL; int temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); @@ -511,7 +510,6 @@ void mpsc_init2 (void) int galbrg_set_baudrate (int channel, int rate) { - DECLARE_GLOBAL_DATA_PTR; int clock; galbrg_disable (channel); /*ok */ diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 3c5dee7..e5a87ad 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -732,6 +732,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ pkt_info.byte_cnt = dataSize; pkt_info.buf_ptr = (unsigned int) dataPtr; + pkt_info.return_info = 0; status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index d2635f8..f04aaf9 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -42,6 +42,8 @@ #include "64360.h" #include "mv_regs.h" +DECLARE_GLOBAL_DATA_PTR; + #undef DEBUG #define MAP_PCI @@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte) /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long spd_checksum; #ifdef ZUMA_NTL diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c index 33fbc49..b783aff 100644 --- a/board/Marvell/db64460/mpsc.c +++ b/board/Marvell/db64460/mpsc.c @@ -42,6 +42,8 @@ #include "../include/memory.h" +DECLARE_GLOBAL_DATA_PTR; + /* Define this if you wish to use the MPSC as a register based UART. * This will force the serial port to not use the SDMA engine at all. */ @@ -114,9 +116,7 @@ static void mpsc_debug_init (void) /* Clear the CFR (CHR4) */ /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" - -REG_GAP)); + temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); temp &= 0xffffff00; temp |= BIT29; GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), @@ -158,7 +158,6 @@ char mpsc_getchar_debug (void) * global variables [josh] */ int mpsc_putchar_early (char ch) { - DECLARE_GLOBAL_DATA_PTR; int mpsc = CHANNEL; int temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); @@ -511,7 +510,6 @@ void mpsc_init2 (void) int galbrg_set_baudrate (int channel, int rate) { - DECLARE_GLOBAL_DATA_PTR; int clock; galbrg_disable (channel); /*ok */ diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index ec5d581..b2c7835 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -731,6 +731,7 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ pkt_info.byte_cnt = dataSize; pkt_info.buf_ptr = (unsigned int) dataPtr; + pkt_info.return_info = 0; status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index 8cfe84c..1762202 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -42,6 +42,8 @@ #include "64460.h" #include "mv_regs.h" +DECLARE_GLOBAL_DATA_PTR; + #undef DEBUG #define MAP_PCI @@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte) /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long spd_checksum; #ifdef ZUMA_NTL diff --git a/board/adder/adder.c b/board/adder/adder.c index cab6e2f..aa781584 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -28,7 +28,8 @@ #include <mpc8xx.h> /* - * SDRAM is single Samsung K4S643232F-T70 chip. + * SDRAM is single Samsung K4S643232F-T70 chip (8MB) + * or single Micron MT48LC4M32B2TG-7 chip (16MB). * Minimal CPU frequency is 40MHz. */ static uint sdram_table[] = { @@ -53,7 +54,7 @@ static uint sdram_table[] = { 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, @@ -63,7 +64,7 @@ static uint sdram_table[] = { long int initdram (int board_type) { - long int msize = CFG_SDRAM_SIZE; + long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -72,11 +73,11 @@ long int initdram (int board_type) /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - memctl->memc_mamr = (94 << 24) | CFG_MAMR; - memctl->memc_mar = 0x0; + memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */ udelay(200); /* Run precharge from location 0x15 */ + memctl->memc_mar = 0x0; memctl->memc_mcr = 0x80002115; udelay(200); @@ -84,13 +85,18 @@ long int initdram (int board_type) memctl->memc_mcr = 0x80002830; udelay(200); - memctl->memc_mar = 0x88; - udelay(200); - /* Run MRS pattern from location 0x16 */ + memctl->memc_mar = 0x88; memctl->memc_mcr = 0x80002116; udelay(200); + memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ + memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + + msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + memctl->memc_or1 |= ~(msize - 1); + return msize; } diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c index 5e770e9..c430d63 100644 --- a/board/adsvix/adsvix.c +++ b/board/adsvix/adsvix.c @@ -30,6 +30,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* @@ -38,8 +40,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -62,8 +62,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c new file mode 100644 index 0000000..8a7b14e --- /dev/null +++ b/board/altera/common/AMDLV065D.c @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#if defined(CONFIG_NIOS) +#include <nios.h> +#else +#include <asm/io.h> +#endif + +#define SECTSZ (64 * 1024) +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + int i; + unsigned long addr; + flash_info_t *fli = &flash_info[0]; + + fli->size = CFG_FLASH_SIZE; + fli->sector_count = CFG_MAX_FLASH_SECT; + fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; + + addr = CFG_FLASH_BASE; + for (i = 0; i < fli->sector_count; ++i) { + fli->start[i] = addr; + addr += SECTSZ; + fli->protect[i] = 1; + } + + return (CFG_FLASH_SIZE); +} +/*--------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i, k; + int erased; + unsigned long *addr; + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + + /* Check if whole sector is erased */ + erased = 1; + addr = (unsigned long *) info->start[i]; + for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { + if ( readl(addr++) != (unsigned long)-1) { + erased = 0; + break; + } + } + + /* Print the info */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*-------------------------------------------------------------------*/ + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + unsigned char *addr = (unsigned char *) info->start[0]; + unsigned char *addr2; + int prot, sect; + ulong start; + + /* Some sanity checking */ + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* It's ok to erase multiple sectors provided we don't delay more + * than 50 usec between cmds ... at which point the erase time-out + * occurs. So don't go and put printf() calls in the loop ... it + * won't be very helpful ;-) + */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (unsigned char *) info->start[sect]; + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr, 0x80); + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr2, 0x30); + /* Now just wait for 0xff & provide some user + * feedback while we wait. + */ + start = get_timer (0); + while ( readb (addr2) != 0xff) { + udelay (1000 * 1000); + putc ('.'); + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("timeout\n"); + return 1; + } + } + } + } + printf ("\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + + vu_char *cmd = (vu_char *) info->start[0]; + vu_char *dst = (vu_char *) addr; + unsigned char b; + ulong start; + + while (cnt) { + /* Check for sufficient erase */ + b = *src; + if ((readb (dst) & b) != b) { + printf ("%02x : %02x\n", readb (dst), b); + return (2); + } + + writeb (cmd, 0xaa); + writeb (cmd, 0x55); + writeb (cmd, 0xa0); + writeb (dst, b); + + /* Verify write */ + start = get_timer (0); + while (readb (dst) != b) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + dst++; + src++; + cnt--; + } + + return (0); +} diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c new file mode 100644 index 0000000..c75fe8c --- /dev/null +++ b/board/altera/common/epled.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <nios2-io.h> +#include <status_led.h> + +/* The LED port is configured as output only, so we + * must track the state manually. + */ +static led_id_t val = 0; + +void __led_init (led_id_t mask, int state) +{ + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + + if (state == STATUS_LED_ON) + val &= ~mask; + else + val |= mask; + writel (&pio->data, val); +} + +void __led_set (led_id_t mask, int state) +{ + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + + if (state == STATUS_LED_ON) + val &= ~mask; + else + val |= mask; + writel (&pio->data, val); +} + +void __led_toggle (led_id_t mask) +{ + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + + val ^= mask; + writel (&pio->data, val); +} diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile new file mode 100644 index 0000000..a92b258 --- /dev/null +++ b/board/altera/ep1c20/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o ../common/epled.o + +OBJS := $(BOARD).o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk new file mode 100644 index 0000000..dab2740 --- /dev/null +++ b/board/altera/ep1c20/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005, Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt@psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01fc0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c new file mode 100644 index 0000000..2949139 --- /dev/null +++ b/board/altera/ep1c20/ep1c20.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("BOARD : Altera EP-1C20\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/altera/ep1c20/u-boot.lds b/board/altera/ep1c20/u-boot.lds new file mode 100644 index 0000000..b99b82c --- /dev/null +++ b/board/altera/ep1c20/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile new file mode 100644 index 0000000..a92b258 --- /dev/null +++ b/board/altera/ep1s10/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o ../common/epled.o + +OBJS := $(BOARD).o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk new file mode 100644 index 0000000..dab2740 --- /dev/null +++ b/board/altera/ep1s10/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005, Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt@psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01fc0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c new file mode 100644 index 0000000..9c7e28e --- /dev/null +++ b/board/altera/ep1s10/ep1s10.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("BOARD : Altera EP-1S10\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/altera/ep1s10/u-boot.lds b/board/altera/ep1s10/u-boot.lds new file mode 100644 index 0000000..b99b82c --- /dev/null +++ b/board/altera/ep1s10/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile new file mode 100644 index 0000000..a92b258 --- /dev/null +++ b/board/altera/ep1s40/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o ../common/epled.o + +OBJS := $(BOARD).o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk new file mode 100644 index 0000000..dab2740 --- /dev/null +++ b/board/altera/ep1s40/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005, Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt@psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01fc0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c new file mode 100644 index 0000000..cb75550 --- /dev/null +++ b/board/altera/ep1s40/ep1s40.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int checkboard (void) +{ + puts ("BOARD : Altera EP-1S40\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/altera/ep1s40/u-boot.lds b/board/altera/ep1s40/u-boot.lds new file mode 100644 index 0000000..b99b82c --- /dev/null +++ b/board/altera/ep1s40/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 803995a..7c98920 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -277,7 +277,7 @@ int board_early_init_f(void) } #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; /*----------------------------------------------------------------------------+ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index a2595ee..dcafac9 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -28,6 +28,8 @@ #define FLASH_ONBD_N 2 /* 00000010 */ #define FLASH_SRAM_SEL 1 /* 00000001 */ +DECLARE_GLOBAL_DATA_PTR; + long int fixed_sdram(void); int board_early_init_f(void) @@ -107,7 +109,7 @@ long int initdram(int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(0); + dram_size = spd_sdram(); #else dram_size = fixed_sdram(); #endif @@ -235,8 +237,6 @@ int pci_pre_init(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index c6b79a9..06a57f6 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -28,6 +28,7 @@ #include <spd_sdram.h> #include "epld.h" +DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -291,8 +292,6 @@ int pci_pre_init( struct pci_controller *hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index d1a29c5..3f6d204 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -30,6 +30,8 @@ #include <spd_sdram.h> #include <ppc4xx_enet.h> +DECLARE_GLOBAL_DATA_PTR; + #define BOOT_SMALL_FLASH 32 /* 00100000 */ #define FLASH_ONBD_N 2 /* 00000010 */ #define FLASH_SRAM_SEL 1 /* 00000001 */ @@ -204,7 +206,7 @@ long int initdram (int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); + dram_size = spd_sdram (); #else dram_size = fixed_sdram (); #endif @@ -334,8 +336,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index f1a96a6..292e026 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -99,7 +99,7 @@ void sdram_init(void) */ long int initdram(int board_type) { - return spd_sdram(0); + return spd_sdram(); } int testdram(void) diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 8ddf910..86d0db7 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -24,6 +24,8 @@ #include <asm/processor.h> #include <spd_sdram.h> +DECLARE_GLOBAL_DATA_PTR; + extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ int board_early_init_f(void) @@ -77,8 +79,8 @@ int board_early_init_f(void) out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); #if 0 /* test-only */ @@ -136,7 +138,6 @@ int board_early_init_f(void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; uint pbcr; int size_val = 0; diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 509d8e4..6742441 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -24,6 +24,8 @@ #include <asm/processor.h> #include <spd_sdram.h> +DECLARE_GLOBAL_DATA_PTR; + extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ int board_early_init_f(void) @@ -77,8 +79,8 @@ int board_early_init_f(void) out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); /*setup USB 2.0 */ @@ -132,7 +134,6 @@ int board_early_init_f(void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; uint pbcr; int size_val = 0; diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h index 91caee8..66f7584 100644 --- a/board/amcc/yucca/yucca.h +++ b/board/amcc/yucca/yucca.h @@ -349,25 +349,6 @@ void display_config_selection(config_selection_t *config_select_P); | +----------------------------------------------------------------------------*/ -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ -/*----------------------------------------------------------------------------+ -| Declare GPIO Configuration values -+----------------------------------------------------------------------------*/ -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { - unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - unsigned long auto_calc_speed(void); /*----------------------------------------------------------------------------+ | Prototypes diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index dd836ce..7d11b29 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -36,8 +36,8 @@ int board_pre_init (void) /** serial number and platform display at startup */ int checkboard (void) { - unsigned char *s = getenv ("serial#"); - unsigned char *e; + char *s = getenv ("serial#"); + char *e; /* After a loadace command, the SystemAce control register is left in a wonky state. */ /* this code did not work in board_pre_init */ @@ -135,13 +135,13 @@ int checkboard (void) long int initdram (int board_type) { - unsigned char *s = getenv ("dramsize"); + char *s = getenv ("dramsize"); if (s != NULL) { if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { s += 2; } - return simple_strtoul (s, NULL, 16); + return (long int)simple_strtoul (s, NULL, 16); } else { /* give all 64 MB */ return 64 * 1024 * 1024; @@ -293,7 +293,7 @@ int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Writing to Flash... "); write_result = - flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, + flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR, SW_BYTE_SECTOR_SIZE); if (write_result != 0) { flash_perror (write_result); diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c index 39c4157..c6ee772 100644 --- a/board/amirix/ap1000/serial.c +++ b/board/amirix/ap1000/serial.c @@ -27,9 +27,7 @@ #include <ns16550.h> -#if 0 -#include "serial.h" -#endif +DECLARE_GLOBAL_DATA_PTR; const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; @@ -40,8 +38,6 @@ static int gComPort = 0; int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; (void) NS16550_init (COM_PORTS[0], clock_divisor); @@ -71,8 +67,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c index de04c66..ca5bd1d 100644 --- a/board/armadillo/armadillo.c +++ b/board/armadillo/armadillo.c @@ -28,6 +28,8 @@ #include <common.h> #include <clps7111.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ @@ -37,8 +39,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -53,8 +53,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c index d3ccbb5..4f84a58 100644 --- a/board/assabet/assabet.c +++ b/board/assabet/assabet.c @@ -27,6 +27,8 @@ #include <common.h> #include <SA-1100.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* @@ -99,8 +101,6 @@ neponset_init(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_arch_number = MACH_TYPE_ASSABET; gd->bd->bi_boot_params = 0xc0000100; @@ -112,8 +112,6 @@ board_init(void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c index 3c00132..f886fe4 100644 --- a/board/at91rm9200dk/at45.c +++ b/board/at91rm9200dk/at45.c @@ -593,7 +593,7 @@ int AT91F_DataFlashRead( if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) return -1; size -= SizeToRead; diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c index 77caed3..002981a 100644 --- a/board/at91rm9200dk/at91rm9200dk.c +++ b/board/at91rm9200dk/at91rm9200dk.c @@ -27,6 +27,8 @@ #include <at91rm9200_net.h> #include <dm9161.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* * Miscelaneous platform dependent initialisations @@ -34,14 +36,12 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Enable Ctrlc */ console_init_f (); /* Correct IRDA resistor problem */ /* Set PA23_TXD in Output */ - (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; + ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -56,8 +56,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c index f6228ef..0513d61 100644 --- a/board/at91rm9200dk/flash.c +++ b/board/at91rm9200dk/flash.c @@ -393,8 +393,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; @@ -409,7 +408,6 @@ volatile static int write_word (flash_info_t * info, ulong dest, if ((result & data) != data) return ERR_NOT_ERASED; - /* * Disable interrupts which might cause a timeout * here. Remember that our exception vectors are diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile new file mode 100644 index 0000000..4dec44f --- /dev/null +++ b/board/bc3450/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o cmd_bc3450.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c new file mode 100644 index 0000000..0d86518 --- /dev/null +++ b/board/bc3450/bc3450.c @@ -0,0 +1,672 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * (C) Copyright 2006 + * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +#ifdef CONFIG_VIDEO_SM501 +#include <sm501.h> +#endif + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifdef CONFIG_RTC_MPC5200 +#include <rtc.h> +#endif + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ + + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined (CONFIG_TQM5200) + puts ("Board: TQM5200 (TQ-Components GmbH)\n"); +#endif + +#if defined (CONFIG_BC3450) + puts ("Dev: GERSYS BC3450\n"); +#endif + + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_POST +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ + struct mpc5xxx_gpio *gpio; + + gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + gpio->port_config &= ~(0x07000000); + gpio->port_config |= 0x03000000; + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + gpio->simple_gpioe |= 0x20000000; + + /* Configure GPIO_IRDA_1 as input */ + gpio->simple_ddr &= ~(0x20000000); + + return ((gpio->simple_ival & 0x20000000) ? 0 : 1); +} +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_RTC_MPC5200 + struct rtc_time t; + + /* set to Wed Dec 31 19:00:00 1969 */ + t.tm_sec = t.tm_min = 0; + t.tm_hour = 19; + t.tm_mday = 31; + t.tm_mon = 12; + t.tm_year = 1969; + t.tm_wday = 3; + + rtc_set(&t); +#endif /* CONFIG_RTC_MPC5200 */ + +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ + + +int last_stage_init (void) +{ + /* + * auto scan for really existing devices and re-set chip select + * configuration. + */ + u16 save, tmp; + int restore; + + /* + * Check for SRAM and SRAM size + */ + + /* save original SRAM content */ + save = *(volatile u16 *)CFG_CS2_START; + restore = 1; + + /* write test pattern to SRAM */ + *(volatile u16 *)CFG_CS2_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in SRAM detection\n"); + + if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + /* no SRAM at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + /* make sure that we access a mirrored address */ + *(volatile u16 *)CFG_CS2_START = 0x1111; + __asm__ volatile ("sync"); + if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + /* SRAM size = 512 kByte */ + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + 0x80000); + __asm__ volatile ("sync"); + puts ("SRAM: 512 kB\n"); + } + else + puts ("!! possible error in SRAM detection\n"); + } else { + puts ("SRAM: 1 MB\n"); + } + /* restore origianl SRAM content */ + if (restore) { + *(volatile u16 *)CFG_CS2_START = save; + __asm__ volatile ("sync"); + } + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else { + puts ("VGA: SMI501 (Voyager) with 8 MB\n"); + } + /* restore origianl FB content */ + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + + return 0; +} + +#ifdef CONFIG_VIDEO_SM501 + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#error CONFIG_VIDEO_SM501_16BPP not supported. +#endif /* CONFIG_VIDEO_SM501_16BPP */ + +#ifdef CONFIG_VIDEO_SM501_32BPP +static const SMI_REGS init_regs [] = +{ +#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT) + /* FP only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x01013106}, + {0x80004, 0xc428bb17}, + {0x80000, 0x03013106}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010200}, + {0x80000, 0x0f013106}, +#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP) + /* CRT only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x10090a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x10090a01}, + {0x00054, 0x0}, + {0x80200, 0x00010000}, + {0x80204, 0x0}, + {0x80208, 0x0A000A00}, + {0x8020C, 0x02fa027f}, + {0x80210, 0x004a028b}, + {0x80214, 0x020c01df}, + {0x80218, 0x000201e9}, + {0x80200, 0x00013306}, +#else /* panel + CRT */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010000}, +#endif + {0, 0} +}; +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { +#if defined (CONFIG_TQM5200) + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); +#else +#error No supported board selected +#endif /* CONFIG_TQM5200 */ + +#if defined (CONFIG_BC3450) + } else if (line_number == 2) { + strcpy (info, " Dev: GERSYS BC3450"); +#endif /* CONFIG_BC3450 */ + } + else { + info [0] = '\0'; + } +} +#endif + +/* + * Returns SM501 register base address. First thing called in the + * driver. Checks if SM501 is physically present. + */ +unsigned int board_video_init (void) +{ + u16 save, tmp; + int restore, ret; + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller found */ + restore = 0; + ret = 0; + } else { + ret = SM501_MMIO_BASE; + } + + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + return ret; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + return SM501_FB_BASE; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c new file mode 100644 index 0000000..6bbe4e6 --- /dev/null +++ b/board/bc3450/cmd_bc3450.c @@ -0,0 +1,827 @@ +/* + * (C) Copyright 2005 + * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de + * + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +/* + * BC3450 specific commands + */ +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#undef DEBUG +#ifdef DEBUG +# define dprintf(fmt,args...) printf(fmt, ##args) +#else +# define dprintf(fmt,args...) +#endif + +/* + * Definitions for DS1620 chip + */ +#define THERM_START_CONVERT 0xee +#define THERM_RESET 0xaf +#define THERM_READ_CONFIG 0xac +#define THERM_READ_TEMP 0xaa +#define THERM_READ_TL 0xa2 +#define THERM_READ_TH 0xa1 +#define THERM_WRITE_CONFIG 0x0c +#define THERM_WRITE_TL 0x02 +#define THERM_WRITE_TH 0x01 + +#define CFG_CPU 2 +#define CFG_1SHOT 1 +#define CFG_STANDALONE 0 + +struct therm { + int hi; + int lo; +}; + +/* + * SM501 Register + */ +#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */ +#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */ +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL +#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL + +/* SM501 CRT Display Control Bits */ +#define SM501_CDC_SEL (1 << 9) +#define SM501_CDC_TE (1 << 8) +#define SM501_CDC_E (1 << 2) + +/* SM501 Panel Display Control Bits */ +#define SM501_PDC_FPEN (1 << 27) +#define SM501_PDC_BIAS (1 << 26) +#define SM501_PDC_DATA (1 << 25) +#define SM501_PDC_VDDEN (1 << 24) + +/* SM501 GPIO Data LOW Bits */ +#define SM501_GPIO24 0x01000000 +#define SM501_GPIO25 0x02000000 +#define SM501_GPIO26 0x04000000 +#define SM501_GPIO27 0x08000000 +#define SM501_GPIO28 0x10000000 +#define SM501_GPIO29 0x20000000 +#define SM501_GPIO30 0x40000000 +#define SM501_GPIO31 0x80000000 + +/* SM501 GPIO Data HIGH Bits */ +#define SM501_GPIO46 0x00004000 +#define SM501_GPIO47 0x00008000 +#define SM501_GPIO48 0x00010000 +#define SM501_GPIO49 0x00020000 +#define SM501_GPIO50 0x00040000 +#define SM501_GPIO51 0x00080000 + +/* BC3450 GPIOs @ SM501 Data LOW */ +#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27) +#define DS1620_DQ SM501_GPIO29 /* I/O */ +#define DS1620_CLK SM501_GPIO30 /* High active O/P */ +#define DS1620_RES SM501_GPIO31 /* Low active O/P */ +/* BC3450 GPIOs @ SM501 Data HIGH */ +#define BUZZER SM501_GPIO47 /* Low active O/P */ +#define DS1620_TLOW SM501_GPIO48 /* High active I/P */ +#define PWR_OFF SM501_GPIO49 /* Low active O/P */ +#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */ + + +/* + * Initialise GPIO on SM501 + * + * This function may be called from several other functions. + * Yet, the initialisation sequence is executed only the first + * time the function is called. + */ +int sm501_gpio_init (void) +{ + static int init_done = 0; + + if (init_done) { +/* dprintf("sm501_gpio_init: nothing to be done.\n"); */ + return 1; + } + + /* enable SM501 GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + + /* set up default O/Ps */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~(DS1620_RES | DS1620_CLK); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ; + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~(FP_DATA_TRI); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= + (BUZZER | PWR_OFF); + + /* configure directions for SM501 GPIO pins */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= + ~(0x3F << 14); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= + ~(DIP | DS1620_DQ); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= + (DS1620_RES | DS1620_CLK); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= + ~DS1620_TLOW; + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= + (PWR_OFF | BUZZER | FP_DATA_TRI); + + init_done = 1; +/* dprintf("sm501_gpio_init: done.\n"); */ + return 0; +} + + +/* + * dip - read Config Inputs + * + * read and prints the dip switch + * and/or external config inputs (4bits) 0...0x0F + */ +int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + vu_long rc = 0; + + sm501_gpio_init (); + + /* read dip switch */ + rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); + rc = ~rc; + rc &= DIP; + rc = (int) (rc >> 24); + + /* plausibility check */ + if (rc > 0x0F) + return -1; + + printf ("0x%x\n", rc); + return 0; +} + +U_BOOT_CMD (dip, 1, 1, cmd_dip, + "dip - read dip switch and config inputs\n", + "\n" + " - prints the state of the dip switch and/or\n" + " external configuration inputs as hex value.\n" + " - \"Config 1\" is the LSB\n"); + + +/* + * buz - turns Buzzer on/off + */ +#ifdef CONFIG_BC3450_BUZZER +static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 2) { + printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); + return 1; + } + + sm501_gpio_init (); + + if (strncmp (argv[1], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~(BUZZER); + return 0; + } else if (strncmp (argv[1], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= + BUZZER; + return 0; + } + printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); + return 1; +} + +U_BOOT_CMD (buz, 2, 1, cmd_buz, + "buz - turns buzzer on/off\n", + "\n" "buz <on/off>\n" " - turns the buzzer on or off\n"); +#endif /* CONFIG_BC3450_BUZZER */ + + +/* + * fp - front panel commands + */ +static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + sm501_gpio_init (); + + if (strncmp (argv[1], "on", 2) == 0) { + /* turn on VDD first */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN; + udelay (1000); + /* then put data on */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA; + /* wait some time and enable backlight */ + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN; + return 0; + } else if (strncmp (argv[1], "off", 3) == 0) { + /* turn off the backlight first */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS; + udelay (200000); + /* wait some time, then remove data */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA; + udelay (1000); + /* and remove VDD last */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_VDDEN; + return 0; + } else if (strncmp (argv[1], "bl", 2) == 0) { + /* turn on/off backlight only */ + if (strncmp (argv[2], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= + SM501_PDC_BIAS; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= + SM501_PDC_FPEN; + return 0; + } else if (strncmp (argv[2], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_FPEN; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_BIAS; + return 0; + } + } +#ifdef CONFIG_BC3450_CRT + else if (strncmp (argv[1], "crt", 3) == 0) { + /* enables/disables the crt output (debug only) */ + if (strncmp (argv[2], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) |= + (SM501_CDC_TE | SM501_CDC_E); + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) &= + ~SM501_CDC_SEL; + return 0; + } else if (strncmp (argv[2], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) &= + ~(SM501_CDC_TE | SM501_CDC_E); + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) |= + SM501_CDC_SEL; + return 0; + } + } +#endif /* CONFIG_BC3450_CRT */ + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (fp, 3, 1, cmd_fp, + "fp - front panes access functions\n", + "\n" + "fp bl <on/off>\n" + " - turns the CCFL backlight of the display on/off\n" + "fp <on/off>\n" " - turns the whole display on/off\n" +#ifdef CONFIG_BC3450_CRT + "fp crt <on/off>\n" + " - enables/disables the crt output (debug only)\n" +#endif /* CONFIG_BC3450_CRT */ + ); + + +/* + * temp - DS1620 thermometer + */ +/* GERSYS BC3450 specific functions */ +static inline void bc_ds1620_set_clk (int clk) +{ + if (clk) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= + DS1620_CLK; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~DS1620_CLK; +} + +static inline void bc_ds1620_set_data (int dat) +{ + if (dat) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= + DS1620_DQ; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~DS1620_DQ; +} + +static inline int bc_ds1620_get_data (void) +{ + vu_long rc; + + rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); + rc &= DS1620_DQ; + if (rc != 0) + rc = 1; + return (int) rc; +} + +static inline void bc_ds1620_set_data_dir (int dir) +{ + if (dir) /* in */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ; + else /* out */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ; +} + +static inline void bc_ds1620_set_reset (int res) +{ + if (res) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES; +} + +/* hardware independent functions */ +static void ds1620_send_bits (int nr, int value) +{ + int i; + + for (i = 0; i < nr; i++) { + bc_ds1620_set_data (value & 1); + bc_ds1620_set_clk (0); + udelay (1); + bc_ds1620_set_clk (1); + udelay (1); + + value >>= 1; + } +} + +static unsigned int ds1620_recv_bits (int nr) +{ + unsigned int value = 0, mask = 1; + int i; + + bc_ds1620_set_data (0); + + for (i = 0; i < nr; i++) { + bc_ds1620_set_clk (0); + udelay (1); + + if (bc_ds1620_get_data ()) + value |= mask; + + mask <<= 1; + + bc_ds1620_set_clk (1); + udelay (1); + } + + return value; +} + +static void ds1620_out (int cmd, int bits, int value) +{ + bc_ds1620_set_clk (1); + bc_ds1620_set_data_dir (0); + + bc_ds1620_set_reset (0); + udelay (1); + bc_ds1620_set_reset (1); + + udelay (1); + + ds1620_send_bits (8, cmd); + if (bits) + ds1620_send_bits (bits, value); + + udelay (1); + + /* go stand alone */ + bc_ds1620_set_data_dir (1); + bc_ds1620_set_reset (0); + bc_ds1620_set_clk (0); + + udelay (10000); +} + +static unsigned int ds1620_in (int cmd, int bits) +{ + unsigned int value; + + bc_ds1620_set_clk (1); + bc_ds1620_set_data_dir (0); + + bc_ds1620_set_reset (0); + udelay (1); + bc_ds1620_set_reset (1); + + udelay (1); + + ds1620_send_bits (8, cmd); + + bc_ds1620_set_data_dir (1); + value = ds1620_recv_bits (bits); + + /* go stand alone */ + bc_ds1620_set_data_dir (1); + bc_ds1620_set_reset (0); + bc_ds1620_set_clk (0); + + return value; +} + +static int cvt_9_to_int (unsigned int val) +{ + if (val & 0x100) + val |= 0xfffffe00; + + return val; +} + +/* set thermostate thresholds */ +static void ds1620_write_state (struct therm *therm) +{ + ds1620_out (THERM_WRITE_TL, 9, therm->lo); + ds1620_out (THERM_WRITE_TH, 9, therm->hi); + ds1620_out (THERM_START_CONVERT, 0, 0); +} + +static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + struct therm therm; + + sm501_gpio_init (); + + /* print temperature */ + if (argc == 1) { + i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9)); + printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0); + return 0; + } + + /* set to default operation */ + if (strncmp (argv[1], "set", 3) == 0) { + if (strncmp (argv[2], "default", 3) == 0) { + therm.hi = +88; + therm.lo = -20; + therm.hi <<= 1; + therm.lo <<= 1; + ds1620_write_state (&therm); + ds1620_out (THERM_WRITE_CONFIG, 8, CFG_STANDALONE); + return 0; + } + } + + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (temp, 3, 1, cmd_temp, + "temp - print current temperature\n", + "\n" "temp\n" " - print current temperature\n"); + +#ifdef CONFIG_BC3450_CAN +/* + * Initialise CAN interface + * + * return 1 on CAN initialization failure + * return 0 if no failure + */ +int can_init (void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + + /* GPIO configuration of the CAN pins is done in BC3450.h */ + + if (!init_done) { + /* init CAN 1 */ + can1->canctl1 |= 0x80; /* CAN enable */ + udelay (100); + + i = 0; + can1->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can1->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can1->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can1->canctl1 & 0x01)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can1->canctl1 = 0x80; + can1->canctl1 |= 0x40; + can1->canbtr0 = 0x0F; + can1->canbtr1 = 0x7F; + can1->canidac &= ~(0x30); + can1->canidar1 = 0x00; + can1->canidar3 = 0x00; + can1->canidar5 = 0x00; + can1->canidar7 = 0x00; + can1->canidmr0 = 0xFF; + can1->canidmr1 = 0xFF; + can1->canidmr2 = 0xFF; + can1->canidmr3 = 0xFF; + can1->canidmr4 = 0xFF; + can1->canidmr5 = 0xFF; + can1->canidmr6 = 0xFF; + can1->canidmr7 = 0xFF; + + i = 0; + can1->canctl0 &= ~(0x01); /* leave init mode */ + can1->canctl0 &= ~(0x02); + /* wait until init and sleep mode left */ + while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + + /* init CAN 2 */ + can2->canctl1 |= 0x80; /* CAN enable */ + udelay (100); + + i = 0; + can2->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can2->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can2->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can2->canctl1 & 0x01)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can2->canctl1 = 0x80; + can2->canctl1 |= 0x40; + can2->canbtr0 = 0x0F; + can2->canbtr1 = 0x7F; + can2->canidac &= ~(0x30); + can2->canidar1 = 0x00; + can2->canidar3 = 0x00; + can2->canidar5 = 0x00; + can2->canidar7 = 0x00; + can2->canidmr0 = 0xFF; + can2->canidmr1 = 0xFF; + can2->canidmr2 = 0xFF; + can2->canidmr3 = 0xFF; + can2->canidmr4 = 0xFF; + can2->canidmr5 = 0xFF; + can2->canidmr6 = 0xFF; + can2->canidmr7 = 0xFF; + can2->canctl0 &= ~(0x01); /* leave init mode */ + can2->canctl0 &= ~(0x02); + + i = 0; + /* wait until init mode left */ + while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + init_done = 1; + } + return 0; +} + +/* + * Do CAN test + * by sending message between CAN1 and CAN2 + * + * return 1 on CAN failure + * return 0 if no failure + */ +int do_can (char *argv[]) +{ + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + + /* send a message on CAN1 */ + can1->cantbsel = 0x01; + can1->cantxfg.idr[0] = 0x55; + can1->cantxfg.idr[1] = 0x00; + can1->cantxfg.idr[1] &= ~0x8; + can1->cantxfg.idr[1] &= ~0x10; + can1->cantxfg.dsr[0] = 0xCC; + can1->cantxfg.dlr = 1; + can1->cantxfg.tbpr = 0; + can1->cantflg = 0x01; + + i = 0; + while ((can1->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN1 send timeout, " + "can not send message!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + udelay (1000); + + i = 0; + while (!(can2->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN2 receive timeout, " + "no message received!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + + if (can2->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN2 receive error, " + "data mismatch!\n", __FUNCTION__); + return 1; + } + + /* send a message on CAN2 */ + can2->cantbsel = 0x01; + can2->cantxfg.idr[0] = 0x55; + can2->cantxfg.idr[1] = 0x00; + can2->cantxfg.idr[1] &= ~0x8; + can2->cantxfg.idr[1] &= ~0x10; + can2->cantxfg.dsr[0] = 0xCC; + can2->cantxfg.dlr = 1; + can2->cantxfg.tbpr = 0; + can2->cantflg = 0x01; + + i = 0; + while ((can2->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN2 send error, " + "can not send message!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + udelay (1000); + + i = 0; + while (!(can1->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN1 receive timeout, " + "no message received!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + + if (can1->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN1 receive error 0x%02x\n", + __FUNCTION__, (can1->canrxfg.dsr[0])); + return 1; + } + + return 0; +} +#endif /* CONFIG_BC3450_CAN */ + +/* + * test - BC3450 HW test routines + */ +int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ +#ifdef CONFIG_BC3450_CAN + int rcode; + + can_init (); +#endif /* CONFIG_BC3450_CAN */ + + sm501_gpio_init (); + + if (argc != 2) { + printf ("Usage:%s\n", cmdtp->help); + return 1; + } + + if (strncmp (argv[1], "unit-off", 8) == 0) { + printf ("waiting 2 seconds...\n"); + udelay (2000000); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~PWR_OFF; + return 0; + } +#ifdef CONFIG_BC3450_CAN + else if (strncmp (argv[1], "can", 2) == 0) { + rcode = do_can (argv); + if (simple_strtoul (argv[2], NULL, 10) == 2) { + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + } + return rcode; + } +#endif /* CONFIG_BC3450_CAN */ + + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n" +#ifdef CONFIG_BC3450_CAN + "test can\n" + " - connect CAN1 (X8) with CAN2 (X9) for this test\n" +#endif /* CONFIG_BC3450_CAN */ + "test unit-off\n" + " - turns off the BC3450 unit\n" + " WARNING: Unsaved environment variables will be lost!\n"); +#endif /* CFG_CMD_BSP */ diff --git a/board/bc3450/config.mk b/board/bc3450/config.mk new file mode 100644 index 0000000..47e9955 --- /dev/null +++ b/board/bc3450/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# BC3450 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFC000000 boot low (standard configuration with room for max 64 MByte +# Flash ROM) +# 0x00100000 boot from RAM (for testing only) +# + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFC000000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h new file mode 100644 index 0000000..3f1e169 --- /dev/null +++ b/board/bc3450/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/bc3450/u-boot.lds b/board/bc3450/u-boot.lds new file mode 100644 index 0000000..93b98a8 --- /dev/null +++ b/board/bc3450/u-boot.lds @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bmw/serial.c b/board/bmw/serial.c index f36a41b..712a95b 100644 --- a/board/bmw/serial.c +++ b/board/bmw/serial.c @@ -24,6 +24,8 @@ #include <common.h> #include "ns16550.h" +DECLARE_GLOBAL_DATA_PTR; + #if CONFIG_CONS_INDEX == 1 static struct NS16550 *console = (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); @@ -38,8 +40,6 @@ extern ulong get_bus_freq (ulong); int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = gd->bus_clk / 16 / gd->baudrate; NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); @@ -75,8 +75,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; NS16550_reinit (console, clock_divisor); diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c index cc1bc16..307894f 100644 --- a/board/cerf250/cerf250.c +++ b/board/cerf250/cerf250.c @@ -27,6 +27,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ @@ -36,8 +38,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -60,8 +60,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c index 4d2013b..d34737c 100644 --- a/board/cm4008/cm4008.c +++ b/board/cm4008/cm4008.c @@ -31,6 +31,8 @@ #include <common.h> #include <asm/arch/platform.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ #define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) @@ -75,8 +77,6 @@ int board_late_init (void) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of CM4008 */ gd->bd->bi_arch_number = 624; @@ -92,8 +92,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c index 65eaa94..02d05af 100644 --- a/board/cm41xx/cm41xx.c +++ b/board/cm41xx/cm41xx.c @@ -31,6 +31,8 @@ #include <common.h> #include <asm/arch/platform.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ #define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) @@ -75,8 +77,6 @@ int board_late_init (void) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of CM41xx */ gd->bd->bi_arch_number = 672; @@ -92,8 +92,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c index 14168e6..9ae3c42 100644 --- a/board/cmc_pu2/cmc_pu2.c +++ b/board/cmc_pu2/cmc_pu2.c @@ -33,6 +33,8 @@ #include <at91rm9200_net.h> #include <dm9161.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* * Miscelaneous platform dependent initialisations @@ -45,7 +47,6 @@ int hw_detect (void); int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; AT91PS_PIO piob = AT91C_BASE_PIOB; AT91PS_PIO pioc = AT91C_BASE_PIOC; @@ -109,8 +110,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c index 94aa30d..354566c 100644 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ b/board/cmc_pu2/load_sernum_ethaddr.c @@ -69,8 +69,8 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen, void load_sernum_ethaddr (void) { struct manufacturer_data data; - unsigned char serial [9]; - unsigned char ethaddr[18]; + char ethaddr[18]; + char serial [9]; unsigned short chksum; unsigned char *p; unsigned short i, is, id; diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 6f5874a..82452e2 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info) printf ("\n"); Done: + return; } @@ -256,8 +257,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/cogent/serial.c b/board/cogent/serial.c index 4c20017..2b595a8 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -6,6 +6,8 @@ #include <common.h> #include <board/cogent/serial.h> +DECLARE_GLOBAL_DATA_PTR; + #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ @@ -25,76 +27,65 @@ int serial_init (void) { -/* DECLARE_GLOBAL_DATA_PTR; */ - - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ - serial_setbrg (); - cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ + cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */ + serial_setbrg (); + cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ + cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */ + cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - return (0); + return (0); } -void -serial_setbrg (void) +void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - unsigned int divisor; - unsigned char lcr; - - if ((divisor = br_to_div(gd->baudrate)) == 0) - divisor = DEFDIV; - - lcr = cma_mb_reg_read(&mbsp->ser_lcr); - cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/ - cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write(&mbsp->ser_lcr, lcr); /* unset DLAB */ + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; + unsigned int divisor; + unsigned char lcr; + + if ((divisor = br_to_div (gd->baudrate)) == 0) + divisor = DEFDIV; + + lcr = cma_mb_reg_read (&mbsp->ser_lcr); + cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80); /* Access baud rate(set DLAB) */ + cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff); + cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff); + cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */ } -void -serial_putc(const char c) +void serial_putc (const char c) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - if (c == '\n') - serial_putc('\r'); + if (c == '\n') + serial_putc ('\r'); - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) - ; + while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0); - cma_mb_reg_write(&mbsp->ser_thr, c); + cma_mb_reg_write (&mbsp->ser_thr, c); } -void -serial_puts(const char *s) +void serial_puts (const char *s) { - while (*s != '\0') - serial_putc(*s++); + while (*s != '\0') + serial_putc (*s++); } -int -serial_getc(void) +int serial_getc (void) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) - ; + while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0); - return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); + return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f); } -int -serial_tstc(void) +int serial_tstc (void) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0); + return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0); } #endif /* CONS_NONE */ @@ -118,71 +109,63 @@ serial_tstc(void) #error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial #endif -void -kgdb_serial_init(void) +void kgdb_serial_init (void) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - unsigned int divisor; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; + unsigned int divisor; - if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0) - divisor = DEFDIV; + if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0) + divisor = DEFDIV; - cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ - cma_mb_reg_write(&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB)*/ - cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ + cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */ + cma_mb_reg_write (&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB) */ + cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff); + cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff); + cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ + cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */ + cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - printf("[on cma10x serial port B] "); + printf ("[on cma10x serial port B] "); } -void -putDebugChar(int c) +void putDebugChar (int c) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) - ; + while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0); - cma_mb_reg_write(&mbsp->ser_thr, c & 0xff); + cma_mb_reg_write (&mbsp->ser_thr, c & 0xff); } -void -putDebugStr(const char *str) +void putDebugStr (const char *str) { - while (*str != '\0') { - if (*str == '\n') - putDebugChar('\r'); - putDebugChar(*str++); - } + while (*str != '\0') { + if (*str == '\n') + putDebugChar ('\r'); + putDebugChar (*str++); + } } -int -getDebugChar(void) +int getDebugChar (void) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) - ; + while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0); - return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); + return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f); } -void -kgdb_interruptible(int yes) +void kgdb_interruptible (int yes) { - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - - if (yes == 1) { - printf("kgdb: turning serial ints on\n"); - cma_mb_reg_write(&mbsp->ser_ier, 0xf); - } - else { - printf("kgdb: turning serial ints off\n"); - cma_mb_reg_write(&mbsp->ser_ier, 0x0); - } + cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; + + if (yes == 1) { + printf ("kgdb: turning serial ints on\n"); + cma_mb_reg_write (&mbsp->ser_ier, 0xf); + } else { + printf ("kgdb: turning serial ints off\n"); + cma_mb_reg_write (&mbsp->ser_ier, 0x0); + } } #endif /* KGDB && KGDB_NONE */ diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c index 6f65f32..6d8d555 100644 --- a/board/cradle/cradle.c +++ b/board/cradle/cradle.c @@ -28,6 +28,8 @@ #include <asm/arch/pxa-regs.h> #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ @@ -181,8 +183,6 @@ int board_init (void) /**********************************************************/ { - DECLARE_GLOBAL_DATA_PTR; - led_code (0xf, YELLOW); /* arch number of HHP Cradle */ @@ -209,8 +209,6 @@ int dram_init (void) /**********************************************************/ { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c index c99a715..80caf8b 100644 --- a/board/csb226/csb226.c +++ b/board/csb226/csb226.c @@ -26,6 +26,8 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_SHOW_BOOT_PROGRESS # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) #else @@ -65,8 +67,6 @@ int misc_init_r(void) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -88,8 +88,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c index 6100a53..aeb1a13 100644 --- a/board/csb637/csb637.c +++ b/board/csb637/csb637.c @@ -26,6 +26,8 @@ #include <at91rm9200_net.h> #include <bcm5221.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* * Miscelaneous platform dependent initialisations @@ -33,8 +35,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Enable Ctrlc */ console_init_f (); @@ -51,8 +51,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index 5844a5c..3edd27a 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. * - * (C) Copyright 2001, 2002 + * (C) Copyright 2001-2006 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * See file CREDITS for list of people who contributed to this @@ -29,12 +29,12 @@ #include <asm/processor.h> #include <pci.h> +DECLARE_GLOBAL_DATA_PTR; + #define BOARD_REV_REG 0xFE80002B int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char revision = *(volatile char *)(BOARD_REV_REG); char buf[32]; diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c index 29676b8..64fe948 100644 --- a/board/dave/B2/B2.c +++ b/board/dave/B2/B2.c @@ -27,13 +27,14 @@ #include <common.h> #include <asm/hardware.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Miscelaneous platform dependent initialization */ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; u32 temp; /* Configuration Port Control Register*/ @@ -119,8 +120,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile index 39d2fec..581a580 100644 --- a/board/dave/PPChameleonEVB/Makefile +++ b/board/dave/PPChameleonEVB/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o nand.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 5f2c705..e8302d9 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -29,6 +29,8 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* Prototypes */ @@ -81,8 +83,6 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart = 0 - flash_info[0].size; gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN; @@ -238,33 +238,6 @@ int testdram (void) /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - -void -nand_init(void) -{ - ulong totlen = 0; - -/* - The HI model is equipped with a large block NAND chip not supported yet - by U-Boot - (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -*/ - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); -#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ - - debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); - totlen += nand_probe (CFG_NAND1_BASE); - - printf ("%3lu MB\n", totlen >>20); -} -#endif - #ifdef CONFIG_CFB_CONSOLE # ifdef CONFIG_CONSOLE_EXTRA_INFO # include <video_fb.h> diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 5856aec..9083aac 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000, 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,7 +22,7 @@ # # Reserve 256 kB for Monitor -TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0xFFFC0000 # Reserve 320 kB for Monitor -#TEXT_BASE = 0xFFFB0000 +TEXT_BASE = 0xFFFB0000 diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c new file mode 100644 index 0000000..40a827c --- /dev/null +++ b/board/dave/PPChameleonEVB/nand.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + switch(cmd) { + case NAND_CTL_SETCLE: + MACRO_NAND_CTL_SETCLE((unsigned long)base); + break; + case NAND_CTL_CLRCLE: + MACRO_NAND_CTL_CLRCLE((unsigned long)base); + break; + case NAND_CTL_SETALE: + MACRO_NAND_CTL_SETALE((unsigned long)base); + break; + case NAND_CTL_CLRALE: + MACRO_NAND_CTL_CLRALE((unsigned long)base); + break; + case NAND_CTL_SETNCE: + MACRO_NAND_ENABLE_CE((unsigned long)base); + break; + case NAND_CTL_CLRNCE: + MACRO_NAND_DISABLE_CE((unsigned long)base); + break; + } +} + + +/* + * read device ready pin + * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong rb_gpio_pin; + + /* use the base addr to find out which chip are we dealing with */ + switch((ulong) this->IO_ADDR_W) { + case CFG_NAND0_BASE: + rb_gpio_pin = CFG_NAND0_RDY; + break; + case CFG_NAND1_BASE: + rb_gpio_pin = CFG_NAND1_RDY; + break; + default: /* this should never happen */ + return 0; + break; + } + + if (in32(GPIO0_IR) & rb_gpio_pin) + return 1; + return 0; +} + + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + + nand->hwcontrol = ppchameleonevb_hwcontrol; + nand->dev_ready = ppchameleonevb_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 7afd584..14a7846 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -185,6 +185,8 @@ tlbloop: bne t0, t2, tlbloop nop +#endif /* CONFIG_DBAU1550 */ + /* First setup pll:s to make serial work ok */ /* We have a 12 MHz crystal */ li t0, SYS_CPUPLL @@ -205,6 +207,7 @@ tlbloop: sw t1, 0(t0) /* aux pll */ sync +#ifdef CONFIG_DBAU1550 /* Static memory controller */ /* RCE0 - can not change while fetching, do so from icache */ move t2, ra /* Store return address */ @@ -237,7 +240,7 @@ noCacheJump: sw t1, 0(t0) #else /* CONFIG_DBAU1550 */ li t0, MEM_STTIME0 - li t1, 0x00014C0F + li t1, 0x040181D7 sw t1, 0(t0) /* RCE0 AMD 29LV640M MirrorBit Flash */ diff --git a/board/delta/Makefile b/board/delta/Makefile new file mode 100644 index 0000000..e744eec --- /dev/null +++ b/board/delta/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := delta.o nand.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/delta/config.mk b/board/delta/config.mk new file mode 100644 index 0000000..3fe406c --- /dev/null +++ b/board/delta/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x83008000 diff --git a/board/delta/delta.c b/board/delta/delta.c new file mode 100644 index 0000000..b127ac8 --- /dev/null +++ b/board/delta/delta.c @@ -0,0 +1,364 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <da9030.h> +#include <malloc.h> +#include <command.h> +#include <asm/arch/pxa-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +static void init_DA9030(void); +static void keys_init(void); +static void get_pressed_keys(uchar *s); +static uchar *key_match(uchar *kbd_data); + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board mk@tbd: fix this! */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ +#ifdef DELTA_CHECK_KEYBD + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + char *str; + int i; +#endif /* DELTA_CHECK_KEYBD */ + + setenv("stdout", "serial"); + setenv("stderr", "serial"); + +#ifdef DELTA_CHECK_KEYBD + keys_init(); + + memset(kbd_data, '\0', KEYBD_DATALEN); + + /* check for pressed keys and setup keybd_env */ + get_pressed_keys(kbd_data); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ + +# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +# endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } +#endif /* DELTA_CHECK_KEYBD */ + + init_DA9030(); + return 0; +} + + +/* + * Magic Key Handling, mainly copied from board/lwmon/lwmon.c + */ +#ifdef DELTA_CHECK_KEYBD + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +/* + * Get pressed keys + * s is a buffer of size KEYBD_DATALEN-1 + */ +static void get_pressed_keys(uchar *s) +{ + unsigned long val; + val = GPLR3; + + if(val & (1<<31)) + *s++ = KEYBD_KP_DKIN0; + if(val & (1<<18)) + *s++ = KEYBD_KP_DKIN1; + if(val & (1<<29)) + *s++ = KEYBD_KP_DKIN2; + if(val & (1<<22)) + *s++ = KEYBD_KP_DKIN5; +} + +static void keys_init() +{ + CKENB |= CKENB_7_GPIO; + udelay(100); + + /* Configure GPIOs */ + GPIO127 = 0xa840; /* KP_DKIN0 */ + GPIO114 = 0xa840; /* KP_DKIN1 */ + GPIO125 = 0xa840; /* KP_DKIN2 */ + GPIO118 = 0xa840; /* KP_DKIN5 */ + + /* Configure GPIOs as inputs */ + GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22); + GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22); + + udelay(100); +} + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + /* uchar compare[KEYBD_DATALEN-1]; */ + uchar compare[KEYBD_DATALEN]; + char *nxt; + int i; + + /* Don't include modifier byte */ + /* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */ + memcpy (compare, kbd_data, KEYBD_DATALEN); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + + +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); +#if 0 + printf ("### Check magic \"%s\"\n", magic); +#endif + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); +#if 0 + printf ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<<NULL>>"); +#endif + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } +#if 0 + printf ("### Delete PREBOOT\n"); +#endif + *kbd_data = '\0'; + return (NULL); +} + +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + int i; + + /* Read keys */ + get_pressed_keys(kbd_data); + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +#endif /* DELTA_CHECK_KEYBD */ + + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} + +void i2c_init_board() +{ + CKENB |= (CKENB_4_I2C); + + /* setup I2C GPIO's */ + GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ + GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ +} + +/* initialize the DA9030 Power Controller */ +static void init_DA9030() +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + + CKENB |= CKENB_7_GPIO; + udelay(100); + + /* Rising Edge on EXTON to reset DA9030 */ + GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */ + GPDR0 |= (1<<17); /* GPIO17 is output */ + GSDR0 = (1<<17); + GPCR0 = (1<<17); /* drive GPIO17 low */ + GPSR0 = (1<<17); /* drive GPIO17 high */ + +#if CFG_DA9030_EXTON_DELAY + udelay((unsigned long) CFG_DA9030_EXTON_DELAY); /* wait for DA9030 */ +#endif + GPCR0 = (1<<17); /* drive GPIO17 low */ + + /* reset the watchdog and go active (0xec) */ + val = (SYS_CONTROL_A_HWRES_ENABLE | + (0x6<<4) | + SYS_CONTROL_A_WDOG_ACTION | + SYS_CONTROL_A_WATCHDOG); + if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) { + printf("Error accessing DA9030 via i2c.\n"); + return; + } + + i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ + i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */ + i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */ + i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */ + i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */ + i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */ + i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */ + i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */ + i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */ + i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */ + i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */ + i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */ + i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */ + i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */ + i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */ + + val = i2c_reg_read(addr, STATUS); + if(val & STATUS_CHDET) + printf("Charger detected, turning on LED.\n"); + else { + printf("No charger detetected.\n"); + /* undervoltage? print error and power down */ + } +} + + +#if 0 +/* reset the DA9030 watchdog */ +void hw_watchdog_reset(void) +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + val = i2c_reg_read(addr, SYS_CONTROL_A); + val |= SYS_CONTROL_A_WATCHDOG; + i2c_reg_write(addr, SYS_CONTROL_A, val); +} +#endif diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S new file mode 100644 index 0000000..f059db5 --- /dev/null +++ b/board/delta/lowlevel_init.S @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first */ + mov r10, lr + + /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ + ldr r0, =GPIO97 + ldr r1, =0x801 + str r1, [r0] + + ldr r0, =GPIO98 + ldr r1, =0x801 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + +mem_init: + /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ + ldr r0, =ACCR + ldr r1, [r0] + orr r1, r1, #0x3000 + str r1, [r0] + ldr r1, [r0] + + /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ + ldr r0, =MDCNFG + ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) + /* ldr r1, =0x80000403 */ + str r1, [r0] + ldr r1, [r0] /* delay until written */ + + /* 3. wait nop power up waiting period (200ms) + * optimization: Steps 4+6 can be done during this + */ + wait #300 + + /* 4. Perform an initial Rcomp-calibration cycle */ + ldr r0, =RCOMP + ldr r1, =0x80000000 + str r1, [r0] + ldr r1, [r0] /* delay until written */ + /* missing: program for automatic rcomp evaluation cycles */ + + /* 5. DDR DRAM strobe delay calibration */ + ldr r0, =DDR_HCAL + ldr r1, =0x88000007 + str r1, [r0] + wait #5 + ldr r1, [r0] /* delay until written */ + + /* Set MDMRS */ + ldr r0, =MDMRS + ldr r1, =0x60000033 + str r1, [r0] + wait #300 + + /* Configure MDREFR */ + ldr r0, =MDREFR + ldr r1, =0x00000006 + str r1, [r0] + ldr r1, [r0] + + /* Enable the dynamic memory controller */ + ldr r0, =MDCNFG + ldr r1, [r0] + orr r1, r1, #MDCNFG_DMCEN + str r1, [r0] + +#ifndef CFG_SKIP_DRAM_SCRUB + /* scrub/init SDRAM if enabled/present */ + ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 8 words/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b +#endif /* CFG_SKIP_DRAM_SCRUB */ + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +endlowlevel_init: + mov pc, lr diff --git a/board/delta/nand.c b/board/delta/nand.c new file mode 100644 index 0000000..fe648fc --- /dev/null +++ b/board/delta/nand.c @@ -0,0 +1,584 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if !defined(CFG_NAND_LEGACY) + +#include <nand.h> +#include <asm/arch/pxa-regs.h> + +#ifdef CFG_DFC_DEBUG1 +# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG1(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG2 +# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG2(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG3 +# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG3(fmt, args...) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +/* These really don't belong here, as they are specific to the NAND Model */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr delta_bbt_descr = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_oobinfo delta_oob = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 6, + .eccpos = {2, 3, 4, 5, 6, 7}, + .oobfree = { {8, 2}, {12, 4} } +}; + + +/* + * not required for Monahans DFC + */ +static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + +#if 0 +/* read device ready pin */ +static int dfc_device_ready(struct mtd_info *mtdinfo) +{ + if(NDSR & NDSR_RDY) + return 1; + else + return 0; + return 0; +} +#endif + +/* + * Write buf to the DFC Controller Data Buffer + */ +static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + int i; + + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + NDDB = *long_buf; + } + } + if(rest) { + printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); + } + return; +} + + +/* + * These functions are quite problematic for the DFC. Luckily they are + * not used in the current nand code, except for nand_command, which + * we've defined our own anyway. The problem is, that we always need + * to write 4 bytes to the DFC Data Buffer, but in these functions we + * don't know if to buffer the bytes/half words until we've gathered 4 + * bytes or if to send them straight away. + * + * Solution: Don't use these with Mona's DFC and complain loudly. + */ +static void dfc_write_word(struct mtd_info *mtd, u16 word) +{ + printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); +} +static void dfc_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); +} + +/* The original: + * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) + * + * Shouldn't this be "u_char * const buf" ? + */ +static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) +{ + int i=0, j; + + /* we have to be carefull not to overflow the buffer if len is + * not a multiple of 4 */ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + + DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); + /* if there are any, first copy multiple of 4 bytes */ + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + *long_buf = NDDB; + } + } + + /* ...then the rest */ + if(rest) { + unsigned long rest_data = NDDB; + for(j=0;j<rest; j++) + buf[i+j] = (u_char) ((rest_data>>j) & 0xff); + } + + return; +} + +/* + * read a word. Not implemented as not used in NAND code. + */ +static u16 dfc_read_word(struct mtd_info *mtd) +{ + printf("dfc_write_byte: UNIMPLEMENTED.\n"); + return 0; +} + +/* global var, too bad: mk@tbd: move to ->priv pointer */ +static unsigned long read_buf = 0; +static int bytes_read = -1; + +/* + * read a byte from NDDB Because we can only read 4 bytes from NDDB at + * a time, we buffer the remaining bytes. The buffer is reset when a + * new command is sent to the chip. + * + * WARNING: + * This function is currently only used to read status and id + * bytes. For these commands always 8 bytes need to be read from + * NDDB. So we read and discard these bytes right now. In case this + * function is used for anything else in the future, we must check + * what was the last command issued and read the appropriate amount of + * bytes respectively. + */ +static u_char dfc_read_byte(struct mtd_info *mtd) +{ + unsigned char byte; + unsigned long dummy; + + if(bytes_read < 0) { + read_buf = NDDB; + dummy = NDDB; + bytes_read = 0; + } + byte = (unsigned char) (read_buf>>(8 * bytes_read++)); + if(bytes_read >= 4) + bytes_read = -1; + + DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); + return byte; +} + +/* calculate delta between OSCR values start and now */ +static unsigned long get_delta(unsigned long start) +{ + unsigned long cur = OSCR; + + if(cur < start) /* OSCR overflowed */ + return (cur + (start^0xffffffff)); + else + return (cur - start); +} + +/* delay function, this doesn't belong here */ +static void wait_us(unsigned long us) +{ + unsigned long start = OSCR; + us *= OSCR_CLK_FREQ; + + while (get_delta(start) < us) { + /* do nothing */ + } +} + +static void dfc_clear_nddb(void) +{ + NDCR &= ~NDCR_ND_RUN; + wait_us(CFG_NAND_OTHER_TO); +} + +/* wait_event with timeout */ +static unsigned long dfc_wait_event(unsigned long event) +{ + unsigned long ndsr, timeout, start = OSCR; + + if(!event) + return 0xff000000; + else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) + timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + else + timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + + while(1) { + ndsr = NDSR; + if(ndsr & event) { + NDSR |= event; + break; + } + if(get_delta(start) > timeout) { + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); + return 0xff000000; + } + + } + return ndsr; +} + +/* we don't always wan't to do this */ +static void dfc_new_cmd(void) +{ + int retry = 0; + unsigned long status; + + while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + /* Clear NDSR */ + NDSR = 0xFFF; + + /* set NDCR[NDRUN] */ + if(!(NDCR & NDCR_ND_RUN)) + NDCR |= NDCR_ND_RUN; + + status = dfc_wait_event(NDSR_WRCMDREQ); + + if(status & NDSR_WRCMDREQ) + return; + + DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); + dfc_clear_nddb(); + } + DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); +} + +/* this function is called after Programm and Erase Operations to + * check for success or failure */ +static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long ndsr=0, event=0; + + if(state == FL_WRITING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } else if(state == FL_ERASING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } + + ndsr = dfc_wait_event(event); + + if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) + return(0x1); /* Status Read error */ + return 0; +} + +/* cmdfunc send commands to the DFC */ +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + /* register struct nand_chip *this = mtd->priv; */ + unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; + + /* clear the ugly byte read buffer */ + bytes_read = -1; + read_buf = 0; + + switch (command) { + case NAND_CMD_READ0: + DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (NAND_CMD_READ0 | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_READ1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); + goto end; + case NAND_CMD_READOOB: + DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); + goto end; + case NAND_CMD_READID: + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); + ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_PAGEPROG: + /* sent as a multicommand in NAND_CMD_SEQIN */ + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); + goto end; + case NAND_CMD_ERASE1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); + ndcb1 = (page_addr & 0x00ffffff); + goto write_cmd; + case NAND_CMD_ERASE2: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); + goto end; + case NAND_CMD_SEQIN: + /* send PAGE_PROG command(0x1080) */ + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_WRDREQ; + goto write_cmd; + case NAND_CMD_STATUS: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); + dfc_new_cmd(); + ndcb0 = NAND_CMD_STATUS | (4<<21); + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_RESET: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); + ndcb0 = NAND_CMD_RESET | (5<<21); + event = NDSR_CS0_CMDD; + goto write_cmd; + default: + printk("dfc_cmdfunc: error, unsupported command.\n"); + goto end; + } + + write_cmd: + NDCB0 = ndcb0; + NDCB0 = ndcb1; + NDCB0 = ndcb2; + + /* wait_event: */ + dfc_wait_event(event); + end: + return; +} + +static void dfc_gpio_init(void) +{ + DFC_DEBUG2("Setting up DFC GPIO's.\n"); + + /* no idea what is done here, see zylonite.c */ + GPIO4 = 0x1; + + DF_ALE_WE1 = 0x00000001; + DF_ALE_WE2 = 0x00000001; + DF_nCS0 = 0x00000001; + DF_nCS1 = 0x00000001; + DF_nWE = 0x00000001; + DF_nRE = 0x00000001; + DF_IO0 = 0x00000001; + DF_IO8 = 0x00000001; + DF_IO1 = 0x00000001; + DF_IO9 = 0x00000001; + DF_IO2 = 0x00000001; + DF_IO10 = 0x00000001; + DF_IO3 = 0x00000001; + DF_IO11 = 0x00000001; + DF_IO4 = 0x00000001; + DF_IO12 = 0x00000001; + DF_IO5 = 0x00000001; + DF_IO13 = 0x00000001; + DF_IO6 = 0x00000001; + DF_IO14 = 0x00000001; + DF_IO7 = 0x00000001; + DF_IO15 = 0x00000001; + + DF_nWE = 0x1901; + DF_nRE = 0x1901; + DF_CLE_NOE = 0x1900; + DF_ALE_WE1 = 0x1901; + DF_INT_RnB = 0x1900; +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; + + /* set up GPIO Control Registers */ + dfc_gpio_init(); + + /* turn on the NAND Controller Clock (104 MHz @ D0) */ + CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + +#undef CFG_TIMING_TIGHT +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), + DFC_MAX_tAR); +#else /* this is the tight timing */ + + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), + DFC_MAX_tAR); +#endif /* CFG_TIMING_TIGHT */ + + + DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); + + /* tRP value is split in the register */ + if(tRP & (1 << 4)) { + tRP_high = 1; + tRP &= ~(1 << 4); + } else { + tRP_high = 0; + } + + NDTR0CS0 = (tCH << 19) | + (tCS << 16) | + (tWH << 11) | + (tWP << 8) | + (tRP_high << 6) | + (tRH << 3) | + (tRP << 0); + + NDTR1CS0 = (tR << 16) | + (tWHR << 4) | + (tAR << 0); + + /* If it doesn't work (unlikely) think about: + * - ecc enable + * - chip select don't care + * - read id byte count + * + * Intentionally enabled by not setting bits: + * - dma (DMA_EN) + * - page size = 512 + * - cs don't care, see if we can enable later! + * - row address start position (after second cycle) + * - pages per block = 32 + * - ND_RDY : clears command buffer + */ + /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ + + NDCR = (NDCR_SPARE_EN | /* use the spare area */ + NDCR_DWIDTH_C | /* 16bit DFC data bus width */ + NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ + (2 << 16) | /* read id count = 7 ???? mk@tbd */ + NDCR_ND_ARB_EN | /* enable bus arbiter */ + NDCR_RDYM | /* flash device ready ir masked */ + NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ + NDCR_CS1_PAGEDM | + NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ + NDCR_CS1_CMDDM | + NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ + NDCR_CS1_BBDM | + NDCR_DBERRM | /* double bit error ir masked */ + NDCR_SBERRM | /* single bit error ir masked */ + NDCR_WRDREQM | /* write data request ir masked */ + NDCR_RDDREQM | /* read data request ir masked */ + NDCR_WRCMDREQM); /* write command request ir masked */ + + + /* wait 10 us due to cmd buffer clear reset */ + /* wait(10); */ + + + nand->hwcontrol = dfc_hwcontrol; +/* nand->dev_ready = dfc_device_ready; */ + nand->eccmode = NAND_ECC_SOFT; + nand->options = NAND_BUSWIDTH_16; + nand->waitfunc = dfc_wait; + nand->read_byte = dfc_read_byte; + nand->write_byte = dfc_write_byte; + nand->read_word = dfc_read_word; + nand->write_word = dfc_write_word; + nand->read_buf = dfc_read_buf; + nand->write_buf = dfc_write_buf; + + nand->cmdfunc = dfc_cmdfunc; + nand->autooob = &delta_oob; + nand->badblock_pattern = &delta_bbt_descr; +} + +#else + #error "U-Boot legacy NAND support not available for Monahans DFC." +#endif +#endif diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/delta/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c index 24c3e00..ab8e7be 100644 --- a/board/dnp1110/dnp1110.c +++ b/board/dnp1110/dnp1110.c @@ -24,8 +24,8 @@ #include <common.h> #include <SA-1100.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -33,25 +33,21 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ /* arch number of DNP1110-Board */ gd->bd->bi_arch_number = MACH_TYPE_DNP1110; - /* flash vpp on */ - PPDR |= 0x80; /* assumes LCD controller is off */ - PPSR |= 0x80; + /* flash vpp on */ + PPDR |= 0x80; /* assumes LCD controller is off */ + PPSR |= 0x80; return 0; } int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c index fc48ed5..555475e 100644 --- a/board/eltec/bab7xx/bab7xx.c +++ b/board/eltec/bab7xx/bab7xx.c @@ -31,6 +31,8 @@ #include <ns87308.h> #include <video_fb.h> +DECLARE_GLOBAL_DATA_PTR; + /*---------------------------------------------------------------------------*/ /* * Get Bus clock frequency @@ -169,8 +171,6 @@ long int initdram (int board_type) void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c index a9dbeb2..108adb1 100644 --- a/board/eltec/elppc/elppc.c +++ b/board/eltec/elppc/elppc.c @@ -26,6 +26,8 @@ #include <mpc106.h> #include <video_fb.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ int checkboard (void) @@ -137,8 +139,6 @@ void watchdog_reset (void) void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c index 11eab23..6968a5d 100644 --- a/board/ep7312/ep7312.c +++ b/board/ep7312/ep7312.c @@ -25,8 +25,7 @@ #include <common.h> #include <clps7111.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -34,8 +33,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -50,8 +47,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile new file mode 100644 index 0000000..9123a80 --- /dev/null +++ b/board/ep88x/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2004 Arabella Software Ltd. +# Yuli Barcohen <yuli@arabellasw.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ep88x/config.mk b/board/ep88x/config.mk new file mode 100644 index 0000000..72b326c --- /dev/null +++ b/board/ep88x/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2005 Arabella Software Ltd. +# Yuli Barcohen <yuli@arabellasw.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Embedded Planet EP88x boards +# +TEXT_BASE = 0xFC000000 diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c new file mode 100644 index 0000000..5f57f36 --- /dev/null +++ b/board/ep88x/ep88x.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2005 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Embedded Planet EP88x boards. + * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> + +/* + * SDRAM uses two Micron chips. + * Minimal CPU frequency is 40MHz. + */ +static uint sdram_table[] = { + /* Single read (offset 0x00 in UPM RAM) */ + 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404, + 0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + + /* Burst read (offset 0x08 in UPM RAM) */ + 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404, + 0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00, + 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + + /* Single write (offset 0x18 in UPM RAM) */ + 0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404, + 0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + + /* Burst write (offset 0x20 in UPM RAM) */ + 0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400, + 0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05, + 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, + + /* Refresh (offset 0x30 in UPM RAM) */ + 0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04, + 0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34, + 0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4, + + /* Exception (offset 0x3C in UPM RAM) */ + 0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05 +}; + +int board_early_init_f (void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + bcsr[0] |= 0x0C; /* Turn the LEDs off */ + bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for + flash detection by CFI driver + */ + +#if defined(CONFIG_8xx_CONS_SMC1) + bcsr[6] |= 0x10; /* Enables RS-232 transceiver */ +#endif +#if defined(CONFIG_8xx_CONS_SCC2) + bcsr[7] |= 0x10; /* Enables RS-232 transceiver */ +#endif +#ifdef CONFIG_ETHER_ON_FEC1 + bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */ +#endif +#ifdef CONFIG_ETHER_ON_FEC2 + bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */ +#endif + + return 0; +} + +long int initdram (int board_type) +{ + long int msize; + volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* Configure SDRAM refresh */ + memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ + + memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */ + udelay(100); + + /* Run MRS pattern from location 0x36 */ + memctl->memc_mar = 0x88; + memctl->memc_mcr = 0x80002236; + udelay(100); + + memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ + memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + + msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + memctl->memc_or1 |= ~(msize - 1); + + return msize; +} + +int checkboard( void ) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + puts("Board: "); + switch (bcsr[15]) { + case 0xE7: + puts("EP88xC 1.0"); + break; + default: + printf("unknown ID=%02X", bcsr[15]); + } + printf(" CPLD revision %d\n", bcsr[14]); + + return 0; +} diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds new file mode 100644 index 0000000..1d2a7d7 --- /dev/null +++ b/board/ep88x/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen <yuli@arabellasw.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 4b2b07a..078df00 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -26,7 +26,7 @@ #include <command.h> #include <malloc.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #if 0 #define FPGA_DEBUG @@ -166,8 +166,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile unsigned short *fpga_mode = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); volatile unsigned short *fpga_ctrl2 = @@ -301,8 +299,6 @@ int misc_init_r (void) int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 3aac3c6..dfead33 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -26,6 +26,8 @@ #include <asm/processor.h> #include <command.h> +DECLARE_GLOBAL_DATA_PTR; + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -53,8 +55,6 @@ const unsigned char fpgadata_xl30[] = { int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - int index, len, i; int status; @@ -151,8 +151,6 @@ int board_early_init_f (void) int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - int index; int len; char str[64]; diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 03ae7fd..84fc3a0 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 2ced6cb..055a397 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <command.h> +DECLARE_GLOBAL_DATA_PTR; /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -50,8 +51,6 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long cntrl0Reg; int index, len, i; int status; diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 649619d..cb04710 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -26,10 +26,10 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); - /* fpga configuration data - not compressed, generated by bin2c */ const unsigned char fpgadata[] = { @@ -87,8 +87,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; @@ -114,7 +112,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int flashcnt; int delay; volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); @@ -238,7 +236,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index d48e972..5cd3423 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -23,10 +23,15 @@ */ #include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + #include <command.h> #include <image.h> #include <asm/byteorder.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> #include <fat.h> #include "auto_update.h" @@ -69,17 +74,17 @@ extern int flash_write (char *, ulong, ulong); /* change char* to void* to shutup the compiler */ extern block_dev_desc_t *get_dev (char*, int); -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) /* references to names in cmd_nand.c */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; @@ -183,7 +188,7 @@ int au_do_update(int i, long sz) int off, rc; uint nbytes; int k; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) int total; #endif @@ -257,11 +262,11 @@ int au_do_update(int i, long sz) debug ("flash_sect_erase(%lx, %lx);\n", start, end); flash_sect_erase(start, end); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) printf("Updating NAND FLASH with image %s\n", au_image[i].name); - debug ("nand_erase(%lx, %lx);\n", start, end); - rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); - debug ("nand_erase returned %x\n", rc); + debug ("nand_legacy_erase(%lx, %lx);\n", start, end); + rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -283,13 +288,13 @@ int au_do_update(int i, long sz) */ if (au_image[i].type != AU_NAND) { debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((uchar *)addr, start, nbytes); + rc = flash_write((char *)addr, start, nbytes); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); #endif } if (rc != 0) { @@ -303,8 +308,8 @@ int au_do_update(int i, long sz) if (au_image[i].type != AU_NAND) { rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, start, nbytes, (size_t *)&total, (uchar *)addr); rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); #endif diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c new file mode 100644 index 0000000..bf796ff --- /dev/null +++ b/board/esd/common/cmd_loadpci.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); +extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); + +#define ADDRMASK 0xfffff000 + +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr = 0; + int count = 0; + int count2 = 0; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + while(1) { + /* + * Mark sync address + */ + ptr = 0; + memset(ptr, 0, 0x20); + + *ptr = 0xffffffff; + puts("\nWaiting for action from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + printf("\nGot bootcode %08x: ", *ptr); + sprintf(addr, "%08x", *ptr & ADDRMASK); + + switch (*ptr & ~ADDRMASK) { + case 0: + /* + * Boot image via bootm + */ + printf("booting image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + do_bootm (cmdtp, 0, 0, NULL); + break; + + case 1: + /* + * Boot image via autoscr + */ + printf("executing script at addr 0x%s ...\n", addr); + + local_args[0] = addr; + local_args[1] = NULL; + do_autoscript(cmdtp, 0, 1, local_args); + break; + + case 2: + /* + * Call run_cmd + */ + printf("running command at addr 0x%s ...\n", addr); + run_command ((char*)(*ptr & ADDRMASK), 0); + break; + + default: + printf("unhandled boot method\n"); + break; + } + } +} + +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "loadpci - Wait for pci bootcmd and boot it\n", + NULL + ); + +#endif diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 0edc083..196171c 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Detect epson */ + lcd_reg[0] = 0x00; + lcd_reg[1] = 0x00; + if (lcd_reg[0] == 0x1c) { /* * Big epson detected diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index a60495a..88b0ae3 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ../common/misc.o +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index df10c0e..36bf329 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -26,22 +26,22 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; + int board_early_init_f (void) { unsigned long cntrl0Reg; /* - * Setup GPIO pins (CS4+CS7 as GPIO) + * Setup GPIO pins */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00900000); + mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); /* set output pins to high */ - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); - /* INTA# is open drain */ - out32(GPIO0_ODR, CFG_INTA_FAKE); - /* setup for output */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); + out32(GPIO0_OR, CFG_EEPROM_WP); + /* setup for output (LED=off) */ + out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -76,7 +76,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; unsigned long cntrl0Reg; /* adjust flash start and offset */ @@ -130,16 +129,6 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - #if defined(CFG_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state @@ -207,8 +196,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL - ); + eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL + ); #endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 2ab9673..f803610 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -27,7 +27,8 @@ #include <malloc.h> #include <net.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ #if 0 #define FPGA_DEBUG @@ -100,8 +101,6 @@ int board_early_init_f (void) #endif #ifdef FPGA_DEBUG - DECLARE_GLOBAL_DATA_PTR; - /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; @@ -126,8 +125,6 @@ int board_early_init_f (void) if (status != 0) { /* booting FPGA failed */ #ifndef FPGA_DEBUG - DECLARE_GLOBAL_DATA_PTR; - /* set up serial port with default baudrate */ (void) get_clocks (); gd->baudrate = CONFIG_BAUDRATE; @@ -268,7 +265,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; unsigned long cntrl0Reg; /* adjust flash start and offset */ @@ -707,8 +703,6 @@ U_BOOT_CMD( */ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; char *buf; ulong crc; diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 0486729..cd38b2d 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -29,7 +29,7 @@ SOBJS = misc.o OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ mv_eth.o mpsc.o i2c.o \ - sdram_init.o strataflash.o ide.o + sdram_init.o ide.o $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index e4b062b..dbed597 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -56,6 +56,7 @@ extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); +extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ @@ -363,6 +364,21 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif + if (flash_info[3].size < CFG_FLASH_INCREMENT) { + unsigned int flash_offset; + unsigned int l; + + flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + if (flash_info[3].start[l] != 0) { + flash_info[3].start[l] += flash_offset; + } + } + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + } return 0; } diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index 52398b2..25c10e0 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -42,6 +42,8 @@ #include "../../Marvell/include/memory.h" +DECLARE_GLOBAL_DATA_PTR; + /* Define this if you wish to use the MPSC as a register based UART. * This will force the serial port to not use the SDMA engine at all. */ @@ -157,7 +159,6 @@ char mpsc_getchar_debug (void) * global variables [josh] */ int mpsc_putchar_early (char ch) { - DECLARE_GLOBAL_DATA_PTR; int mpsc = CHANNEL; int temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); @@ -510,7 +511,6 @@ void mpsc_init2 (void) int galbrg_set_baudrate (int channel, int rate) { - DECLARE_GLOBAL_DATA_PTR; int clock; galbrg_disable (channel); /*ok */ diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index be176dc..bc84ef0 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -733,6 +733,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ pkt_info.byte_cnt = dataSize; pkt_info.buf_ptr = (unsigned int) dataPtr; + pkt_info.return_info = 0; status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index 3e44fb9..c335ebf 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, }; +#ifdef CONFIG_USE_CPCIDVI +typedef struct { + unsigned int base; + unsigned int init; +} GT_CPCIDVI_ROM_T; + +static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; +#endif #ifdef DEBUG static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; @@ -125,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = { /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, @@ -172,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. +* spec) +* pciDevNum: The device number needs to be addressed. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, @@ -220,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * * The configuration Address is configure as type-I (bits[1:0] = '01') due to * PCI spec referring to P2P. @@ -265,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host, /******************************************************************** * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, @@ -385,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) /******************************************************************** * pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! +* - If the PCI size is 0 then this base address has no meaning!!! * * * INPUT: Bus, Region - The bus and region we ask for its base address. @@ -493,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. +* feature bits given as an input. +* - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, @@ -533,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, /******************************************************************** * pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. +* to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. @@ -580,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host) * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, @@ -611,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. * * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, @@ -647,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, /******************************************************************** * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. * * Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. +* grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) @@ -670,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) /******************************************************************** * pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. * * Inputs: N/A * Returns: true. @@ -689,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host) /******************************************************************** * pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. +* For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. * * Returns: true. *********************************************************************/ @@ -715,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, @@ -746,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, GT_REG_WRITE (snoopXtopAddress, 0); return true; } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ data = (baseAddress >> 20) | snoopType << 12; GT_REG_WRITE (snoopXbaseAddress, data); snoopHigh = (snoopHigh & 0xfff00000) >> 20; @@ -800,23 +808,65 @@ static void gt_setup_ide (struct pci_controller *hose, unsigned int offset = (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); pciauto_region_allocate (bar_response & PCI_BASE_ADDRESS_SPACE_IO ? hose-> pci_io : hose->pci_mem, ide_bar[bar], &bar_value); - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); } } +#ifdef CONFIG_USE_CPCIDVI +static void gt_setup_cpcidvi (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + u32 bar_value, pci_response; + + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); + pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); + pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); + gt_cpcidvi_rom.base = bar_value & 0xffffff00; + gt_cpcidvi_rom.init = 1; +} + +unsigned char gt_cpcidvi_in8(unsigned int offset) +{ + unsigned char data; + + if (gt_cpcidvi_rom.init == 0) { + return(0); + } + data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); + return(data); +} + +void gt_cpcidvi_out8(unsigned int offset, unsigned char data) +{ + unsigned int off; -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ + if (gt_cpcidvi_rom.init == 0) { + return; + } + off = data; + off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; + in8(off); + return; +} +#endif + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ /* and is curently not called *. */ #if 0 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) @@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) #endif struct pci_config_table gt_config_table[] = { +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, +#endif {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} }; @@ -857,10 +910,21 @@ void pci_init_board (void) #ifdef CONFIG_PCI_PNP unsigned int bar; #endif - #ifdef DEBUG gt_pci_bus_mode_display (PCI_HOST0); #endif +#ifdef CONFIG_USE_CPCIDVI + gt_cpcidvi_rom.init = 0; + gt_cpcidvi_rom.base = 0; +#endif + + pci0_hose.config_table = gt_config_table; + pci1_hose.config_table = gt_config_table; + +#ifdef CONFIG_USE_CPCIDVI + gt_config_table[0].config_device = gt_setup_cpcidvi; +#endif + gt_config_table[1].config_device = gt_setup_ide; pci0_hose.first_busno = 0; pci0_hose.last_busno = 0xff; diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index db545ef..6bdfc1d 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -45,6 +45,7 @@ #include "64360.h" #include "mv_regs.h" +DECLARE_GLOBAL_DATA_PTR; #undef DEBUG /* #define DEBUG */ @@ -250,8 +251,6 @@ NSto10PS(unsigned char spd_byte) /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long spd_checksum; uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index 44de052..ba32ac1 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -38,13 +38,12 @@ #include "../../Marvell/include/memory.h" #include "serial.h" - #include "mpsc.h" +DECLARE_GLOBAL_DATA_PTR; + int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - mpsc_init (gd->baudrate); return (0); @@ -70,8 +69,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c deleted file mode 100644 index c22fe5d..0000000 --- a/board/esd/cpci750/strataflash.c +++ /dev/null @@ -1,763 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/cache.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - invalidate_dcache_range(base, base+0x400); - - if(flash_detect_cfi(info)){ - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index 7bf7bb5..fcb8cbb 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -26,6 +26,8 @@ #include <asm/processor.h> #include <command.h> +DECLARE_GLOBAL_DATA_PTR; + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -55,8 +57,6 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - int index, len, i; volatile unsigned char dummy; int status; diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index fd51f7f..240ab78 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -26,6 +26,7 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; /* fpga configuration data - not compressed, generated by bin2c */ const unsigned char fpgadata[] = @@ -84,8 +85,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 26e8341..a019ce4 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -28,6 +28,8 @@ #include <405gp_i2c.h> #include <command.h> +DECLARE_GLOBAL_DATA_PTR; + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -55,8 +57,6 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - int index, len, i; int status; diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c index 58ee3a8..64bca46 100644 --- a/board/esd/hh405/fpgadata.c +++ b/board/esd/hh405/fpgadata.c @@ -1,2520 +1,2517 @@ - 0x1f,0x8b,0x08,0x08,0x9c,0xc4,0xe8,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f, - 0x31,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x14,0xd7,0x91, - 0x2f,0x0c,0x57,0x9f,0x6e,0x89,0xa3,0xe9,0x91,0xa6,0x91,0x84,0x57,0xb6,0x31,0x6e, - 0x8d,0x04,0x1e,0x94,0x91,0x18,0x46,0x58,0xc8,0x42,0x8c,0x5a,0x23,0xd9,0x19,0x1b, - 0x6c,0x26,0x8e,0x93,0x65,0x77,0xfd,0xe5,0x0e,0x84,0x64,0x95,0xbc,0xc4,0x2b,0x3b, - 0xb9,0x7b,0x49,0xd6,0xeb,0x1c,0x8d,0x04,0x8c,0x90,0x0c,0x03,0x28,0x31,0x4e,0x58, - 0x6f,0x23,0x64,0x5b,0x38,0x24,0x3b,0x08,0x0c,0x02,0x1c,0xdc,0xc2,0xb2,0x2d,0xfe, - 0x18,0x2b,0x0e,0xeb,0xe0,0x3f,0x71,0x06,0x47,0x26,0xb2,0x23,0xdb,0x32,0xc6,0x8e, - 0x04,0x02,0xde,0x3a,0x3d,0x92,0xa6,0x47,0x64,0xf7,0xe6,0xbe,0xf7,0xf9,0xde,0x6f, - 0x9f,0xe7,0xbb,0xf2,0xf3,0xec,0x9e,0xb4,0x8e,0x9a,0xee,0xd3,0xe7,0x54,0xfd,0xaa, - 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0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1, + 0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe, + 0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3, + 0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd, + 0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff, + 0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f, + 0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06, + 0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1, + 0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09, + 0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b, + 0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 3158803..ea344c0 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,6 +34,7 @@ #include <pci.h> #include <sm501.h> +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_VIDEO_SM501 @@ -66,10 +70,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -100,10 +106,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -144,10 +152,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -178,10 +188,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -272,6 +284,9 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); +/* + * Get version of HH405 board from GPIO's + */ int board_revision(void) { unsigned long osrh_reg; @@ -280,10 +295,6 @@ int board_revision(void) unsigned long value; /* - * Get version of HH405 board from GPIO's - */ - - /* * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) */ osrh_reg = in32(GPIO0_OSRH); @@ -305,15 +316,13 @@ int board_revision(void) if (value & 0x80000000) { /* Revision 1.0 or 1.1 detected */ - return 0x0101; + return 1; } else { if (value & 0x00400000) { /* unused */ - return 0x0103; + return 3; } else { - /* Revision >= 2.0 detected */ - /* rev. 2.x uses four SM501 GPIOs for revision coding */ - return 0x0200; + return 2; } } } @@ -349,11 +358,39 @@ int board_early_init_f (void) return 0; } +int cf_enable(void) +{ + int i; + + volatile unsigned short *fpga_ctrl = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + + if (gd->board_type >= 2) { + if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) { + if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN; + + for (i=0; i<300; i++) + udelay(1000); + + *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + + for (i=0; i<20; i++) + udelay(1000); + } + } else { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN; + } + } + + return 0; +} int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile unsigned short *fpga_ctrl = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); volatile unsigned short *lcd_contrast = @@ -433,9 +470,6 @@ int misc_init_r (void) * Write Board revision into FPGA */ *fpga_ctrl |= gd->board_type & 0x0003; - if (gd->board_type >= 0x0200) { - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; - } /* * Setup and enable EEPROM write protection @@ -471,7 +505,7 @@ int misc_init_r (void) contrast0 = simple_strtol(str, NULL, 16); if (contrast0 > 255) { printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); - contrast0 = 0; + contrast0 = 0xffffffff; } } @@ -544,9 +578,9 @@ int misc_init_r (void) */ *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; /* - * Set lcd clock (small epson) + * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330; + *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE; lcd_setup(0, 1); lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, @@ -565,8 +599,10 @@ int misc_init_r (void) puts("VGA: SM501 with 8 MB "); if (strcmp(str, "ppc221") == 0) { printf("(800*600, %dbpp)\n", BPP); + *lcd_backlight = 0x002d; /* max. allowed brightness */ } else if (strcmp(str, "ppc231") == 0) { printf("(1024*768, %dbpp)\n", BPP); + *lcd_backlight = 0x0000; } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; @@ -578,6 +614,8 @@ int misc_init_r (void) #endif /* CONFIG_VIDEO_SM501 */ } + cf_enable(); + return (0); } @@ -588,9 +626,7 @@ int misc_init_r (void) int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -608,14 +644,7 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev %ld.%ld)\n", - (gd->board_type >> 8) & 0xff, - gd->board_type & 0xff); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + printf(", Rev %ld.x)\n", gd->board_type); return 0; } @@ -637,35 +666,32 @@ long int initdram (int board_type) } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { volatile unsigned short *fpga_mode = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) || + (gd->board_type < 2)) { + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + cf_enable(); + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } } } #endif /* CONFIG_IDE_RESET */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) @@ -756,8 +782,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, */ void video_get_info_str (int line_number, char *info) { - DECLARE_GLOBAL_DATA_PTR; - char str[64]; char str2[64]; int i = getenv_r("serial#", str2, sizeof(str)); @@ -778,8 +802,7 @@ void video_get_info_str (int line_number, char *info) strcat(str, " (Missing bd_type!"); } - sprintf(str2, ", Rev %ld.%ld)", - (gd->board_type >> 8) & 0xff, gd->board_type & 0xff); + sprintf(str2, ", Rev %ld.x)", gd->board_type); strcat(str, str2); strcpy(info, str); } else { @@ -822,7 +845,11 @@ unsigned int board_video_get_fb (void) devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); if (devbusfn != -1) { pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - return (addr & 0xfffffffe); + addr &= 0xfffffffe; +#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET + addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; +#endif + return addr; } return 0; @@ -875,3 +902,15 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index e77dba8..1e0accb 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -26,10 +26,10 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); - int board_revision(void) { unsigned long osrl_reg; @@ -110,8 +110,6 @@ int misc_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); @@ -208,8 +206,6 @@ int misc_init_r (void) */ int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); @@ -265,7 +261,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 4be4d7e..e5d2273 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -30,6 +30,7 @@ #include "pci405.h" +DECLARE_GLOBAL_DATA_PTR; /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); @@ -111,8 +112,6 @@ int board_revision(void) unsigned long fpga_done_state(void) { - DECLARE_GLOBAL_DATA_PTR; - if (gd->board_type < 2) { return FPGA_DONE_STATE_V11; } else { @@ -123,8 +122,6 @@ unsigned long fpga_done_state(void) unsigned long fpga_init_state(void) { - DECLARE_GLOBAL_DATA_PTR; - if (gd->board_type < 2) { return FPGA_INIT_STATE_V11; } else { @@ -320,8 +317,6 @@ int misc_init_r (void) int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 5b9d063..37b92fb 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -269,7 +269,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index 1281be7..741e4aa 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -30,7 +30,7 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -OBJS = $(BOARD).o ../common/misc.o $(CPLD) +OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 33b5f77..7499671 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -1,6 +1,9 @@ /* * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. @@ -26,10 +29,10 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); - /* fpga configuration data - not compressed, generated by bin2c */ const unsigned char fpgadata[] = { @@ -66,16 +69,27 @@ int board_early_init_f (void) mtebc (epcr, 0xa8400000); /* - * Setup GPIO pins (CS6+CS7 as GPIO) + * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000); - /* - * Configure GPIO pins + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \ + CFG_FPGA_DONE | \ + CFG_XEREADY | \ + CFG_NONMONARCH | \ + CFG_REV1_2) << 5)); + + if (!(in32(GPIO0_IR) & CFG_REV1_2)) { + /* rev 1.2 boards */ + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \ + CFG_SELF_RST) << 5)); + } + + out32(GPIO0_OR, 0); + out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */ + + /* - check if rev1_2 is low, then: + * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST# */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */ - out32(GPIO0_OR, 0); /* outputs -> low */ return 0; } @@ -83,30 +97,37 @@ int board_early_init_f (void) /* ------------------------------------------------------------------------- */ -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */ return (0); } +ushort pmc405_pci_subsys_deviceid(void) +{ + ulong val; + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + if (val & CFG_NONMONARCH) { /* monarch# signal */ + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_MONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; +} /* * Check Board Identity: */ - int checkboard (void) { + ulong val; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); @@ -118,12 +139,18 @@ int checkboard (void) puts(str); } - putc ('\n'); + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + puts(" rev1.2 ("); + if (val & CFG_NONMONARCH) { /* monarch# signal */ + puts("non-"); + } + puts("monarch)"); + } else { + puts(" <=rev1.1"); + } - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + putc ('\n'); return 0; } @@ -145,17 +172,19 @@ long int initdram (int board_type) return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ -int testdram (void) +/* ------------------------------------------------------------------------- */ +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } -/* ------------------------------------------------------------------------- */ int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index eda3fd9..22995b5 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -343,7 +343,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index 445b8fc..8be552e 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -26,10 +26,10 @@ #include <command.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); - /* fpga configuration data - not compressed, generated by bin2c */ const unsigned char fpgadata[] = { @@ -81,8 +81,6 @@ int board_early_init_f (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; @@ -97,7 +95,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); int flashcnt; int delay; diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index db24122..5a1a3f3 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c index 93c502c..08ed635 100644 --- a/board/etin/debris/debris.c +++ b/board/etin/debris/debris.c @@ -26,6 +26,8 @@ #include <pci.h> #include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + int checkboard (void) { /*TODO: Check processor type */ @@ -170,8 +172,6 @@ void nvram_write(long dest, const void *src, size_t count) int misc_init_r(void) { - DECLARE_GLOBAL_DATA_PTR; - /* Write ethernet addr in NVRAM for VxWorks */ nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS, (char*)&gd->bd->bi_enetaddr[0], 6); diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c index dba3c11..eb58b5d 100644 --- a/board/etx094/etx094.c +++ b/board/etx094/etx094.c @@ -24,6 +24,8 @@ #include <common.h> #include <mpc8xx.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ static long int dram_size (long int, long int *, long int); @@ -90,8 +92,6 @@ const uint sdram_table[] = { int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char *s = getenv ("serial#"); char *e; diff --git a/board/evb4510/evb4510.c b/board/evb4510/evb4510.c index 0008e5a..13abbb7 100644 --- a/board/evb4510/evb4510.c +++ b/board/evb4510/evb4510.c @@ -25,6 +25,8 @@ #include <asm/hardware.h> #include <command.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_EVB4510 /* ------------------------------------------------------------------------- */ @@ -35,8 +37,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - icache_enable(); /* address for the kernel command line */ @@ -52,7 +52,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; #if CONFIG_NR_DRAM_BANKS == 2 diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index 6a9d164..ab59941 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -37,6 +37,9 @@ #include "mpsc.h" #include "i2c.h" #include "64260.h" + +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_ZUMA_V2 extern void zuma_mbox_init(void); #endif @@ -323,8 +326,6 @@ int misc_init_r (void) void after_reloc(ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index ee623ca..98ac7f6 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -32,6 +32,8 @@ #include <malloc.h> #include "mpsc.h" +DECLARE_GLOBAL_DATA_PTR; + int (*mpsc_putchar)(char ch) = mpsc_putchar_early; static volatile unsigned int *rx_desc_base=NULL; @@ -115,7 +117,6 @@ struct _tag_mirror_hack { int mpsc_putchar_early(char ch) { - DECLARE_GLOBAL_DATA_PTR; int mpsc=CHANNEL; int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); galmpsc_set_tcschar(mpsc,ch); @@ -177,79 +178,82 @@ mpsc_putchar_sdma(char ch) return 0; } -char -mpsc_getchar(void) +char mpsc_getchar (void) { - DECLARE_GLOBAL_DATA_PTR; - static unsigned int done = 0; - volatile char ch; - unsigned int len=0, idx=0, temp; - - volatile unsigned int *p; - - - do { - p=&rx_desc_base[rx_desc_index*8]; - - INVALIDATE_DCACHE(&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER){ - udelay(100); - INVALIDATE_DCACHE(&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1<<15)) { - printf("oops, error: %08x\n", p[1]); - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP); - temp |= (1 << 23); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay(100); + static unsigned int done = 0; + volatile char ch; + unsigned int len = 0, idx = 0, temp; - galsdma_enable_rx(); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) idx = 4; - if (done > 7) idx = 7; - if (done > 11) idx = 6; - - INVALIDATE_DCACHE(&p[idx], &p[idx+1]); - ch = p[idx] & 0xff; - done++; - } + volatile unsigned int *p; - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE(&p[idx], &p[idx+1]); - } - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE(&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len==0); /* galileo bug.. len might be zero */ - - return ch; + do { + p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER) { + udelay (100); + INVALIDATE_DCACHE (&p[0], &p[1]); + } + + /* Handle error case */ + if (p[1] & (1 << 15)) { + printf ("oops, error: %08x\n", p[1]); + + temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2, + CHANNEL, GALMPSC_REG_GAP); + temp |= (1 << 23); + GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL, + GALMPSC_REG_GAP, temp); + + /* Can't poll on abort bit, so we just wait. */ + udelay (100); + + galsdma_enable_rx (); + } + + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; + + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) + idx = 4; + if (done > 7) + idx = 7; + if (done > 11) + idx = 6; + + INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); + ch = p[idx] & 0xff; + done++; + } + + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE (&p[idx], &p[idx + 1]); + } + + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE (&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len == 0); /* galileo bug.. len might be zero */ + + return ch; } int @@ -266,8 +270,6 @@ mpsc_test_char(void) int mpsc_init(int baud) { - DECLARE_GLOBAL_DATA_PTR; - memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack)); MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; @@ -382,7 +384,6 @@ mpsc_init2(void) int galbrg_set_baudrate(int channel, int rate) { - DECLARE_GLOBAL_DATA_PTR; int clock; galbrg_disable(channel); @@ -410,7 +411,6 @@ galbrg_set_baudrate(int channel, int rate) static int galbrg_set_CDV(int channel, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); @@ -424,7 +424,6 @@ galbrg_set_CDV(int channel, int value) static int galbrg_enable(int channel) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); @@ -437,7 +436,6 @@ galbrg_enable(int channel) static int galbrg_disable(int channel) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); @@ -450,7 +448,6 @@ galbrg_disable(int channel) static int galbrg_set_clksrc(int channel, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); @@ -583,7 +580,6 @@ galsdma_set_burstsize(int channel, unsigned int value) static int galmpsc_connect(int channel, int connect) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); @@ -629,7 +625,6 @@ galmpsc_route_serial(int channel, int connect) static int galmpsc_route_rx_clock(int channel, int brg) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); @@ -647,7 +642,6 @@ galmpsc_route_rx_clock(int channel, int brg) static int galmpsc_route_tx_clock(int channel, int brg) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); @@ -688,7 +682,6 @@ galmpsc_write_config_regs(int mpsc, int mode) static int galmpsc_config_channel_regs(int mpsc) { - DECLARE_GLOBAL_DATA_PTR; GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); @@ -709,7 +702,6 @@ galmpsc_config_channel_regs(int mpsc) static int galmpsc_set_brkcnt(int mpsc, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); @@ -723,7 +715,6 @@ galmpsc_set_brkcnt(int mpsc, int value) static int galmpsc_set_tcschar(int mpsc, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); @@ -737,7 +728,6 @@ galmpsc_set_tcschar(int mpsc, int value) static int galmpsc_set_char_length(int mpsc, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); @@ -751,7 +741,6 @@ galmpsc_set_char_length(int mpsc, int value) static int galmpsc_set_stop_bit_length(int mpsc, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); @@ -764,7 +753,6 @@ galmpsc_set_stop_bit_length(int mpsc, int value) static int galmpsc_set_parity(int mpsc, int value) { - DECLARE_GLOBAL_DATA_PTR; unsigned int temp; temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); @@ -784,7 +772,6 @@ galmpsc_set_parity(int mpsc, int value) static int galmpsc_enter_hunt(int mpsc) { - DECLARE_GLOBAL_DATA_PTR; int temp; temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); @@ -802,7 +789,6 @@ galmpsc_enter_hunt(int mpsc) static int galmpsc_shutdown(int mpsc) { - DECLARE_GLOBAL_DATA_PTR; #if 0 unsigned int temp; diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index 8d63c6f..fae6d10 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -35,6 +35,8 @@ #include "i2c.h" #include "64260.h" +DECLARE_GLOBAL_DATA_PTR; + /* #define DEBUG */ #define MAP_PCI @@ -199,7 +201,6 @@ static int check_dimm (uchar slot, sdram_info_t * info) * the array which is passed in with the relevant information */ static int check_dimm (uchar slot, sdram_info_t * info) { - DECLARE_GLOBAL_DATA_PTR; uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; uchar rows, cols, sdram_banks, supp_cal, width, cal_val; diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index d9c7a15..191445c 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -39,6 +39,8 @@ #include "mpsc.h" +DECLARE_GLOBAL_DATA_PTR; + #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; @@ -48,8 +50,6 @@ const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #endif @@ -90,8 +90,6 @@ serial_tstc(void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); } @@ -99,8 +97,6 @@ serial_setbrg (void) int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 @@ -137,8 +133,6 @@ serial_tstc(void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile new file mode 100644 index 0000000..c9b3c92 --- /dev/null +++ b/board/ezkit533/Makefile @@ -0,0 +1,44 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ezkit533.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk new file mode 100644 index 0000000..36c9f99 --- /dev/null +++ b/board/ezkit533/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c new file mode 100644 index 0000000..8d6c8de --- /dev/null +++ b/board/ezkit533/ezkit533.c @@ -0,0 +1,72 @@ +/* + * U-boot - ezkit533.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_MISC_INIT_R) +#include "psd4256.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf("Board: ADI BF533 EZ-Kit Lite board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + printf(" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram(int board_type) +{ +#ifdef DEBUG + int brate; + char *tmp = getenv("baudrate"); + brate = simple_strtoul(tmp, NULL, 16); + printf("Serial Port initialized with Baud rate = %x\n",brate); + printf("SDRAM attributes:\n"); + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", + 3, 3, 6, 2, 3); + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return CFG_MAX_RAM_SIZE; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + /* Set direction bits for Video en/decoder reset as output */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; + /* Deactivate Video en/decoder reset lines */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; +} +#endif diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h new file mode 100644 index 0000000..8f9dff5 --- /dev/null +++ b/board/ezkit533/flash-defines.h @@ -0,0 +1,130 @@ +/* + * U-boot - flash-defines.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FLASHDEFINES_H__ +#define __FLASHDEFINES_H__ + +#include <common.h> + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) +#define TRUE 0x1 +#define FALSE 0x0 +#define BUFFER_SIZE 0x80000 +#define NO_COMMAND 0 +#define GET_CODES 1 +#define RESET 2 +#define WRITE 3 +#define FILL 4 +#define ERASE_ALL 5 +#define ERASE_SECT 6 +#define READ 7 +#define GET_SECTNUM 8 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define FLASH_MAN_ST 2 +#define CFG_FLASH0_BASE 0x20000000 +#define RESET_VAL 0xF0 + + +asm("#define FLASH_START_L 0x0000"); +asm("#define FLASH_START_H 0x2000"); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +int get_codes(void); +int poll_toggle_bit(long lOffset); +void reset_flash(void); +int erase_flash(void); +int erase_block_flash(int,unsigned long); +void unlock_flash(long lOffset); +int write_data(long lStart, long lCount, long lStride, int *pnData); +int FillData(long lStart, long lCount, long lStride, int *pnData); +int read_data(long lStart, long lCount, long lStride, int *pnData); +int read_flash(long nOffset, int *pnValue); +int write_flash(long nOffset, int nValue); +void get_sector_number(long lOffset, int *pnSector); +int GetSectorProtectionStatus(flash_info_t * info, int nSector); +int GetOffset(int nBlock); +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + +#define WRITESEQ1 0x0AAA +#define WRITESEQ2 0x0554 +#define WRITESEQ3 0x0AAA +#define WRITESEQ4 0x0AAA +#define WRITESEQ5 0x0554 +#define WRITESEQ6 0x0AAA +#define WRITEDATA1 0xaa +#define WRITEDATA2 0x55 +#define WRITEDATA3 0x80 +#define WRITEDATA4 0xaa +#define WRITEDATA5 0x55 +#define WRITEDATA6 0x10 +#define PriFlashABegin 0 +#define SecFlashABegin 32 +#define SecFlashBBegin 36 +#define PriFlashAOff 0x0 +#define PriFlashBOff 0x100000 +#define SecFlashAOff 0x200000 +#define SecFlashBOff 0x280000 +#define INVALIDLOCNSTART 0x20270000 +#define INVALIDLOCNEND 0x20280000 +#define BlockEraseVal 0x30 +#define UNLOCKDATA1 0xaa +#define UNLOCKDATA2 0x55 +#define UNLOCKDATA3 0xa0 +#define GETCODEDATA1 0xaa +#define GETCODEDATA2 0x55 +#define GETCODEDATA3 0x90 +#define SecFlashASec1Off 0x200000 +#define SecFlashASec2Off 0x204000 +#define SecFlashASec3Off 0x206000 +#define SecFlashASec4Off 0x208000 +#define SecFlashAEndOff 0x210000 +#define SecFlashBSec1Off 0x280000 +#define SecFlashBSec2Off 0x284000 +#define SecFlashBSec3Off 0x286000 +#define SecFlashBSec4Off 0x288000 +#define SecFlashBEndOff 0x290000 + +#define SECT32 32 +#define SECT33 33 +#define SECT34 34 +#define SECT35 35 +#define SECT36 36 +#define SECT37 37 +#define SECT38 38 +#define SECT39 39 + +#define FLASH_SUCCESS 0 +#define FLASH_FAIL -1 + +#endif diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c new file mode 100644 index 0000000..b0a0796 --- /dev/null +++ b/board/ezkit533/flash.c @@ -0,0 +1,476 @@ +/* + * U-boot - flash.c Flash driver for PSD4256GV + * + * Copyright (c) 2005 blackfin.uclinux.org + * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "flash-defines.h" + +void flash_reset(void) +{ + reset_flash(); +} + +unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, + int bank_flag) +{ + int id = 0, i = 0; + static int FlagDev = 1; + + id = get_codes(); + if(FlagDev) { +#ifdef DEBUG + printf("Device ID of the Flash is %x\n", id); +#endif + FlagDev = 0; + } + info->flash_id = id; + + switch (bank_flag) { + case 0: + for (i = PriFlashABegin; i < SecFlashABegin; i++) + info->start[i] = (baseaddr + (i * AFP_SectorSize1)); + info->size = 0x200000; + info->sector_count = 32; + break; + case 1: + info->start[0] = baseaddr + SecFlashASec1Off; + info->start[1] = baseaddr + SecFlashASec2Off; + info->start[2] = baseaddr + SecFlashASec3Off; + info->start[3] = baseaddr + SecFlashASec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + case 2: + info->start[0] = baseaddr + SecFlashBSec1Off; + info->start[1] = baseaddr + SecFlashBSec2Off; + info->start[2] = baseaddr + SecFlashBSec3Off; + info->start[3] = baseaddr + SecFlashBSec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + } + return (info->size); +} + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1, size_b2; + int i; + + size_b0 = size_b1 = size_b2 = 0; +#ifdef DEBUG + printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); + printf("Memory Map for the Flash\n"); + printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); + printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); + printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n"); + printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); + printf("Please type command flinfo for information on Sectors \n"); +#endif + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); + size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); + size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]); + + return (size_b0 + size_b1 + size_b2); +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id) { + case FLASH_PSD4256GV: + printf("ST Microelectronics "); + break; + default: + printf("Unknown Vendor "); + break; + } + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int cnt = 0,i; + int prot,sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + cnt = s_last - s_first + 1; + + if (cnt == FLASH_TOT_SECT) { + printf("Erasing flash, Please Wait \n"); + if(erase_flash() < 0) { + printf("Erasing flash failed \n"); + return FLASH_FAIL; + } + } else { + printf("Erasing Flash locations, Please Wait\n"); + for (i = s_first; i <= s_last; i++) { + if (info->protect[i] == 0) { /* not protected */ + if(erase_block_flash(i, info->start[i]) < 0) { + printf("Error Sector erasing \n"); + return FLASH_FAIL; + } + } + } + } + return FLASH_SUCCESS; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int ret; + + ret = write_data(addr, cnt, 1, (int *) src); + if(ret == FLASH_FAIL) + return ERR_NOT_ERASED; + return FLASH_SUCCESS; +} + + +int write_data(long lStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + unsigned long ulOffset = lStart - CFG_FLASH_BASE; + int d; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; (j < iNumWords); + j++, ulOffset += (lStride * 2)) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) { + printf("Invalid locations, Try writing to another location \n"); + return FLASH_FAIL; + } + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + iShift += 16; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash already programmed. Please erase to reprogram \n"); + printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, pnData[i]) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + } + return FLASH_SUCCESS; +} + +int read_data(long ulStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + long ulOffset = ulStart; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nHi, nLow; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; j < iNumWords; j += 2) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &nLow); + ulOffset += (lStride * 2); + read_flash(ulOffset, &nHi); + ulOffset += (lStride * 2); + pnData[i] = (nHi << 16) | nLow; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &pnData[i]); + } + return FLASH_SUCCESS; +} + +int write_flash(long nOffset, int nValue) +{ + long addr; + + addr = (CFG_FLASH_BASE + nOffset); + asm("ssync;"); + *(unsigned volatile short *) addr = nValue; + asm("ssync;"); + if(poll_toggle_bit(nOffset) < 0) + return FLASH_FAIL; + return FLASH_SUCCESS; +} + +int read_flash(long nOffset, int *pnValue) +{ + int nValue = 0x0; + long addr = (CFG_FLASH_BASE + nOffset); + + if (nOffset != 0x2) + reset_flash(); + asm("ssync;"); + nValue = *(volatile unsigned short *) addr; + asm("ssync;"); + *pnValue = nValue; + return TRUE; +} + +int poll_toggle_bit(long lOffset) +{ + unsigned int u1,u2; + unsigned long timeout = 0xFFFFFFFF; + volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset); + while(1) { + if(timeout < 0) + break; + u1 = *(volatile unsigned short *)FB; + u2 = *(volatile unsigned short *)FB; + if((u1 & 0x0040) == (u2 & 0x0040)) + return FLASH_SUCCESS; + if((u2 & 0x0020) == 0x0000) + continue; + u1 = *(volatile unsigned short *)FB; + if((u2 & 0x0040) == (u1 & 0x0040)) + return FLASH_SUCCESS; + else { + reset_flash(); + return FLASH_FAIL; + } + timeout--; + } + printf("Time out occured \n"); + if(timeout <0) return FLASH_FAIL; +} + +void reset_flash(void) +{ + write_flash(WRITESEQ1, RESET_VAL); + /* Wait for 10 micro seconds */ + udelay(10); +} + +int erase_flash(void) +{ + write_flash(WRITESEQ1, WRITEDATA1); + write_flash(WRITESEQ2, WRITEDATA2); + write_flash(WRITESEQ3, WRITEDATA3); + write_flash(WRITESEQ4, WRITEDATA4); + write_flash(WRITESEQ5, WRITEDATA5); + write_flash(WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(0x0000) < 0) + return FLASH_FAIL; + + write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashASec1Off) < 0) + return FLASH_FAIL; + + write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(PriFlashBOff) <0) + return FLASH_FAIL; + + write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashBOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +int erase_block_flash(int nBlock, unsigned long address) +{ + long ulSectorOff = 0x0; + + if ((nBlock < 0) || (nBlock > AFP_NumSectors)) + return FALSE; + + ulSectorOff = (address - CFG_FLASH_BASE); + + write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); + write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); + write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); + write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); + write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); + + write_flash(ulSectorOff, BlockEraseVal); + + if(poll_toggle_bit(ulSectorOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +void unlock_flash(long ulOffset) +{ + unsigned long ulOffsetAddr = ulOffset; + ulOffsetAddr &= 0xFFFF0000; + + write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); + write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); + write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); +} + +int get_codes() +{ + int dev_id = 0; + + write_flash(WRITESEQ1, GETCODEDATA1); + write_flash(WRITESEQ2, GETCODEDATA2); + write_flash(WRITESEQ3, GETCODEDATA3); + + read_flash(0x0002, &dev_id); + dev_id &= 0x00FF; + + reset_flash(); + + return dev_id; +} + +void get_sector_number(long ulOffset, int *pnSector) +{ + int nSector = 0; + + if (ulOffset >= SecFlashAOff) { + if ((ulOffset < SecFlashASec1Off) + && (ulOffset < SecFlashASec2Off)) { + nSector = SECT32; + } else if ((ulOffset >= SecFlashASec2Off) + && (ulOffset < SecFlashASec3Off)) { + nSector = SECT33; + } else if ((ulOffset >= SecFlashASec3Off) + && (ulOffset < SecFlashASec4Off)) { + nSector = SECT34; + } else if ((ulOffset >= SecFlashASec4Off) + && (ulOffset < SecFlashAEndOff)) { + nSector = SECT35; + } + } else if (ulOffset >= SecFlashBOff) { + if ((ulOffset < SecFlashBSec1Off) + && (ulOffset < SecFlashBSec2Off)) { + nSector = SECT36; + } + if ((ulOffset < SecFlashBSec2Off) + && (ulOffset < SecFlashBSec3Off)) { + nSector = SECT37; + } + if ((ulOffset < SecFlashBSec3Off) + && (ulOffset < SecFlashBSec4Off)) { + nSector = SECT38; + } + if ((ulOffset < SecFlashBSec4Off) + && (ulOffset < SecFlashBEndOff)) { + nSector = SECT39; + } + } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) { + nSector = ulOffset & 0xffff0000; + nSector = ulOffset >> 16; + nSector = nSector & 0x000ff; + } + + if ((nSector >= 0) && (nSector < AFP_NumSectors)) { + *pnSector = nSector; + } +} diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h new file mode 100644 index 0000000..01f6566 --- /dev/null +++ b/board/ezkit533/psd4256.h @@ -0,0 +1,67 @@ +/* + * U-boot - psd4256.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Flash A/B Port A configuration registers. + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTA_DIN 0x070000 +#define PSD_PORTA_DOUT 0x070004 +#define PSD_PORTA_DIR 0x070006 + +/* + * Flash A/B Port B configuration registers + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTB_DIN 0x070001 +#define PSD_PORTB_DOUT 0x070005 +#define PSD_PORTB_DIR 0x070007 + +/* + * Flash A Port A Bit definitions + */ + +#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ +#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ +#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ +#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ +#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ + +/* + * Flash A Port B Bit definitions + */ + +#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ +#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ +#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ +#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ +#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ +#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds new file mode 100644 index 0000000..10203ff --- /dev/null +++ b/board/ezkit533/u-boot.lds @@ -0,0 +1,148 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + board/ezkit533/ezkit533.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/fads.c b/board/fads/fads.c index 013b3cb..7b04af5 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -726,24 +726,23 @@ static void checkdboard(void) int checkboard (void) { - /* get revision from BCSR 3 */ +#if defined(CONFIG_MPC86xADS) + puts ("Board: MPC86xADS\n"); +#elif defined(CONFIG_MPC885ADS) + puts ("Board: MPC885ADS\n"); +#else /* Only old ADS/FADS have got revision ID in BCSR3 */ uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) | (((*((uint *) BCSR3) >> 19) & 1) << 2) | (((*((uint *) BCSR3) >> 16) & 3)); puts ("Board: "); - -#if defined(CONFIG_MPC86xADS) - puts ("MPC86xADS"); -#elif defined(CONFIG_MPC885ADS) - puts ("MPC885ADS"); - r = 0; /* I've got NR (No Revision) board */ -#elif defined(CONFIG_FADS) +#if defined(CONFIG_FADS) puts ("FADS"); checkdboard (); #else puts ("ADS"); #endif + puts (" rev "); switch (r) { @@ -758,13 +757,9 @@ int checkboard (void) puts ("A - warning, read errata \n"); break; case 0x03: - puts ("B \n"); + puts ("B\n"); break; -#elif defined(CONFIG_MPC885ADS) - case 0x00: - puts ("NR\n"); - break; -#else /* FADS and newer */ +#else /* FADS */ case 0x00: puts ("ENG\n"); break; @@ -776,6 +771,7 @@ int checkboard (void) printf ("unknown (0x%x)\n", r); return -1; } +#endif /* CONFIG_MPC86xADS */ return 0; } @@ -848,7 +844,7 @@ int pcmcia_init(void) switch ((pcmp->pcmc_pipr >> 14) & 3) #endif { - case 0x00 : + case 0x03 : printf("5V"); v = 5; break; @@ -860,7 +856,7 @@ int pcmcia_init(void) v = 5; #endif break; - case 0x03 : + case 0x00 : printf("5V, 3V and x.xV"); #ifdef CONFIG_FADS v = 3; /* User lower voltage if supported! */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 1127c7f..e981be0 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -55,18 +55,26 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NFSBOOTCOMMAND \ "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ "bootm" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ + "bootm fe080000" + +#undef CONFIG_BOOTARGS + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ /* - * New MPC86xADS and Duet provide two Ethernet connectivity options: + * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * got FEC so FEC is the default. @@ -89,7 +97,9 @@ #ifndef CONFIG_COMMANDS #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ @@ -104,16 +114,18 @@ /* * Miscellaneous configurable options */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -126,6 +138,7 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ + /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ @@ -148,6 +161,14 @@ #define CFG_SDRAM_BASE 0x00000000 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +/* + * 2048 SDRAM rows + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) #elif defined(CONFIG_FADS) /* Old/new FADS */ #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ #else /* Old ADS */ @@ -223,9 +244,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif /*----------------------------------------------------------------------- * I2C configuration @@ -277,31 +296,21 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) +#define CFG_SCCR SCCR_TBS /*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + * DER - Debug Enable Register *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#ifndef CFG_PLPRCR -#define CFG_PLPRCR PLPRCR_TEXPS -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * + * Set to zero to prevent the processor from entering debug mode */ #define CFG_DER 0 -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ +/* Because of the way the 860 starts up and assigns CS0 the entire + * address space, we have to set the memory controller differently. + * Normally, you write the option register first, and then enable the + * chip select by writing the base register. For CS0, you must write + * the base register first, followed by the option register. + */ /* * Init Memory Controller: @@ -335,9 +344,6 @@ /* values according to the manual */ -#define PCMCIA_MEM_ADDR ((uint)0xFF020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - #define BCSR0 ((uint) (BCSR_ADDR + 0x00)) #define BCSR1 ((uint) (BCSR_ADDR + 0x04)) #define BCSR2 ((uint) (BCSR_ADDR + 0x08)) @@ -396,59 +402,28 @@ #define BCSR4_TFPLDL ((uint)0x40000000) #define BCSR4_TPSQEL ((uint)0x20000000) #define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#ifdef CONFIG_MPC823 +#if defined(CONFIG_MPC823) #define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 +#elif defined(CONFIG_MPC850) #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ +#elif defined(CONFIG_MPC860SAR) +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#else /* MPC860T and other chips with FEC */ +#define BCSR4_FETH_EN ((uint)0x08000000) +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#define BCSR4_FETHFDE ((uint)0x02000000) +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#define BCSR4_FETHRST ((uint)0x00200000) +#endif -/* BSCR5 exists on MPC86xADS and Duet ADS only */ +/* BSCR5 exists on MPC86xADS and MPC885ADS only */ #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) @@ -511,4 +486,4 @@ #define CFG_ATA_ALT_OFFSET 0x0000 #define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ +/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 3f78753..39b5c70 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -185,7 +185,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c index 261e894..829b597 100644 --- a/board/gcplus/gcplus.c +++ b/board/gcplus/gcplus.c @@ -26,7 +26,8 @@ #include <common.h> #include <SA-1100.h> -/* ------------------------------------------------------------------------- */ + +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -35,8 +36,6 @@ int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT; gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */ @@ -62,8 +61,6 @@ board_init(void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 37788d5..2ba7e0e 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -32,6 +32,8 @@ #include <command.h> #include "fpga.h" +DECLARE_GLOBAL_DATA_PTR; + #if (CONFIG_FPGA) #if 0 @@ -189,8 +191,6 @@ void fpga_selectmap_init (void) */ int gen860t_init_fpga (void) { - DECLARE_GLOBAL_DATA_PTR; - int i; PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index b7a1b56..eb73221 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -30,6 +30,8 @@ #include "fpga.h" #include "ioport.h" +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_STATUS_LED #include <status_led.h> #endif @@ -126,8 +128,6 @@ const uint selectmap_upm_table[] = { */ int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char *s; char buf[64]; int i; @@ -305,5 +305,3 @@ int post_hotkeys_pressed (void) return 0; /* No hotkeys supported */ } #endif - -/* vim: set ts=4 sw=4 tw=78 : */ diff --git a/board/gth2/Makefile b/board/gth2/Makefile new file mode 100644 index 0000000..8ef3a51 --- /dev/null +++ b/board/gth2/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ee_access.o +SOBJS = lowlevel_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/gth2/config.mk b/board/gth2/config.mk new file mode 100644 index 0000000..6d21ba1 --- /dev/null +++ b/board/gth2/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2004-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMD Alchemy AU1000, MIPS32 core +# + +ifeq ($(TBASE),0) +TEXT_BASE = 0 +else +ifeq ($(TBASE),1) +TEXT_BASE = 0xbfc10070 +else +ifeq ($(TBASE),2) +TEXT_BASE = 0xbfc30070 +else +## Only to make ordinary make work +TEXT_BASE = 0x90000000 +endif +endif +endif + diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c new file mode 100644 index 0000000..e293139 --- /dev/null +++ b/board/gth2/ee_access.c @@ -0,0 +1,347 @@ +/* Module for handling DALLAS DS2438, smart battery monitor + Chip can store up to 40 bytes of user data in EEPROM, + perform temp, voltage and current measurements. + Chip also contains a unique serial number. + + Always read/write LSb first + + For documentaion, see data sheet for DS2438, 2438.pdf + + By Thomas.Lange@corelatus.com 001025 + + Copyright (C) 2000-2005 Corelatus AB */ + +/* This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/au1x00.h> +#include <asm/io.h> +#include "ee_dev.h" +#include "ee_access.h" + +/* static int Debug = 1; */ +#undef E_DEBUG +#define E_DEBUG(fmt,args...) /* */ +/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */ + +/* We dont have kernel functions */ +#define printk printf +#define KERN_DEBUG +#define KERN_ERR +#define EIO 1 + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */ + +static u8 crc_lookup[256] = { + 0, 94, 188, 226, 97, 63, 221, 131, + 194, 156, 126, 32, 163, 253, 31, 65, + 157, 195, 33, 127, 252, 162, 64, 30, + 95, 1, 227, 189, 62, 96, 130, 220, + 35, 125, 159, 193, 66, 28, 254, 160, + 225, 191, 93, 3, 128, 222, 60, 98, + 190, 224, 2, 92, 223, 129, 99, 61, + 124, 34, 192, 158, 29, 67, 161, 255, + 70, 24, 250, 164, 39, 121, 155, 197, + 132, 218, 56, 102, 229, 187, 89, 7, + 219, 133, 103, 57, 186, 228, 6, 88, + 25, 71, 165, 251, 120, 38, 196, 154, + 101, 59, 217, 135, 4, 90, 184, 230, + 167, 249, 27, 69, 198, 152, 122, 36, + 248, 166, 68, 26, 153, 199, 37, 123, + 58, 100, 134, 216, 91, 5, 231, 185, + 140, 210, 48, 110, 237, 179, 81, 15, + 78, 16, 242, 172, 47, 113, 147, 205, + 17, 79, 173, 243, 112, 46, 204, 146, + 211, 141, 111, 49, 178, 236, 14, 80, + 175, 241, 19, 77, 206, 144, 114, 44, + 109, 51, 209, 143, 12, 82, 176, 238, + 50, 108, 142, 208, 83, 13, 239, 177, + 240, 174, 76, 18, 145, 207, 45, 115, + 202, 148, 118, 40, 171, 245, 23, 73, + 8, 86, 180, 234, 105, 55, 213, 139, + 87, 9, 235, 181, 54, 104, 138, 212, + 149, 203, 41, 119, 244, 170, 72, 22, + 233, 183, 85, 11, 136, 214, 52, 106, + 43, 117, 151, 201, 74, 20, 246, 168, + 116, 42, 200, 150, 21, 75, 169, 247, + 182, 232, 10, 84, 215, 137, 107, 53 +}; + +static void +write_gpio_data(int value ){ + if(value){ + /* Tristate */ + gpio_tristate(GPIO_EEDQ); + } + else{ + /* Drive 0 */ + gpio_clear(GPIO_EEDQ); + } +} + +static u8 make_new_crc( u8 Old_crc, u8 New_value ){ + /* Compute a new checksum with new byte, using previous checksum as input + See DS app note 17, understanding and using cyclic redundancy checks... + Also see DS2438, page 11 */ + return( crc_lookup[Old_crc ^ New_value ]); +} + +int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ + /* Check if the checksum for this buffer is correct */ + u8 Curr_crc=0; + int i; + u8 *Curr_byte = Buffer; + + for(i=0;i<Len;i++){ + Curr_crc = make_new_crc( Curr_crc, *Curr_byte); + Curr_byte++; + } + E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); + + if(Curr_crc == Crc){ + /* Good */ + return(TRUE); + } + printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); + return(FALSE); +} + +static void +set_idle(void){ + /* Send idle and keep start time + Continous 1 is idle */ + WRITE_PORT(1); +} + + +static int +do_cpu_reset(void){ + /* Release reset and verify that chip responds with presence pulse */ + int Retries=0; + while(Retries<15){ + udelay(RESET_LOW_TIME); + + /* Send reset */ + WRITE_PORT(0); + udelay(RESET_LOW_TIME); + + /* Release reset */ + WRITE_PORT(1); + + /* Wait for EEPROM to drive output */ + udelay(PRESENCE_TIMEOUT); + if(!READ_PORT){ + /* Ok, EEPROM is driving a 0 */ + E_DEBUG("Presence detected\n"); + if(Retries){ + E_DEBUG("Retries %d\n",Retries); + } + /* Make sure chip releases pin */ + udelay(PRESENCE_LOW_TIME); + return 0; + } + Retries++; + } + + printk(KERN_ERR"eeprom did not respond when releasing reset\n"); + + /* Make sure chip releases pin */ + udelay(PRESENCE_LOW_TIME); + + /* Set to idle again */ + set_idle(); + + return(-EIO); +} + +static u8 +read_cpu_byte(void){ + /* Read a single byte from EEPROM + Read LSb first */ + int i; + int Value; + u8 Result=0; + u32 Flags; + + E_DEBUG("Reading byte\n"); + + for(i=0;i<8;i++){ + /* Small delay between pulses */ + udelay(1); + +#ifdef __KERNEL__ + /* Disable irq */ + save_flags(Flags); + cli(); +#endif + + /* Pull down pin short time to start read + See page 26 in data sheet */ + + WRITE_PORT(0); + udelay(READ_LOW); + WRITE_PORT(1); + + /* Wait for chip to drive pin */ + udelay(READ_TIMEOUT); + + Value = READ_PORT; + if(Value) + Value=1; + +#ifdef __KERNEL__ + /* Enable irq */ + restore_flags(Flags); +#endif + + /* Wait for chip to release pin */ + udelay(TOTAL_READ_LOW-READ_TIMEOUT); + + /* LSb first */ + Result|=Value<<i; + /* E_DEBUG("Read %d\n",Value); */ + + } + + E_DEBUG("Read byte 0x%x\n",Result); + + return(Result); +} + +static void +write_cpu_byte(u8 Byte){ + /* Write a single byte to EEPROM + Write LSb first */ + int i; + int Value; + u32 Flags; + + E_DEBUG("Writing byte 0x%x\n",Byte); + + for(i=0;i<8;i++){ + /* Small delay between pulses */ + udelay(1); + Value = Byte&1; + +#ifdef __KERNEL__ + /* Disable irq */ + save_flags(Flags); + cli(); +#endif + + /* Pull down pin short time for a 1, long time for a 0 + See page 26 in data sheet */ + + WRITE_PORT(0); + if(Value){ + /* Write a 1 */ + udelay(WRITE_1_LOW); + } + else{ + /* Write a 0 */ + udelay(WRITE_0_LOW); + } + + WRITE_PORT(1); + +#ifdef __KERNEL__ + /* Enable irq */ + restore_flags(Flags); +#endif + + if(Value) + /* Wait for chip to read the 1 */ + udelay(TOTAL_WRITE_LOW-WRITE_1_LOW); + + /* E_DEBUG("Wrote %d\n",Value); */ + Byte>>=1; + } +} + +int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ + /* Execute this command string, including + giving reset and setting to idle after command + if Rx_len is set, we read out data from EEPROM */ + int i; + + E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); + + if(do_cpu_reset()){ + /* Failed! */ + return(-EIO); + } + + if(Send_skip) + /* Always send SKIP_ROM first to tell chip we are sending a command, + except when we read out rom data for chip */ + write_cpu_byte(SKIP_ROM); + + /* Always have Tx data */ + for(i=0;i<Tx_len;i++){ + write_cpu_byte(Tx[i]); + } + + if(Rx_len){ + for(i=0;i<Rx_len;i++){ + Rx[i]=read_cpu_byte(); + } + } + + set_idle(); + + E_DEBUG("Command done\n"); + + return(0); +} + +int ee_init_cpu_data(void){ + int i; + u8 Tx[10]; + + /* Leave it floting since altera is driving the same pin */ + set_idle(); + + /* Copy all User EEPROM data to scratchpad */ + for(i=0;i<USER_PAGES;i++){ + Tx[0]=RECALL_MEMORY; + Tx[1]=EE_USER_PAGE_0+i; + if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); + } + + /* Make sure chip doesnt store measurements in NVRAM */ + Tx[0]=WRITE_SCRATCHPAD; + Tx[1]=0; /* Page */ + Tx[2]=9; + if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO); + + Tx[0]=COPY_SCRATCHPAD; + if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); + + for(i=0;i<10;i++){ + udelay(1000); + } + + return(0); +} diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h new file mode 100644 index 0000000..c21730e --- /dev/null +++ b/board/gth2/ee_access.h @@ -0,0 +1,30 @@ +/* By Thomas.Lange@Corelatus.com 001025 */ + +/* Definitions for EEPROM/VOLT METER DS2438 */ +/* Copyright (C) 2000-2005 Corelatus AB */ + +#ifndef INCeeaccessh +#define INCeeaccessh + +#include <asm/types.h> +#include "ee_dev.h" + +int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ); +int ee_init_cpu_data(void); + +int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ); + +/* Defs for altera reg */ +#define EE_WRITE_SHIFT 8 /* bits to shift left */ +#define EE_READ_SHIFT 16 /* bits to shift left */ +#define EE_DONE 0x80000000 +#define EE_BUSY 0x40000000 +#define EE_ERROR 0x20000000 + +/* Commands */ +#define EE_CMD_NOP 0 +#define EE_CMD_INIT_RES 1 +#define EE_CMD_WR_BYTE 2 +#define EE_CMD_RD_BYTE 3 + +#endif /* INCeeaccessh */ diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h new file mode 100644 index 0000000..acc3418 --- /dev/null +++ b/board/gth2/ee_dev.h @@ -0,0 +1,96 @@ +/* By Thomas.Lange@Corelatus.com 001025 */ +/* Definitions for EEPROM/VOLT METER DS2438 */ +/* Copyright (C) 2000-2005 Corelatus AB */ + +/* This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef INCeedevh +#define INCeedevh + +#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) + +/* MIPS */ +#define WRITE_PORT(Value) write_gpio_data(Value) + +#define READ_PORT (gpio_read()&GPIO_EEDQ) + +/* 64 bytes chip */ +#define EE_CHIP_SIZE 64 + +/* Board with new current resistor */ +#define EE_GTH_0304 1 + +/* new dsp and 64 MB SDRAM */ +#define EE_DSP_64 0x10 + +/* microsecs */ +/* Pull line down at least this long for reset pulse */ +#define RESET_LOW_TIME 490 + +/* Read presence pulse after we release reset pulse */ +#define PRESENCE_TIMEOUT 100 +#define PRESENCE_LOW_TIME 200 + +#define WRITE_0_LOW 60 +#define WRITE_1_LOW 1 +#define TOTAL_WRITE_LOW 60 + +#define READ_LOW 1 +#define READ_TIMEOUT 10 +#define TOTAL_READ_LOW 70 + +/* Rom function commands */ +#define READ_ROM 0x33 +#define MATCH_ROM 0x55 +#define SKIP_ROM 0xCC +#define SEARCH_ROM 0xF0 + + +/* Memory_command_function */ +#define WRITE_SCRATCHPAD 0x4E +#define READ_SCRATCHPAD 0xBE +#define COPY_SCRATCHPAD 0x48 +#define RECALL_MEMORY 0xB8 +#define CONVERT_TEMP 0x44 +#define CONVERT_VOLTAGE 0xB4 + +/* Chip is divided in 8 pages, 8 bytes each */ + +#define EE_PAGE_SIZE 8 + +/* All chip data we want are in page 0 */ + +/* Bytes in page 0 */ +#define EE_P0_STATUS 0 +#define EE_P0_TEMP_LSB 1 +#define EE_P0_TEMP_MSB 2 +#define EE_P0_VOLT_LSB 3 +#define EE_P0_VOLT_MSB 4 +#define EE_P0_CURRENT_LSB 5 +#define EE_P0_CURRENT_MSB 6 + + +/* 40 byte user data is located at page 3-7 */ +#define EE_USER_PAGE_0 3 +#define USER_PAGES 5 + +/* Layout of gth user pages usage */ +/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */ + +#define EE_ETHERNET_OFFSET 0 + +#endif /* INCeedevh */ diff --git a/board/gth2/flash.c b/board/gth2/flash.c new file mode 100644 index 0000000..f96edff --- /dev/null +++ b/board/gth2/flash.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + printf ("Skipping flash_init\n"); + return (0); +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + printf ("write_buff not implemented\n"); + return (-1); +} diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c new file mode 100644 index 0000000..77fc5b4 --- /dev/null +++ b/board/gth2/gth2.c @@ -0,0 +1,435 @@ +/* + * (C) Copyright 2005 + * Thomas.Lange@corelatus.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/au1x00.h> +#include <asm/addrspace.h> +#include <asm/mipsregs.h> +#include <watchdog.h> + +#include "ee_access.h" + +static int wdi_status = 0; + +unsigned long mips_io_port_base = 0; + +#define SDRAM_SIZE ((64*1024*1024)-(12*4096)) + + +#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) + +void inline log_serial_char(char c){ + char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; + int serial_log_offset; + u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; + + serial_log_offset = *serial_log_offsetp; + + *(serial_log_buffer + serial_log_offset) = c; + + serial_log_offset++; + + if(serial_log_offset >= 4096){ + serial_log_offset = 4; + } + *serial_log_offsetp = serial_log_offset; +} + +void init_log_serial(void){ + char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; + u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; + + /* Copy buffer from last run */ + memcpy(serial_log_buffer + 4096, + serial_log_buffer, + 4096); + + memset(serial_log_buffer, 0, 4096); + + *serial_log_offsetp = 4; +} + + +void hw_watchdog_reset(void){ + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; + volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR; + if(wdi_status){ + *sys_outputset = GPIO_CPU_LED|GPIO_WDI; + wdi_status = 0; + } + else{ + *sys_outputclear = GPIO_CPU_LED|GPIO_WDI; + wdi_status = 1; + } +} + +long int initdram(int board_type) +{ + /* Sdram is setup by assembler code */ + /* If memory could be changed, we should return the true value here */ + + WATCHDOG_RESET(); + + return (SDRAM_SIZE); +} + +/* In cpu/mips/cpu.c */ +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); + +void set_ledcard(u32 value){ + /* Clock 24 bits to led card */ + int i; + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; + volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; + + /* Start with known values */ + *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD; + + for(i=0;i<24;i++){ + if(value&0x00800000){ + *sys_outputset = GPIO_LEDD; + } + else{ + *sys_outputclr = GPIO_LEDD; + } + udelay(1); + *sys_outputset = GPIO_LEDCLK; + udelay(1); + *sys_outputclr = GPIO_LEDCLK; + udelay(1); + + value<<=1; + } + /* Data is enable output */ + *sys_outputset = GPIO_LEDD; +} + +int checkboard (void) +{ + volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; + volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; + u32 proc_id; + + WATCHDOG_RESET(); + + *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ + + proc_id = read_32bit_cp0_register(CP0_PRID); + + switch (proc_id >> 24) { + case 0: + puts ("Board: GTH2\n"); + printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + default: + printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); + } +#ifdef CONFIG_IDE_PCMCIA + /* PCMCIA is on a 36 bit physical address. + We need to map it into a 32 bit addresses */ + write_one_tlb(20, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_IO_BASE, /* Hi */ + 0x3C000017, /* Lo0 */ + 0x3C200017); /* Lo1 */ + + write_one_tlb(21, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_ATTR_BASE, /* Hi */ + 0x3D000017, /* Lo0 */ + 0x3D200017); /* Lo1 */ + + write_one_tlb(22, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_MEM_ADDR, /* Hi */ + 0x3E000017, /* Lo0 */ + 0x3E200017); /* Lo1 */ + +#endif /* CONFIG_IDE_PCMCIA */ + + /* Wait for GPIO ports to become stable */ + udelay(5000); /* FIXME */ + + /* Release reset of ethernet PHY chips */ + /* Always do this, because linux does not know about it */ + *sys_outputset = GPIO_ERESET; + + /* Kill FPGA:s */ + *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG; + udelay(2); + *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG; + + /* Turn front led yellow */ + set_ledcard(0x00100000); + + return 0; +} + +#define POWER_OFFSET 0xF0000 +#define SW_WATCHDOG_REASON 13 + +#define BOOTDATA_OFFSET 0xF8000 +#define MAX_ATTEMPTS 5 + +#define FAILSAFE_BOOT 1 +#define SYSTEM_BOOT 2 +#define SYSTEM2_BOOT 3 + +#define WRITE_FLASH16(a, d) \ +do \ +{ \ + *((volatile u16 *) (a)) = (d);\ + } while(0) + +static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) +{ + u16 data; + volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + + switch(System){ + case FAILSAFE_BOOT: + printf ("Setting failsafe boot in flash\n"); + break; + case SYSTEM_BOOT: + printf ("Setting system boot in flash\n"); + break; + case SYSTEM2_BOOT: + printf ("Setting system2 boot in flash\n"); + break; + default: + printf ("Invalid system data %u, setting failsafe\n", System); + System = FAILSAFE_BOOT; + } + + if ((Count < 1) | (Count > MAX_ATTEMPTS)) { + printf ("Invalid boot count %u, setting 1\n", Count); + Count = 1; + } + + printf ("Boot attempt %d\n", Count); + + data = (System << 8) | Count; + /* AMD 16 bit */ + WRITE_FLASH16 (&flash[0x555], 0xAAAA); + WRITE_FLASH16 (&flash[0x2AA], 0x5555); + WRITE_FLASH16 (&flash[0x555], 0xA0A0); + + WRITE_FLASH16 (addr, data); +} + +static int random_system(void){ + /* EEPROM read failed. Just try to choose one + system release and hope it works */ + + /* FIXME */ + return(SYSTEM_BOOT); +} + +static int switch_system(int old_system){ + u8 Rx[10]; + u8 Tx[5]; + int valid_release; + + if(old_system==FAILSAFE_BOOT){ + /* Find out which system release to use */ + + /* Copy from nvram to scratchpad */ + Tx[0] = RECALL_MEMORY; + Tx[1] = 7; /* Page */ + if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { + printf ("EE user page 7 recall failed\n"); + return (random_system()); + } + + Tx[0] = READ_SCRATCHPAD; + if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) { + printf ("EE user page 7 read failed\n"); + return (random_system()); + } + /* Crc in 9:th byte */ + if (!ee_crc_ok (Rx, 8, *(Rx + 8))) { + printf ("EE read failed, page 7. CRC error\n"); + return (random_system()); + } + + valid_release = Rx[7]; + if((valid_release==0xFF)| + ((valid_release&1) == 0)){ + return(SYSTEM_BOOT); + } + else{ + return(SYSTEM2_BOOT); + } + } + else{ + return(FAILSAFE_BOOT); + } +} + +static void check_boot_tries (void) +{ + /* Count the number of boot attemps + switch system if too many */ + + int i; + volatile u16 *addr; + volatile u16 data; + u8 system = FAILSAFE_BOOT; + u8 count; + + addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); + + if (*addr == 0xFFFF) { + printf ("*** No bootdata exists. ***\n"); + write_bootdata (addr, FAILSAFE_BOOT, 1); + } else { + /* Search for latest written bootdata */ + i = 0; + while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { + addr++; + i++; + } + if (i >= 8000) { + /* Whoa, dont write any more */ + printf ("*** No bootdata found. Not updating flash***\n"); + } else { + /* See how many times we have tried to boot real system */ + data = *addr; + system = data >> 8; + count = data & 0xFF; + if ((system != SYSTEM_BOOT) & + (system != SYSTEM2_BOOT) & + (system != FAILSAFE_BOOT)) { + printf ("*** Wrong system %d\n", system); + system = FAILSAFE_BOOT; + count = 1; + } else { + switch (count) { + case 0: + case 1: + case 2: + case 3: + case 4: + /* Try same system again if needed */ + count++; + break; + + case 5: + /* Switch system and reset tries */ + count = 1; + system = switch_system(system); + printf ("***Too many boot attempts, switching system***\n"); + break; + default: + /* Switch system, start over and hope it works */ + printf ("***Unexpected data on addr 0x%x, %u***\n", + (u32) addr, data); + count = 1; + system = switch_system(system); + } + } + write_bootdata (addr + 1, system, count); + } + } + switch(system){ + case FAILSAFE_BOOT: + printf ("Booting failsafe system\n"); + setenv ("bootargs", "panic=1 root=/dev/hda7"); + setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm"); + break; + + case SYSTEM_BOOT: + printf ("Using normal system\n"); + setenv ("bootargs", "panic=1 root=/dev/hda4"); + setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm"); + break; + + case SYSTEM2_BOOT: + printf ("Using normal system2\n"); + setenv ("bootargs", "panic=1 root=/dev/hda9"); + setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm"); + break; + default: + printf ("Invalid system %d\n", system); + printf ("Hanging\n"); + while(1); + } +} + +int misc_init_r(void){ + u8 Rx[80]; + u8 Tx[5]; + int page; + int read = 0; + + WATCHDOG_RESET(); + + if (ee_init_cpu_data ()) { + printf ("EEPROM init failed\n"); + return (0); + } + + /* Check which release to boot */ + check_boot_tries (); + + /* Read the pages where ethernet address is stored */ + + for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { + /* Copy from nvram to scratchpad */ + Tx[0] = RECALL_MEMORY; + Tx[1] = page; + if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { + printf ("EE user page %d recall failed\n", page); + return (0); + } + + Tx[0] = READ_SCRATCHPAD; + if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) { + printf ("EE user page %d read failed\n", page); + return (0); + } + /* Crc in 9:th byte */ + if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { + printf ("EE read failed, page %d. CRC error\n", page); + return (0); + } + read += 8; + } + + /* Add eos after eth addr */ + Rx[17] = 0; + + printf ("Ethernet addr read from eeprom: %s\n\n", Rx); + + if ((Rx[2] != ':') | + (Rx[5] != ':') | + (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { + printf ("*** ethernet addr invalid, using default ***\n"); + } else { + setenv ("ethaddr", Rx); + } + return (0); +} diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S new file mode 100644 index 0000000..62e3657 --- /dev/null +++ b/board/gth2/lowlevel_init.S @@ -0,0 +1,454 @@ +/* Memory sub-system initialization code */ + +#include <config.h> +#include <version.h> +#include <asm/regdef.h> +#include <asm/au1x00.h> +#include <asm/mipsregs.h> + +#define CP0_Config0 $16 +#define MEM_1MS ((CFG_MHZ) * 1000) +#define GPIO_RJ1LY (1<<22) +#define GPIO_CFRESET (1<<10) + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set OD, set K0=3) + */ + li t1, 0x00080003 + mtc0 t1, CP0_CONFIG + + /* + * Step 4) Disable Watchpoint facilities + */ + li t1, 0x00000000 + mtc0 t1, CP0_WATCHLO + mtc0 t1, CP0_IWATCHLO + /* + * Step 5) Disable the performance counters + */ + mtc0 zero, CP0_PERFORMANCE + nop + + /* + * Step 6) Establish EJTAG Debug register + */ + mtc0 zero, CP0_DEBUG + nop + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + /* No workaround if running from ram */ + lui t0, 0xffc0 + lui t3, 0xbfc0 + and t1, ra, t0 + bne t1, t3, noCacheJump + nop + + /*** From AMD YAMON ***/ + /* + * Step 8) Initialize the caches + */ + li t0, (16*1024) + li t1, 32 + li t2, 0x80000000 + addu t3, t0, t2 +cacheloop: + cache 0, 0(t2) + cache 1, 0(t2) + addu t2, t1 + bne t2, t3, cacheloop + nop + + /* Save return address */ + move t3, ra + + /* Run from cacheable space now */ + bal cachehere + nop +cachehere: + li t1, ~0x20000000 /* convert to KSEG0 */ + and t0, ra, t1 + addi t0, 5*4 /* 5 insns beyond cachehere */ + jr t0 + nop + + /* Restore return address */ + move ra, t3 + + /* + * Step 9) Initialize the TLB + */ + li t0, 0 # index value + li t1, 0x00000000 # entryhi value + li t2, 32 # 32 entries + +tlbloop: + /* Probe TLB for matching EntryHi */ + mtc0 t1, CP0_ENTRYHI + tlbp + nop + + /* Examine Index[P], 1=no matching entry */ + mfc0 t3, CP0_INDEX + li t4, 0x80000000 + and t3, t4, t3 + addiu t1, t1, 1 # increment t1 (asid) + beq zero, t3, tlbloop + nop + + /* Initialize the TLB entry */ + mtc0 t0, CP0_INDEX + mtc0 zero, CP0_ENTRYLO0 + mtc0 zero, CP0_ENTRYLO1 + mtc0 zero, CP0_PAGEMASK + tlbwi + + /* Do it again */ + addiu t0, t0, 1 + bne t0, t2, tlbloop + nop + + /* First setup pll:s to make serial work ok */ + /* We have a 12.5 MHz crystal */ + li t0, SYS_CPUPLL + li t1, 0x28 /* CPU clock, 500 MHz */ + sw t1, 0(t0) + sync + nop + nop + + /* wait 1mS for clocks to settle */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + /* Setup AUX PLL */ + li t0, SYS_AUXPLL + li t1, 0 + sw t1, 0(t0) /* aux pll */ + sync + + /* Static memory controller */ + /* RCE0 - can not change while fetching, do so from icache */ + move t2, ra /* Store return address */ + bal getAddr + nop + +getAddr: + move t1, ra + move ra, t2 /* Move return addess back */ + + cache 0x14,0(t1) + cache 0x14,32(t1) + /*** /From YAMON ***/ + +noCacheJump: + + /* Static memory controller */ + + /* RCE0 AMD 29LV800 Flash */ + li t0, MEM_STCFG0 + li t1, 0x00000243 + sw t1, 0(t0) + + li t0, MEM_STTIME0 + li t1, 0x040181D7 /* FIXME */ + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11E03F80 + sw t1, 0(t0) + + /* RCE1 PCMCIA 250ns */ + li t0, MEM_STCFG1 + li t1, 0x00000002 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x280E3E07 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x10000000 + sw t1, 0(t0) + + /* RCE2 CP Altera */ + li t0, MEM_STCFG2 + li t1, 0x00000280 /* BE, EW */ + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x0303000c + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x10c03f80 /* 1 MB */ + sw t1, 0(t0) + + /* RCE3 DP Altera */ + li t0, MEM_STCFG3 + li t1, 0x00000280 /* BE, EW */ + sw t1, 0(t0) + + li t0, MEM_STTIME3 + li t1, 0x0303000c + sw t1, 0(t0) + + li t0, MEM_STADDR3 + li t1, 0x10e03f80 /* 1 MB */ + sw t1, 0(t0) + + sync + + /* Set peripherals to a known state */ + li t0, IC0_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC0_CFG0CLR + sw t1, 0(t0) + + li t0, IC0_CFG1CLR + sw t1, 0(t0) + + li t0, IC0_CFG2CLR + sw t1, 0(t0) + + li t0, IC0_SRCSET + sw t1, 0(t0) + + li t0, IC0_ASSIGNSET + sw t1, 0(t0) + + li t0, IC0_WAKECLR + sw t1, 0(t0) + + li t0, IC0_RISINGCLR + sw t1, 0(t0) + + li t0, IC0_FALLINGCLR + sw t1, 0(t0) + + li t0, IC0_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, IC1_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC1_CFG0CLR + sw t1, 0(t0) + + li t0, IC1_CFG1CLR + sw t1, 0(t0) + + li t0, IC1_CFG2CLR + sw t1, 0(t0) + + li t0, IC1_SRCSET + sw t1, 0(t0) + + li t0, IC1_ASSIGNSET + sw t1, 0(t0) + + li t0, IC1_WAKECLR + sw t1, 0(t0) + + li t0, IC1_RISINGCLR + sw t1, 0(t0) + + li t0, IC1_FALLINGCLR + sw t1, 0(t0) + + li t0, IC1_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, SYS_FREQCTRL0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_FREQCTRL1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_CLKSRC + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_PININPUTEN + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, 0xB1100100 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, 0xB1400100 + li t1, 0x00000000 + sw t1, 0(t0) + + + li t0, SYS_WAKEMSK + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_WAKESRC + li t1, 0x00000000 + sw t1, 0(t0) + + /* wait 1mS before setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + +/* SDCS 0 SDRAM */ + li t0, MEM_SDMODE0 + li t1, 0x592CD1 + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x00000000 + sw t1, 0(t0) + +/* 64 MB SDRAM at addr 0 */ + li t0, MEM_SDADDR0 + li t1, 0x001003F0 + sw t1, 0(t0) + + + li t0, MEM_SDADDR1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0x00000000 + sw t1, 0(t0) + + sync + + li t0, MEM_SDREFCFG + li t1, 0x880007A1 /* Disable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + sw zero, 0(t0) + sync + + li t0, MEM_SDREFCFG + li t1, 0x8A0007A1 /* Enable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + /* wait 1mS after setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + /* Setup GPIO pins */ + + li t0, SYS_PINFUNC + li t1, 0x00007025 /* 0x8080 */ + sw t1, 0(t0) + + li t0, SYS_TRIOUTCLR + li t1, 0xFFFFFFFF /* 0x1FFF */ + sw t1, 0(t0) + + /* Turn yellow front led on */ + /* Release reset on CF */ + li t0, SYS_OUTPUTCLR + li t1, GPIO_RJ1LG + sw t1, 0(t0) + li t0, SYS_OUTPUTSET + li t1, GPIO_RJ1LY|GPIO_CFRESET + sw t1, 0(t0) + sync + j clearmem + nop + + .globl memtest +memtest: + /* Fill memory with address */ + li t0, 0x80000000 + li t1, 0xFFF000 /* 64 MB */ +mt0: sw t0, 0(t0) + add t1, -1 + add t0, 4 + bne t1, zero, mt0 + nop + nop + /* Verify addr */ + li t0, 0x80000000 + li t1, 0xFFF000 /* 64 MB */ +mt1: lw t2, 0(t0) + bne t0, t2, memhang + add t1, -1 + add t0, 4 + bne t1, zero, mt1 + nop + nop + .globl clearmem +clearmem: + /* Clear memory */ + li t0, 0x80000000 + li t1, 0xFFF000 /* 64 MB */ +mtc: sw zero, 0(t0) + add t1, -1 + add t0, 4 + bne t1, zero, mtc + nop + nop +memtestend: + j ra + nop + +memhang: + b memhang + nop diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds new file mode 100644 index 0000000..8ba0b6d --- /dev/null +++ b/board/gth2/u-boot.lds @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk Engineering, <wd@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c index e95d9ee..a523db1 100644 --- a/board/hermes/hermes.c +++ b/board/hermes/hermes.c @@ -32,6 +32,8 @@ # define SHOW_BOOT_PROGRESS(arg) #endif +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ static long int dram_size (long int, long int *, long int); @@ -105,8 +107,6 @@ const uint sdram_table[] = { int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char *s = getenv ("serial#"); char *e; diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 0596fa4..6868f26 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -28,6 +28,8 @@ #include <net.h> #include <asm/iopin_8260.h> +DECLARE_GLOBAL_DATA_PTR; + /*----------------------------------------------------------------------- * Board Special Commands: FPGA load/store, EEPROM erase */ @@ -75,8 +77,6 @@ int fpga_load (int mezz, uchar *addr, ulong size) { - DECLARE_GLOBAL_DATA_PTR; - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; xlx_info_t *fp; xlx_iopins_t *fpgaio; diff --git a/board/hymod/env.c b/board/hymod/env.c index f9e1421..062553b 100644 --- a/board/hymod/env.c +++ b/board/hymod/env.c @@ -23,6 +23,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* imports from fetch.c */ extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); @@ -32,8 +34,6 @@ static char *def_global_env_path = "/hymod/global_env"; static int env_callback (uchar *name, uchar *value) { - DECLARE_GLOBAL_DATA_PTR; - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver; int override = 1, append = 0, remove = 0, nnl, ovl, nvl; diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index dea0a70..5e98e9e 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -30,6 +30,8 @@ #include <i2c.h> #include <asm/iopin_8260.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* imports from eeprom.c */ @@ -424,8 +426,6 @@ initdram (int board_type) int last_stage_init (void) { - DECLARE_GLOBAL_DATA_PTR; - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; int rc; diff --git a/board/icecube/flash.c b/board/icecube/flash.c index 713011c..15e86d3 100644 --- a/board/icecube/flash.c +++ b/board/icecube/flash.c @@ -23,6 +23,7 @@ #include <common.h> +#ifndef CFG_FLASH_CFI_DRIVER flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it @@ -489,3 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) return (res); } +#endif /*CFG_FLASH_CFI_DRIVER*/ diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 1f1a74c..4f056b2 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -27,13 +27,17 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" +#if defined(CONFIG_LITE5200B) +#include "mt46v32m16.h" #else +# if defined(CONFIG_MPC5200_DDR) +# include "mt46v16m16-75.h" +# else #include "mt48lc16m16a2-75.h" +# endif #endif - #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -86,6 +90,8 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; + #ifndef CFG_RAMBOOT ulong test1, test2; @@ -180,6 +186,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } @@ -236,7 +260,9 @@ long int initdram (int board_type) int checkboard (void) { -#if defined(CONFIG_MPC5200) +#if defined (CONFIG_LITE5200B) + puts ("Board: Freescale Lite5200B\n"); +#elif defined(CONFIG_MPC5200) puts ("Board: Motorola MPC5200 (IceCube)\n"); #elif defined(CONFIG_MGT5100) puts ("Board: Motorola MGT5100 (IceCube)\n"); diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h new file mode 100644 index 0000000..de2b48b --- /dev/null +++ b/board/icecube/mt46v32m16.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 081ef65..7b9a83d 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -25,6 +25,8 @@ #include <ioports.h> #include <mpc8260.h> +DECLARE_GLOBAL_DATA_PTR; + /* * I/O Port configuration table * @@ -295,8 +297,6 @@ long int initdram (int board_type) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_flashstart = 0xff800000; } diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c index e496923..3230dd4 100644 --- a/board/impa7/impa7.c +++ b/board/impa7/impa7.c @@ -25,6 +25,8 @@ #include <common.h> #include <clps7111.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ @@ -34,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -50,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index ae5402e..7f8f47c 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -27,6 +27,8 @@ #include <asm/arch/pxa-regs.h> #include <asm/mach-types.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_SHOW_BOOT_PROGRESS # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) #else @@ -95,8 +97,6 @@ int misc_init_r(void) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -116,8 +116,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c index d4f61d6..e659907 100644 --- a/board/integratorap/integratorap.c +++ b/board/integratorap/integratorap.c @@ -39,6 +39,8 @@ #include <pci.h> #endif +DECLARE_GLOBAL_DATA_PTR; + void flash__init (void); void ether__init (void); void peripheral_power_enable (void); @@ -65,8 +67,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of Integrator Board */ gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; @@ -480,8 +480,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c index 216876b..d6d6e13 100644 --- a/board/integratorcp/integratorcp.c +++ b/board/integratorcp/integratorcp.c @@ -35,6 +35,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + void flash__init (void); void ether__init (void); void peripheral_power_enable (void); @@ -54,8 +56,6 @@ void show_boot_progress(int progress) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of Integrator Board */ gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; @@ -105,8 +105,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile index e4282c4..59d6964 100644 --- a/board/ixdp425/Makefile +++ b/board/ixdp425/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := ixdp425.o flash.o +OBJS := ixdp425.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk index 9f616f3..3420586 100644 --- a/board/ixdp425/config.mk +++ b/board/ixdp425/config.mk @@ -1,2 +1,4 @@ -#TEXT_BASE = 0x00100000 TEXT_BASE = 0x00f80000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index c04626a..eaf7cde 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * (C) Copyright 2002 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net * @@ -25,55 +28,91 @@ * MA 02111-1307 USA */ -#include <asm/arch/ixp425.h> #include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations */ - -/**********************************************************/ - int board_post_init (void) { return (0); } -/**********************************************************/ - int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of IXDP */ gd->bd->bi_arch_number = MACH_TYPE_IXDP425; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; +#ifdef CONFIG_IXDPG425 + /* arch number of IXDP */ + gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; + + /* + * Get realtek RTL8305 switch and SLIC out of reset + */ + GPIO_OUTPUT_SET(CFG_GPIO_SWITCH_RESET_N); + GPIO_OUTPUT_ENABLE(CFG_GPIO_SWITCH_RESET_N); + GPIO_OUTPUT_SET(CFG_GPIO_SLIC_RESET_N); + GPIO_OUTPUT_ENABLE(CFG_GPIO_SLIC_RESET_N); + + /* + * Setup GPIO's for PCI INTA & INTB + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA_N); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA_N); + GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB_N); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB_N); + + /* + * Setup GPIO's for 33MHz clock output + */ + *IXP425_GPIO_GPCLKR = 0x01FF01FF; + GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); +#endif + return 0; } -/**********************************************************/ +/* + * Check Board Identity + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + +#ifdef CONFIG_IXDPG425 + puts("Board: IXDPG425 - Intel Network Gateway Reference Platform"); +#else + puts("Board: IXDP425 - Intel Development Platform"); +#endif + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; return (0); } -/**********************************************************/ - +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) extern struct pci_controller hose; extern void pci_ixp_init(struct pci_controller * hose); @@ -83,3 +122,4 @@ void pci_init_board(void) pci_ixp_init(&hose); } +#endif diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c index 4a7cf77..ec51dca 100644 --- a/board/kb9202/kb9202.c +++ b/board/kb9202/kb9202.c @@ -31,7 +31,8 @@ #include <at91rm9200_net.h> #include <lxt971a.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; + /* * Miscelaneous platform dependent initialisations */ @@ -42,8 +43,6 @@ void lowlevel_init(void) { int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Enable Ctrlc */ console_init_f (); @@ -60,8 +59,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index e621c43..4e377a1 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -29,6 +29,8 @@ #include "s1d13706.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #undef DEBUG #ifdef DEBUG # define debugk(fmt,args...) printf(fmt ,##args) @@ -44,10 +46,6 @@ typedef struct { /* ------------------------------------------------------------------------- */ -#if 0 -static long int dram_size (long int, long int *, long int); -#endif - #ifdef CONFIG_KUP4K_LOGO void lcd_logo(bd_t *bd); #endif @@ -235,62 +233,8 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -#if 0 -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} -#endif - int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_STATUS_LED volatile immap_t *immap = (immap_t *) CFG_IMMR; #endif diff --git a/board/lart/flash.c b/board/lart/flash.c index 5232ed2..28c4531 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -348,7 +348,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/lart/lart.c b/board/lart/lart.c index 66b730d..8d534c8 100644 --- a/board/lart/lart.c +++ b/board/lart/lart.c @@ -24,6 +24,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ @@ -33,8 +35,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -49,7 +49,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; bd->bi_dram[0].start = PHYS_SDRAM_1; diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index 95634ac..14fd28f 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -25,6 +25,8 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +DECLARE_GLOBAL_DATA_PTR; + /** * board_init: - setup some data structures * @@ -33,8 +35,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -57,8 +57,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index 2dfe376..d18720e 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -351,8 +351,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c index 4c373ee..e12bbf0 100644 --- a/board/lpd7a40x/lpd7a40x.c +++ b/board/lpd7a40x/lpd7a40x.c @@ -37,14 +37,14 @@ #include <lpd7a400_cpld.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Miscellaneous platform dependent initialisations */ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* set up the I/O ports */ /* enable flash programming */ @@ -74,8 +74,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index e618ab9..5829170 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -27,8 +27,7 @@ #include <common.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -36,8 +35,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -60,8 +57,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index a174b57..9e8ea2d 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -45,6 +45,8 @@ V* Verification: dzu@denx.de #include <linux/types.h> #include <linux/string.h> /* for strdup */ +DECLARE_GLOBAL_DATA_PTR; + /*------------------------ Local prototypes ---------------------------*/ static long int dram_size (long int, long int *, long int); static void kbd_init (void); @@ -455,8 +457,6 @@ Z* for the lwmon board. ***********************************************************************/ int board_postclk_init (void) { - DECLARE_GLOBAL_DATA_PTR; - kbd_init(); #ifdef CONFIG_MODEM_SUPPORT @@ -471,15 +471,11 @@ int board_postclk_init (void) struct serial_device * default_serial_console (void) { - DECLARE_GLOBAL_DATA_PTR; - return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device; } static void kbd_init (void) { - DECLARE_GLOBAL_DATA_PTR; - uchar kbd_data[KEYBD_DATALEN]; uchar tmp_data[KEYBD_DATALEN]; uchar val, errcd; @@ -571,8 +567,6 @@ V* Verification: dzu@denx.de ***********************************************************************/ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - uchar kbd_data[KEYBD_DATALEN]; char keybd_env[2 * KEYBD_DATALEN + 1]; uchar kbd_init_status = gd->kbd_status >> 8; diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile new file mode 100644 index 0000000..34de983 --- /dev/null +++ b/board/m5271evb/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/m5271evb/config.mk b/board/m5271evb/config.mk new file mode 100644 index 0000000..9a7af7c --- /dev/null +++ b/board/m5271evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c new file mode 100644 index 0000000..c26c91d --- /dev/null +++ b/board/m5271evb/m5271evb.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/m5271.h> +#include <asm/immap_5271.h> + +int checkboard (void) { + puts ("Board: Freescale M5271EVB\n"); + return 0; +}; + +long int initdram (int board_type) { + + int i; + + /* Enable Address lines 23-21 and lower 16bits of data path */ + mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | + MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | + MCF_GPIO_AD_DATAL); + + /* Set CS2 pin to be SD_CS0 */ + mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) + | MCF_GPIO_PAR_CS_PAR_CS2); + + /* Configure SDRAM Control Pin Assignemnt Register */ + mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | + MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | + MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | + MCF_GPIO_SDRAM_SDCS_11); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCF_SDRAMC_DCR, + MCF_SDRAMC_DCR_RTIM(0x01) + | MCF_SDRAMC_DCR_RC(0x30)); + + /* + * Initialize DACR0 + * + * CASL: 01 + * CBM: cmd at A20, bank select bits 21 and up + * PS: 32bit port size + */ + mbar_writeLong(MCF_SDRAMC_DACR0, + MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) + | MCF_SDRAMC_DACRn_CASL(1) + | MCF_SDRAMC_DACRn_CBM(3) + | MCF_SDRAMC_DACRn_PS(0)); + + /* Initialize DMR0 */ + mbar_writeLong(MCF_SDRAMC_DMR0, + MCF_SDRAMC_DMRn_BAM_16M + | MCF_SDRAMC_DMRn_V); + + /* Set IP bit in DACR */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_IP); + + /* Wait at least 20ns to allow banks to precharge */ + for (i = 0; i < 5; i++) + asm(" nop"); + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5; + + /* Set RE bit in DACR */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_RE); + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) + asm(" nop"); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_MRS); + + /* + * Write to the SDRAM Mode Register A0-A11 = 0x400 + * + * Write Burst Mode = Programmed Burst Length + * Op Mode = Standard Op + * CAS Latency = 2 + * Burst Type = Sequential + * Burst Length = 1 + */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + +int testdram (void) { + + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/m5271evb/u-boot.lds b/board/m5271evb/u-boot.lds new file mode 100644 index 0000000..69f3179 --- /dev/null +++ b/board/m5271evb/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +GROUP(libgcc.a) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c index fb91843..ea0b1fd 100644 --- a/board/m5272c3/flash.c +++ b/board/m5272c3/flash.c @@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info) printf ("\n"); Done: + return; } @@ -256,8 +257,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c index ff70783..36a7c31 100644 --- a/board/m5282evb/flash.c +++ b/board/m5282evb/flash.c @@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info) printf ("\n"); Done: + return; } @@ -256,8 +257,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile new file mode 100644 index 0000000..7fdc088 --- /dev/null +++ b/board/mcc200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk new file mode 100644 index 0000000..fa55673 --- /dev/null +++ b/board/mcc200/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MCC200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c new file mode 100644 index 0000000..b9b9a71 --- /dev/null +++ b/board/mcc200/mcc200.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +/* Two MT48LC8M32B2 for 32 MB */ +/* #include "mt48lc8m32b2-6-7.h" */ + +/* One MT48LC16M32S2 for 64 MB */ +#include "mt48lc16m32s2-75.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +ulong flash_get_size (ulong base, int banknum); + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); + + udelay(10); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard (void) +{ + puts ("Board: MCC200\n"); + return 0; +} + +int misc_init_r (void) +{ + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(gd->bd->bi_flashstart); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + if (gd->bd->bi_flashsize > (32 << 20)) { + /* Unprotect the upper bank of the Flash */ + *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[0].start[0] + flash_info[0].size / 2, + (flash_info[0].start[0] + flash_info[0].size) / 2 - 1, + &flash_info[0]); + *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); + } + + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/mcc200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m32s2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000..13aebbd --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds new file mode 100644 index 0000000..4fdea6b --- /dev/null +++ b/board/mcc200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ml2/serial.c b/board/ml2/serial.c index 92baba9..74687f1 100644 --- a/board/ml2/serial.c +++ b/board/ml2/serial.c @@ -29,70 +29,59 @@ #include <ns16550.h> #endif -#if 0 -#include "serial.h" -#endif +DECLARE_GLOBAL_DATA_PTR; #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, - (NS16550_t) CFG_NS16550_COM2 }; + (NS16550_t) CFG_NS16550_COM2 +}; #endif -int -serial_init (void) +int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 - (void)NS16550_init(COM_PORTS[0], clock_divisor); + (void) NS16550_init (COM_PORTS[0], clock_divisor); #endif #ifdef CFG_INIT_CHAN2 - (void)NS16550_init(COM_PORTS[1], clock_divisor); + (void) NS16550_init (COM_PORTS[1], clock_divisor); #endif - return 0; + return 0; } -void -serial_putc(const char c) +void serial_putc (const char c) { - if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + if (c == '\n') + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); } -int -serial_getc(void) +int serial_getc (void) { - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); } -int -serial_tstc(void) +int serial_tstc (void) { - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); } -void -serial_setbrg (void) +void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); + NS16550_reinit (COM_PORTS[0], clock_divisor); #endif #ifdef CFG_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); + NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } -void -serial_puts (const char *s) +void serial_puts (const char *s) { while (*s) { serial_putc (*s++); @@ -100,32 +89,27 @@ serial_puts (const char *s) } #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void -kgdb_serial_init(void) +void kgdb_serial_init (void) { } -void -putDebugChar (int c) +void putDebugChar (int c) { serial_putc (c); } -void -putDebugStr (const char *str) +void putDebugStr (const char *str) { serial_puts (str); } -int -getDebugChar (void) +int getDebugChar (void) { - return serial_getc(); + return serial_getc (); } -void -kgdb_interruptible (int yes) +void kgdb_interruptible (int yes) { return; } -#endif /* CFG_CMD_KGDB */ +#endif /* CFG_CMD_KGDB */ diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c index 448c623..4544069 100644 --- a/board/modnet50/modnet50.c +++ b/board/modnet50/modnet50.c @@ -24,8 +24,7 @@ #include <common.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -33,7 +32,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; /* address for the kernel command line */ gd->bd->bi_boot_params = 0x800; return 0; @@ -41,7 +39,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; if (CONFIG_NR_DRAM_BANKS == 2) { diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c index e75be1e..486d44c 100644 --- a/board/mp2usb/mp2usb.c +++ b/board/mp2usb/mp2usb.c @@ -31,15 +31,14 @@ #include <dm9161.h> #include <asm/mach-types.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; + /* * Miscelaneous platform dependent initialisations */ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Enable Ctrlc */ console_init_f (); @@ -56,8 +55,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c deleted file mode 100644 index da8d3d7..0000000 --- a/board/mpc8349ads/mpc8349ads.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include <common.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <asm/mpc8349_pci.h> -#include <i2c.h> -#include <spd.h> -#include <miiphy.h> -#if defined(CONFIG_PCI) -#include <pci.h> -#endif -#if defined(CONFIG_SPD_EEPROM) -#include <spd_sdram.h> -#endif -int fixed_sdram(void); -void sdram_init(void); - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CFG_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - - return 0; -} - - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) - -long int initdram (int board_type) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(NULL); -#else - msize = fixed_sdram(); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - puts(" DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif - - im->ddr.csbnds[0].csbnds = 0x00100017; - im->ddr.csbnds[1].csbnds = 0x0018001f; - im->ddr.csbnds[2].csbnds = 0x00000007; - im->ddr.csbnds[3].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; - im->ddr.cs_config[3] = CFG_DDR_CONFIG; - im->ddr.timing_cfg_1 = - 3 << TIMING_CFG1_PRETOACT_SHIFT | - 7 << TIMING_CFG1_ACTTOPRE_SHIFT | - 3 << TIMING_CFG1_ACTTORW_SHIFT | - 4 << TIMING_CFG1_CASLAT_SHIFT | - 3 << TIMING_CFG1_REFREC_SHIFT | - 3 << TIMING_CFG1_WRREC_SHIFT | - 2 << TIMING_CFG1_ACTTOACT_SHIFT | - 1 << TIMING_CFG1_WRTORD_SHIFT; - im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; - im->ddr.sdram_cfg = - SDRAM_CFG_SREN -#if defined(CONFIG_DDR_2T_TIMING) - | SDRAM_CFG_2T_EN -#endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; - im->ddr.sdram_mode = - 0x2000 << SDRAM_MODE_ESD_SHIFT | - 0x0162 << SDRAM_MODE_SD_SHIFT; - - im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | - 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif/*!CFG_SPD_EEPROM*/ - - -int checkboard (void) -{ - puts("Board: Freescale MPC8349ADS\n"); - return 0; -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxads_config_table[] = { - {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER - } }, - {} -} -#endif - - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc83xx_init(volatile struct pci_controller *hose); - - pci_mpc83xx_init(hose); -#endif /* CONFIG_PCI */ -} - -/* - * if MPC8349ADS is soldered with SDRAM - */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void -sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile lbus8349_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus*/ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733;mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void -sdram_init(void) -{ - put("SDRAM on Local Bus is NOT available!\n"); -} -#endif diff --git a/board/mpc8349ads/Makefile b/board/mpc8349emds/Makefile index 4327b0d..38bbb67 100644 --- a/board/mpc8349ads/Makefile +++ b/board/mpc8349emds/Makefile @@ -1,5 +1,6 @@ # -# Copyright 2004 Freescale Semiconductor, Inc. +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/mpc8349ads/config.mk b/board/mpc8349emds/config.mk index 4602169..edf64d1 100644 --- a/board/mpc8349ads/config.mk +++ b/board/mpc8349emds/config.mk @@ -1,5 +1,6 @@ # -# Copyright 2004 Freescale Semiconductor, Inc. +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -21,7 +22,7 @@ # # -# MPC83xxADS +# MPC8349EMDS # -TEXT_BASE = 0xFE700000 +TEXT_BASE = 0xFE000000 diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c new file mode 100644 index 0000000..b5ccb53 --- /dev/null +++ b/board/mpc8349emds/mpc8349emds.c @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mpc8349_pci.h> +#include <i2c.h> +#include <spd.h> +#include <miiphy.h> +#include <command.h> +#if defined(CONFIG_SPD_EEPROM) +#include <spd_sdram.h> +#endif +int fixed_sdram(void); +void sdram_init(void); + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +void ddr_enable_ecc(unsigned int dram_size); +#endif + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + +#ifdef CFG_USE_MPC834XSYS_USB_PHY + /* Use USB PHY on SYS board */ + bcsr[5] |= 0x02; +#endif + + return 0; +} + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif + im->ddr.csbnds[2].csbnds = 0x0000000f; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + + /* currently we use only one CS, so disable the other banks */ + im->ddr.cs_config[0] = 0; + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[3] = 0; + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; +#if defined (CONFIG_DDR_32BIT) + /* for 32-bit mode burst length is 8 */ + im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +#endif + im->ddr.sdram_mode = CFG_DDR_MODE; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349EMDS\n"); + return 0; +} + +/* + * if MPC8349EMDS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile lbus8349_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /* setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733; mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void sdram_init(void) +{ + put("SDRAM on Local Bus is NOT available!\n"); +} +#endif + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) +/* + * ECC user commands + */ +void ecc_print_status(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + + printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); + + /* Interrupts */ + printf("Memory Error Interrupt Enable:\n"); + printf(" Multiple-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); + printf(" Single-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); + printf(" Memory Select Error Interrupt Enable: %d\n\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); + + /* Error disable */ + printf("Memory Error Disable:\n"); + printf(" Multiple-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); + printf(" Sinle-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); + printf(" Memory Select Error Disable: %d\n\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); + + /* Error injection */ + printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", + ddr->data_err_inject_hi, ddr->data_err_inject_lo); + + printf("Memory Data Path Error Injection Mask ECC:\n"); + printf(" ECC Mirror Byte: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); + printf(" ECC Injection Enable: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); + printf(" ECC Error Injection Mask: 0x%02x\n\n", + ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); + + /* SBE counter/threshold */ + printf("Memory Single-Bit Error Management (0..255):\n"); + printf(" Single-Bit Error Threshold: %d\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); + printf(" Single-Bit Error Counter: %d\n\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); + + /* Error detect */ + printf("Memory Error Detect:\n"); + printf(" Multiple Memory Errors: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); + printf(" Multiple-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); + printf(" Single-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); + printf(" Memory Select Error: %d\n\n", + (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); + + /* Capture data */ + printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); + printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", + ddr->capture_data_hi, ddr->capture_data_lo); + printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", + ddr->capture_ecc & CAPTURE_ECC_ECE); + + printf("Memory Error Attributes Capture:\n"); + printf(" Data Beat Number: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); + printf(" Transaction Size: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); + printf(" Transaction Source: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); + printf(" Transaction Type: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); + printf(" Error Information Valid: %d\n\n", + ddr->capture_attributes & ECC_CAPT_ATTR_VLD); +} + +int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + volatile u32 val; + u64 *addr, count, val64; + register u64 *i; + + if (argc > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc == 2) { + if (strcmp(argv[1], "status") == 0) { + ecc_print_status(); + return 0; + } else if (strcmp(argv[1], "captureclear") == 0) { + ddr->capture_address = 0; + ddr->capture_data_hi = 0; + ddr->capture_data_lo = 0; + ddr->capture_ecc = 0; + ddr->capture_attributes = 0; + return 0; + } + } + + if (argc == 3) { + if (strcmp(argv[1], "sbecnt") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBEC_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "sbethr") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBET_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "errdisable") == 0) { + val = ddr->err_disable; + + if (strcmp(argv[2], "+sbe") == 0) { + val |= ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "+mbe") == 0) { + val |= ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "+mse") == 0) { + val |= ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "+all") == 0) { + val |= (ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else if (strcmp(argv[2], "-sbe") == 0) { + val &= ~ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "-mbe") == 0) { + val &= ~ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "-mse") == 0) { + val &= ~ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "-all") == 0) { + val &= ~(ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else { + printf("Incorrect err_disable field\n"); + return 1; + } + + ddr->err_disable = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "errdetectclr") == 0) { + val = ddr->err_detect; + + if (strcmp(argv[2], "mme") == 0) { + val |= ECC_ERROR_DETECT_MME; + } else if (strcmp(argv[2], "sbe") == 0) { + val |= ECC_ERROR_DETECT_SBE; + } else if (strcmp(argv[2], "mbe") == 0) { + val |= ECC_ERROR_DETECT_MBE; + } else if (strcmp(argv[2], "mse") == 0) { + val |= ECC_ERROR_DETECT_MSE; + } else if (strcmp(argv[2], "all") == 0) { + val |= (ECC_ERROR_DETECT_MME | + ECC_ERROR_DETECT_MBE | + ECC_ERROR_DETECT_SBE | + ECC_ERROR_DETECT_MSE); + } else { + printf("Incorrect err_detect field\n"); + return 1; + } + + ddr->err_detect = val; + return 0; + } else if (strcmp(argv[1], "injectdatahi") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_hi = val; + return 0; + } else if (strcmp(argv[1], "injectdatalo") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_lo = val; + return 0; + } else if (strcmp(argv[1], "injectecc") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + if (val > 0xff) { + printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); + return 1; + } + val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); + + ddr->ecc_err_inject = val; + return 0; + } else if (strcmp(argv[1], "inject") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EIEN; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EIEN; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "mirror") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EMB; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EMB; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + return 0; + } + } + + if (argc == 4) { + if (strcmp(argv[1], "test") == 0) { + addr = (u64 *)simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if ((u32)addr % 8) { + printf("Address not alligned on double word boundary\n"); + return 1; + } + + disable_interrupts(); + icache_disable(); + + for (i = addr; i < addr + count; i++) { + /* enable injects */ + ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* write memory location injecting errors */ + *i = 0x1122334455667788ULL; + __asm__ __volatile__ ("sync"); + + /* disable injects */ + ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* read data, this generates ECC error */ + val64 = *i; + __asm__ __volatile__ ("sync"); + + /* disable errors for ECC */ + ddr->err_disable |= ~ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* re-initialize memory, write the location again + * NOT injecting errors this time */ + *i = 0xcafecafecafecafeULL; + __asm__ __volatile__ ("sync"); + + /* enable errors for ECC */ + ddr->err_disable &= ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + } + + icache_enable(); + enable_interrupts(); + + return 0; + } + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + ecc, 4, 0, do_ecc, + "ecc - support for DDR ECC features\n", + "status - print out status info\n" + "ecc captureclear - clear capture regs data\n" + "ecc sbecnt <val> - set Single-Bit Error counter\n" + "ecc sbethr <val> - set Single-Bit Threshold\n" + "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" + " [-|+]sbe - Single-Bit Error\n" + " [-|+]mbe - Multiple-Bit Error\n" + " [-|+]mse - Memory Select Error\n" + " [-|+]all - all errors\n" + "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" + " mme - Multiple Memory Errors\n" + " sbe - Single-Bit Error\n" + " mbe - Multiple-Bit Error\n" + " mse - Memory Select Error\n" + " all - all errors\n" + "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" + "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" + "ecc injectecc <ecc> - set ECC Error Injection Mask\n" + "ecc inject <en|dis> - enable/disable error injection\n" + "ecc mirror <en|dis> - enable/disable mirror byte\n" + "ecc test <addr> <cnt> - test mem region:\n" + " - enables injects\n" + " - writes pattern injecting errors\n" + " - disables injects\n" + " - reads pattern back, generates error\n" + " - re-inits memory" +); +#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c new file mode 100644 index 0000000..63e4405 --- /dev/null +++ b/board/mpc8349emds/pci.c @@ -0,0 +1,382 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <asm/mmu.h> +#include <common.h> +#include <asm/global_data.h> +#include <pci.h> +#include <asm/mpc8349_pci.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349emds_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + } +}; + +/************************************************************************** + * + * pib_init() -- initialize the PCA9555PW IO expander on the PIB board + * + */ +void +pib_init(void) +{ + u8 val8; + /* + * Assign PIB PMC slot to desired PCI bus + */ + mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(PCI_64BIT) + val8 = 0xf4; /* PMC2:PCI1/64-bit */ +#elif defined(PCI_ALL_PCI1) + val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ +#elif defined(PCI_ONE_PCI1) + val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ +#else + val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + asm("eieio"); + +#if defined(PCI_64BIT) + printf("PCI1: 64-bit on PMC2\n"); +#elif defined(PCI_ALL_PCI1) + printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); +#elif defined(PCI_ONE_PCI1) + printf("PCI1: 32-bit on PMC1\n"); + printf("PCI2: 32-bit on PMC2, PMC3\n"); +#else + printf("PCI1: 32-bit on PMC1, PMC2\n"); + printf("PCI2: 32-bit on PMC3\n"); +#endif +} + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk8349_t * clk; + volatile law8349_t * pci_law; + volatile pot8349_t * pci_pot; + volatile pcictrl8349_t * pci_ctrl; + volatile pciconf8349_t * pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMRBAR; + clk = (clk8349_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + pib_init(); + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + clk->occr = 0xff000000; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; ++i) + udelay (1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, + CFG_PCI1_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8300), + (CFG_IMMRBAR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, + CFG_PCI2_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8380), + (CFG_IMMRBAR+0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif + +} + +#endif /* CONFIG_PCI */ diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349emds/u-boot.lds index 020cfa6..937c87a 100644 --- a/board/mpc8349ads/u-boot.lds +++ b/board/mpc8349emds/u-boot.lds @@ -1,5 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor, Inc. + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index b331d6e..06d021a 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -42,6 +42,9 @@ #include "../mip405/mip405.h" #include <405gp_pci.h> #endif + +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_PATI) #define FIRM_START 0xFFF00000 #endif @@ -584,7 +587,6 @@ extern int get_boot_mode(void); void video_get_info_str (int line_number, char *info) { /* init video info strings for graphic console */ - DECLARE_GLOBAL_DATA_PTR; PPC405_SYS_INFO sys_info; char rev; int i,boot; diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c index 2c77d37..ff1190a 100644 --- a/board/mpl/common/memtst.c +++ b/board/mpl/common/memtst.c @@ -50,13 +50,15 @@ int testdram (void) #include <asm/processor.h> #include <405gp_i2c.h> +DECLARE_GLOBAL_DATA_PTR; + #define FALSE 0 #define TRUE 1 -#define TEST_QUIET 8 +#define TEST_QUIET 8 #define TEST_SHOW_PROG 4 #define TEST_SHOW_ERR 2 -#define TEST_SHOW_ALL 1 +#define TEST_SHOW_ALL 1 #define TESTPAT1 0xAA55AA55 #define TESTPAT2 0x55AA55AA @@ -468,7 +470,6 @@ static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { void mem_test_reloc(void) { - DECLARE_GLOBAL_DATA_PTR; unsigned long addr; int i; for (i=0; i< TEST_STAGES; i++) { diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index 692930b..bde14be 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -32,7 +32,7 @@ #ifdef CONFIG_405GP #ifdef CONFIG_PCI -#undef DEBUG +DECLARE_GLOBAL_DATA_PTR; #include "piix4_pci.h" #include "pci_parts.h" @@ -94,7 +94,6 @@ static struct pci_controller hose = { static void reloc_pci_cfg_table(struct pci_config_table *table) { - DECLARE_GLOBAL_DATA_PTR; unsigned long addr; for (; table && table->vendor; table++) { diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 9c469b0..34f3289 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -70,6 +70,9 @@ #include "../common/common_util.h" #include <i2c.h> #include <rtc.h> + +DECLARE_GLOBAL_DATA_PTR; + extern block_dev_desc_t * scsi_get_dev(int dev); extern block_dev_desc_t * ide_get_dev(int dev); @@ -189,8 +192,6 @@ const sdram_t sdram_table[] = { void SDRAM_err (const char *s) { #ifndef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; - (void) get_clocks (); gd->baudrate = 9600; serial_init (); @@ -241,8 +242,6 @@ void write_4hex (unsigned long val) int init_sdram (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long tmp, baseaddr; unsigned short i; unsigned char trp_clocks, @@ -681,7 +680,6 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index a398362..3828608 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -31,6 +31,8 @@ #include "../common/isa.h" #include "../common/common_util.h" +DECLARE_GLOBAL_DATA_PTR; + #undef SDRAM_DEBUG #define FALSE 0 @@ -134,8 +136,6 @@ unsigned short NSto10PS (unsigned char spd_byte) void SDRAM_err (const char *s) { #ifndef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; - (void) get_clocks (); gd->baudrate = 9600; serial_init (); @@ -191,9 +191,6 @@ int board_early_init_f (void) trc_clocks, tctp_clocks; unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; -#ifdef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; -#endif /* set up the config port */ mtdcr (ebccfga, pb7ap); mtdcr (ebccfgd, CONFIG_PORT_AP); @@ -613,8 +610,6 @@ static int test_dram (unsigned long ramsize); long int initdram (int board_type) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long bank_reg[4], tmp, bank_size; int i, ds; unsigned long TotalSize; @@ -666,7 +661,6 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index ffdba5d..0d2003d 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -32,7 +32,7 @@ #include "vcma9.h" #include "../common/common_util.h" -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -71,7 +71,6 @@ static inline void delay(unsigned long loops) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -275,8 +274,6 @@ static void Show_VCMA9_Info(char *board_name, char *serial) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index 20a551d..ee8f3e3 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -14,6 +14,8 @@ #include <pci.h> #endif +DECLARE_GLOBAL_DATA_PTR; + u32 get_BoardType (void); #define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ @@ -50,7 +52,6 @@ void hw_watchdog_reset (void) } int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; ulong busfreq = get_bus_freq (0); char buf[32]; u32 BoardType = get_BoardType (); diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index 5c33ba3..abf2fd5 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -27,7 +27,7 @@ /*#include <mc9328.h>*/ #include <asm/arch/imx-regs.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -55,10 +55,11 @@ #if 0 -static inline void delay (unsigned long loops) { +static inline void delay (unsigned long loops) +{ __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); } #endif @@ -67,62 +68,58 @@ static inline void delay (unsigned long loops) { * Miscellaneous platform dependent initialisations */ -void SetAsynchMode(void) { - __asm__ ( - "mrc p15,0,r0,c1,c0,0 \n" - "mov r2, #0xC0000000 \n" - "orr r0,r2,r0 \n" - "mcr p15,0,r0,c1,c0,0 \n" - ); +void SetAsynchMode (void) +{ + __asm__ ("mrc p15,0,r0,c1,c0,0 \n" + "mov r2, #0xC0000000 \n" + "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); } static u32 mc9328sid; -int board_init (void) { +int board_init (void) +{ + volatile unsigned int tmp; - DECLARE_GLOBAL_DATA_PTR; + mc9328sid = SIDR; - volatile unsigned int tmp; + GPCR = 0x000003AB; /* I/O pad driving strength */ - mc9328sid = SIDR; - - GPCR = 0x000003AB; /* I/O pad driving strength */ - -/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ + /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ /* MX1_CS1L = 0x11110601; */ - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ + MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and * BCLK divider to 2 (i.e. BCLK to 48 MHz) */ - CSCR = 0xAF000403; + CSCR = 0xAF000403; - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ + CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ + CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ /* setup cs4 for cs8900 ethernet */ - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ - CS4L = 0x00001501; + CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ + CS4L = 0x00001501; - GIUS(0) &= 0xFF3FFFFF; - GPR(0) &= 0xFF3FFFFF; + GIUS (0) &= 0xFF3FFFFF; + GPR (0) &= 0xFF3FFFFF; - tmp = *(unsigned int *)(0x1500000C); - tmp = *(unsigned int *)(0x1500000C); + tmp = *(unsigned int *) (0x1500000C); + tmp = *(unsigned int *) (0x1500000C); - SetAsynchMode(); + SetAsynchMode (); gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - icache_enable(); - dcache_enable(); + icache_enable (); + dcache_enable (); /* set PERCLKs */ - PCDR = 0x00000055; /* set PERCLKS */ + PCDR = 0x00000055; /* set PERCLKS */ /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place @@ -135,34 +132,38 @@ int board_init (void) { return 0; } -int board_late_init(void) { - - setenv("stdout", "serial"); - setenv("stderr", "serial"); - - switch (mc9328sid) { - case 0x0005901d : - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - case 0x04d4c01d : - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - case 0x00d4c01d : - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - - default : - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid); - break; +int board_late_init (void) +{ + + setenv ("stdout", "serial"); + setenv ("stderr", "serial"); + + switch (mc9328sid) { + case 0x0005901d: + printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", + mc9328sid); + break; + case 0x04d4c01d: + printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", + mc9328sid); + break; + case 0x00d4c01d: + printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", + mc9328sid); + break; + + default: + printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", + mc9328sid); + break; } return 0; } -int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - +int dram_init (void) +{ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c index 9e7a06c..1c026f0 100644 --- a/board/mx1fs2/mx1fs2.c +++ b/board/mx1fs2/mx1fs2.c @@ -19,9 +19,10 @@ */ #include <common.h> - #include <asm/arch/imx-regs.h> +DECLARE_GLOBAL_DATA_PTR; + #define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) extern void imx_gpio_mode(int gpio_mode); @@ -79,8 +80,6 @@ static void logo_init(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_arch_number = MACH_TYPE_MX1FS2; gd->bd->bi_boot_params = 0x08000100; serial_init(); @@ -91,8 +90,6 @@ serial_init(); int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - #if ( CONFIG_NR_DRAM_BANKS > 0 ) gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1; gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE; diff --git a/board/nc650/Makefile b/board/nc650/Makefile index a4dd85f..8dc4934 100644 --- a/board/nc650/Makefile +++ b/board/nc650/Makefile @@ -1,4 +1,5 @@ # +# (C) Copyright 2006 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -25,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o nand.o flash.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/nc650/config.mk b/board/nc650/config.mk index fa8ba31..5b2284a 100644 --- a/board/nc650/config.mk +++ b/board/nc650/config.mk @@ -1,4 +1,5 @@ # +# (C) Copyright 2006 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -26,3 +27,4 @@ # TEXT_BASE = 0x40700000 +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/nc650/flash.c b/board/nc650/flash.c index ce2f83b..8d7c172 100644 --- a/board/nc650/flash.c +++ b/board/nc650/flash.c @@ -32,6 +32,8 @@ #include <common.h> #include <mpc8xx.h> +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_OR_TIMING_FLASH_AT_50MHZ #define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_2_CLK | OR_EHTR | OR_BI) @@ -95,8 +97,6 @@ unsigned long flash_init (void) #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ int scy, trlx, flash_or_timing, clk_diff; - DECLARE_GLOBAL_DATA_PTR; - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { trlx = OR_TRLX; diff --git a/board/nc650/nand.c b/board/nc650/nand.c new file mode 100644 index 0000000..de54386 --- /dev/null +++ b/board/nc650/nand.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +#if defined(CONFIG_IDS852_REV1) +/* + * hardware specific access to control-lines + */ +static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + + switch(cmd) { + case NAND_CTL_SETCLE: + this->IO_ADDR_W += 2; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W -= 2; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W += 1; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W -= 1; + break; + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + /* nop */ + break; + } +} +#elif defined(CONFIG_IDS852_REV2) +/* + * hardware specific access to control-lines + */ +static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + + switch(cmd) { + case NAND_CTL_SETCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; + break; + case NAND_CTL_CLRCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; + break; + case NAND_CTL_CLRALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_CLRNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; + break; + } +} +#else +#error Unknown IDS852 module revision +#endif + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + + nand->hwcontrol = nc650_hwcontrol; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = 12; +/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/ +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index fe96b93..8a6b5b0 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -1,4 +1,5 @@ /* + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -108,7 +109,16 @@ const uint nand_flash_table[] = { int checkboard (void) { - puts ("Board: NC650\n"); +#if !defined(CONFIG_CP850) + puts ("Board: NC650"); +#else + puts ("Board: CP850"); +#endif +#if defined(CONFIG_IDS852_REV1) + puts (" with IDS852 rev 1 module\n"); +#elif defined(CONFIG_IDS852_REV2) + puts (" with IDS852 rev 2 module\n"); +#endif return 0; } @@ -241,13 +251,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize return (get_ram_size(base, maxsize)); } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init(void) + +#if defined(CONFIG_CP850) + +#define DPRAM_VARNAME "KP850DIP" +#define PARAM_ADDR 0x7C0 +#define NAME_ADDR 0x7F8 +#define BOARD_NAME "KP01" +#define DEFAULT_LB "241111" + +int misc_init_r(void) { - extern unsigned long nand_probe(unsigned long physadr); + int iCompatMode = 0; + char *pParam = NULL; + char *envlb; - unsigned long totlen = nand_probe(CFG_NAND_BASE); + /* + First byte in CPLD read address space signals compatibility mode + 0 - cp850 + 1 - kp852 + */ + pParam = (char*)(CFG_CPLD_BASE); + if( *pParam != 0) + iCompatMode = 1; + + if ( iCompatMode != 0) { + /* + In KP852 compatibility mode we have to write to + DPRAM as early as possible the binary coded + line config and board name. + The line config is derived from the environment + variable DPRAM_VARNAME by converting from ASCII + to binary per character. + */ + if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) { + setenv( DPRAM_VARNAME, DEFAULT_LB); + envlb = DEFAULT_LB; + } + + /* Status string */ + printf("Mode: KP852(LB=%s)\n", envlb); + + /* copy appl init */ + pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR); + while (*envlb) { + *(pParam++) = *(envlb++) - '0'; + } + *pParam = '\0'; + + /* copy board id */ + pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR); + strcpy( pParam, BOARD_NAME); + } else { + puts("Mode: CP850\n"); + } - printf ("%4lu MB\n", totlen >> 20); + return 0; } #endif diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index dd03e4b..297de97 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -599,7 +599,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netstar/Makefile b/board/netstar/Makefile new file mode 100644 index 0000000..3a20501 --- /dev/null +++ b/board/netstar/Makefile @@ -0,0 +1,85 @@ +# +# (C) Copyright 2005 +# Ladislav Michl, 2N Telekomunikace, michl@2n.cz +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := netstar.o flash.o nand.o +SOBJS := setup.o crcek.o + +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds + +HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include + +all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ + -L$(gcclibdir) -lgcc + $(OBJCOPY) -O srec $(<:.o=) $@ + +eeprom.bin: eeprom.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcek.srec: crcek.o + $(LD) -g -Ttext 0x00000000 \ + -o $(<:.o=) -e $(<:.o=) $^ + $(OBJCOPY) -O srec $(<:.o=) $@ + +crcek.bin: crcek.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcit: crcit.o crc32.o + $(HOSTCC) $(HOST_CFLAGS) -o $@ $^ + +crcit.o: crcit.c + $(HOSTCC) $(HOST_CFLAGS) -c $< + +crc32.o: $(TOPDIR)/tools/crc32.c + $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $< + +clean: + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \ + crcek crcek.srec crcek.bin + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netstar/config.mk b/board/netstar/config.mk new file mode 100644 index 0000000..8b73e97 --- /dev/null +++ b/board/netstar/config.mk @@ -0,0 +1,11 @@ +# +# Linux-Kernel is expected to be at 1000'8000, +# entry 1000'8000 (mem base + reserved) +# +# We load ourself to internal RAM at 2001'2000 +# Check map file when changing TEXT_BASE. +# Everything has fit into 192kB internal SRAM! +# + +# XXX TEXT_BASE = 0x20012000 +TEXT_BASE = 0x13FC0000 diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S new file mode 100644 index 0000000..6ca4d11 --- /dev/null +++ b/board/netstar/crcek.S @@ -0,0 +1,177 @@ +/** + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2. + * + * Image layout looks like following: + * u32 - size + * u32 - version + * ... - data + * u32 - crc32 + */ + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + mov r0, #0 + ldr r1, \offset + ldr r2, [r1] + cmp r2, r0 @ no data, no problem + beq 2f + tst r2, #3 @ unaligned size + bne 2f + ldr r3, \size + cmp r2, r3 @ bogus size + bhi 2f + add r1, r1, #4 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + b crc2_bad + mov r6, #0 + crcuj _LOADER1_OFFSET, _LOADER_SIZE + bne crc1_bad + orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + b boot_2nd + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h new file mode 100644 index 0000000..30c0860 --- /dev/null +++ b/board/netstar/crcek.h @@ -0,0 +1,3 @@ +#define LOADER_SIZE (448 * 1024) +#define LOADER1_OFFSET (128 * 1024) +#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) diff --git a/board/netstar/crcit b/board/netstar/crcit Binary files differnew file mode 100755 index 0000000..98ae42e --- /dev/null +++ b/board/netstar/crcit diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c new file mode 100644 index 0000000..f6d3066 --- /dev/null +++ b/board/netstar/crcit.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <fcntl.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include "crcek.h" + +extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int); + +uint32_t data[LOADER_SIZE/4 + 3]; + +int doit(char *path, unsigned version) +{ + uint32_t *p; + ssize_t size; + int fd; + + fd = open(path, O_RDONLY); + if (fd == -1) { + perror("Error opening file"); + return EXIT_FAILURE; + } + p = data + 2; + size = read(fd, p, LOADER_SIZE + 4); + if (size == -1) { + perror("Error reading file"); + return EXIT_FAILURE; + } + if (size > LOADER_SIZE) { + fprintf(stderr, "File too large\n"); + return EXIT_FAILURE; + } + size = (((size - 1) >> 2) + 1) << 2; + data[0] = size + 4; /* add size of version field */ + data[1] = version; + data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]); + close(fd); + + if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + perror("Error writing file"); + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} + +int main(int argc, char **argv) +{ + if (argc == 2) { + return doit(argv[1], 0); + } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { + char *endptr, *nptr = argv[2]; + unsigned ver = strtoul(nptr, &endptr, 0); + if (nptr != '\0' && endptr == '\0') + return doit(argv[3], ver); + } + fprintf(stderr, "Usage: crcit [-v version] <image>\n"); + + return EXIT_FAILURE; +} diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c new file mode 100644 index 0000000..fef3822 --- /dev/null +++ b/board/netstar/eeprom.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, michl@2n.cz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some code shamelessly stolen back from Robin Getz. + */ + +#define DEBUG + +#include <common.h> +#include <exports.h> +#include "../drivers/smc91111.h" + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +static u16 read_eeprom_reg(u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + CTL_REG); + timeout = 100; + while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + udelay(100); + if (timeout == 0) { + printf("Timeout Reading EEPROM register %02x\n", reg); + return 0; + } + + return SMC_inw (GP_REG); +} + +static int write_eeprom_reg(u16 value, u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(value, GP_REG); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + timeout = 100; + while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + udelay (100); + if (timeout == 0) { + printf("Timeout Writing EEPROM register %02x\n", reg); + return 0; + } + + return 1; +} + +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + +static int verify_macaddr(char *s) +{ + u16 reg; + int i, err = 0; + + printf("MAC Address: "); + err = i = 0; + for (i = 0; i < 3; i++) { + reg = read_eeprom_reg(0x20 + i); + printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); + if (s) + err |= reg != ((u16 *)s)[i]; + } + + return err ? 0 : 1; +} + +static int set_mac(char *s) +{ + int i; + char *e, eaddr[6]; + + /* turn string into mac value */ + for (i = 0; i < 6; i++) { + eaddr[i] = simple_strtoul(s, &e, 16); + s = (*e) ? e+1 : e; + } + + for (i = 0; i < 3; i++) + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + + return 0; +} + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +extern int crcek(void); + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + return crcek(); + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/netstar/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S new file mode 100644 index 0000000..75d9f05 --- /dev/null +++ b/board/netstar/eeprom_start.S @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + ldr r1, \offset + ldr r2, [r1] + cmp r2, #0 @ no data, no problem + beq 2f + mov r7, #1 + tst r2, #3 @ unaligned size + bne 2f + mov r7, #2 + ldr r0, \size + cmp r2, r0 @ bogus size + bhi 2f + mov r7, #3 + add r1, r1, #4 + mov r0, #0 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + mov r6, #0 +@ crcuj _LOADER1_OFFSET, _LOADER_SIZE +@ bne crc1_bad +@ orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: +@ mov r0, r6 + mov pc, lr + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/flash.c b/board/netstar/flash.c new file mode 100644 index 0000000..692c416 --- /dev/null +++ b/board/netstar/flash.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. <www.2n.cz> + * Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/*#if 0 */ +#if (PHYS_SDRAM_1_SIZE != SZ_32M) + +#include "crcek.h" + +#if (CFG_MAX_FLASH_BANKS > 1) +#error There is always only _one_ flash chip +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x000000f0 +#define CMD_UNLOCK1 0x000000aa +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000a0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i; + + flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); + flash_info[0].size = PHYS_FLASH_1_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < flash_info[0].sector_count; i++) { + switch (i) { + case 0: /* 16kB */ + flash_info[0].start[0] = CFG_FLASH_BASE; + break; + case 1: /* 8kB */ + flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000; + break; + case 2: /* 8kB */ + flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 + + 0x2000; + break; + case 3: /* 32 KB */ + flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000; + break; + case 4: + flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000 + 0x8000; + break; + default: /* 64kB */ + flash_info[0].start[i] = flash_info[0].start[i-1] + + 0x10000; + break; + } + } + + /* U-Boot */ + flash_protect(FLAG_PROTECT_SET, + LOADER1_OFFSET, + LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); + /* Protect crcek, env and r_env as well */ + flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); + + return flash_info[0].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + puts("AMD: "); + break; + default: + puts("Unknown vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV800B & FLASH_TYPEMASK): + puts("AM29LV800BB (8Mb)\n"); + break; + default: + puts("Unknown chip type\n"); + return; + } + + printf(" Size: %ld MB in %d sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector start addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + puts("\n "); + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + puts("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ushort result; + int prot, sect; + int rc = ERR_OK; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + putc('\n'); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + rc = ERR_TIMOUT; + break; + } + + if ((result & 0xfff) & BIT_ERASE_DONE) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + rc = ERR_PROG_ERROR; + break; + } + } + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (rc != ERR_OK) + goto out; + + putc('.'); + } + } +out: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_hword(flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + + /* check if flash is (sufficiently) erased */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + rc = ERR_TIMOUT; + break; + } + + if ((result & 0x80) == (data & 0x80)) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + result = *addr; + + if ((result & 0x80) != (data & 0x80)) + rc = ERR_PROG_ERROR; + } + } + + *addr = CMD_READ_ARRAY; + + if (*addr != data) + rc = ERR_PROG_ERROR; + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + return write_hword(info, wp, data); +} + +#endif diff --git a/board/netstar/nand.c b/board/netstar/nand.c new file mode 100644 index 0000000..f470c1a --- /dev/null +++ b/board/netstar/nand.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_CLE 0x02 +#define MASK_ALE 0x04 + +static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; + case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +/* + * chip R/B detection + */ +/*** +static int netstar_nand_ready(struct mtd_info *mtd) +{ + return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; +} +***/ + +void board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = netstar_nand_hwcontrol; +/* nand->dev_ready = netstar_nand_ready; */ + nand->chip_delay = 18; +} +#endif diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c new file mode 100644 index 0000000..4b7eba1 --- /dev/null +++ b/board/netstar/netstar.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* arch number of NetStar board */ + /* TODO: use define from asm/mach-types.h */ + gd->bd->bi_arch_number = 692; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + /* Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; + udelay(10); /* doesn't work before interrupt_init call */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; + udelay(500); + + return 0; +} + +extern void partition_flash(void); + +int misc_init_r(void) +{ + return 0; +} + +extern void nand_init(void); + +int board_late_init(void) +{ + return 0; +} diff --git a/board/netstar/setup.S b/board/netstar/setup.S new file mode 100644 index 0000000..f67786d --- /dev/null +++ b/board/netstar/setup.S @@ -0,0 +1,287 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 Ales Jindra <jindra@2n.cz> + * (C) Copyright 2005 Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +_TEXT_BASE: + .word TEXT_BASE /* SDRAM load addr from config.mk */ + +OMAP5910_LPG1_BASE: .word 0xfffbd000 +OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 +OMAP5910_MPU_TC_BASE: .word 0xfffecc00 +OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 +OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 +OMAP5910_DPLL1_BASE: .word 0xfffecf00 +OMAP5910_GPIO_BASE: .word 0xfffce000 +OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 +OMAP5910_MPUI_BASE: .word 0xfffec900 + +_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL +_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK + +OMAP5910_MPUI_CTRL: .word 0x0000ff1b + +VAL_EMIFS_CS0_CONFIG: .word 0x00009090 +VAL_EMIFS_CS1_CONFIG: .word 0x00003031 +VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 +VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 +VAL_EMIFS_DYN_WAIT: .word 0x00000000 +/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ + /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ + +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#else +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#endif + +VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 +VAL_EMIFF_MRS: .word 0x00000037 + +/* + * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) + * GPIO07 - LAN91C111 reset + */ +GPIO_DIRECTION: + .word 0x0000ff6f +/* + * Disable everything (green LED is connected via invertor) + */ +GPIO_OUTPUT: + .word 0x00000010 + +MUX_CONFIG_BASE: + .word 0xfffe1000 + +MUX_CONFIG_VALUES: + .align 4 + .word 0x00000000 @ FUNC_MUX_CTRL_0 + .word 0x00000000 @ FUNC_MUX_CTRL_1 + .word 0x00000000 @ FUNC_MUX_CTRL_2 + .word 0x00000000 @ FUNC_MUX_CTRL_3 + .word 0x00000000 @ FUNC_MUX_CTRL_4 + .word 0x02080480 @ FUNC_MUX_CTRL_5 + .word 0x0100001c @ FUNC_MUX_CTRL_6 + .word 0x0004800b @ FUNC_MUX_CTRL_7 + .word 0x10001200 @ FUNC_MUX_CTRL_8 + .word 0x01201012 @ FUNC_MUX_CTRL_9 + .word 0x02082248 @ FUNC_MUX_CTRL_A + .word 0x00000248 @ FUNC_MUX_CTRL_B + .word 0x12240000 @ FUNC_MUX_CTRL_C + .word 0x00002000 @ FUNC_MUX_CTRL_D + .word 0x00000000 @ PULL_DWN_CTRL_0 + .word 0x00000800 @ PULL_DWN_CTRL_1 + .word 0x01801000 @ PULL_DWN_CTRL_2 + .word 0x00000000 @ PULL_DWN_CTRL_3 + .word 0x00000000 @ GATE_INH_CTRL_0 + .word 0x00000000 @ VOLTAGE_CTRL_0 + .word 0x00000000 @ TEST_DBG_CTRL_0 + .word 0x00000006 @ MOD_CONF_CTRL_0 + .word 0x0000eaef @ COMP_MODE_CTRL_0 + +MUX_CONFIG_OFFSETS: + .align 1 + .byte 0x00 @ FUNC_MUX_CTRL_0 + .byte 0x04 @ FUNC_MUX_CTRL_1 + .byte 0x08 @ FUNC_MUX_CTRL_2 + .byte 0x10 @ FUNC_MUX_CTRL_3 + .byte 0x14 @ FUNC_MUX_CTRL_4 + .byte 0x18 @ FUNC_MUX_CTRL_5 + .byte 0x1c @ FUNC_MUX_CTRL_6 + .byte 0x20 @ FUNC_MUX_CTRL_7 + .byte 0x24 @ FUNC_MUX_CTRL_8 + .byte 0x28 @ FUNC_MUX_CTRL_9 + .byte 0x2c @ FUNC_MUX_CTRL_A + .byte 0x30 @ FUNC_MUX_CTRL_B + .byte 0x34 @ FUNC_MUX_CTRL_C + .byte 0x38 @ FUNC_MUX_CTRL_D + .byte 0x40 @ PULL_DWN_CTRL_0 + .byte 0x44 @ PULL_DWN_CTRL_1 + .byte 0x48 @ PULL_DWN_CTRL_2 + .byte 0x4c @ PULL_DWN_CTRL_3 + .byte 0x50 @ GATE_INH_CTRL_0 + .byte 0x60 @ VOLTAGE_CTRL_0 + .byte 0x70 @ TEST_DBG_CTRL_0 + .byte 0x80 @ MOD_CONF_CTRL_0 + .byte 0x0c @ COMP_MODE_CTRL_0 + .byte 0xff + +.globl lowlevel_init +lowlevel_init: + /* Improve performance a bit... */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit + ldrh r1, [r0, #0x18] @ get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 @ set wait counter to 100 clock cycles + +icache_loop: + cmp r2, #0x01 + streqh r1, [r0, #0x18] + add r2, r2, #0x01 + cmp r2, #0x10 + bne icache_loop + nop + + /* Setup clock divisors */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldr r1, _OMAP5910_ARM_CKCTL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0, #0x00] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, _OMAP5910_ARM_EN_CLK + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + @ max delayed ( 32 x CLKIN ) + strh r1, [r0, #0x0c] + + /* Configure 5910 pins functions to match our board. */ + ldr r0, MUX_CONFIG_BASE + adr r1, MUX_CONFIG_VALUES + adr r2, MUX_CONFIG_OFFSETS +next_mux_cfg: + ldrb r3, [r2], #1 + ldr r4, [r1], #4 + cmp r3, #0xff + strne r4, [r0, r3] + bne next_mux_cfg + + /* Configure GPIO pins (also disables Green LED) */ + ldr r0, OMAP5910_GPIO_BASE + ldr r1, GPIO_OUTPUT + strh r1, [r0, #0x04] + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] + + /* EnablePeripherals */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit + mov r1, #0x0001 @ Peripheral enable + strh r1, [r0, #0x14] + + /* Program LED Pulse Generator */ + ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator + mov r1, #0x7F @ Set obscure frequency in + strb r1, [r0, #0x00] @ LCR + mov r1, #0x01 @ Enable clock (CLK_EN) in + strb r1, [r0, #0x04] @ PMR + + /* TIPB Lock UART1 */ + ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches + mov r1, #1 @ ARM allocated + strh r1, [r0,#0x04] @ clear IRQ line and status bits + strh r1, [r0,#0x00] + ldrh r1, [r0,#0x04] + + /* Disable watchdog */ + ldr r0, OMAP5910_MPU_WD_TIMER_BASE + mov r1, #0xf5 + strh r1, [r0, #0x8] + mov r1, #0xa0 + strh r1, [r0, #0x8] + + /* Enable MCLK */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE + mov r1, #0x6 + strh r1, [r0, #0x34] + strh r1, [r0, #0x34] + + /* Setup clock divisors */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register + + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + strh r1, [r0] @ write + +ulocking: + ldrh r1, [r0] @ get DPLL value + tst r1, #1 + beq ulocking @ while LOCK not set + + /* EMIF init */ + ldr r0, OMAP5910_MPU_TC_BASE + ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG + bic r1, r1, #0x0c @ pwr down disabled, flash WP + orr r1, r1, #0x01 + str r1, [r0, #0x0c] + + ldr r1, VAL_EMIFS_CS0_CONFIG + str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG + ldr r1, VAL_EMIFS_CS1_CONFIG + str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG + ldr r1, VAL_EMIFS_CS2_CONFIG + str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG + ldr r1, VAL_EMIFS_CS3_CONFIG + str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG + ldr r1, VAL_EMIFS_DYN_WAIT + str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT + + /* Setup SDRAM */ + ldr r1, VAL_EMIFF_SDRAM_CONFIG + str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG + ldr r1, VAL_EMIFF_SDRAM_CONFIG2 + str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 + ldr r1, VAL_EMIFF_MRS + str r1, [r0, #0x24] @ EMIFF_MRS + /* SDRAM needs 100us to stabilize */ + mov r0, #0x4000 +sdelay: + subs r0, r0, #0x1 + bne sdelay + + /* back to arch calling code */ + mov pc, lr +.end diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds new file mode 100644 index 0000000..8317f72 --- /dev/null +++ b/board/netstar/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netta/netta.c b/board/netta/netta.c index 9194bfb..4923e3a 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -555,9 +555,9 @@ int board_early_init_f(void) return 0; } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index c9b4051..3ca7bd3 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -597,7 +597,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index fb7f770..3e6c616 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -418,7 +418,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c index ea00d5a..1dd348a 100644 --- a/board/ns9750dev/ns9750dev.c +++ b/board/ns9750dev/ns9750dev.c @@ -41,6 +41,8 @@ # include <./ns9750_bbus.h> #endif +DECLARE_GLOBAL_DATA_PTR; + void flash__init( void ); void ether__init( void ); @@ -60,8 +62,6 @@ static inline void delay( unsigned long loops ) int board_init( void ) { - DECLARE_GLOBAL_DATA_PTR; - /* Active BBUS modules */ *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; @@ -114,8 +114,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 65d45c1..4a426ec 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -28,12 +28,10 @@ #include <malloc.h> #include <mpc8xx.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - #define _NOT_USED_ 0xFFFFFFFF const uint sdram_table[] = { @@ -366,8 +364,6 @@ u_long *my_sernum; int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - char tmp[50]; u_char *e = gd->bd->bi_enetaddr; @@ -387,8 +383,6 @@ int misc_init_r (void) void load_sernum_ethaddr (void) { - DECLARE_GLOBAL_DATA_PTR; - int i; bd_t *bd = gd->bd; diff --git a/board/omap1510inn/omap1510innovator.c b/board/omap1510inn/omap1510innovator.c index f037f42..8941209 100644 --- a/board/omap1510inn/omap1510innovator.c +++ b/board/omap1510inn/omap1510innovator.c @@ -31,6 +31,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + static void flash__init (void); static void ether__init (void); @@ -47,8 +49,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of OMAP 1510-Board */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; @@ -122,8 +122,6 @@ static void ether__init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S index eaf1742..cc8347f 100644 --- a/board/omap1610inn/lowlevel_init.S +++ b/board/omap1610inn/lowlevel_init.S @@ -382,7 +382,7 @@ REG_WATCHDOG: .word 0xfffec808 REG_MPU_LOAD_TIMER: - .word 0xfffec600 + .word 0xfffec504 REG_MPU_CNTL_TIMER: .word 0xfffec500 diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c index 7842518..8dbe686 100644 --- a/board/omap1610inn/omap1610innovator.c +++ b/board/omap1610inn/omap1610innovator.c @@ -36,6 +36,8 @@ #include <./configs/omap1510.h> #endif +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_CS_AUTOBOOT unsigned long omap_flash_base; #endif @@ -60,8 +62,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - if (machine_is_omap_h2()) gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; else if (machine_is_omap_innovator()) @@ -153,8 +153,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 6ae1a49..f7f75e0 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -32,11 +32,13 @@ #include <i2c.h> #include <asm/mach-types.h> #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif - void wait_for_command_complete(unsigned int wd_base); +DECLARE_GLOBAL_DATA_PTR; + +void wait_for_command_complete(unsigned int wd_base); /******************************************************* * Routine: delay @@ -54,8 +56,6 @@ static inline void delay (unsigned long loops) *****************************************/ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gpmc_init(); /* in SRAM or SDRM, finish GPMC */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ @@ -195,7 +195,6 @@ void ether_init (void) **********************************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; unsigned int size0=0,size1=0; u32 mtype, btype, rev, cpu; u8 chg_on = 0x5; /* enable charge of back up battery */ diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S index 3b9633a..a1fa097 100644 --- a/board/omap5912osk/lowlevel_init.S +++ b/board/omap5912osk/lowlevel_init.S @@ -41,6 +41,13 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: + /*------------------------------------------------------* + * Ensure i-cache is enabled * + * To configure TC regs without fetching instruction * + *------------------------------------------------------*/ + mrc p15, 0, r0, c1, c0 + orr r0, r0, #0x1000 + mcr p15, 0, r0, c1, c0 /*------------------------------------------------------* *mask all IRQs by setting all bits in the INTMR default* @@ -59,33 +66,34 @@ lowlevel_init: str r1, [r0] /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * + * Set up ARM CLM registers (IDLECT2) * *------------------------------------------------------*/ ldr r0, REG_ARM_IDLECT2 ldr r1, VAL_ARM_IDLECT2 str r1, [r0] /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * + * Set up ARM CLM registers (IDLECT3) * *------------------------------------------------------*/ ldr r0, REG_ARM_IDLECT3 ldr r1, VAL_ARM_IDLECT3 str r1, [r0] - - mov r1, #0x01 /* PER_EN bit */ + mov r1, #0x01 /* PER_EN bit */ ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ + strh r1, [r0] /* CLKM; Peripheral reset. */ - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x0000 + /* Set CLKM to Sync-Scalable */ + mov r1, #0x1000 ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ + + mov r2, #0 +1: cmp r2, #1 + streqh r1, [r0] + add r2, r2, #1 + cmp r2, #0x100 /* wait for any bubbles to finish */ bne 1b + ldr r1, VAL_ARM_CKCTL ldr r0, REG_ARM_CKCTL strh r1, [r0] @@ -107,17 +115,16 @@ lowlevel_init: ldr r1, VAL_DPLL1_CTL ldr r0, REG_DPLL1_CTL strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ 2: ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ + ands r1, r1, #0x01 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ lock_end: - /*------------------------------------------------------* - * Turn off the watchdog during init... * + * Turn off the watchdog during init... * *------------------------------------------------------*/ ldr r0, REG_WATCHDOG ldr r1, WATCHDOG_VAL1 @@ -143,30 +150,49 @@ watch2Wait: tst r1, #0x10 bne watch2Wait - /* Set memory timings corresponding to the new clock speed */ + ldr r3, VAL_SDRAM_CONFIG_SDF0 /* Check execution location to determine current execution location * and branch to appropriate initialization code. */ - /* Load physical SDRAM base. */ - mov r0, #0x10000000 - /* Get current execution location. */ - mov r1, pc - /* Compare. */ - cmp r1, r0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram + mov r0, #0x10000000 /* Load physical SDRAM base. */ + mov r1, pc /* Get current execution location. */ + cmp r1, r0 /* Compare. */ + bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ + + /* identify the device revision, -- TMX or TMP(TMS) */ + ldr r0, REG_DEVICE_ID + ldr r1, [r0] + + ldr r0, VAL_DEVICE_ID_TMP + mov r1, r1, lsl #15 + mov r1, r1, lsr #16 + cmp r0, r1 + bne skip_TMP_Patch + + /* Enable TMP/TMS device new features */ + mov r0, #1 + ldr r1, REG_TC_EMIFF_DOUBLER + str r0, [r1] + + /* Enable new ac parameters */ + mov r0, #0x0b + ldr r1, REG_SDRAM_CONFIG2 + str r0, [r1] + + ldr r3, VAL_SDRAM_CONFIG_SDF1 + +skip_TMP_Patch: /* * Delay for SDRAM initialization. */ - mov r3, #0x1800 /* value should be checked */ + mov r0, #0x1800 /* value should be checked */ 3: - subs r3, r3, #0x1 /* Decrement count */ + subs r0, r0, #0x1 /* Decrement count */ bne 3b - /* * Set SDRAM control values. Disable refresh before MRS command. */ @@ -178,14 +204,15 @@ watch2Wait: /* config register */ ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] + str r3, [r0] /* manual command register */ ldr r0, REG_SDRAM_MANUAL_CMD + /* issue set cke high */ mov r1, #CMD_SDRAM_CKE_SET_HIGH str r1, [r0] + /* issue nop */ mov r1, #CMD_SDRAM_NOP str r1, [r0] @@ -228,25 +255,23 @@ waitMDDR1: str r1, [r0] /* delay loop */ - mov r2, #0x0100 + mov r0, #0x0100 waitMDDR2: - subs r2, r2, #1 + subs r0, r0, #1 bne waitMDDR2 /* * Delay for SDRAM initialization. */ - mov r3, #0x1800 + mov r0, #0x1800 4: - subs r3, r3, #1 /* Decrement count. */ + subs r0, r0, #1 /* Decrement count. */ bne 4b b common_tc skip_sdram: - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] + str r3, [r0] common_tc: /* slow interface */ @@ -257,10 +282,15 @@ common_tc: ldr r1, VAL_TC_EMIFS_CS1_CONFIG ldr r0, REG_TC_EMIFS_CS1_CONFIG str r1, [r0] /* Chip Select 1 */ + ldr r1, VAL_TC_EMIFS_CS3_CONFIG ldr r0, REG_TC_EMIFS_CS3_CONFIG str r1, [r0] /* Chip Select 3 */ + ldr r1, VAL_TC_EMIFS_DWS + ldr r0, REG_TC_EMIFS_DWS + str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */ + #ifdef CONFIG_H2_OMAP1610 /* inserting additional 2 clock cycle hold time for LAN */ ldr r0, REG_TC_EMIFS_CS1_ADVANCED @@ -282,8 +312,9 @@ common_tc: /* the literal pools origin */ .ltorg - -REG_TC_EMIFS_CONFIG: /* 32 bits */ +REG_DEVICE_ID: /* 32 bits */ + .word 0xfffe2004 +REG_TC_EMIFS_CONFIG: .word 0xfffecc0c REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ .word 0xfffecc10 @@ -293,7 +324,8 @@ REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ .word 0xfffecc18 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ .word 0xfffecc1c - +REG_TC_EMIFS_DWS: /* 32 bits */ + .word 0xfffecc40 #ifdef CONFIG_H2_OMAP1610 REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ .word 0xfffecc54 @@ -302,18 +334,17 @@ REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ /* MPU clock/reset/power mode control registers */ REG_ARM_CKCTL: /* 16 bits */ .word 0xfffece00 - REG_ARM_IDLECT3: /* 16 bits */ .word 0xfffece24 REG_ARM_IDLECT2: /* 16 bits */ .word 0xfffece08 REG_ARM_IDLECT1: /* 16 bits */ .word 0xfffece04 - REG_ARM_RSTCT2: /* 16 bits */ .word 0xfffece14 REG_ARM_SYSST: /* 16 bits */ .word 0xfffece18 + /* DPLL control registers */ REG_DPLL1_CTL: /* 16 bits */ .word 0xfffecf00 @@ -335,6 +366,10 @@ WSPRDOG_VAL2: counter @8192 rows, 10 ns, 8 burst */ REG_SDRAM_CONFIG: .word 0xfffecc20 +REG_SDRAM_CONFIG2: + .word 0xfffecc3c +REG_TC_EMIFF_DOUBLER: /* 32 bits */ + .word 0xfffecc60 /* Operation register */ REG_SDRAM_OPERATION: @@ -356,35 +391,47 @@ REG_SDRAM_EMRS1: REG_DLL_WRT_CONTROL: .word 0xfffecc68 DLL_WRT_CONTROL_VAL: - .word 0x03f00002 + .word 0x03f00002 /* Phase of 72deg, write offset +31 */ /* URD DLL register */ REG_DLL_URD_CONTROL: .word 0xfffeccc0 DLL_URD_CONTROL_VAL: - .word 0x00800002 + .word 0x00800002 /* Phase of 72deg, read offset +31 */ /* LRD DLL register */ REG_DLL_LRD_CONTROL: .word 0xfffecccc +DLL_LRD_CONTROL_VAL: + .word 0x00800002 /* read offset +31 */ REG_WATCHDOG: .word 0xfffec808 +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 REG_MPU_LOAD_TIMER: - .word 0xfffec600 + .word 0xfffec504 REG_MPU_CNTL_TIMER: .word 0xfffec500 +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 /* 96 MHz Samsung Mobile DDR */ -SDRAM_CONFIG_VAL: - .word 0x001200f4 +/* Original setting for TMX device */ +VAL_SDRAM_CONFIG_SDF0: + .word 0x0014e6fe -DLL_LRD_CONTROL_VAL: - .word 0x00800002 +/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */ +VAL_SDRAM_CONFIG_SDF1: + .word 0x0114e6fe VAL_ARM_CKCTL: - .word 0x3000 + .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */ VAL_DPLL1_CTL: .word 0x2830 @@ -392,11 +439,15 @@ VAL_DPLL1_CTL: VAL_TC_EMIFS_CS0_CONFIG: .word 0x002130b0 VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001131 + .word 0x00001133 VAL_TC_EMIFS_CS2_CONFIG: .word 0x000055f0 VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 + .word 0x88013141 +VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */ + .word 0x000000c0 +VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */ + .word 0xb65f #endif #ifdef CONFIG_H2_OMAP1610 @@ -407,36 +458,20 @@ VAL_TC_EMIFS_CS1_CONFIG: VAL_TC_EMIFS_CS2_CONFIG: .word 0xf800f22a VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 + .word 0x88013141 VAL_TC_EMIFS_CS1_ADVANCED: .word 0x00000022 #endif -VAL_TC_EMIFF_SDRAM_CONFIG: - .word 0x010290fc -VAL_TC_EMIFF_MRS: - .word 0x00000027 - VAL_ARM_IDLECT1: .word 0x00000400 - VAL_ARM_IDLECT2: .word 0x00000886 VAL_ARM_IDLECT3: .word 0x00000015 -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - /* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 +.equ CMD_SDRAM_NOP, 0x00000000 +.equ CMD_SDRAM_PRECHARGE, 0x00000001 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c index 1faa084..6993b13 100644 --- a/board/omap5912osk/omap5912osk.c +++ b/board/omap5912osk/omap5912osk.c @@ -38,6 +38,8 @@ #include <./configs/omap1510.h> #endif +DECLARE_GLOBAL_DATA_PTR; + void flash__init (void); void ether__init (void); void set_muxconf_regs (void); @@ -58,8 +60,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; /* adress of boot parameters */ @@ -136,8 +136,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; @@ -290,3 +288,21 @@ void peripheral_power_enable (void) *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; } + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: OSK5912"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S index 6c6f482..9ab71cf 100644 --- a/board/omap730p2/lowlevel_init.S +++ b/board/omap730p2/lowlevel_init.S @@ -317,7 +317,7 @@ REG_WATCHDOG: .word 0xfffec808 REG_MPU_LOAD_TIMER: - .word 0xfffec600 + .word 0xfffec504 REG_MPU_CNTL_TIMER: .word 0xfffec500 diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c index 256c6a6..309d667 100644 --- a/board/omap730p2/omap730p2.c +++ b/board/omap730p2/omap730p2.c @@ -34,6 +34,8 @@ #include <./configs/omap730.h> #endif +DECLARE_GLOBAL_DATA_PTR; + int test_boot_mode(void); void spin_up_leds(void); void flash__init (void); @@ -84,8 +86,6 @@ void toggle_backup_led(void) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; @@ -180,8 +180,6 @@ void ether__init (void) ******************************/ int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c index fa7ff02..6cc3cc5 100644 --- a/board/oxc/oxc.c +++ b/board/oxc/oxc.c @@ -26,6 +26,8 @@ #include <pci.h> #include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + int checkboard (void) { puts ( "Board: OXC8240\n" ); @@ -184,8 +186,6 @@ int misc_init_r (void) #ifdef CFG_OXC_GENERATE_IP { - DECLARE_GLOBAL_DATA_PTR; - char str[32]; unsigned long ip = CFG_OXC_IPMASK; bd_t *bd = gd->bd; diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c index 579bfc7..5f89d9b 100644 --- a/board/pcippc2/fpga_serial.c +++ b/board/pcippc2/fpga_serial.c @@ -29,6 +29,8 @@ #include "hardware.h" #include "pcippc2.h" +DECLARE_GLOBAL_DATA_PTR; + /* 8 data, 1 stop, no parity */ #define LCRVAL 0x03 @@ -92,8 +94,6 @@ int fpga_serial_tstc (void) void fpga_serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor = 115200 / gd->baudrate; fpga_serial_wait (); diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 231b505..a216c55 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -34,6 +34,8 @@ #include "sconsole.h" #include "fpga_serial.h" +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_WATCHDOG) static int pcippc2_wdt_init_done = 0; @@ -108,8 +110,6 @@ int board_early_init_f (void) void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* Jump to the main U-Boot board init code */ board_init_r ((gd_t *)gd, dest_addr); diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c index a9f2b29..3b19069 100644 --- a/board/pcippc2/sconsole.c +++ b/board/pcippc2/sconsole.c @@ -26,6 +26,8 @@ #include "sconsole.h" +DECLARE_GLOBAL_DATA_PTR; + void (*sconsole_putc) (char) = 0; void (*sconsole_puts) (const char *) = 0; int (*sconsole_getc) (void) = 0; @@ -34,8 +36,6 @@ void (*sconsole_setbrg) (void) = 0; int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - sconsole_buffer_t *sb = SCONSOLE_BUFFER; sb->pos = 0; @@ -104,8 +104,6 @@ int serial_tstc (void) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - if (sconsole_setbrg) { (*sconsole_setbrg) (); } else { diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile new file mode 100644 index 0000000..4a2a388 --- /dev/null +++ b/board/pcs440ep/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk new file mode 100644 index 0000000..319c4fa --- /dev/null +++ b/board/pcs440ep/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PCS440EP board +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c new file mode 100644 index 0000000..ece5478 --- /dev/null +++ b/board/pcs440ep/flash.c @@ -0,0 +1,608 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#ifndef CFG_FLASH_READ0 +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Functions + */ +static int write_word(flash_info_t *info, ulong dest, ulong data); +static ulong flash_get_size(vu_long *addr, flash_info_t *info); + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1; + int i; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + base_b0 = FLASH_BASE0_PRELIM; + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + base_b1 = FLASH_BASE1_PRELIM; + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + return (size_b0 + size_b1); +} + +void flash_print_info(flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n"); + break; + case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; k<size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + /* print empty and read-only info */ + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size(vu_long *addr, flash_info_t *info) +{ + short i; + short n; + volatile CFG_FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + + value = addr2[CFG_FLASH_READ0]; + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + info->flash_id = FLASH_MAN_EXCEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[CFG_FLASH_READ1]; /* device ID */ + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 0.5 MB */ + break; + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF020: + info->flash_id += FLASH_SST020; + info->sector_count = 64; + info->size = 0x00040000; + break; /* => 256 kB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF040: + info->flash_id += FLASH_SST040; + info->sector_count = 128; + info->size = 0x00080000; + break; /* => 512 kB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00001000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) + info->protect[i] = 0; + else + info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + flag = 0; + } + + /* data polling for D7 */ + start = get_timer (0); + while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (CFG_FLASH_WORD_SIZE)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } else { + if (sect == s_first) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + } + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) + data = (data << 8) | *src++; + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + wp += 4; + cnt -= 4; + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) + data = (data << 8) | (*(uchar *)cp); + + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S new file mode 100644 index 0000000..0eee4d8 --- /dev/null +++ b/board/pcs440ep/init.S @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c new file mode 100644 index 0000000..8858f0a --- /dev/null +++ b/board/pcs440ep/pcs440ep.c @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <spd_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static void set_leds(int val) +{ + unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, + 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; + out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27)); +} + +int board_early_init_f(void) +{ + register uint reg; + + set_leds(0); /* display boot info counter */ + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + /*-------------------------------------------------------------------- + * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c + * via define from board config file. + *-------------------------------------------------------------------*/ + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ + mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ + + return 0; +} + +int misc_init_r (void) +{ + uint pbcr; + int size_val = 0; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[1]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[1]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: PCS440EP"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +long int initdram (int board_type) +{ + long dram_size = 0; + + set_leds(1); /* display boot info counter */ + dram_size = spd_sdram(); + set_leds(2); /* display boot info counter */ + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440 EP PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* PCS440EP is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + +} +#endif diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds new file mode 100644 index 0000000..6ab476a --- /dev/null +++ b/board/pcs440ep/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + board/pcs440ep/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c index ce9245c..dc6fac4 100644 --- a/board/pleb2/pleb2.c +++ b/board/pleb2/pleb2.c @@ -28,8 +28,7 @@ #include <common.h> #include <asm-arm/mach-types.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -37,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -61,8 +58,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 3868221..38f579b 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -168,6 +168,10 @@ void flash_print_info (flash_info_t *info) } switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256J3A: + printf ("28F256J3A\n"); + break; + case FLASH_28F128J3A: printf ("28F128J3A\n"); break; @@ -236,25 +240,33 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) switch (value) { + case (FPW) INTEL_ID_28F256J3A: + info->flash_id += FLASH_28F256J3A; + /* In U-Boot we support only 32 MB (no bank-switching) */ + info->sector_count = 256 / 2; + info->size = 0x04000000 / 2; + info->start[0] = CFG_FLASH_BASE + 0x02000000; + break; /* => 32 MB */ + case (FPW) INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 0x02000000; - info->start[0] = CFG_FLASH_BASE; + info->start[0] = CFG_FLASH_BASE + 0x02000000; break; /* => 32 MB */ case (FPW) INTEL_ID_28F640J3A: info->flash_id += FLASH_28F640J3A; info->sector_count = 64; info->size = 0x01000000; - info->start[0] = CFG_FLASH_BASE + 0x01000000; + info->start[0] = CFG_FLASH_BASE + 0x03000000; break; /* => 16 MB */ case (FPW) INTEL_ID_28F320J3A: info->flash_id += FLASH_28F320J3A; info->sector_count = 32; info->size = 0x800000; - info->start[0] = CFG_FLASH_BASE + 0x01800000; + info->start[0] = CFG_FLASH_BASE + 0x03800000; break; /* => 8 MB */ default: @@ -285,6 +297,7 @@ static void flash_sync_real_protect (flash_info_t * info) switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256J3A: case FLASH_28F128J3A: case FLASH_28F640J3A: case FLASH_28F320J3A: diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index d4cc5cb..65c5291 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -34,6 +34,8 @@ #include "mt48lc16m16a2-75.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -281,7 +283,6 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; /* adjust flash start */ gd->bd->bi_flashstart = flash_info[0].start[0]; return (0); diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c index 377aaa8..b2f348d 100644 --- a/board/pn62/pn62.c +++ b/board/pn62/pn62.c @@ -26,6 +26,7 @@ #include "pn62.h" +DECLARE_GLOBAL_DATA_PTR; static int get_serial_number (char *string, int size); static int get_mac_address (int id, u8 * mac, char *string, int size); @@ -122,8 +123,6 @@ void pci_init_board (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - char str[20]; u8 mac[6]; diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile new file mode 100644 index 0000000..c378677 --- /dev/null +++ b/board/ppmc7xx/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ppmc7xx.o pci.o flash.o +SOBJS := init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk new file mode 100644 index 0000000..bcb6c81 --- /dev/null +++ b/board/ppmc7xx/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2005 +# Richard Danter, Wind River Systems +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# +# + +TEXT_BASE = 0xFFF00000 +TEXT_END = 0xFFF40000 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c new file mode 100644 index 0000000..1cbcadc --- /dev/null +++ b/board/ppmc7xx/flash.c @@ -0,0 +1,494 @@ +/* + * flash.c + * ------- + * + * Flash programming routines for the Wind River PPMC 74xx/7xx + * based on flash.c from the TQM8260 board. + * + * By Richard Danter (richard.danter@windriver.com) + * Copyright (C) 2005 Wind River Systems + */ + +#include <common.h> +#include <asm/processor.h> +#include <74xx_7xx.h> + +#define DWORD unsigned long long + +/* Local function prototypes */ +static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata); +static void write_via_fpu (volatile DWORD* addr, DWORD* data); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +void flash_reset (void) +{ + unsigned long msr; + DWORD cmd_reset = 0x00F000F000F000F0LL; + + if (flash_info[0].flash_id != FLASH_UNKNOWN) { + msr = get_msr (); + set_msr (msr | MSR_FP); + + write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset ); + + set_msr (msr); + } +} + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + int i; + unsigned long msr; + DWORD flashtest; + DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, + 0x0090009000900090LL }; + + /* Enable FPU */ + msr = get_msr (); + set_msr (msr | MSR_FP); + + /* Write auto-select command sequence */ + write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] ); + write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] ); + write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] ); + + /* Restore FPU */ + set_msr (msr); + + /* Read manufacturer ID */ + flashtest = *(volatile DWORD*)baseaddr; + switch ((int)flashtest) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + /* No, faulty or unknown flash */ + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); + } + + /* Read device ID */ + flashtest = *(volatile DWORD*)(baseaddr + 8); + switch ((long)flashtest) { + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00400000; + break; + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; + break; + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00800000; + break; + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00800000; + break; + case AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x01000000; + break; + case AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x01000000; + break; + case AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x01000000; + break; + case AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; + break; + case AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x02000000; + break; + default: + /* Unknown flash type */ + info->flash_id = FLASH_UNKNOWN; + return (0); + } + + if ((long)flashtest == AMD_ID_LV640U) { + /* set up sector start adress table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = baseaddr + (i * 0x00040000); + } else if (info->flash_id & FLASH_BTYPE) { + /* set up sector start adress table (bottom sector type) */ + info->start[0] = baseaddr + 0x00000000; + info->start[1] = baseaddr + 0x00010000; + info->start[2] = baseaddr + 0x00018000; + info->start[3] = baseaddr + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; + } + } else { + /* set up sector start adress table (top sector type) */ + i = info->sector_count - 1; + info->start[i--] = baseaddr + info->size - 0x00010000; + info->start[i--] = baseaddr + info->size - 0x00018000; + info->start[i--] = baseaddr + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = baseaddr + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + + flash_reset (); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* + * protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + printf ("29LV800T (8 M, top sector)\n"); + break; + case FLASH_AM800B: + printf ("29LV800T (8 M, bottom sector)\n"); + break; + case FLASH_AM160T: + printf ("29LV160T (16 M, top sector)\n"); + break; + case FLASH_AM160B: + printf ("29LV160B (16 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: + printf ("29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: + printf ("29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: + printf ("29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: + printf ("29LV640D (64 M, uniform sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned long msr; + DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, + 0x0080008000800080LL, 0x00AA00AA00AA00AALL, + 0x0055005500550055LL, 0x0030003000300030LL }; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Enable FPU */ + msr = get_msr(); + set_msr ( msr | MSR_FP ); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] ); + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] ); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* Restore FPU */ + set_msr (msr); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL ) + != 0x0080008000800080LL ) + { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + flash_reset (); + + printf (" done\n"); + return 0; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong dp; + static unsigned char bb[8]; + int i, l, rc, cc = cnt; + + dp = (addr & ~7); /* get lower dword aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - dp) != 0) { + for (i = 0; i < 8; i++) + bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++; + if ((rc = write_dword (info, dp, bb)) != 0) { + return (rc); + } + dp += 8; + cc -= 8 - l; + } + + /* + * handle word aligned part + */ + while (cc >= 8) { + if ((rc = write_dword (info, dp, src)) != 0) { + return (rc); + } + dp += 8; + src += 8; + cc -= 8; + } + + if (cc <= 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + for (i = 0; i < 8; i++) { + bb[i] = (i < cc) ? *src++ : *(char*)(dp + i); + } + return (write_dword (info, dp, bb)); +} + +/*----------------------------------------------------------------------- + * Write a dword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) +{ + ulong start; + unsigned long msr; + int flag, i; + DWORD data; + DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, + 0x00A000A000A000A0LL }; + + for (data = 0, i = 0; i < 8; i++) + data = (data << 8) + *pdata++; + + /* Check if Flash is (sufficiently) erased */ + if ((*(DWORD*)dest & data) != data) { + return (2); + } + + /* Enable FPU */ + msr = get_msr(); + set_msr( msr | MSR_FP ); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] ); + write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] ); + write_via_fpu ((DWORD*)dest, &data ); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* Restore FPU */ + set_msr(msr); + + /* data polling for D7 */ + start = get_timer (0); + while (*(volatile DWORD*)dest != data ) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu (volatile DWORD* addr, DWORD* data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); + __asm__ __volatile__ ("eieio"); +} diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S new file mode 100644 index 0000000..e4ed7a6 --- /dev/null +++ b/board/ppmc7xx/init.S @@ -0,0 +1,336 @@ +/* + * init.S + * ------ + * + * Wind River PPMC 7xx/74xx init code. + * + * By Richard Danter (richard.danter@windriver.com) + * Copyright (C) 2005 Wind River Systems + * + * NOTE: The following code was generated automatically by Workbench + * from the ppmc7400_107.reg register file. + */ + +#include <ppc_asm.tmpl> + + +.globl board_asm_init +board_asm_init: + + lis r4,0xFEC0 + ori r4,r4,0x0000 + lis r5,0xFEE0 + ori r5,r5,0x0000 + lis r3,0x8000 # ADDR_00 + ori r3,r3,0x0000 + stwbrx r3,0,r4 + li r3,0x1057 # VENDOR + li r8, 0x0 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_02 + ori r3,r3,0x0002 + stwbrx r3,0,r4 + li r3,0x0004 # ID + li r8, 0x2 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_04 + ori r3,r3,0x0004 + stwbrx r3,0,r4 + li r3,0x0006 # PCICMD + li r8, 0x0 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_06 + ori r3,r3,0x0006 + stwbrx r3,0,r4 + li r3,0x00A0 # PCISTAT + li r8, 0x2 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_08 + ori r3,r3,0x0008 + stwbrx r3,0,r4 + li r3,0x10 # REVID + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_09 + ori r3,r3,0x0009 + stwbrx r3,0,r4 + li r3,0x00 # PROGIR + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_0A + ori r3,r3,0x000A + stwbrx r3,0,r4 + li r3,0x00 # SUBCCODE + stb r3,0x2(r5) + lis r3,0x8000 # ADDR_0B + ori r3,r3,0x000B + stwbrx r3,0,r4 + li r3,0x06 # PBCCR + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_0C + ori r3,r3,0x000C + stwbrx r3,0,r4 + li r3,0x08 # PCLSR + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_0D + ori r3,r3,0x000D + stwbrx r3,0,r4 + li r3,0x00 # PLTR + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_0E + ori r3,r3,0x000E + stwbrx r3,0,r4 + li r3,0x00 # HEADTYPE + stb r3,0x2(r5) + lis r3,0x8000 # ADDR_0F + ori r3,r3,0x000F + stwbrx r3,0,r4 + li r3,0x00 # BISTCTRL + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_10 + ori r3,r3,0x0010 + stwbrx r3,0,r4 + lis r3,0x0000 # LMBAR + ori r3,r3,0x0008 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_14 + ori r3,r3,0x0014 + stwbrx r3,0,r4 + lis r3,0xF000 # PCSRBAR + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_3C + ori r3,r3,0x003C + stwbrx r3,0,r4 + li r3,0x00 # ILR + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_3D + ori r3,r3,0x003D + stwbrx r3,0,r4 + li r3,0x01 # INTPIN + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_3E + ori r3,r3,0x003E + stwbrx r3,0,r4 + li r3,0x00 # MIN_GNT + stb r3,0x2(r5) + lis r3,0x8000 # ADDR_3F + ori r3,r3,0x003F + stwbrx r3,0,r4 + li r3,0x00 # MAX_LAT + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_40 + ori r3,r3,0x0040 + stwbrx r3,0,r4 + li r3,0x00 # BUSNB + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_41 + ori r3,r3,0x0041 + stwbrx r3,0,r4 + li r3,0x00 # SBUSNB + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_46 + ori r3,r3,0x0046 + stwbrx r3,0,r4 +# li r3,0xE080 # PCIARB + li r3,-0x1F80 # PCIARB + li r8, 0x2 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_70 + ori r3,r3,0x0070 + stwbrx r3,0,r4 + li r3,0x0000 # PMCR1 + li r8, 0x0 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_72 + ori r3,r3,0x0072 + stwbrx r3,0,r4 + li r3,0xC0 # PMCR2 + stb r3,0x2(r5) + lis r3,0x8000 # ADDR_73 + ori r3,r3,0x0073 + stwbrx r3,0,r4 + li r3,0xEF # ODCR + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_74 + ori r3,r3,0x0074 + stwbrx r3,0,r4 + li r3,0x7D00 # CLKDCR + li r8, 0x0 + sthbrx r3,r8,r5 + lis r3,0x8000 # ADDR_76 + ori r3,r3,0x0076 + stwbrx r3,0,r4 + li r3,0x00 # MDCR + stb r3,0x2(r5) + lis r6,0xFCE0 + ori r6,r6,0x0000 # r6 is the EUMBAR Base Address + lis r3,0x8000 # ADDR_78 + ori r3,r3,0x0078 + stwbrx r3,0,r4 + lis r3,0xFCE0 # EUMBBAR + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_80 + ori r3,r3,0x0080 + stwbrx r3,0,r4 + lis r3,0xFFFF # MSADDR1 + ori r3,r3,0x4000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_84 + ori r3,r3,0x0084 + stwbrx r3,0,r4 + lis r3,0xFFFF # MSADDR2 + ori r3,r3,0xFFFF + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_88 + ori r3,r3,0x0088 + stwbrx r3,0,r4 + lis r3,0x0303 # EMSADDR1 + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_8C + ori r3,r3,0x008C + stwbrx r3,0,r4 + lis r3,0x0303 # EMSADDR2 + ori r3,r3,0x0303 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_90 + ori r3,r3,0x0090 + stwbrx r3,0,r4 + lis r3,0xFFFF # EMEADDR1 + ori r3,r3,0x7F3F + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_94 + ori r3,r3,0x0094 + stwbrx r3,0,r4 + lis r3,0xFFFF # EMEADDR2 + ori r3,r3,0xFFFF + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_98 + ori r3,r3,0x0098 + stwbrx r3,0,r4 + lis r3,0x0303 # EXTEMEM1 + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_9C + ori r3,r3,0x009C + stwbrx r3,0,r4 + lis r3,0x0303 # EXTEMEM2 + ori r3,r3,0x0303 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_A0 + ori r3,r3,0x00A0 + stwbrx r3,0,r4 + li r3,0x03 # MEMBNKEN + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_A3 + ori r3,r3,0x00A3 + stwbrx r3,0,r4 + li r3,0x00 # MEMPMODE + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_B8 + ori r3,r3,0x00B8 + stwbrx r3,0,r4 + li r3,0x00 # ECCCNT + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_B9 + ori r3,r3,0x00B9 + stwbrx r3,0,r4 + li r3,0x00 # ECCTRG + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_C0 + ori r3,r3,0x00C0 + stwbrx r3,0,r4 + li r3,0xFF # ERRENR1 + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_C1 + ori r3,r3,0x00C1 + stwbrx r3,0,r4 + li r3,0x00 # ERRDR1 + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_C3 + ori r3,r3,0x00C3 + stwbrx r3,0,r4 + li r3,0x50 # IPBESR + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_C4 + ori r3,r3,0x00C4 + stwbrx r3,0,r4 + li r3,0xBF # ERRENR2 + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_C5 + ori r3,r3,0x00C5 + stwbrx r3,0,r4 + li r3,0x00 # ERRDR2 + stb r3,0x1(r5) + lis r3,0x8000 # ADDR_C7 + ori r3,r3,0x00C7 + stwbrx r3,0,r4 + li r3,0x00 # PCIBESR + stb r3,0x3(r5) + lis r3,0x8000 # ADDR_C8 + ori r3,r3,0x00C8 + stwbrx r3,0,r4 + lis r3,0x0000 # BERRADDR + ori r3,r3,0xE0FE + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_E0 + ori r3,r3,0x00E0 + stwbrx r3,0,r4 + li r3,0xC0 # AMBOR + stb r3,0x0(r5) + lis r3,0x8000 # ADDR_F4 + ori r3,r3,0x00F4 + stwbrx r3,0,r4 + lis r3,0x0000 # MCCR2 + ori r3,r3,0x020C + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_F8 + ori r3,r3,0x00F8 + stwbrx r3,0,r4 + lis r3,0x0230 # MCCR3 + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_FC + ori r3,r3,0x00FC + stwbrx r3,0,r4 + lis r3,0x2532 # MCCR4 + ori r3,r3,0x2220 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_F0 + ori r3,r3,0x00F0 + stwbrx r3,0,r4 + lis r3,0xFFC8 # MCCR1 + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_A8 + ori r3,r3,0x00A8 + stwbrx r3,0,r4 + lis r3,0xFF14 # PICR1 + ori r3,r3,0x1CC8 + li r8, 0x0 + stwbrx r3,r8,r5 + lis r3,0x8000 # ADDR_AC + ori r3,r3,0x00AC + stwbrx r3,0,r4 + lis r3,0x0000 # PICR2 + ori r3,r3,0x0000 + li r8, 0x0 + stwbrx r3,r8,r5 + + blr diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c new file mode 100644 index 0000000..5b115ea --- /dev/null +++ b/board/ppmc7xx/pci.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling <fgottschling@eltec.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI initialisation for the MPC10x. + */ + +#include <common.h> +#include <pci.h> +#include <mpc106.h> + +#ifdef CONFIG_PCI + +struct pci_controller local_hose; + +void pci_init_board(void) +{ + struct pci_controller* hose = (struct pci_controller *)&local_hose; + u16 reg16; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI_MEM_BUS, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + CFG_ISA_MEM_BUS, + CFG_ISA_MEM_PHYS, + CFG_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + CFG_PCI_IO_BUS, + CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + CFG_ISA_IO_BUS, + CFG_ISA_IO_PHYS, + CFG_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_indirect(hose, + MPC106_REG_ADDR, + MPC106_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + /* Initialises the MPC10x PCI Configuration regs. */ + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* Clear non-reserved bits in status register */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); +} + +#endif /* CONFIG_PCI */ diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c new file mode 100644 index 0000000..0597c72 --- /dev/null +++ b/board/ppmc7xx/ppmc7xx.c @@ -0,0 +1,104 @@ +/* + * ppmc7xx.c + * --------- + * + * Main board-specific routines for Wind River PPMC 7xx/74xx board. + * + * By Richard Danter (richard.danter@windriver.com) + * Copyright (C) 2005 Wind River Systems + */ + +#include <common.h> +#include <command.h> + + +/* Define some MPC107 (memory controller) registers */ +#define MPC107_EUMB_GCR 0xfce41020 +#define MPC107_EUMB_IACKR 0xfce600a0 + + +/* Function prototypes */ +extern void unlock_ram_in_cache( void ); +extern void _start_warm(void); + + +/* + * initdram() + * + * This function normally initialises the (S)DRAM of the system. For this board + * the SDRAM was already initialised by board_asm_init (see init.S) so we just + * return the size of RAM. + */ +long initdram( int board_type ) +{ + return CFG_SDRAM_SIZE; +} + + +/* + * after_reloc() + * + * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives + * us an opportunity to do some additional setup before the rest of the system + * is initialised. We don't need to do anything, so we just call board_init_r() + * which should never return. + */ +void after_reloc( ulong dest_addr, gd_t* gd ) +{ + /* Jump to the main U-Boot board init code */ + board_init_r( gd, dest_addr ); +} + + +/* + * checkboard() + * + * We could do some board level checks here, such as working out what version + * it is, but for this board we simply display it's name (on the console). + */ +int checkboard( void ) +{ + puts( "Board: Wind River PPMC 7xx/74xx\n" ); + return 0; +} + + +/* + * misc_init_r + * + * Used for other setup which needs to be done late in the bring-up phase. + */ +int misc_init_r( void ) +{ + /* Reset the EPIC and clear pending interrupts */ + out32r(MPC107_EUMB_GCR, 0xa0000000); + while( in32r( MPC107_EUMB_GCR ) & 0x80000000 ); + out32r( MPC107_EUMB_GCR, 0x20000000 ); + while( in32r( MPC107_EUMB_IACKR ) != 0xff ); + + /* Enable the I-Cache */ + icache_enable(); + + return 0; +} + + +/* + * do_reset() + * + * Shell command to reset the board. + */ +void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + printf( "Resetting...\n" ); + + /* Disabe and invalidate cache */ + icache_disable(); + dcache_disable(); + + /* Jump to warm start (in RAM) */ + _start_warm(); + + /* Should never get here */ + while(1); +} diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds new file mode 100644 index 0000000..0dfa8c0 --- /dev/null +++ b/board/ppmc7xx/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c new file mode 100644 index 0000000..8630cc1 --- /dev/null +++ b/board/prodrive/common/flash.c @@ -0,0 +1,556 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Functions + */ +static int write_word(flash_info_t *info, ulong dest, ulong data); + +void flash_print_info(flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n"); + break; + case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; k<size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + /* print empty and read-only info */ + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size(vu_long *addr, flash_info_t *info) +{ + short i; + short n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + + value = addr2[CFG_FLASH_READ0]; + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + info->flash_id = FLASH_MAN_EXCEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[CFG_FLASH_READ1]; /* device ID */ + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF020: + info->flash_id += FLASH_SST020; + info->sector_count = 64; + info->size = 0x00040000; + break; /* => 256 kB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF040: + info->flash_id += FLASH_SST040; + info->sector_count = 128; + info->size = 0x00080000; + break; /* => 512 kB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00001000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) + info->protect[i] = 0; + else + info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + flag = 0; + } + + /* data polling for D7 */ + start = get_timer (0); + while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (CFG_FLASH_WORD_SIZE)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } else { + if (sect == s_first) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + } + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) + data = (data << 8) | *src++; + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + wp += 4; + cnt -= 4; + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) + data = (data << 8) | (*(uchar *)cp); + + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c new file mode 100644 index 0000000..f9412a2 --- /dev/null +++ b/board/prodrive/common/fpga.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2001-2004 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <command.h> + +/* ------------------------------------------------------------------------- */ + +#ifdef FPGA_DEBUG +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif /* DEBUG */ + +#define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (cpu output)*/ +#define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (cpu output) */ +#define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (cpu output) */ +#define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (cpu input) */ +#define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (cpu input) */ + +#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ +#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ +#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ + +#ifndef OLD_VAL +# define OLD_VAL 0 +#endif + +#if 0 /* test-only */ +#define FPGA_WRITE_1 { \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 ); /* set clock to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ +#else +#define FPGA_WRITE_1 { \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 );} /* set data to 1 */ +#endif + +static int fpga_boot(unsigned char *fpgadata, int size) +{ + int i,index,len; + int count; + int j; + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = fpgadata[index]; + DBG("FPGA: %s\n", &(fpgadata[index+1])); + index += len+3; + } + + /* search for preamble 0xFFFFFFFF */ + while (1) { + if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && + (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) + break; /* preamble found */ + else + index++; + } + + DBG("FPGA: configdata starts at position 0x%x\n",index); + DBG("FPGA: length of fpga-data %d\n", size-index); + + /* + * Setup port pins for fpga programming + */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* + * Init fpga by asserting and deasserting PROGRAM* + */ + SET_FPGA(0 | FPGA_CLK | FPGA_DATA); /* set prog active */ + + /* Wait for FPGA init line low */ + count = 0; + while (FPGA_INIT_STATE) { + udelay(1000); /* wait 1ms */ + /* Check for timeout - 100us max, so use 3ms */ + if (count++ > 3) { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_LOW; + } + } + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* deassert PROGRAM* */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set prog inactive */ + + /* Wait for FPGA end of init period . */ + count = 0; + while (!(FPGA_INIT_STATE)) { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_HIGH; + } + } + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + DBG("write configuration data into fpga\n"); + /* write configuration-data into fpga... */ + + /* + * Load uncompressed image into fpga + */ + for (i=index; i<size; i++) { + for (j=0; j<8; j++) { + if ((fpgadata[i] & 0x80) == 0x80) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + fpgadata[i] <<= 1; + } + } + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* + * Check if fpga's DONE signal - correctly booted ? + */ + + /* Wait for FPGA end of programming period . */ + count = 0; + while (!(FPGA_DONE_STATE)) { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_DONE; + } + } + + DBG("FPGA: Booting successful!\n"); + return 0; +} diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index d42a643..2f28e9d 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -29,6 +29,8 @@ #include "p3p440.h" +DECLARE_GLOBAL_DATA_PTR; + void set_led(int color) { switch (color) { @@ -141,8 +143,6 @@ int checkboard(void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - /* * Adjust flash start and offset to detected values */ @@ -206,8 +206,6 @@ int pci_pre_init(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile new file mode 100644 index 0000000..f3cd5a3 --- /dev/null +++ b/board/prodrive/pdnb3/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := flash.o pdnb3.o nand.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk new file mode 100644 index 0000000..6b0f18b --- /dev/null +++ b/board/prodrive/pdnb3/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x01f00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c new file mode 100644 index 0000000..d0e5fe7 --- /dev/null +++ b/board/prodrive/pdnb3/flash.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/ixp425.h> + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/* + * Prototypes + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); + +static inline ulong ld(ulong x) +{ + ulong k = 0; + + while (x >>= 1) + ++k; + + return k; +} + +unsigned long flash_init(void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; i++) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size<<20); + + /* Reconfigure CS0 to actual FLASH size */ + *IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10); + + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + flash_info[0].size = size; + + return size; +} diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c new file mode 100644 index 0000000..1931d64 --- /dev/null +++ b/board/prodrive/pdnb3/nand.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +struct pdnb3_ndfc_regs { + uchar cmd; + uchar wait; + uchar addr; + uchar term; + uchar data; +}; + +static u8 hwctl; +static struct pdnb3_ndfc_regs *pdnb3_ndfc; + +#define readb(addr) *(volatile u_char *)(addr) +#define readl(addr) *(volatile u_long *)(addr) +#define writeb(d,addr) *(volatile u_char *)(addr) = (d) + +/* + * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to + * the NAND devices. The NDFC has command, address and data registers that + * when accessed will set up the NAND flash pins appropriately. We'll use the + * hwcontrol function to save the configuration in a global variable. + * We can then use this information in the read and write functions to + * determine which NDFC register to access. + * + * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte). + */ +static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + + case NAND_CTL_SETNCE: + break; + case NAND_CTL_CLRNCE: + writeb(0x00, &(pdnb3_ndfc->term)); + break; + } +} + +static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + if (hwctl & 0x1) + writeb(byte, &(pdnb3_ndfc->cmd)); + else if (hwctl & 0x2) + writeb(byte, &(pdnb3_ndfc->addr)); + else + writeb(byte, &(pdnb3_ndfc->data)); +} + +static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) +{ + return readb(&(pdnb3_ndfc->data)); +} + +static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (hwctl & 0x1) + writeb(buf[i], &(pdnb3_ndfc->cmd)); + else if (hwctl & 0x2) + writeb(buf[i], &(pdnb3_ndfc->addr)); + else + writeb(buf[i], &(pdnb3_ndfc->data)); + } +} + +static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + + if (len % 4) { + for (i = 0; i < len; i++) + buf[i] = readb(&(pdnb3_ndfc->data)); + } else { + ulong *ptr = (ulong *)buf; + int count = len >> 2; + + for (i = 0; i < count; i++) + *ptr++ = readl(&(pdnb3_ndfc->data)); + } +} + +static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != readb(&(pdnb3_ndfc->data))) + return i; + + return 0; +} + +static int pdnb3_nand_dev_ready(struct mtd_info *mtd) +{ + volatile u_char val; + + /* + * Blocking read to wait for NAND to be ready + */ + val = readb(&(pdnb3_ndfc->wait)); + + /* + * Return always true + */ + return 1; +} + +void board_nand_init(struct nand_chip *nand) +{ + pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE; + + nand->eccmode = NAND_ECC_SOFT; + + /* Set address of NAND IO lines (Using Linear Data Access Region) */ + nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); + nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); + /* Reference hardware control function */ + nand->hwcontrol = pdnb3_nand_hwcontrol; + /* Set command delay time */ + nand->hwcontrol = pdnb3_nand_hwcontrol; + nand->write_byte = pdnb3_nand_write_byte; + nand->read_byte = pdnb3_nand_read_byte; + nand->write_buf = pdnb3_nand_write_buf; + nand->read_buf = pdnb3_nand_read_buf; + nand->verify_buf = pdnb3_nand_verify_buf; + nand->dev_ready = pdnb3_nand_dev_ready; +} +#endif diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c new file mode 100644 index 0000000..e2fed5d --- /dev/null +++ b/board/prodrive/pdnb3/pdnb3.c @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* predefine these here for FPGA programming (before including fpga.c) */ +#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) +#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE) +#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT) +#define OLD_VAL old_val + +static unsigned long old_val = 0; + +/* + * include common fpga code (for prodrive boards) + */ +#include "../common/fpga.c" + +/* + * Miscelaneous platform dependent initialisations + */ +int board_post_init(void) +{ + return (0); +} + +int board_init(void) +{ + /* arch number of PDNB3 */ + gd->bd->bi_arch_number = MACH_TYPE_PDNB3; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET); + GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET); + + GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING); + GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING); + + /* + * Setup GPIO's for FPGA programming + */ + GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG); + GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK); + GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA); + GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG); + GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA); + GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT); + GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE); + + /* + * Setup GPIO's for interrupts + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA); + GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB); + GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT); + GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT); + + /* + * Setup GPIO's for 33MHz clock output + */ + *IXP425_GPIO_GPCLKR = 0x01FF0000; + GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M); + + /* + * Setup other chip select's + */ + *IXP425_EXP_CS1 = CFG_EXP_CS1; + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: PDNB3"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +int do_fpga_boot(unsigned char *fpgadata) +{ + unsigned char *dst; + int status; + int index; + int i; + ulong len = CFG_MALLOC_LEN; + + /* + * Setup GPIO's for FPGA programming + */ + GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG); + GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK); + GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA); + + /* + * Save value so no readback is required upon programming + */ + old_val = *IXP425_GPIO_GPOUTR; + + /* + * First try to decompress fpga image (gzip compressed?) + */ + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf("Error: Image has to be gzipp'ed!\n"); + return -1; + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=5; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc('\n'); + + free(dst); + + /* + * Reset FPGA + */ + GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET); + udelay(10); + GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET); + + return (0); +} + +int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + return do_fpga_boot((unsigned char *)addr); +} + +U_BOOT_CMD( + fpga, 2, 0, do_fpga, + "fpga - boot FPGA\n", + "address size\n - boot FPGA with gzipped image at <address>\n" +); + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) +extern struct pci_controller hose; +extern void pci_ixp_init(struct pci_controller * hose); + +void pci_init_board(void) +{ + extern void pci_ixp_init (struct pci_controller *hose); + + pci_ixp_init(&hose); +} +#endif diff --git a/board/prodrive/pdnb3/u-boot.lds b/board/prodrive/pdnb3/u-boot.lds new file mode 100644 index 0000000..f05f093 --- /dev/null +++ b/board/prodrive/pdnb3/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 4965743..8a7b14e 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -26,7 +26,7 @@ #if defined(CONFIG_NIOS) #include <nios.h> #else -#include <nios2.h> +#include <asm/io.h> #endif #define SECTSZ (64 * 1024) @@ -56,9 +56,8 @@ unsigned long flash_init (void) void flash_print_info (flash_info_t * info) { int i, k; - unsigned long size; int erased; - volatile unsigned char *flash; + unsigned long *addr; printf (" Size: %ld KB in %d Sectors\n", info->size >> 10, info->sector_count); @@ -66,14 +65,10 @@ void flash_print_info (flash_info_t * info) for (i = 0; i < info->sector_count; ++i) { /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; erased = 1; - flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]); - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { + addr = (unsigned long *) info->start[i]; + for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { + if ( readl(addr++) != (unsigned long)-1) { erased = 0; break; } @@ -83,7 +78,7 @@ void flash_print_info (flash_info_t * info) if ((i % 5) == 0) printf ("\n "); printf (" %08lX%s%s", - CACHE_NO_BYPASS(info->start[i]), + info->start[i], erased ? " E" : " ", info->protect[i] ? "RO " : " "); } @@ -95,9 +90,8 @@ void flash_print_info (flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + unsigned char *addr = (unsigned char *) info->start[0]; + unsigned char *addr2; int prot, sect; ulong start; @@ -127,19 +121,18 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS((info->start[sect])); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; + addr2 = (unsigned char *) info->start[sect]; + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr, 0x80); + writeb (addr, 0xaa); + writeb (addr, 0x55); + writeb (addr2, 0x30); /* Now just wait for 0xff & provide some user * feedback while we wait. */ start = get_timer (0); - while (*addr2 != 0xff) { + while ( readb (addr2) != 0xff) { udelay (1000 * 1000); putc ('.'); if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { @@ -163,27 +156,27 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { - vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]); - vu_char *dst = (vu_char *) CACHE_BYPASS(addr); + vu_char *cmd = (vu_char *) info->start[0]; + vu_char *dst = (vu_char *) addr; unsigned char b; ulong start; while (cnt) { /* Check for sufficient erase */ b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); + if ((readb (dst) & b) != b) { + printf ("%02x : %02x\n", readb (dst), b); return (2); } - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; + writeb (cmd, 0xaa); + writeb (cmd, 0x55); + writeb (cmd, 0xa0); + writeb (dst, b); /* Verify write */ start = get_timer (0); - while (*dst != b) { + while (readb (dst) != b) { if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { return 1; } diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk index d72bcee..d65780d 100644 --- a/board/psyent/pk1c20/config.mk +++ b/board/psyent/pk1c20/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x018e0000 +TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index c175c9b..c75fe8c 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <status_led.h> @@ -33,30 +33,30 @@ static led_id_t val = 0; void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - pio->data = val; + writel (&pio->data, val); } void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - pio->data = val; + writel (&pio->data, val); } void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; val ^= mask; - pio->data = val; + writel (&pio->data, val); } diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index d5b993a..5765c55 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -33,8 +33,7 @@ #include <common.h> #include <command.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -42,8 +41,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -86,8 +83,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c index 2861bc3..afa6e11 100644 --- a/board/quantum/quantum.c +++ b/board/quantum/quantum.c @@ -170,14 +170,14 @@ static long int dram_size (long int mamr_value, long int *base, memctl->memc_mamr = mamr_value; for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ + addr = (volatile ulong *)(base + cnt); /* pointer arith! */ save[i++] = *addr; *addr = ~cnt; } /* write 0 to base address */ - addr = base; + addr = (volatile ulong *)base; save[i] = *addr; *addr = 0; @@ -194,7 +194,7 @@ static long int dram_size (long int mamr_value, long int *base, } for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ + addr = (volatile ulong *)(base + cnt); /* pointer arith! */ val = *addr; *addr = save[--i]; diff --git a/board/r5200/Makefile b/board/r5200/Makefile new file mode 100644 index 0000000..d0364ed --- /dev/null +++ b/board/r5200/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/r5200/config.mk b/board/r5200/config.mk new file mode 100644 index 0000000..8fc5319 --- /dev/null +++ b/board/r5200/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x10000000 diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c new file mode 100644 index 0000000..69f3a76 --- /dev/null +++ b/board/r5200/r5200.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/m5271.h> +#include <asm/immap_5271.h> + + +int checkboard (void) { + puts ("Board: R5200 Ethernet Module\n"); + return 0; +}; + +long int initdram (int board_type) { + int i; + + /* + * Set CS2 pin to be SD_CS0 + */ + mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) + | MCF_GPIO_PAR_CS_PAR_CS2); + + mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM) + | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01)); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { + /* + * Initialize DRAM Control Register: DCR + */ + mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01) + | MCF_SDRAMC_DCR_RC(0x30)); + + /* + * Initialize DACR0 + */ + mbar_writeLong(MCF_SDRAMC_DACR0, + MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) + | MCF_SDRAMC_DACRn_CASL(0) + | MCF_SDRAMC_DACRn_CBM(3) + | MCF_SDRAMC_DACRn_PS(2)); + + /* + * Initialize DMR0 + */ + mbar_writeLong(MCF_SDRAMC_DMR0, + MCF_SDRAMC_DMRn_BAM_8M + | MCF_SDRAMC_DMRn_V); + + /* + * Set IP bit in DACR + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_IP); + + /* + * Wait at least 20ns to allow banks to precharge + */ + for (i = 0; i < 5; i++) + asm(" nop"); + + /* + * Write to this block to initiate precharge + */ + *(u16 *)(CFG_SDRAM_BASE) = 0x9696; + + /* + * Set RE bit in DACR + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_RE); + + + /* + * Wait for at least 8 auto refresh cycles to occur + */ + for (i = 0; i < 2000; i++) + asm(" nop"); + + /* + * Finish the configuration by issuing the MRS. + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_MRS); + + + /* + * Write to the SDRAM Mode Register + */ + *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/r5200/u-boot.lds b/board/r5200/u-boot.lds new file mode 100644 index 0000000..f7dc070 --- /dev/null +++ b/board/r5200/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c index c27929d..6d530f6 100644 --- a/board/rbc823/kbd.c +++ b/board/rbc823/kbd.c @@ -33,6 +33,8 @@ #include <devices.h> #include <lcd.h> +DECLARE_GLOBAL_DATA_PTR; + #define SMC_INDEX 0 #define PROFF_SMC PROFF_SMC1 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1 @@ -46,8 +48,6 @@ void smc1_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *im = (immap_t *)CFG_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c index ea4c65d..edb775d 100644 --- a/board/sacsng/clkinit.c +++ b/board/sacsng/clkinit.c @@ -30,6 +30,8 @@ #include "clkinit.h" +DECLARE_GLOBAL_DATA_PTR; + int Daq64xSampling = 0; @@ -257,7 +259,6 @@ void Daq_BRG_Set_ExtClk(uint brg, uint extc) uint Daq_BRG_Rate(uint brg) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immr = (immap_t *)CFG_IMMR; uint *brg_ptr; uint brg_cnt; @@ -295,7 +296,6 @@ uint Daq_Get_SampleRate(void) void Daq_Init_Clocks(int sample_rate, int sample_64x) { - DECLARE_GLOBAL_DATA_PTR; volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); uint mclk_divisor; /* MCLK divisor */ int flag; /* Interrupt state */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 3530416..7816472 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -29,6 +29,8 @@ #include "ppc440gx_i2c.h" #include "sb_common.h" +DECLARE_GLOBAL_DATA_PTR; + long int fixed_sdram (void); /************************************************************************* @@ -203,7 +205,7 @@ long int initdram (int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); + dram_size = spd_sdram (); #else dram_size = fixed_sdram (); #endif @@ -341,8 +343,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index cad5873..0ae6d0b 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -98,7 +98,7 @@ int checkboard (void) long int initdram (int board_type) { - return spd_sdram (0); + return spd_sdram (); } /* ------------------------------------------------------------------------- */ diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c index a6d3bab..8a52f67 100644 --- a/board/sbc8240/sbc8240.c +++ b/board/sbc8240/sbc8240.c @@ -29,12 +29,12 @@ #include <asm/processor.h> #include <pci.h> +DECLARE_GLOBAL_DATA_PTR; + #define BOARD_REV_REG 0xFE80002B int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char revision = *(volatile char *)(BOARD_REV_REG); char buf[32]; diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index cd52324..b6add59 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -30,6 +30,8 @@ #include <asm/ic/ali512x.h> #include <spi.h> +DECLARE_GLOBAL_DATA_PTR; + #undef SC520_CDP_DEBUG #ifdef SC520_CDP_DEBUG @@ -481,8 +483,6 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - init_sc520(); bus_init(); irq_init(); diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index e7a7d51..ed226fd 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -29,9 +29,7 @@ #include <asm/pci.h> #include <asm/ic/sc520.h> - -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Theory: @@ -483,8 +481,6 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - init_sc520(); bus_init(); irq_init(); diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 3ed8753..3f6831b 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -20,42 +20,41 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_SHOW_BOOT_PROGRESS # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) #else # define SHOW_BOOT_PROGRESS(arg) #endif -int board_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_SCB9328; - gd->bd->bi_boot_params = 0x08000100; +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_SCB9328; + gd->bd->bi_boot_params = 0x08000100; - return 0; + return 0; } -int dram_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - +int dram_init (void) +{ #if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; - gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; + gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; + gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; - gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; + gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; + gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; - gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; + gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; + gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; - gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; + gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; + gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; #endif - - return 0; + return 0; } /** diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 13c01d8..475b76b 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -315,7 +315,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/shannon/shannon.c b/board/shannon/shannon.c index 0d9f146..8cd1fc3 100644 --- a/board/shannon/shannon.c +++ b/board/shannon/shannon.c @@ -24,8 +24,7 @@ #include <common.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -33,8 +32,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* but if we use InfernoLoader, we must do some inits here */ @@ -75,7 +72,6 @@ int dram_init (void) { #if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \ defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4) - DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; #endif diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index d20688d..8783aaf 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -27,6 +27,8 @@ #include "scm.h" +DECLARE_GLOBAL_DATA_PTR; + static void config_scoh_cs(void); extern int fpga_init(void); @@ -300,8 +302,6 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ int power_on_reset (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Test Reset Status Register */ return gd->reset_status & RSR_CSRS ? 0 : 1; } diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 867589f..a4cb4dc 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -34,10 +34,12 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif +DECLARE_GLOBAL_DATA_PTR; + #define ORMASK(size) ((-size) & OR_AM_MSK) static long ram_size(ulong *, long); @@ -256,8 +258,6 @@ int board_postclk_init (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; char* s; diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c index a108af7..fd9992d 100644 --- a/board/smdk2400/flash.c +++ b/board/smdk2400/flash.c @@ -353,8 +353,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c index cb70218..4d1f1a6 100644 --- a/board/smdk2400/smdk2400.c +++ b/board/smdk2400/smdk2400.c @@ -28,7 +28,7 @@ #include <common.h> #include <s3c2400.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_MODEM_SUPPORT static int key_pressed(void); @@ -45,7 +45,6 @@ extern int do_mdm_init; /* defined in common/main.c */ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -94,8 +93,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c index 9623aef..802348d 100644 --- a/board/smdk2410/smdk2410.c +++ b/board/smdk2410/smdk2410.c @@ -28,7 +28,7 @@ #include <common.h> #include <s3c2410.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -67,7 +67,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -117,8 +116,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/stamp/Makefile b/board/stamp/Makefile new file mode 100644 index 0000000..ab97e1b --- /dev/null +++ b/board/stamp/Makefile @@ -0,0 +1,68 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o stamp.o +SOBJS = + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stamp/config.mk b/board/stamp/config.mk new file mode 100644 index 0000000..0d00730 --- /dev/null +++ b/board/stamp/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x07FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c new file mode 100644 index 0000000..7e3af20 --- /dev/null +++ b/board/stamp/stamp.c @@ -0,0 +1,276 @@ +/* + * U-boot - stamp.c STAMP board specific routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mem_init.h> +#include "stamp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define STATUS_LED_OFF 0 +#define STATUS_LED_ON 1 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +int checkboard (void) +{ + printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf ("Board: ADI BF533 Stamp board\n"); + printf (" Support: http://blackfin.uclinux.org/\n"); + printf (" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram (int board_type) +{ +#ifdef DEBUG + printf ("SDRAM attributes:\n"); + printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " + "CAS Latency:%d cycles\n", + (SDRAM_tRCD >> 15), + (SDRAM_tRP >> 11), + (SDRAM_tRAS >> 6), + (SDRAM_tWR >> 19), + (SDRAM_CL >> 2)); + printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf ("Bank size = %d MB\n", 128); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return (gd->bd->bi_memsize); +} + +void swap_to (int device_id) +{ + + if (device_id == ETHERNET) { + *pFIO_DIR = PF0; + asm ("ssync;"); + *pFIO_FLAG_S = PF0; + asm ("ssync;"); + } else if (device_id == FLASH) { + *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); + *pFIO_FLAG_S = (PF4 | PF3 | PF2); + *pFIO_MASKA_D = (PF8 | PF6 | PF5); + *pFIO_MASKB_D = (PF7); + *pFIO_POLAR = (PF8 | PF6 | PF5); + *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); + *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); + *pFIO_FLAG_D = (PF4 | PF3 | PF2); + asm ("ssync;"); + } else { + printf ("Unknown bank to switch\n"); + } + + return; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r (void) +{ + int i; + int cf_stat = 0; + + /* Check whether CF card is inserted */ + *pFIO_EDGE = FIO_EDGE_CF_BITS; + *pFIO_POLAR = FIO_POLAR_CF_BITS; + for (i = 0; i < 0x300; i++) + asm ("nop;"); + + if ((*pFIO_FLAG_S) & CF_STAT_BITS) { + cf_stat = 0; + } else { + cf_stat = 1; + } + + *pFIO_EDGE = FIO_EDGE_BITS; + *pFIO_POLAR = FIO_POLAR_BITS; + + + if (cf_stat) { + printf ("Booting from COMPACT flash\n"); + + /* Set cycle time for CF */ + *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL; + + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + + serial_setbrg (); + ide_init (); + + setenv ("bootargs", ""); + setenv ("bootcmd", + "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000"); + } else { + printf ("Booting from FLASH\n"); + } + + return 1; +} +#endif + +#ifdef CONFIG_STAMP_CF + +void cf_outb (unsigned char val, volatile unsigned char *addr) +{ + /* + * Set PF1 PF0 respectively to 0 1 to divert address + * to the expansion memory banks + */ + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + *(addr) = val; + asm ("ssync;"); + + /* Setback PF1 PF0 to 0 0 to address external + * memory banks */ + *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +unsigned char cf_inb (volatile unsigned char *addr) +{ + volatile unsigned char c; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + c = *(addr); + asm ("ssync;"); + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); + + return c; +} + +void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(sect_buf + i) = *(addr); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(addr) = *(sect_buf + i); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} +#endif + +void stamp_led_set (int LED1, int LED2, int LED3) +{ + *pFIO_INEN &= ~(PF2 | PF3 | PF4); + *pFIO_DIR |= (PF2 | PF3 | PF4); + + if (LED1 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF2; + else + *pFIO_FLAG_C = PF2; + if (LED2 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF3; + else + *pFIO_FLAG_C = PF3; + if (LED3 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF4; + else + *pFIO_FLAG_C = PF4; + asm ("ssync;"); +} + +void show_boot_progress (int status) +{ + switch (status) { + case 1: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 2: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 3: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON); + break; + case 4: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF); + break; + case 5: + case 6: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 7: + case 8: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, + STATUS_LED_OFF); + break; + default: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON); + break; + } +} diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h new file mode 100644 index 0000000..7bc33b4 --- /dev/null +++ b/board/stamp/stamp.h @@ -0,0 +1,57 @@ +/* + * U-boot - stamp.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __STAMP_H__ +#define __STAMP_H__ + +extern void init_Flags(void); + +extern volatile unsigned long *ambctl0; +extern volatile unsigned long *ambctl1; +extern volatile unsigned long *amgctl; + +extern unsigned long pll_div_fact; +extern void serial_setbrg(void); +extern void pll_set(int vco, int crystal_frq, int pll_div); + +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + +/* CF Flags used to switch between expansion and external + * memory banks + */ +#define CF_PF0 0x0001 +#define CF_PF1 0x0002 +#define CF_PF1_PF0 0x0003 + +#endif diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds new file mode 100644 index 0000000..9a22e50 --- /dev/null +++ b/board/stamp/u-boot.lds @@ -0,0 +1,147 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index aa3d129..7caf06a 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -576,7 +576,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/sx1/sx1.c b/board/sx1/sx1.c index e45f6ae..aaef76e 100644 --- a/board/sx1/sx1.c +++ b/board/sx1/sx1.c @@ -27,6 +27,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + static void flash__init (void); static void ether__init (void); @@ -43,8 +45,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of SX1 Board */ gd->bd->bi_arch_number = MACH_TYPE_SX1; @@ -116,8 +116,6 @@ static void ether__init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile index c234332..ab0ff1a 100644 --- a/board/tqm5200/Makefile +++ b/board/tqm5200/Makefile @@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -#OBJS := $(BOARD).o flash.o OBJS := $(BOARD).o cmd_stk52xx.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c deleted file mode 100644 index af4d78a..0000000 --- a/board/tqm5200/flash.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CPU to flash interface is 32-bit, so make declaration accordingly - */ -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - extern void flash_preinit(void); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = - flash_get_size((FPW *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV128U: - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (FPW)AMD_ID_LV160B: - debug ("Chip: AM29LV160MB\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * 2 * (64 << 10)) - 0x00060000; - break; /* => 4 MB */ - - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - - switch(addr[14]) { - case AMD_ID_LV128U_2: - if (addr[15] != AMD_ID_LV128U_3) { - debug ("Chip: AM29LVxxxM -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } else { - debug ("Chip: AM29LV128M\n"); - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x02000000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - } - break; /* => 32 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - /* - * Get lower word aligned address. Assumes 32 bit flash bus width. - */ - wp = (addr & ~3); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word_amd(info, (FPW *)wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 6aad920..310abd2 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -254,13 +254,7 @@ int checkboard (void) puts ("Board: AEVFIFO\n"); return 0; #endif -#if defined (CONFIG_TQM5200_AA) - puts ("Board: TQM5200-AA (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200_AB) - puts ("Board: TQM5200-AB (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200_AC) - puts ("Board: TQM5200-AC (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200) +#if defined (CONFIG_TQM5200) puts ("Board: TQM5200 (TQ-Components GmbH)\n"); #endif #if defined (CONFIG_STK52XX) @@ -572,17 +566,7 @@ static const SMI_REGS init_regs [] = void video_get_info_str (int line_number, char *info) { if (line_number == 1) { -#if defined (CONFIG_TQM5200_AA) - strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200_AB) - strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200_AC) - strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200) - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#else -#error No supported board selected -#endif + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); #if defined (CONFIG_STK52XX) } else if (line_number == 2) { strcpy (info, " on a STK52XX baseboard"); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index dada673..d992aec 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -32,6 +32,8 @@ #include <asm-ppc/mmu.h> #include <pci.h> +DECLARE_GLOBAL_DATA_PTR; + #define IOSYNC asm("eieio") #define ISYNC asm("isync") #define SYNC asm("sync") @@ -142,7 +144,6 @@ int checkboard (void) puts("Board: TQM834x\n"); #ifdef CONFIG_PCI - DECLARE_GLOBAL_DATA_PTR; volatile immap_t * immr; u32 w, f; @@ -405,4 +406,28 @@ static void set_ddr_config(void) { (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); SYNC; + + /* Workaround for DDR6 Erratum + * see MPC8349E Device Errata Rev.8, 2/2006 + * This workaround influences the MPC internal "input enables" + * dependent on CAS latency and MPC revision. According to errata + * sheet the internal reserved registers for this workaround are + * not available from revision 2.0 and up. + */ + + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 + * (0x200) + */ + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { + + /* There is a internal reserved register at IMMRBAR+0x2F00 + * which has to be written with a certain value defined by + * errata sheet. + */ +#if defined(DDR_CASLAT_20) + *((u8 *)im + 0x2f00) = 0x201c0000; +#else + *((u8 *)im + 0x2f00) = 0x202c0000; +#endif + } } diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 13ea6f4..befe8b7 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -27,6 +27,9 @@ * MA 02111-1307 USA */ +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif #include <common.h> #include <pci.h> @@ -36,6 +39,8 @@ #include <spd.h> #include <flash.h> +DECLARE_GLOBAL_DATA_PTR; + extern flash_info_t flash_info[]; /* FLASH chips info */ void local_bus_init (void); @@ -257,7 +262,6 @@ int checkboard (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; @@ -296,7 +300,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, 0xffffffff, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ @@ -409,3 +413,14 @@ void pci_init_board (void) pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ + diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c index 97bb5c3..ab57ee5 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqm8xx/flash.c @@ -31,6 +31,8 @@ #include <asm/processor.h> +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ # define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ @@ -63,8 +65,6 @@ unsigned long flash_init (void) #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ int scy, trlx, flash_or_timing, clk_diff; - DECLARE_GLOBAL_DATA_PTR; - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { trlx = OR_TRLX; diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index 017bdf9..b292231 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -31,12 +31,10 @@ #include <ps2mult.h> #endif -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - #define _NOT_USED_ 0xFFFFFFFF const uint sdram_table[] = @@ -104,8 +102,6 @@ const uint sdram_table[] = int checkboard (void) { - DECLARE_GLOBAL_DATA_PTR; - char *s = getenv ("serial#"); puts ("Board: "); @@ -128,6 +124,9 @@ int checkboard (void) break; putc (*s); } +#ifdef CONFIG_VIRTLAB2 + puts (" (Virtlab2)"); +#endif putc ('\n'); return (0); diff --git a/board/trab/Makefile b/board/trab/Makefile index ced9bc5..159404b 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -47,7 +47,7 @@ trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) $(OBJCOPY) -O srec $(<:.o=) $@ trab_fkt.bin: trab_fkt.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index 00eb385..edea8f0 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -729,6 +729,7 @@ static void led_blink (void) /* blink LED. This function does not return! */ while (1) { + reset_timer_masked (); led_set (1); udelay (1000000 / LED_BLINK_FREQ / 2); led_set (0); diff --git a/board/trab/flash.c b/board/trab/flash.c index b4435e3..8cdd824 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -308,8 +308,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/trab/memory.c b/board/trab/memory.c index 9104413..4097892 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -454,10 +454,11 @@ int memory_post_tests (unsigned long start, unsigned long size) } #if 0 +DECLARE_GLOBAL_DATA_PTR; + int memory_post_test (int flags) { int ret = 0; - DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? 256 << 20 : bd->bi_memsize) - (1 << 20); diff --git a/board/trab/trab.c b/board/trab/trab.c index e8dfd2c..346406e 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -28,7 +28,7 @@ #include <s3c2400.h> #include <command.h> -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_BRIGHTNESS static void spi_init(void); @@ -52,8 +52,6 @@ extern int do_mdm_init; /* defined in common/main.c */ #define KBD_MDELAY 5000 static void udelay_no_timer (int usec) { - DECLARE_GLOBAL_DATA_PTR; - int i; int delay = usec * 3; @@ -70,7 +68,6 @@ int board_init () #if defined(CONFIG_VFD) extern int vfd_init_clocks(void); #endif - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -141,8 +138,6 @@ int board_init () int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; return 0; @@ -166,6 +161,19 @@ int misc_init_r (void) uchar *str; int i; +#ifdef CONFIG_VERSION_VARIABLE + { + /* Set version variable. Please note, that this variable is + * also set in main_loop() later in the boot process. The + * version variable has to be set this early, because so it + * could be used in script files on an usb stick, which + * might be called during do_auto_update() */ + extern char version_string[]; + + setenv ("ver", version_string); + } +#endif /* CONFIG_VERSION_VARIABLE */ + #ifdef CONFIG_AUTO_UPDATE extern int do_auto_update(void); /* this has priority over all else */ diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index ca68682..382a85b 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -223,7 +223,7 @@ u16 tsc2000_read_channel (unsigned int channel) u16 res; tsc2000_set_mux(channel); - udelay(3 * TSC2000_DELAY_BASE); + udelay(20 * TSC2000_DELAY_BASE); tsc2000_write(TSC2000_REG_ADC, 0x2036); adc_wait_conversion_done (); diff --git a/board/trab/vfd.c b/board/trab/vfd.c index f510ee5..2f1e7d7 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -39,6 +39,8 @@ #include <devices.h> #include <s3c2400.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_VFD /************************************************************************/ @@ -86,7 +88,6 @@ unsigned char bit_vfd_table[112][18][2][4][2]; */ void init_grid_ctrl(void) { - DECLARE_GLOBAL_DATA_PTR; ulong adr, grid_cycle; unsigned int bit, display; unsigned char temp, bit_nr; @@ -172,7 +173,6 @@ void init_grid_ctrl(void) */ void create_vfd_table(void) { - DECLARE_GLOBAL_DATA_PTR; unsigned long vfd_table[112][18][2][4][2]; unsigned int x, y, color, display, entry, pixel; unsigned int x_abcdef = 0; @@ -280,7 +280,6 @@ void set_vfd_pixel(unsigned char x, unsigned char y, unsigned char color, unsigned char display, unsigned char value) { - DECLARE_GLOBAL_DATA_PTR; ulong adr; unsigned char bit_nr, temp; @@ -359,6 +358,8 @@ void transfer_pic(int display, unsigned char *adr, int height, int width) */ int vfd_init_clocks (void) { + int i; + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); @@ -368,7 +369,9 @@ int vfd_init_clocks (void) */ gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */ gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */ - udelay (10); /* allow signals to settle */ + /* allow signals to settle */ + for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */ + __asm("NOP"); vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ VFD_DISABLE; /* activate blank for the vfd */ @@ -435,8 +438,6 @@ int drv_vfd_init(void) static int vfd_init_done = 0; int vfd_inv_data = 0; - DECLARE_GLOBAL_DATA_PTR; - if (vfd_init_done != 0) return (0); vfd_init_done = 1; diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh index 35c663e..576f238 100755 --- a/board/versatile/split_by_variant.sh +++ b/board/versatile/split_by_variant.sh @@ -36,5 +36,5 @@ fi # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -./mkconfig -a versatile arm arm926ejs versatile +./mkconfig -a versatile arm arm926ejs versatile NULL versatile echo "Variant:: $variant" diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c index 0274027..9d1a25e 100644 --- a/board/versatile/versatile.c +++ b/board/versatile/versatile.c @@ -35,6 +35,8 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + void flash__init (void); void ether__init (void); void peripheral_power_enable (void); @@ -61,9 +63,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - - /* * set clock frequency: * VERSATILE_REFCLK is 32KHz diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk index c73cd27..b77c91c 100644 --- a/board/voiceblue/config.mk +++ b/board/voiceblue/config.mk @@ -12,5 +12,5 @@ ifeq ($(VOICEBLUE_SMALL_FLASH),y) TEXT_BASE = 0x20012000 else # Running in SDRAM... -TEXT_BASE = 0x13000000 +TEXT_BASE = 0x13FD0000 endif diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c index 7a2d243..04093d1 100644 --- a/board/voiceblue/voiceblue.c +++ b/board/voiceblue/voiceblue.c @@ -21,10 +21,10 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; /* arch number of VoiceBlue board */ @@ -39,8 +39,6 @@ int board_init(void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; /* Take the Ethernet controller out of reset and wait diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c index 56cb855..fe4b6a9 100644 --- a/board/wepep250/wepep250.c +++ b/board/wepep250/wepep250.c @@ -23,45 +23,45 @@ #include <common.h> #include <asm/arch/pxa-regs.h> -int board_init( void ){ - DECLARE_GLOBAL_DATA_PTR; +DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250; - gd->bd->bi_boot_params = 0xa0000000; +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250; + gd->bd->bi_boot_params = 0xa0000000; /* * Setup GPIO stuff to get serial working */ #if defined( CONFIG_FFUART ) - GPDR1 = 0x80; - GAFR1_L = 0x8010; + GPDR1 = 0x80; + GAFR1_L = 0x8010; #elif defined( CONFIG_BTUART ) - GPDR1 = 0x800; - GAFR1_L = 0x900000; + GPDR1 = 0x800; + GAFR1_L = 0x900000; #endif - PSSR = 0x20; + PSSR = 0x20; - return 0; + return 0; } -int dram_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - +int dram_init (void) +{ #if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = WEP_SDRAM_1; - gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; + gd->bd->bi_dram[0].start = WEP_SDRAM_1; + gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = WEP_SDRAM_2; - gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; + gd->bd->bi_dram[1].start = WEP_SDRAM_2; + gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = WEP_SDRAM_3; - gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; + gd->bd->bi_dram[2].start = WEP_SDRAM_3; + gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; #endif #if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = WEP_SDRAM_4; - gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; + gd->bd->bi_dram[3].start = WEP_SDRAM_4; + gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; #endif - return 0; + return 0; } diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 26fb312..9baa457 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -30,8 +30,7 @@ #include <common.h> -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -39,8 +38,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -63,8 +60,6 @@ int board_late_init(void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; /* gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/ diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c index 19bcc6f..c204b88 100644 --- a/board/xilinx/ml300/serial.c +++ b/board/xilinx/ml300/serial.c @@ -43,6 +43,8 @@ #include <configs/ml300.h> #include "xparameters.h" +DECLARE_GLOBAL_DATA_PTR; + #define USE_CHAN1 \ ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) #define USE_CHAN2 \ @@ -64,7 +66,6 @@ int serial_init(void) { #if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; int clock_divisor; clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; @@ -103,7 +104,6 @@ void serial_setbrg(void) { #if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; int clock_divisor; clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index 1076345..b30e897 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -39,7 +39,6 @@ #include <common.h> #include <net.h> -#include <configs/ml300.h> #include "xparameters.h" #include "xemac.h" @@ -148,7 +147,7 @@ eth_rx(void) RecvFrameLength = PKTSIZE; Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); if (Result == XST_SUCCESS) { - NetReceive((uchar)etherrxbuff, RecvFrameLength); + NetReceive((uchar *)etherrxbuff, RecvFrameLength); return (1); } else { return (0); diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c index f3ecba7..163fe15 100644 --- a/board/xilinx/xilinx_iic/iic_adapter.c +++ b/board/xilinx/xilinx_iic/iic_adapter.c @@ -40,7 +40,6 @@ #include <common.h> #include <environment.h> #include <net.h> -#include <configs/ml300.h> #include "xparameters.h" #ifdef CFG_ENV_IS_IN_EEPROM diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c index ef5e9da..528d323 100644 --- a/board/xm250/xm250.c +++ b/board/xm250/xm250.c @@ -28,6 +28,8 @@ #include <asm/arch/pxa-regs.h> #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* ------------------------------------------------------------------------- */ /* local prototypes */ @@ -61,7 +63,6 @@ int board_init (void) /**********************************************************/ { - DECLARE_GLOBAL_DATA_PTR; /* arch number of MicroSys XM250 */ gd->bd->bi_arch_number = MACH_TYPE_XM250; @@ -76,8 +77,6 @@ int dram_init (void) /**********************************************************/ { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index bb36c96..a569b53 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -26,6 +26,8 @@ #include <spd_sdram.h> #include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + #define BOOT_SMALL_FLASH 32 /* 00100000 */ #define FLASH_ONBD_N 2 /* 00000010 */ #define FLASH_SRAM_SEL 1 /* 00000001 */ @@ -107,7 +109,7 @@ long int initdram (int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); + dram_size = spd_sdram (); #else dram_size = fixed_sdram (); #endif @@ -238,8 +240,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c index a9919db..23d56c4 100644 --- a/board/xsengine/xsengine.c +++ b/board/xsengine/xsengine.c @@ -27,14 +27,14 @@ #include <common.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Miscelaneous platform dependent initialisations */ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -56,8 +56,6 @@ int board_post_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk index 1072dc7..3e53b2b 100644 --- a/board/zpc1900/config.mk +++ b/board/zpc1900/config.mk @@ -27,4 +27,4 @@ # ZPC.1900 board # -TEXT_BASE = 0xFFE00000 +TEXT_BASE = 0xFE000000 diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 6d16a0d..7db535e 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -2,7 +2,7 @@ * (C) Copyright 2001-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2003 Arabella Software Ltd. + * (C) Copyright 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * See file CREDITS for list of people who contributed to this @@ -27,9 +27,6 @@ #include <common.h> #include <ioports.h> #include <mpc8260.h> -#include <asm/m8260_pci.h> -#include <i2c.h> -#include <spd.h> #include <miiphy.h> /* @@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ @@ -231,11 +228,10 @@ long int initdram(int board_type) vu_char *ramaddr; uchar c = 0xFF; long int msize = CFG_SDRAM_SIZE; - uint psdmr = CFG_PSDMR; int i; if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; @@ -255,10 +251,10 @@ long int initdram(int board_type) */ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; + memctl->memc_or4 = CFG_LSDRAM_OR; + memctl->memc_br4 = CFG_LSDRAM_BR; ramaddr = (vu_char *)CFG_LSDRAM_BASE; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; *ramaddr = c; memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) @@ -271,8 +267,8 @@ long int initdram(int board_type) /* Initialise 60x bus SDRAM */ memctl->memc_psrt = CFG_PSRT; - memctl->memc_or2 = 0xFC0028C0; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + memctl->memc_or2 = CFG_PSDRAM_OR; + memctl->memc_br2 = CFG_PSDRAM_BR; /* * The mode data for Mode Register Write command must appear on * the address lines during a mode-set cycle. It is driven by @@ -283,15 +279,15 @@ long int initdram(int board_type) * length must be 4. */ ramaddr = (vu_char *)(CFG_SDRAM_BASE | - ((psdmr & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; #endif /* CFG_RAMBOOT */ diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile new file mode 100644 index 0000000..f3ad674 --- /dev/null +++ b/board/zylonite/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := zylonite.o nand.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk new file mode 100644 index 0000000..b5d5955 --- /dev/null +++ b/board/zylonite/config.mk @@ -0,0 +1,6 @@ +#TEXT_BASE = 0x0 +#TEXT_BASE = 0xa1700000 +#TEXT_BASE = 0xa3080000 +TEXT_BASE = 0xa3008000 + +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c new file mode 100644 index 0000000..883c1ba --- /dev/null +++ b/board/zylonite/flash.c @@ -0,0 +1,434 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/byteorder/swab.h> + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#if 0 + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +#endif + return 0; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S new file mode 100644 index 0000000..da01765 --- /dev/null +++ b/board/zylonite/lowlevel_init.S @@ -0,0 +1,373 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm + + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first ----------------------------------------- */ + mov r10, lr + + /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */ + ldr r0, =0x40E10438 @ GPIO41 FFRXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1043C @ GPIO42 FFTXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10440 @ GPIO43 FFCTS + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10444 @ GPIO 44 FFDCD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10448 @ GPIO 45 FFDSR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1044C @ GPIO 46 FFRI + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10450 @ GPIO 47 FFDTR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10454 @ GPIO 48 + ldr r1, =0x802 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + /* mk: replaced with wait macro */ +/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */ +/* mov r2, #0 */ +/* str r2, [r3] */ +/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */ +/* /\* so 0x300 should be plenty *\/ */ +/* 1: */ +/* ldr r2, [r3] */ +/* cmp r4, r2 */ +/* bgt 1b */ + wait #300 + +mem_init: + + /* configure the MEMCLKCFG register */ + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[0] to data flash SRAM mode */ + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[1] to data flash SRAM mode */ + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 0 register for SRAM memory */ + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[2] to data flash SRAM mode */ + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[3] to VLIO mode */ + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 1 register for VLIO memory */ + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + +#if 0 + /* This does not work in Zylonite. -SC */ + ldr r0, =0x15fffff0 + ldr r1, =0xb10b + str r1, [r0] + str r1, [r0, #4] +#endif + + /* Configure ACCR Register */ + ldr r0, =ACCR @ ACCR + ldr r1, =0x0180b108 + str r1, [r0] + ldr r1, [r0] + + /* Configure MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, =0x403 + str r1, [r0] + ldr r1, [r0] + + /* Perform Resistive Compensation by configuring RCOMP register */ + ldr r1, =RCOMP @ RCOMP + ldr r2, =0x000000ff + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS0 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0x60000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS1 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0xa0000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDREFR */ + ldr r1, =MDREFR @ MDREFR + ldr r2, =0x00000006 + str r2, [r1] + ldr r2, [r1] + + /* Configure EMPI */ + ldr r1, =EMPI @ EMPI + ldr r2, =0x80000000 + str r2, [r1] + ldr r2, [r1] + + /* Hardware DDR Read-Strobe Delay Calibration */ + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + + /* Here we assume the hardware calibration alwasy be successful. -SC */ + /* Set DMCEN bit in MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, [r0] + orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access + str r1, [r0] + +#ifndef CFG_SKIP_DRAM_SCRUB + /* scrub/init SDRAM if enabled/present */ +/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ +/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ +/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ + ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 32 bytes/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b +#endif /* CFG_SKIP_DRAM_SCRUB */ + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr + +/* +@******************************************************************************** +@ DDR calibration +@ +@ This function is used to calibrate DQS delay lines. +@ Monahans supports three ways to do it. One is software +@ calibration. Two is hardware calibration. Three is hybrid +@ calibration. +@ +@ TBD +@ -SC +ddr_calibration: + + @ Case 1: Write the correct delay value once + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] +*/ +/* @ Case 2: Software Calibration + @ Write test pattern to memory + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] + + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 +ddr_loop1: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 +ddr_loop2: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + +end_loop: + + @ Case 3: Hardware Calibratoin + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr +*/ diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c new file mode 100644 index 0000000..5d2cd65 --- /dev/null +++ b/board/zylonite/nand.c @@ -0,0 +1,584 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CONFIG_NEW_NAND_CODE + +#include <nand.h> +#include <asm/arch/pxa-regs.h> + +#ifdef CFG_DFC_DEBUG1 +# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG1(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG2 +# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG2(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG3 +# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG3(fmt, args...) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +/* These really don't belong here, as they are specific to the NAND Model */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr delta_bbt_descr = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_oobinfo delta_oob = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 6, + .eccpos = {2, 3, 4, 5, 6, 7}, + .oobfree = { {8, 2}, {12, 4} } +}; + + +/* + * not required for Monahans DFC + */ +static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + +#if 0 +/* read device ready pin */ +static int dfc_device_ready(struct mtd_info *mtdinfo) +{ + if(NDSR & NDSR_RDY) + return 1; + else + return 0; + return 0; +} +#endif + +/* + * Write buf to the DFC Controller Data Buffer + */ +static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + int i; + + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + NDDB = *long_buf; + } + } + if(rest) { + printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); + } + return; +} + + +/* + * These functions are quite problematic for the DFC. Luckily they are + * not used in the current nand code, except for nand_command, which + * we've defined our own anyway. The problem is, that we always need + * to write 4 bytes to the DFC Data Buffer, but in these functions we + * don't know if to buffer the bytes/half words until we've gathered 4 + * bytes or if to send them straight away. + * + * Solution: Don't use these with Mona's DFC and complain loudly. + */ +static void dfc_write_word(struct mtd_info *mtd, u16 word) +{ + printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); +} +static void dfc_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); +} + +/* The original: + * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) + * + * Shouldn't this be "u_char * const buf" ? + */ +static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) +{ + int i=0, j; + + /* we have to be carefull not to overflow the buffer if len is + * not a multiple of 4 */ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + + DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); + /* if there are any, first copy multiple of 4 bytes */ + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + *long_buf = NDDB; + } + } + + /* ...then the rest */ + if(rest) { + unsigned long rest_data = NDDB; + for(j=0;j<rest; j++) + buf[i+j] = (u_char) ((rest_data>>j) & 0xff); + } + + return; +} + +/* + * read a word. Not implemented as not used in NAND code. + */ +static u16 dfc_read_word(struct mtd_info *mtd) +{ + printf("dfc_write_byte: UNIMPLEMENTED.\n"); + return 0; +} + +/* global var, too bad: mk@tbd: move to ->priv pointer */ +static unsigned long read_buf = 0; +static int bytes_read = -1; + +/* + * read a byte from NDDB Because we can only read 4 bytes from NDDB at + * a time, we buffer the remaining bytes. The buffer is reset when a + * new command is sent to the chip. + * + * WARNING: + * This function is currently only used to read status and id + * bytes. For these commands always 8 bytes need to be read from + * NDDB. So we read and discard these bytes right now. In case this + * function is used for anything else in the future, we must check + * what was the last command issued and read the appropriate amount of + * bytes respectively. + */ +static u_char dfc_read_byte(struct mtd_info *mtd) +{ + unsigned char byte; + unsigned long dummy; + + if(bytes_read < 0) { + read_buf = NDDB; + dummy = NDDB; + bytes_read = 0; + } + byte = (unsigned char) (read_buf>>(8 * bytes_read++)); + if(bytes_read >= 4) + bytes_read = -1; + + DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); + return byte; +} + +/* calculate delta between OSCR values start and now */ +static unsigned long get_delta(unsigned long start) +{ + unsigned long cur = OSCR; + + if(cur < start) /* OSCR overflowed */ + return (cur + (start^0xffffffff)); + else + return (cur - start); +} + +/* delay function, this doesn't belong here */ +static void wait_us(unsigned long us) +{ + unsigned long start = OSCR; + us *= OSCR_CLK_FREQ; + + while (get_delta(start) < us) { + /* do nothing */ + } +} + +static void dfc_clear_nddb(void) +{ + NDCR &= ~NDCR_ND_RUN; + wait_us(CFG_NAND_OTHER_TO); +} + +/* wait_event with timeout */ +static unsigned long dfc_wait_event(unsigned long event) +{ + unsigned long ndsr, timeout, start = OSCR; + + if(!event) + return 0xff000000; + else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) + timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + else + timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + + while(1) { + ndsr = NDSR; + if(ndsr & event) { + NDSR |= event; + break; + } + if(get_delta(start) > timeout) { + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); + return 0xff000000; + } + + } + return ndsr; +} + +/* we don't always wan't to do this */ +static void dfc_new_cmd(void) +{ + int retry = 0; + unsigned long status; + + while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + /* Clear NDSR */ + NDSR = 0xFFF; + + /* set NDCR[NDRUN] */ + if(!(NDCR & NDCR_ND_RUN)) + NDCR |= NDCR_ND_RUN; + + status = dfc_wait_event(NDSR_WRCMDREQ); + + if(status & NDSR_WRCMDREQ) + return; + + DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); + dfc_clear_nddb(); + } + DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); +} + +/* this function is called after Programm and Erase Operations to + * check for success or failure */ +static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long ndsr=0, event=0; + + if(state == FL_WRITING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } else if(state == FL_ERASING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } + + ndsr = dfc_wait_event(event); + + if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) + return(0x1); /* Status Read error */ + return 0; +} + +/* cmdfunc send commands to the DFC */ +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + /* register struct nand_chip *this = mtd->priv; */ + unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; + + /* clear the ugly byte read buffer */ + bytes_read = -1; + read_buf = 0; + + switch (command) { + case NAND_CMD_READ0: + DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (NAND_CMD_READ0 | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_READ1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); + goto end; + case NAND_CMD_READOOB: + DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); + goto end; + case NAND_CMD_READID: + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); + ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_PAGEPROG: + /* sent as a multicommand in NAND_CMD_SEQIN */ + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); + goto end; + case NAND_CMD_ERASE1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); + ndcb1 = (page_addr & 0x00ffffff); + goto write_cmd; + case NAND_CMD_ERASE2: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); + goto end; + case NAND_CMD_SEQIN: + /* send PAGE_PROG command(0x1080) */ + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_WRDREQ; + goto write_cmd; + case NAND_CMD_STATUS: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); + dfc_new_cmd(); + ndcb0 = NAND_CMD_STATUS | (4<<21); + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_RESET: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); + ndcb0 = NAND_CMD_RESET | (5<<21); + event = NDSR_CS0_CMDD; + goto write_cmd; + default: + printk("dfc_cmdfunc: error, unsupported command.\n"); + goto end; + } + + write_cmd: + NDCB0 = ndcb0; + NDCB0 = ndcb1; + NDCB0 = ndcb2; + + /* wait_event: */ + dfc_wait_event(event); + end: + return; +} + +static void dfc_gpio_init(void) +{ + DFC_DEBUG2("Setting up DFC GPIO's.\n"); + + /* no idea what is done here, see zylonite.c */ + GPIO4 = 0x1; + + DF_ALE_WE1 = 0x00000001; + DF_ALE_WE2 = 0x00000001; + DF_nCS0 = 0x00000001; + DF_nCS1 = 0x00000001; + DF_nWE = 0x00000001; + DF_nRE = 0x00000001; + DF_IO0 = 0x00000001; + DF_IO8 = 0x00000001; + DF_IO1 = 0x00000001; + DF_IO9 = 0x00000001; + DF_IO2 = 0x00000001; + DF_IO10 = 0x00000001; + DF_IO3 = 0x00000001; + DF_IO11 = 0x00000001; + DF_IO4 = 0x00000001; + DF_IO12 = 0x00000001; + DF_IO5 = 0x00000001; + DF_IO13 = 0x00000001; + DF_IO6 = 0x00000001; + DF_IO14 = 0x00000001; + DF_IO7 = 0x00000001; + DF_IO15 = 0x00000001; + + DF_nWE = 0x1901; + DF_nRE = 0x1901; + DF_CLE_NOE = 0x1900; + DF_ALE_WE1 = 0x1901; + DF_INT_RnB = 0x1900; +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; + + /* set up GPIO Control Registers */ + dfc_gpio_init(); + + /* turn on the NAND Controller Clock (104 MHz @ D0) */ + CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + +#undef CFG_TIMING_TIGHT +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), + DFC_MAX_tAR); +#else /* this is the tight timing */ + + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), + DFC_MAX_tAR); +#endif /* CFG_TIMING_TIGHT */ + + + DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); + + /* tRP value is split in the register */ + if(tRP & (1 << 4)) { + tRP_high = 1; + tRP &= ~(1 << 4); + } else { + tRP_high = 0; + } + + NDTR0CS0 = (tCH << 19) | + (tCS << 16) | + (tWH << 11) | + (tWP << 8) | + (tRP_high << 6) | + (tRH << 3) | + (tRP << 0); + + NDTR1CS0 = (tR << 16) | + (tWHR << 4) | + (tAR << 0); + + /* If it doesn't work (unlikely) think about: + * - ecc enable + * - chip select don't care + * - read id byte count + * + * Intentionally enabled by not setting bits: + * - dma (DMA_EN) + * - page size = 512 + * - cs don't care, see if we can enable later! + * - row address start position (after second cycle) + * - pages per block = 32 + * - ND_RDY : clears command buffer + */ + /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ + + NDCR = (NDCR_SPARE_EN | /* use the spare area */ + NDCR_DWIDTH_C | /* 16bit DFC data bus width */ + NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ + (2 << 16) | /* read id count = 7 ???? mk@tbd */ + NDCR_ND_ARB_EN | /* enable bus arbiter */ + NDCR_RDYM | /* flash device ready ir masked */ + NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ + NDCR_CS1_PAGEDM | + NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ + NDCR_CS1_CMDDM | + NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ + NDCR_CS1_BBDM | + NDCR_DBERRM | /* double bit error ir masked */ + NDCR_SBERRM | /* single bit error ir masked */ + NDCR_WRDREQM | /* write data request ir masked */ + NDCR_RDDREQM | /* read data request ir masked */ + NDCR_WRCMDREQM); /* write command request ir masked */ + + + /* wait 10 us due to cmd buffer clear reset */ + /* wait(10); */ + + + nand->hwcontrol = dfc_hwcontrol; +/* nand->dev_ready = dfc_device_ready; */ + nand->eccmode = NAND_ECC_SOFT; + nand->options = NAND_BUSWIDTH_16; + nand->waitfunc = dfc_wait; + nand->read_byte = dfc_read_byte; + nand->write_byte = dfc_write_byte; + nand->read_word = dfc_read_word; + nand->write_word = dfc_write_word; + nand->read_buf = dfc_read_buf; + nand->write_buf = dfc_write_buf; + + nand->cmdfunc = dfc_cmdfunc; + nand->autooob = &delta_oob; + nand->badblock_pattern = &delta_bbt_descr; +} + +#else + #error "U-Boot legacy NAND support not available for Monahans DFC." +#endif +#endif diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/zylonite/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c new file mode 100644 index 0000000..5829170 --- /dev/null +++ b/board/zylonite/zylonite.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} |