diff options
Diffstat (limited to 'board')
111 files changed, 9188 insertions, 3685 deletions
diff --git a/board/adder/adder.c b/board/adder/adder.c index cab6e2f..aa781584 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -28,7 +28,8 @@ #include <mpc8xx.h> /* - * SDRAM is single Samsung K4S643232F-T70 chip. + * SDRAM is single Samsung K4S643232F-T70 chip (8MB) + * or single Micron MT48LC4M32B2TG-7 chip (16MB). * Minimal CPU frequency is 40MHz. */ static uint sdram_table[] = { @@ -53,7 +54,7 @@ static uint sdram_table[] = { 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, @@ -63,7 +64,7 @@ static uint sdram_table[] = { long int initdram (int board_type) { - long int msize = CFG_SDRAM_SIZE; + long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -72,11 +73,11 @@ long int initdram (int board_type) /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - memctl->memc_mamr = (94 << 24) | CFG_MAMR; - memctl->memc_mar = 0x0; + memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */ udelay(200); /* Run precharge from location 0x15 */ + memctl->memc_mar = 0x0; memctl->memc_mcr = 0x80002115; udelay(200); @@ -84,13 +85,18 @@ long int initdram (int board_type) memctl->memc_mcr = 0x80002830; udelay(200); - memctl->memc_mar = 0x88; - udelay(200); - /* Run MRS pattern from location 0x16 */ + memctl->memc_mar = 0x88; memctl->memc_mcr = 0x80002116; udelay(200); + memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ + memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + + msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + memctl->memc_or1 |= ~(msize - 1); + return msize; } diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 803995a..7c98920 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -277,7 +277,7 @@ int board_early_init_f(void) } #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; /*----------------------------------------------------------------------------+ diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index 35cb655..433429b 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -32,3 +32,6 @@ endif ifeq ($(dbcr),1) PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 endif + +# legacy nand support +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index dd836ce..7d11b29 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -36,8 +36,8 @@ int board_pre_init (void) /** serial number and platform display at startup */ int checkboard (void) { - unsigned char *s = getenv ("serial#"); - unsigned char *e; + char *s = getenv ("serial#"); + char *e; /* After a loadace command, the SystemAce control register is left in a wonky state. */ /* this code did not work in board_pre_init */ @@ -135,13 +135,13 @@ int checkboard (void) long int initdram (int board_type) { - unsigned char *s = getenv ("dramsize"); + char *s = getenv ("dramsize"); if (s != NULL) { if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { s += 2; } - return simple_strtoul (s, NULL, 16); + return (long int)simple_strtoul (s, NULL, 16); } else { /* give all 64 MB */ return 64 * 1024 * 1024; @@ -293,7 +293,7 @@ int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Writing to Flash... "); write_result = - flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, + flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR, SW_BYTE_SECTOR_SIZE); if (write_result != 0) { flash_perror (write_result); diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c index 3c00132..f886fe4 100644 --- a/board/at91rm9200dk/at45.c +++ b/board/at91rm9200dk/at45.c @@ -593,7 +593,7 @@ int AT91F_DataFlashRead( if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) return -1; size -= SizeToRead; diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c index f6228ef..0513d61 100644 --- a/board/at91rm9200dk/flash.c +++ b/board/at91rm9200dk/flash.c @@ -393,8 +393,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; @@ -409,7 +408,6 @@ volatile static int write_word (flash_info_t * info, ulong dest, if ((result & data) != data) return ERR_NOT_ERASED; - /* * Disable interrupts which might cause a timeout * here. Remember that our exception vectors are diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c index 94aa30d..354566c 100644 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ b/board/cmc_pu2/load_sernum_ethaddr.c @@ -69,8 +69,8 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen, void load_sernum_ethaddr (void) { struct manufacturer_data data; - unsigned char serial [9]; - unsigned char ethaddr[18]; + char ethaddr[18]; + char serial [9]; unsigned short chksum; unsigned char *p; unsigned short i, is, id; diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 6f5874a..73cc2f2 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile index 39d2fec..581a580 100644 --- a/board/dave/PPChameleonEVB/Makefile +++ b/board/dave/PPChameleonEVB/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o nand.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 5f2c705..52055b8 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -238,33 +238,6 @@ int testdram (void) /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - -void -nand_init(void) -{ - ulong totlen = 0; - -/* - The HI model is equipped with a large block NAND chip not supported yet - by U-Boot - (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -*/ - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); -#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ - - debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); - totlen += nand_probe (CFG_NAND1_BASE); - - printf ("%3lu MB\n", totlen >>20); -} -#endif - #ifdef CONFIG_CFB_CONSOLE # ifdef CONFIG_CONSOLE_EXTRA_INFO # include <video_fb.h> diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 5856aec..1dc635f 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000, 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,7 +22,13 @@ # # Reserve 256 kB for Monitor -TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0xFFFC0000 # Reserve 320 kB for Monitor -#TEXT_BASE = 0xFFFB0000 +TEXT_BASE = 0xFFFB0000 + +# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined) +BOARDLIBS = drivers/nand/libnand.a + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c new file mode 100644 index 0000000..40a827c --- /dev/null +++ b/board/dave/PPChameleonEVB/nand.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + switch(cmd) { + case NAND_CTL_SETCLE: + MACRO_NAND_CTL_SETCLE((unsigned long)base); + break; + case NAND_CTL_CLRCLE: + MACRO_NAND_CTL_CLRCLE((unsigned long)base); + break; + case NAND_CTL_SETALE: + MACRO_NAND_CTL_SETALE((unsigned long)base); + break; + case NAND_CTL_CLRALE: + MACRO_NAND_CTL_CLRALE((unsigned long)base); + break; + case NAND_CTL_SETNCE: + MACRO_NAND_ENABLE_CE((unsigned long)base); + break; + case NAND_CTL_CLRNCE: + MACRO_NAND_DISABLE_CE((unsigned long)base); + break; + } +} + + +/* + * read device ready pin + * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong rb_gpio_pin; + + /* use the base addr to find out which chip are we dealing with */ + switch((ulong) this->IO_ADDR_W) { + case CFG_NAND0_BASE: + rb_gpio_pin = CFG_NAND0_RDY; + break; + case CFG_NAND1_BASE: + rb_gpio_pin = CFG_NAND1_RDY; + break; + default: /* this should never happen */ + return 0; + break; + } + + if (in32(GPIO0_IR) & rb_gpio_pin) + return 1; + return 0; +} + + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + + nand->hwcontrol = ppchameleonevb_hwcontrol; + nand->dev_ready = ppchameleonevb_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/delta/Makefile b/board/delta/Makefile new file mode 100644 index 0000000..e744eec --- /dev/null +++ b/board/delta/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := delta.o nand.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/delta/config.mk b/board/delta/config.mk new file mode 100644 index 0000000..9564625 --- /dev/null +++ b/board/delta/config.mk @@ -0,0 +1,8 @@ +#TEXT_BASE = 0x0 +#TEXT_BASE = 0xa1700000 +#TEXT_BASE = 0xa3080000 +#TEXT_BASE = 0x9ffe0000 +TEXT_BASE = 0xa3008000 + +# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/delta/delta.c b/board/delta/delta.c new file mode 100644 index 0000000..3ffcc2a --- /dev/null +++ b/board/delta/delta.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board mk@tbd: fix this! */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S new file mode 100644 index 0000000..498cf7f --- /dev/null +++ b/board/delta/lowlevel_init.S @@ -0,0 +1,385 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm + + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first ----------------------------------------- */ + mov r10, lr + + /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ + ldr r0, =GPIO97 + ldr r1, =0x801 + str r1, [r0] + + ldr r0, =GPIO98 + ldr r1, =0x801 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ +; wait #300 + +mem_init: + +#define NEW_SDRAM_INIT 1 +#ifdef NEW_SDRAM_INIT + + /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ + ldr r0, =ACCR + ldr r1, [r0] + orr r1, r1, #0x3000 + str r1, [r0] + ldr r1, [r0] + + /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ + ldr r0, =MDCNFG + ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) + /* ldr r1, =0x80000403 */ + str r1, [r0] + ldr r1, [r0] /* delay until written */ + + /* 3. wait nop power up waiting period (200ms) + * optimization: Steps 4+6 can be done during this + */ + wait #300 + + /* 4. Perform an initial Rcomp-calibration cycle */ + ldr r0, =RCOMP + ldr r1, =0x80000000 + str r1, [r0] + ldr r1, [r0] /* delay until written */ + /* missing: program for automatic rcomp evaluation cycles */ + + /* 5. DDR DRAM strobe delay calibration */ + ldr r0, =DDR_HCAL + ldr r1, =0x88000007 + str r1, [r0] + wait #5 + ldr r1, [r0] /* delay until written */ + + /* Set MDMRS */ + ldr r0, =MDMRS + ldr r1, =0x60000033 + str r1, [r0] + wait #300 + + /* Configure MDREFR */ + ldr r0, =MDREFR + ldr r1, =0x00000006 + str r1, [r0] + ldr r1, [r0] + + /* Enable the dynamic memory controller */ + ldr r0, =MDCNFG + ldr r1, [r0] + orr r1, r1, #MDCNFG_DMCEN + str r1, [r0] + + +#else /* NEW_SDRAM_INIT */ + + /* configure the MEMCLKCFG register */ + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[0] to data flash SRAM mode */ + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[1] to data flash SRAM mode */ + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 0 register for SRAM memory */ + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[2] to data flash SRAM mode */ + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[3] to VLIO mode */ + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 1 register for VLIO memory */ + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + +#if 0 + /* This does not work in Zylonite. -SC */ + ldr r0, =0x15fffff0 + ldr r1, =0xb10b + str r1, [r0] + str r1, [r0, #4] +#endif + + /* Configure ACCR Register */ + ldr r0, =ACCR @ ACCR + ldr r1, =0x0180b108 + str r1, [r0] + ldr r1, [r0] + + /* Configure MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, =0x403 + str r1, [r0] + ldr r1, [r0] + + /* Perform Resistive Compensation by configuring RCOMP register */ + ldr r1, =RCOMP @ RCOMP + ldr r2, =0x000000ff + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS0 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0x60000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS1 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0xa0000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDREFR */ + ldr r1, =MDREFR @ MDREFR + ldr r2, =0x00000006 + str r2, [r1] + ldr r2, [r1] + + /* Configure EMPI */ + ldr r1, =EMPI @ EMPI + ldr r2, =0x80000000 + str r2, [r1] + ldr r2, [r1] + + /* Hardware DDR Read-Strobe Delay Calibration */ + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + + /* Here we assume the hardware calibration alwasy be successful. -SC */ + /* Set DMCEN bit in MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, [r0] + orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access + str r1, [r0] + +#endif /* NEW_SDRAM_INIT */ + +#ifndef CFG_SKIP_DRAM_SCRUB + /* scrub/init SDRAM if enabled/present */ + ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 8 words/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b +#endif /* CFG_SKIP_DRAM_SCRUB */ + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +endlowlevel_init: + + mov pc, lr + + +/* +@******************************************************************************** +@ DDR calibration +@ +@ This function is used to calibrate DQS delay lines. +@ Monahans supports three ways to do it. One is software +@ calibration. Two is hardware calibration. Three is hybrid +@ calibration. +@ +@ TBD +@ -SC +ddr_calibration: + + @ Case 1: Write the correct delay value once + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] +*/ +/* @ Case 2: Software Calibration + @ Write test pattern to memory + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] + + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 +ddr_loop1: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 +ddr_loop2: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + +end_loop: + + @ Case 3: Hardware Calibratoin + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr +*/ diff --git a/board/delta/nand.c b/board/delta/nand.c new file mode 100644 index 0000000..c4df6e5 --- /dev/null +++ b/board/delta/nand.c @@ -0,0 +1,590 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CONFIG_NEW_NAND_CODE + +#include <nand.h> +#include <asm/arch/pxa-regs.h> + +#ifdef CFG_DFC_DEBUG1 +# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG1(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG2 +# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG2(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG3 +# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG3(fmt, args...) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +/* These really don't belong here, as they are specific to the NAND Model */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr delta_bbt_descr = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_oobinfo delta_oob = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 6, + .eccpos = {2, 3, 4, 5, 6, 7}, + .oobfree = { {8, 2}, {12, 4} } +}; + + +/* + * not required for Monahans DFC + */ +static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + +#if 0 +/* read device ready pin */ +static int dfc_device_ready(struct mtd_info *mtdinfo) +{ + if(NDSR & NDSR_RDY) + return 1; + else + return 0; + return 0; +} +#endif + +/* + * Write buf to the DFC Controller Data Buffer + */ +static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + int i; + + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + NDDB = *long_buf; + } + } + if(rest) { + printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); + } + return; +} + + +/* + * These functions are quite problematic for the DFC. Luckily they are + * not used in the current nand code, except for nand_command, which + * we've defined our own anyway. The problem is, that we always need + * to write 4 bytes to the DFC Data Buffer, but in these functions we + * don't know if to buffer the bytes/half words until we've gathered 4 + * bytes or if to send them straight away. + * + * Solution: Don't use these with Mona's DFC and complain loudly. + */ +static void dfc_write_word(struct mtd_info *mtd, u16 word) +{ + printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); +} +static void dfc_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); +} + +/* The original: + * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) + * + * Shouldn't this be "u_char * const buf" ? + */ +static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) +{ + int i=0, j; + + /* we have to be carefull not to overflow the buffer if len is + * not a multiple of 4 */ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + + DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); + /* if there are any, first copy multiple of 4 bytes */ + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + *long_buf = NDDB; + } + } + + /* ...then the rest */ + if(rest) { + unsigned long rest_data = NDDB; + for(j=0;j<rest; j++) + buf[i+j] = (u_char) ((rest_data>>j) & 0xff); + } + + return; +} + +/* + * read a word. Not implemented as not used in NAND code. + */ +static u16 dfc_read_word(struct mtd_info *mtd) +{ + printf("dfc_write_byte: UNIMPLEMENTED.\n"); + return 0; +} + +/* global var, too bad: mk@tbd: move to ->priv pointer */ +static unsigned long read_buf = 0; +static int bytes_read = -1; + +/* + * read a byte from NDDB Because we can only read 4 bytes from NDDB at + * a time, we buffer the remaining bytes. The buffer is reset when a + * new command is sent to the chip. + * + * WARNING: + * This function is currently only used to read status and id + * bytes. For these commands always 8 bytes need to be read from + * NDDB. So we read and discard these bytes right now. In case this + * function is used for anything else in the future, we must check + * what was the last command issued and read the appropriate amount of + * bytes respectively. + */ +static u_char dfc_read_byte(struct mtd_info *mtd) +{ + unsigned char byte; + unsigned long dummy; + + if(bytes_read < 0) { + read_buf = NDDB; + dummy = NDDB; + bytes_read = 0; + } + byte = (unsigned char) (read_buf>>(8 * bytes_read++)); + if(bytes_read >= 4) + bytes_read = -1; + + DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); + return byte; +} + +/* calculate delta between OSCR values start and now */ +static unsigned long get_delta(unsigned long start) +{ + unsigned long cur = OSCR; + + if(cur < start) /* OSCR overflowed */ + return (cur + (start^0xffffffff)); + else + return (cur - start); +} + +/* delay function, this doesn't belong here */ +static void wait_us(unsigned long us) +{ + unsigned long start = OSCR; + us *= OSCR_CLK_FREQ; + + while (get_delta(start) < us) { + /* do nothing */ + } +} + +static void dfc_clear_nddb(void) +{ + NDCR &= ~NDCR_ND_RUN; + wait_us(CFG_NAND_OTHER_TO); +} + +/* wait_event with timeout */ +static unsigned long dfc_wait_event(unsigned long event) +{ + unsigned long ndsr, timeout, start = OSCR; + + if(!event) + return 0xff000000; + else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) + timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + else + timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + + while(1) { + ndsr = NDSR; + if(ndsr & event) { + NDSR |= event; + break; + } + if(get_delta(start) > timeout) { + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); + return 0xff000000; + } + + } + return ndsr; +} + +/* we don't always wan't to do this */ +static void dfc_new_cmd(void) +{ + int retry = 0; + unsigned long status; + + while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + /* Clear NDSR */ + NDSR = 0xFFF; + + /* set NDCR[NDRUN] */ + if(!(NDCR & NDCR_ND_RUN)) + NDCR |= NDCR_ND_RUN; + + status = dfc_wait_event(NDSR_WRCMDREQ); + + if(status & NDSR_WRCMDREQ) + return; + + DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); + dfc_clear_nddb(); + } + DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); +} + +/* this function is called after Programm and Erase Operations to + * check for success or failure */ +static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long ndsr=0, event=0; + + /* mk@tbd set appropriate timeouts */ + /* if (state == FL_ERASING) */ + /* timeo = CFG_HZ * 400; */ + /* else */ + /* timeo = CFG_HZ * 20; */ + if(state == FL_WRITING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } else if(state == FL_ERASING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } + + ndsr = dfc_wait_event(event); + + if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) + return(0x1); /* Status Read error */ + return 0; +} + +/* cmdfunc send commands to the DFC */ +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + /* register struct nand_chip *this = mtd->priv; */ + unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; + + /* clear the ugly byte read buffer */ + bytes_read = -1; + read_buf = 0; + + switch (command) { + case NAND_CMD_READ0: + DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (NAND_CMD_READ0 | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_READ1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); + goto end; + case NAND_CMD_READOOB: + DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); + goto end; + case NAND_CMD_READID: + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); + ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_PAGEPROG: + /* sent as a multicommand in NAND_CMD_SEQIN */ + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); + goto end; + case NAND_CMD_ERASE1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); + ndcb1 = (page_addr & 0x00ffffff); + goto write_cmd; + case NAND_CMD_ERASE2: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); + goto end; + case NAND_CMD_SEQIN: + /* send PAGE_PROG command(0x1080) */ + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_WRDREQ; + goto write_cmd; + case NAND_CMD_STATUS: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); + dfc_new_cmd(); + ndcb0 = NAND_CMD_STATUS | (4<<21); + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_RESET: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); + ndcb0 = NAND_CMD_RESET | (5<<21); + event = NDSR_CS0_CMDD; + goto write_cmd; + default: + printk("dfc_cmdfunc: error, unsupported command.\n"); + goto end; + } + + write_cmd: + NDCB0 = ndcb0; + NDCB0 = ndcb1; + NDCB0 = ndcb2; + + /* wait_event: */ + dfc_wait_event(event); + end: + return; +} + +static void dfc_gpio_init(void) +{ + DFC_DEBUG2("Setting up DFC GPIO's.\n"); + + /* no idea what is done here, see zylonite.c */ + GPIO4 = 0x1; + + DF_ALE_WE1 = 0x00000001; + DF_ALE_WE2 = 0x00000001; + DF_nCS0 = 0x00000001; + DF_nCS1 = 0x00000001; + DF_nWE = 0x00000001; + DF_nRE = 0x00000001; + DF_IO0 = 0x00000001; + DF_IO8 = 0x00000001; + DF_IO1 = 0x00000001; + DF_IO9 = 0x00000001; + DF_IO2 = 0x00000001; + DF_IO10 = 0x00000001; + DF_IO3 = 0x00000001; + DF_IO11 = 0x00000001; + DF_IO4 = 0x00000001; + DF_IO12 = 0x00000001; + DF_IO5 = 0x00000001; + DF_IO13 = 0x00000001; + DF_IO6 = 0x00000001; + DF_IO14 = 0x00000001; + DF_IO7 = 0x00000001; + DF_IO15 = 0x00000001; + + DF_nWE = 0x1901; + DF_nRE = 0x1901; + DF_CLE_NOE = 0x1900; + DF_ALE_WE1 = 0x1901; + DF_INT_RnB = 0x1900; +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; + + /* set up GPIO Control Registers */ + dfc_gpio_init(); + + /* turn on the NAND Controller Clock (104 MHz @ D0) */ + CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + +#undef CFG_TIMING_TIGHT +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), + DFC_MAX_tAR); +#else /* this is the tight timing */ + + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), + DFC_MAX_tAR); +#endif /* CFG_TIMING_TIGHT */ + + + DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); + + /* tRP value is split in the register */ + if(tRP & (1 << 4)) { + tRP_high = 1; + tRP &= ~(1 << 4); + } else { + tRP_high = 0; + } + + NDTR0CS0 = (tCH << 19) | + (tCS << 16) | + (tWH << 11) | + (tWP << 8) | + (tRP_high << 6) | + (tRH << 3) | + (tRP << 0); + + NDTR1CS0 = (tR << 16) | + (tWHR << 4) | + (tAR << 0); + + /* If it doesn't work (unlikely) think about: + * - ecc enable + * - chip select don't care + * - read id byte count + * + * Intentionally enabled by not setting bits: + * - dma (DMA_EN) + * - page size = 512 + * - cs don't care, see if we can enable later! + * - row address start position (after second cycle) + * - pages per block = 32 + * - ND_RDY : clears command buffer + */ + /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ + + NDCR = (NDCR_SPARE_EN | /* use the spare area */ + NDCR_DWIDTH_C | /* 16bit DFC data bus width */ + NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ + (2 << 16) | /* read id count = 7 ???? mk@tbd */ + NDCR_ND_ARB_EN | /* enable bus arbiter */ + NDCR_RDYM | /* flash device ready ir masked */ + NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ + NDCR_CS1_PAGEDM | + NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ + NDCR_CS1_CMDDM | + NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ + NDCR_CS1_BBDM | + NDCR_DBERRM | /* double bit error ir masked */ + NDCR_SBERRM | /* single bit error ir masked */ + NDCR_WRDREQM | /* write data request ir masked */ + NDCR_RDDREQM | /* read data request ir masked */ + NDCR_WRCMDREQM); /* write command request ir masked */ + + + /* wait 10 us due to cmd buffer clear reset */ + /* wait(10); */ + + + nand->hwcontrol = dfc_hwcontrol; +/* nand->dev_ready = dfc_device_ready; */ + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_DELAY_US; + nand->options = NAND_BUSWIDTH_16; + nand->waitfunc = dfc_wait; + nand->read_byte = dfc_read_byte; + nand->write_byte = dfc_write_byte; + nand->read_word = dfc_read_word; + nand->write_word = dfc_write_word; + nand->read_buf = dfc_read_buf; + nand->write_buf = dfc_write_buf; + + nand->cmdfunc = dfc_cmdfunc; + nand->autooob = &delta_oob; + nand->badblock_pattern = &delta_bbt_descr; +} + +#else + #error "U-Boot legacy NAND support not available for Monahans DFC." +#endif +#endif diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/delta/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 03ae7fd..84fc3a0 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/ash405/config.mk +++ b/board/esd/ash405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 649619d..e283a92 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -114,7 +114,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int flashcnt; int delay; volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); @@ -238,7 +238,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk index 5c3c01c..0c56c40 100644 --- a/board/esd/cms700/config.mk +++ b/board/esd/cms700/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index d48e972..cad8211 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -23,10 +23,15 @@ */ #include <common.h> + +#ifndef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + #include <command.h> #include <image.h> #include <asm/byteorder.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> #include <fat.h> #include "auto_update.h" @@ -76,9 +81,9 @@ extern block_dev_desc_t *get_dev (char*, int); #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; @@ -259,9 +264,9 @@ int au_do_update(int i, long sz) } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) printf("Updating NAND FLASH with image %s\n", au_image[i].name); - debug ("nand_erase(%lx, %lx);\n", start, end); - rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); - debug ("nand_erase returned %x\n", rc); + debug ("nand_legacy_erase(%lx, %lx);\n", start, end); + rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -283,13 +288,13 @@ int au_do_update(int i, long sz) */ if (au_image[i].type != AU_NAND) { debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((uchar *)addr, start, nbytes); + rc = flash_write((char *)addr, start, nbytes); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, + debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); #endif } if (rc != 0) { @@ -304,7 +309,7 @@ int au_do_update(int i, long sz) rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, + rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, start, nbytes, (size_t *)&total, (uchar *)addr); rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); #endif diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c new file mode 100644 index 0000000..bf796ff --- /dev/null +++ b/board/esd/common/cmd_loadpci.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); +extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); + +#define ADDRMASK 0xfffff000 + +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr = 0; + int count = 0; + int count2 = 0; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + while(1) { + /* + * Mark sync address + */ + ptr = 0; + memset(ptr, 0, 0x20); + + *ptr = 0xffffffff; + puts("\nWaiting for action from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + printf("\nGot bootcode %08x: ", *ptr); + sprintf(addr, "%08x", *ptr & ADDRMASK); + + switch (*ptr & ~ADDRMASK) { + case 0: + /* + * Boot image via bootm + */ + printf("booting image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + do_bootm (cmdtp, 0, 0, NULL); + break; + + case 1: + /* + * Boot image via autoscr + */ + printf("executing script at addr 0x%s ...\n", addr); + + local_args[0] = addr; + local_args[1] = NULL; + do_autoscript(cmdtp, 0, 1, local_args); + break; + + case 2: + /* + * Call run_cmd + */ + printf("running command at addr 0x%s ...\n", addr); + run_command ((char*)(*ptr & ADDRMASK), 0); + break; + + default: + printf("unhandled boot method\n"); + break; + } + } +} + +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "loadpci - Wait for pci bootcmd and boot it\n", + NULL + ); + +#endif diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 0edc083..196171c 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Detect epson */ + lcd_reg[0] = 0x00; + lcd_reg[1] = 0x00; + if (lcd_reg[0] == 0x1c) { /* * Big epson detected diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index a60495a..88b0ae3 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ../common/misc.o +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index df10c0e..1a27ca0 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,17 +31,15 @@ int board_early_init_f (void) unsigned long cntrl0Reg; /* - * Setup GPIO pins (CS4+CS7 as GPIO) + * Setup GPIO pins */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00900000); + mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); /* set output pins to high */ - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); - /* INTA# is open drain */ - out32(GPIO0_ODR, CFG_INTA_FAKE); - /* setup for output */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); + out32(GPIO0_OR, CFG_EEPROM_WP); + /* setup for output (LED=off) */ + out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -130,16 +128,6 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - #if defined(CFG_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state @@ -207,8 +195,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL - ); + eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL + ); #endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 0be45c7..ceff4c4 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -38,3 +38,6 @@ TEXT_BASE = 0xFFFD0000 endif endif endif + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 0486729..cd38b2d 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -29,7 +29,7 @@ SOBJS = misc.o OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ mv_eth.o mpsc.o i2c.o \ - sdram_init.o strataflash.o ide.o + sdram_init.o ide.o $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index e4b062b..dbed597 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -56,6 +56,7 @@ extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); +extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ @@ -363,6 +364,21 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif + if (flash_info[3].size < CFG_FLASH_INCREMENT) { + unsigned int flash_offset; + unsigned int l; + + flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + if (flash_info[3].start[l] != 0) { + flash_info[3].start[l] += flash_offset; + } + } + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + } return 0; } diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index 3e44fb9..c335ebf 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, }; +#ifdef CONFIG_USE_CPCIDVI +typedef struct { + unsigned int base; + unsigned int init; +} GT_CPCIDVI_ROM_T; + +static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; +#endif #ifdef DEBUG static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; @@ -125,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = { /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, @@ -172,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. +* spec) +* pciDevNum: The device number needs to be addressed. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, @@ -220,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * * The configuration Address is configure as type-I (bits[1:0] = '01') due to * PCI spec referring to P2P. @@ -265,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host, /******************************************************************** * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, @@ -385,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) /******************************************************************** * pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! +* - If the PCI size is 0 then this base address has no meaning!!! * * * INPUT: Bus, Region - The bus and region we ask for its base address. @@ -493,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. +* feature bits given as an input. +* - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, @@ -533,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, /******************************************************************** * pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. +* to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. @@ -580,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host) * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, @@ -611,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. * * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, @@ -647,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, /******************************************************************** * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. * * Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. +* grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) @@ -670,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) /******************************************************************** * pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. * * Inputs: N/A * Returns: true. @@ -689,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host) /******************************************************************** * pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. +* For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. * * Returns: true. *********************************************************************/ @@ -715,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, @@ -746,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, GT_REG_WRITE (snoopXtopAddress, 0); return true; } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ data = (baseAddress >> 20) | snoopType << 12; GT_REG_WRITE (snoopXbaseAddress, data); snoopHigh = (snoopHigh & 0xfff00000) >> 20; @@ -800,23 +808,65 @@ static void gt_setup_ide (struct pci_controller *hose, unsigned int offset = (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); pciauto_region_allocate (bar_response & PCI_BASE_ADDRESS_SPACE_IO ? hose-> pci_io : hose->pci_mem, ide_bar[bar], &bar_value); - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); } } +#ifdef CONFIG_USE_CPCIDVI +static void gt_setup_cpcidvi (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + u32 bar_value, pci_response; + + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); + pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); + pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); + gt_cpcidvi_rom.base = bar_value & 0xffffff00; + gt_cpcidvi_rom.init = 1; +} + +unsigned char gt_cpcidvi_in8(unsigned int offset) +{ + unsigned char data; + + if (gt_cpcidvi_rom.init == 0) { + return(0); + } + data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); + return(data); +} + +void gt_cpcidvi_out8(unsigned int offset, unsigned char data) +{ + unsigned int off; -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ + if (gt_cpcidvi_rom.init == 0) { + return; + } + off = data; + off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; + in8(off); + return; +} +#endif + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ /* and is curently not called *. */ #if 0 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) @@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) #endif struct pci_config_table gt_config_table[] = { +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, +#endif {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} }; @@ -857,10 +910,21 @@ void pci_init_board (void) #ifdef CONFIG_PCI_PNP unsigned int bar; #endif - #ifdef DEBUG gt_pci_bus_mode_display (PCI_HOST0); #endif +#ifdef CONFIG_USE_CPCIDVI + gt_cpcidvi_rom.init = 0; + gt_cpcidvi_rom.base = 0; +#endif + + pci0_hose.config_table = gt_config_table; + pci1_hose.config_table = gt_config_table; + +#ifdef CONFIG_USE_CPCIDVI + gt_config_table[0].config_device = gt_setup_cpcidvi; +#endif + gt_config_table[1].config_device = gt_setup_ide; pci0_hose.first_busno = 0; pci0_hose.last_busno = 0xff; diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c deleted file mode 100644 index c22fe5d..0000000 --- a/board/esd/cpci750/strataflash.c +++ /dev/null @@ -1,763 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/cache.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - invalidate_dcache_range(base, base+0x400); - - if(flash_detect_cfi(info)){ - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk index 7129ad5..798a3fa 100644 --- a/board/esd/hh405/config.mk +++ b/board/esd/hh405/config.mk @@ -29,3 +29,6 @@ TEXT_BASE = 0xFFF80000 #TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c index 58ee3a8..64bca46 100644 --- a/board/esd/hh405/fpgadata.c +++ b/board/esd/hh405/fpgadata.c @@ -1,2520 +1,2517 @@ - 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0x00,0xcd,0x58,0xd0,0x70,0x13,0xda,0x5d,0x94,0xd2,0xf4,0xcc,0x31,0x7b,0x69,0xdb, + 0x97,0x85,0x60,0xba,0x87,0x81,0x39,0x36,0x7e,0x0a,0x03,0x4e,0x30,0xfd,0x2b,0xc6, + 0xcc,0x09,0x67,0xe5,0xc5,0xd7,0x5f,0x09,0xa6,0x7b,0x30,0xe7,0xcc,0xdf,0x69,0x66, + 0xbf,0x63,0x3a,0xc1,0xf4,0x9f,0x78,0xf8,0xe0,0x11,0xa7,0xe3,0x93,0xa7,0xb7,0x04, + 0xd3,0x3d,0xce,0xbf,0x18,0x7f,0x50,0xf3,0x1f,0x5f,0x73,0xdc,0x86,0x47,0x57,0x54, + 0x83,0x9b,0xff,0x65,0x18,0x3f,0x5b,0x20,0xa8,0xf9,0x6f,0xce,0x9e,0x9e,0x87,0x7b, + 0x76,0x7c,0xbe,0x29,0x98,0xee,0x71,0xfe,0xc5,0xf8,0x03,0x8b,0xff,0xb5,0x6d,0x1f, + 0xd3,0xa5,0xcf,0xcf,0xa8,0xb7,0x6f,0x7a,0x47,0x32,0xe7,0x06,0x30,0x7e,0x0e,0x05, + 0x17,0xff,0x1a,0xd9,0x00,0xab,0x63,0xf7,0x06,0x17,0xff,0x62,0xfc,0x41,0xcd,0x7f, + 0x22,0x6d,0x0d,0xc3,0xba,0xeb,0xd9,0xa0,0xe2,0xc7,0xac,0x39,0x2c,0x7f,0x9a,0xf3, + 0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1, + 0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe, + 0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3, + 0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd, + 0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff, + 0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f, + 0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06, + 0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1, + 0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09, + 0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b, + 0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 3158803..99fd556 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,7 +34,6 @@ #include <pci.h> #include <sm501.h> - #ifdef CONFIG_VIDEO_SM501 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ @@ -66,10 +68,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -100,10 +104,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -144,10 +150,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -178,10 +186,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -272,6 +282,9 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); +/* + * Get version of HH405 board from GPIO's + */ int board_revision(void) { unsigned long osrh_reg; @@ -280,10 +293,6 @@ int board_revision(void) unsigned long value; /* - * Get version of HH405 board from GPIO's - */ - - /* * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) */ osrh_reg = in32(GPIO0_OSRH); @@ -305,15 +314,13 @@ int board_revision(void) if (value & 0x80000000) { /* Revision 1.0 or 1.1 detected */ - return 0x0101; + return 1; } else { if (value & 0x00400000) { /* unused */ - return 0x0103; + return 3; } else { - /* Revision >= 2.0 detected */ - /* rev. 2.x uses four SM501 GPIOs for revision coding */ - return 0x0200; + return 2; } } } @@ -349,6 +356,38 @@ int board_early_init_f (void) return 0; } +int cf_enable(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + + volatile unsigned short *fpga_ctrl = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + + if (gd->board_type >= 2) { + if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) { + if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN; + + for (i=0; i<300; i++) + udelay(1000); + + *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + + for (i=0; i<20; i++) + udelay(1000); + } + } else { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN; + } + } + + return 0; +} int misc_init_r (void) { @@ -433,9 +472,6 @@ int misc_init_r (void) * Write Board revision into FPGA */ *fpga_ctrl |= gd->board_type & 0x0003; - if (gd->board_type >= 0x0200) { - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; - } /* * Setup and enable EEPROM write protection @@ -471,7 +507,7 @@ int misc_init_r (void) contrast0 = simple_strtol(str, NULL, 16); if (contrast0 > 255) { printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); - contrast0 = 0; + contrast0 = 0xffffffff; } } @@ -544,9 +580,9 @@ int misc_init_r (void) */ *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; /* - * Set lcd clock (small epson) + * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330; + *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE; lcd_setup(0, 1); lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, @@ -565,8 +601,10 @@ int misc_init_r (void) puts("VGA: SM501 with 8 MB "); if (strcmp(str, "ppc221") == 0) { printf("(800*600, %dbpp)\n", BPP); + *lcd_backlight = 0x002d; /* max. allowed brightness */ } else if (strcmp(str, "ppc231") == 0) { printf("(1024*768, %dbpp)\n", BPP); + *lcd_backlight = 0x0000; } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; @@ -578,6 +616,8 @@ int misc_init_r (void) #endif /* CONFIG_VIDEO_SM501 */ } + cf_enable(); + return (0); } @@ -590,7 +630,7 @@ int checkboard (void) { DECLARE_GLOBAL_DATA_PTR; - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -608,14 +648,7 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev %ld.%ld)\n", - (gd->board_type >> 8) & 0xff, - gd->board_type & 0xff); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + printf(", Rev %ld.x)\n", gd->board_type); return 0; } @@ -637,35 +670,34 @@ long int initdram (int board_type) } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { + DECLARE_GLOBAL_DATA_PTR; + volatile unsigned short *fpga_mode = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) || + (gd->board_type < 2)) { + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + cf_enable(); + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } } } #endif /* CONFIG_IDE_RESET */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) @@ -778,8 +810,7 @@ void video_get_info_str (int line_number, char *info) strcat(str, " (Missing bd_type!"); } - sprintf(str2, ", Rev %ld.%ld)", - (gd->board_type >> 8) & 0xff, gd->board_type & 0xff); + sprintf(str2, ", Rev %ld.x)", gd->board_type); strcat(str, str2); strcpy(info, str); } else { @@ -822,7 +853,11 @@ unsigned int board_video_get_fb (void) devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); if (devbusfn != -1) { pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - return (addr & 0xfffffffe); + addr &= 0xfffffffe; +#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET + addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; +#endif + return addr; } return 0; @@ -875,3 +910,15 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk index a6d31aa..4c60c35 100644 --- a/board/esd/hub405/config.mk +++ b/board/esd/hub405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index e77dba8..0c6771f 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -265,7 +265,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 25b2105..916b285 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -27,3 +27,6 @@ TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 5b9d063..37b92fb 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -269,7 +269,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index 1281be7..741e4aa 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -30,7 +30,7 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -OBJS = $(BOARD).o ../common/misc.o $(CPLD) +OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 33b5f77..f9e4d43 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -1,6 +1,9 @@ /* * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. @@ -66,16 +69,27 @@ int board_early_init_f (void) mtebc (epcr, 0xa8400000); /* - * Setup GPIO pins (CS6+CS7 as GPIO) + * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000); - /* - * Configure GPIO pins + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \ + CFG_FPGA_DONE | \ + CFG_XEREADY | \ + CFG_NONMONARCH | \ + CFG_REV1_2) << 5)); + + if (!(in32(GPIO0_IR) & CFG_REV1_2)) { + /* rev 1.2 boards */ + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \ + CFG_SELF_RST) << 5)); + } + + out32(GPIO0_OR, 0); + out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */ + + /* - check if rev1_2 is low, then: + * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST# */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */ - out32(GPIO0_OR, 0); /* outputs -> low */ return 0; } @@ -83,11 +97,6 @@ int board_early_init_f (void) /* ------------------------------------------------------------------------- */ -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - int misc_init_r (void) { @@ -97,16 +106,30 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */ return (0); } +ushort pmc405_pci_subsys_deviceid(void) +{ + ulong val; + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + if (val & CFG_NONMONARCH) { /* monarch# signal */ + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_MONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; +} /* * Check Board Identity: */ - int checkboard (void) { + ulong val; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); @@ -118,12 +141,18 @@ int checkboard (void) puts(str); } - putc ('\n'); + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + puts(" rev1.2 ("); + if (val & CFG_NONMONARCH) { /* monarch# signal */ + puts("non-"); + } + puts("monarch)"); + } else { + puts(" <=rev1.1"); + } - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + putc ('\n'); return 0; } @@ -145,17 +174,19 @@ long int initdram (int board_type) return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ -int testdram (void) +/* ------------------------------------------------------------------------- */ +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } -/* ------------------------------------------------------------------------- */ int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk index 219a4eb..72e8103 100644 --- a/board/esd/voh405/config.mk +++ b/board/esd/voh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFF80000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index eda3fd9..22995b5 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -343,7 +343,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index 445b8fc..bc5fa7c 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -97,7 +97,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); int flashcnt; int delay; diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/wuh405/config.mk +++ b/board/esd/wuh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index db24122..5a1a3f3 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile new file mode 100644 index 0000000..c9b3c92 --- /dev/null +++ b/board/ezkit533/Makefile @@ -0,0 +1,44 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ezkit533.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk new file mode 100644 index 0000000..36c9f99 --- /dev/null +++ b/board/ezkit533/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c new file mode 100644 index 0000000..f8ee900 --- /dev/null +++ b/board/ezkit533/ezkit533.c @@ -0,0 +1,71 @@ +/* + * U-boot - ezkit533.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_MISC_INIT_R) +#include "psd4256.h" +#endif + +int checkboard(void) +{ + printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf("Board: ADI BF533 EZ-Kit Lite board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + printf(" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram(int board_type) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG + int brate; + char *tmp = getenv("baudrate"); + brate = simple_strtoul(tmp, NULL, 16); + printf("Serial Port initialized with Baud rate = %x\n",brate); + printf("SDRAM attributes:\n"); + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", + 3, 3, 6, 2, 3); + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return CFG_MAX_RAM_SIZE; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + /* Set direction bits for Video en/decoder reset as output */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; + /* Deactivate Video en/decoder reset lines */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; +} +#endif diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h new file mode 100644 index 0000000..8f9dff5 --- /dev/null +++ b/board/ezkit533/flash-defines.h @@ -0,0 +1,130 @@ +/* + * U-boot - flash-defines.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FLASHDEFINES_H__ +#define __FLASHDEFINES_H__ + +#include <common.h> + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) +#define TRUE 0x1 +#define FALSE 0x0 +#define BUFFER_SIZE 0x80000 +#define NO_COMMAND 0 +#define GET_CODES 1 +#define RESET 2 +#define WRITE 3 +#define FILL 4 +#define ERASE_ALL 5 +#define ERASE_SECT 6 +#define READ 7 +#define GET_SECTNUM 8 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define FLASH_MAN_ST 2 +#define CFG_FLASH0_BASE 0x20000000 +#define RESET_VAL 0xF0 + + +asm("#define FLASH_START_L 0x0000"); +asm("#define FLASH_START_H 0x2000"); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +int get_codes(void); +int poll_toggle_bit(long lOffset); +void reset_flash(void); +int erase_flash(void); +int erase_block_flash(int,unsigned long); +void unlock_flash(long lOffset); +int write_data(long lStart, long lCount, long lStride, int *pnData); +int FillData(long lStart, long lCount, long lStride, int *pnData); +int read_data(long lStart, long lCount, long lStride, int *pnData); +int read_flash(long nOffset, int *pnValue); +int write_flash(long nOffset, int nValue); +void get_sector_number(long lOffset, int *pnSector); +int GetSectorProtectionStatus(flash_info_t * info, int nSector); +int GetOffset(int nBlock); +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + +#define WRITESEQ1 0x0AAA +#define WRITESEQ2 0x0554 +#define WRITESEQ3 0x0AAA +#define WRITESEQ4 0x0AAA +#define WRITESEQ5 0x0554 +#define WRITESEQ6 0x0AAA +#define WRITEDATA1 0xaa +#define WRITEDATA2 0x55 +#define WRITEDATA3 0x80 +#define WRITEDATA4 0xaa +#define WRITEDATA5 0x55 +#define WRITEDATA6 0x10 +#define PriFlashABegin 0 +#define SecFlashABegin 32 +#define SecFlashBBegin 36 +#define PriFlashAOff 0x0 +#define PriFlashBOff 0x100000 +#define SecFlashAOff 0x200000 +#define SecFlashBOff 0x280000 +#define INVALIDLOCNSTART 0x20270000 +#define INVALIDLOCNEND 0x20280000 +#define BlockEraseVal 0x30 +#define UNLOCKDATA1 0xaa +#define UNLOCKDATA2 0x55 +#define UNLOCKDATA3 0xa0 +#define GETCODEDATA1 0xaa +#define GETCODEDATA2 0x55 +#define GETCODEDATA3 0x90 +#define SecFlashASec1Off 0x200000 +#define SecFlashASec2Off 0x204000 +#define SecFlashASec3Off 0x206000 +#define SecFlashASec4Off 0x208000 +#define SecFlashAEndOff 0x210000 +#define SecFlashBSec1Off 0x280000 +#define SecFlashBSec2Off 0x284000 +#define SecFlashBSec3Off 0x286000 +#define SecFlashBSec4Off 0x288000 +#define SecFlashBEndOff 0x290000 + +#define SECT32 32 +#define SECT33 33 +#define SECT34 34 +#define SECT35 35 +#define SECT36 36 +#define SECT37 37 +#define SECT38 38 +#define SECT39 39 + +#define FLASH_SUCCESS 0 +#define FLASH_FAIL -1 + +#endif diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c new file mode 100644 index 0000000..b0a0796 --- /dev/null +++ b/board/ezkit533/flash.c @@ -0,0 +1,476 @@ +/* + * U-boot - flash.c Flash driver for PSD4256GV + * + * Copyright (c) 2005 blackfin.uclinux.org + * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "flash-defines.h" + +void flash_reset(void) +{ + reset_flash(); +} + +unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, + int bank_flag) +{ + int id = 0, i = 0; + static int FlagDev = 1; + + id = get_codes(); + if(FlagDev) { +#ifdef DEBUG + printf("Device ID of the Flash is %x\n", id); +#endif + FlagDev = 0; + } + info->flash_id = id; + + switch (bank_flag) { + case 0: + for (i = PriFlashABegin; i < SecFlashABegin; i++) + info->start[i] = (baseaddr + (i * AFP_SectorSize1)); + info->size = 0x200000; + info->sector_count = 32; + break; + case 1: + info->start[0] = baseaddr + SecFlashASec1Off; + info->start[1] = baseaddr + SecFlashASec2Off; + info->start[2] = baseaddr + SecFlashASec3Off; + info->start[3] = baseaddr + SecFlashASec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + case 2: + info->start[0] = baseaddr + SecFlashBSec1Off; + info->start[1] = baseaddr + SecFlashBSec2Off; + info->start[2] = baseaddr + SecFlashBSec3Off; + info->start[3] = baseaddr + SecFlashBSec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + } + return (info->size); +} + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1, size_b2; + int i; + + size_b0 = size_b1 = size_b2 = 0; +#ifdef DEBUG + printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); + printf("Memory Map for the Flash\n"); + printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); + printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); + printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n"); + printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); + printf("Please type command flinfo for information on Sectors \n"); +#endif + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); + size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); + size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]); + + return (size_b0 + size_b1 + size_b2); +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id) { + case FLASH_PSD4256GV: + printf("ST Microelectronics "); + break; + default: + printf("Unknown Vendor "); + break; + } + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int cnt = 0,i; + int prot,sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + cnt = s_last - s_first + 1; + + if (cnt == FLASH_TOT_SECT) { + printf("Erasing flash, Please Wait \n"); + if(erase_flash() < 0) { + printf("Erasing flash failed \n"); + return FLASH_FAIL; + } + } else { + printf("Erasing Flash locations, Please Wait\n"); + for (i = s_first; i <= s_last; i++) { + if (info->protect[i] == 0) { /* not protected */ + if(erase_block_flash(i, info->start[i]) < 0) { + printf("Error Sector erasing \n"); + return FLASH_FAIL; + } + } + } + } + return FLASH_SUCCESS; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int ret; + + ret = write_data(addr, cnt, 1, (int *) src); + if(ret == FLASH_FAIL) + return ERR_NOT_ERASED; + return FLASH_SUCCESS; +} + + +int write_data(long lStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + unsigned long ulOffset = lStart - CFG_FLASH_BASE; + int d; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; (j < iNumWords); + j++, ulOffset += (lStride * 2)) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) { + printf("Invalid locations, Try writing to another location \n"); + return FLASH_FAIL; + } + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + iShift += 16; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash already programmed. Please erase to reprogram \n"); + printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, pnData[i]) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + } + return FLASH_SUCCESS; +} + +int read_data(long ulStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + long ulOffset = ulStart; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nHi, nLow; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; j < iNumWords; j += 2) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &nLow); + ulOffset += (lStride * 2); + read_flash(ulOffset, &nHi); + ulOffset += (lStride * 2); + pnData[i] = (nHi << 16) | nLow; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &pnData[i]); + } + return FLASH_SUCCESS; +} + +int write_flash(long nOffset, int nValue) +{ + long addr; + + addr = (CFG_FLASH_BASE + nOffset); + asm("ssync;"); + *(unsigned volatile short *) addr = nValue; + asm("ssync;"); + if(poll_toggle_bit(nOffset) < 0) + return FLASH_FAIL; + return FLASH_SUCCESS; +} + +int read_flash(long nOffset, int *pnValue) +{ + int nValue = 0x0; + long addr = (CFG_FLASH_BASE + nOffset); + + if (nOffset != 0x2) + reset_flash(); + asm("ssync;"); + nValue = *(volatile unsigned short *) addr; + asm("ssync;"); + *pnValue = nValue; + return TRUE; +} + +int poll_toggle_bit(long lOffset) +{ + unsigned int u1,u2; + unsigned long timeout = 0xFFFFFFFF; + volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset); + while(1) { + if(timeout < 0) + break; + u1 = *(volatile unsigned short *)FB; + u2 = *(volatile unsigned short *)FB; + if((u1 & 0x0040) == (u2 & 0x0040)) + return FLASH_SUCCESS; + if((u2 & 0x0020) == 0x0000) + continue; + u1 = *(volatile unsigned short *)FB; + if((u2 & 0x0040) == (u1 & 0x0040)) + return FLASH_SUCCESS; + else { + reset_flash(); + return FLASH_FAIL; + } + timeout--; + } + printf("Time out occured \n"); + if(timeout <0) return FLASH_FAIL; +} + +void reset_flash(void) +{ + write_flash(WRITESEQ1, RESET_VAL); + /* Wait for 10 micro seconds */ + udelay(10); +} + +int erase_flash(void) +{ + write_flash(WRITESEQ1, WRITEDATA1); + write_flash(WRITESEQ2, WRITEDATA2); + write_flash(WRITESEQ3, WRITEDATA3); + write_flash(WRITESEQ4, WRITEDATA4); + write_flash(WRITESEQ5, WRITEDATA5); + write_flash(WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(0x0000) < 0) + return FLASH_FAIL; + + write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashASec1Off) < 0) + return FLASH_FAIL; + + write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(PriFlashBOff) <0) + return FLASH_FAIL; + + write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashBOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +int erase_block_flash(int nBlock, unsigned long address) +{ + long ulSectorOff = 0x0; + + if ((nBlock < 0) || (nBlock > AFP_NumSectors)) + return FALSE; + + ulSectorOff = (address - CFG_FLASH_BASE); + + write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); + write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); + write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); + write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); + write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); + + write_flash(ulSectorOff, BlockEraseVal); + + if(poll_toggle_bit(ulSectorOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +void unlock_flash(long ulOffset) +{ + unsigned long ulOffsetAddr = ulOffset; + ulOffsetAddr &= 0xFFFF0000; + + write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); + write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); + write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); +} + +int get_codes() +{ + int dev_id = 0; + + write_flash(WRITESEQ1, GETCODEDATA1); + write_flash(WRITESEQ2, GETCODEDATA2); + write_flash(WRITESEQ3, GETCODEDATA3); + + read_flash(0x0002, &dev_id); + dev_id &= 0x00FF; + + reset_flash(); + + return dev_id; +} + +void get_sector_number(long ulOffset, int *pnSector) +{ + int nSector = 0; + + if (ulOffset >= SecFlashAOff) { + if ((ulOffset < SecFlashASec1Off) + && (ulOffset < SecFlashASec2Off)) { + nSector = SECT32; + } else if ((ulOffset >= SecFlashASec2Off) + && (ulOffset < SecFlashASec3Off)) { + nSector = SECT33; + } else if ((ulOffset >= SecFlashASec3Off) + && (ulOffset < SecFlashASec4Off)) { + nSector = SECT34; + } else if ((ulOffset >= SecFlashASec4Off) + && (ulOffset < SecFlashAEndOff)) { + nSector = SECT35; + } + } else if (ulOffset >= SecFlashBOff) { + if ((ulOffset < SecFlashBSec1Off) + && (ulOffset < SecFlashBSec2Off)) { + nSector = SECT36; + } + if ((ulOffset < SecFlashBSec2Off) + && (ulOffset < SecFlashBSec3Off)) { + nSector = SECT37; + } + if ((ulOffset < SecFlashBSec3Off) + && (ulOffset < SecFlashBSec4Off)) { + nSector = SECT38; + } + if ((ulOffset < SecFlashBSec4Off) + && (ulOffset < SecFlashBEndOff)) { + nSector = SECT39; + } + } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) { + nSector = ulOffset & 0xffff0000; + nSector = ulOffset >> 16; + nSector = nSector & 0x000ff; + } + + if ((nSector >= 0) && (nSector < AFP_NumSectors)) { + *pnSector = nSector; + } +} diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h new file mode 100644 index 0000000..01f6566 --- /dev/null +++ b/board/ezkit533/psd4256.h @@ -0,0 +1,67 @@ +/* + * U-boot - psd4256.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Flash A/B Port A configuration registers. + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTA_DIN 0x070000 +#define PSD_PORTA_DOUT 0x070004 +#define PSD_PORTA_DIR 0x070006 + +/* + * Flash A/B Port B configuration registers + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTB_DIN 0x070001 +#define PSD_PORTB_DOUT 0x070005 +#define PSD_PORTB_DIR 0x070007 + +/* + * Flash A Port A Bit definitions + */ + +#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ +#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ +#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ +#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ +#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ + +/* + * Flash A Port B Bit definitions + */ + +#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ +#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ +#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ +#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ +#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ +#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds new file mode 100644 index 0000000..10203ff --- /dev/null +++ b/board/ezkit533/u-boot.lds @@ -0,0 +1,148 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + board/ezkit533/ezkit533.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/fads.c b/board/fads/fads.c index 013b3cb..7b04af5 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -726,24 +726,23 @@ static void checkdboard(void) int checkboard (void) { - /* get revision from BCSR 3 */ +#if defined(CONFIG_MPC86xADS) + puts ("Board: MPC86xADS\n"); +#elif defined(CONFIG_MPC885ADS) + puts ("Board: MPC885ADS\n"); +#else /* Only old ADS/FADS have got revision ID in BCSR3 */ uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) | (((*((uint *) BCSR3) >> 19) & 1) << 2) | (((*((uint *) BCSR3) >> 16) & 3)); puts ("Board: "); - -#if defined(CONFIG_MPC86xADS) - puts ("MPC86xADS"); -#elif defined(CONFIG_MPC885ADS) - puts ("MPC885ADS"); - r = 0; /* I've got NR (No Revision) board */ -#elif defined(CONFIG_FADS) +#if defined(CONFIG_FADS) puts ("FADS"); checkdboard (); #else puts ("ADS"); #endif + puts (" rev "); switch (r) { @@ -758,13 +757,9 @@ int checkboard (void) puts ("A - warning, read errata \n"); break; case 0x03: - puts ("B \n"); + puts ("B\n"); break; -#elif defined(CONFIG_MPC885ADS) - case 0x00: - puts ("NR\n"); - break; -#else /* FADS and newer */ +#else /* FADS */ case 0x00: puts ("ENG\n"); break; @@ -776,6 +771,7 @@ int checkboard (void) printf ("unknown (0x%x)\n", r); return -1; } +#endif /* CONFIG_MPC86xADS */ return 0; } @@ -848,7 +844,7 @@ int pcmcia_init(void) switch ((pcmp->pcmc_pipr >> 14) & 3) #endif { - case 0x00 : + case 0x03 : printf("5V"); v = 5; break; @@ -860,7 +856,7 @@ int pcmcia_init(void) v = 5; #endif break; - case 0x03 : + case 0x00 : printf("5V, 3V and x.xV"); #ifdef CONFIG_FADS v = 3; /* User lower voltage if supported! */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 1127c7f..e981be0 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -55,18 +55,26 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NFSBOOTCOMMAND \ "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ "bootm" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ + "bootm fe080000" + +#undef CONFIG_BOOTARGS + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ /* - * New MPC86xADS and Duet provide two Ethernet connectivity options: + * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * got FEC so FEC is the default. @@ -89,7 +97,9 @@ #ifndef CONFIG_COMMANDS #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ @@ -104,16 +114,18 @@ /* * Miscellaneous configurable options */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -126,6 +138,7 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ + /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ @@ -148,6 +161,14 @@ #define CFG_SDRAM_BASE 0x00000000 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +/* + * 2048 SDRAM rows + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) #elif defined(CONFIG_FADS) /* Old/new FADS */ #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ #else /* Old ADS */ @@ -223,9 +244,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif /*----------------------------------------------------------------------- * I2C configuration @@ -277,31 +296,21 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) +#define CFG_SCCR SCCR_TBS /*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + * DER - Debug Enable Register *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#ifndef CFG_PLPRCR -#define CFG_PLPRCR PLPRCR_TEXPS -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * + * Set to zero to prevent the processor from entering debug mode */ #define CFG_DER 0 -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ +/* Because of the way the 860 starts up and assigns CS0 the entire + * address space, we have to set the memory controller differently. + * Normally, you write the option register first, and then enable the + * chip select by writing the base register. For CS0, you must write + * the base register first, followed by the option register. + */ /* * Init Memory Controller: @@ -335,9 +344,6 @@ /* values according to the manual */ -#define PCMCIA_MEM_ADDR ((uint)0xFF020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - #define BCSR0 ((uint) (BCSR_ADDR + 0x00)) #define BCSR1 ((uint) (BCSR_ADDR + 0x04)) #define BCSR2 ((uint) (BCSR_ADDR + 0x08)) @@ -396,59 +402,28 @@ #define BCSR4_TFPLDL ((uint)0x40000000) #define BCSR4_TPSQEL ((uint)0x20000000) #define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#ifdef CONFIG_MPC823 +#if defined(CONFIG_MPC823) #define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 +#elif defined(CONFIG_MPC850) #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ +#elif defined(CONFIG_MPC860SAR) +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#else /* MPC860T and other chips with FEC */ +#define BCSR4_FETH_EN ((uint)0x08000000) +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#define BCSR4_FETHFDE ((uint)0x02000000) +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#define BCSR4_FETHRST ((uint)0x00200000) +#endif -/* BSCR5 exists on MPC86xADS and Duet ADS only */ +/* BSCR5 exists on MPC86xADS and MPC885ADS only */ #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) @@ -511,4 +486,4 @@ #define CFG_ATA_ALT_OFFSET 0x0000 #define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ +/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 3f78753..39b5c70 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -185,7 +185,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/lart/flash.c b/board/lart/flash.c index 5232ed2..28c4531 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -348,7 +348,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index 2dfe376..d18720e 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -351,8 +351,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c index fb91843..f156342 100644 --- a/board/m5272c3/flash.c +++ b/board/m5272c3/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c index ff70783..95f35ad 100644 --- a/board/m5282evb/flash.c +++ b/board/m5282evb/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile new file mode 100644 index 0000000..7fdc088 --- /dev/null +++ b/board/mcc200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk new file mode 100644 index 0000000..fa55673 --- /dev/null +++ b/board/mcc200/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MCC200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c new file mode 100644 index 0000000..d1c99fd --- /dev/null +++ b/board/mcc200/mcc200.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +#include "mt48lc8m32b2-6-7.h" + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +ulong flash_get_size (ulong base, int banknum); + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard (void) +{ + puts ("Board: MCC200\n"); + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(gd->bd->bi_flashstart); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/mcc200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000..13aebbd --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds new file mode 100644 index 0000000..4fdea6b --- /dev/null +++ b/board/mcc200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/config.mk b/board/netphone/config.mk index 8497ebc..de179c2 100644 --- a/board/netphone/config.mk +++ b/board/netphone/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index dd03e4b..297de97 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -599,7 +599,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netstar/Makefile b/board/netstar/Makefile new file mode 100644 index 0000000..3a20501 --- /dev/null +++ b/board/netstar/Makefile @@ -0,0 +1,85 @@ +# +# (C) Copyright 2005 +# Ladislav Michl, 2N Telekomunikace, michl@2n.cz +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := netstar.o flash.o nand.o +SOBJS := setup.o crcek.o + +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds + +HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include + +all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ + -L$(gcclibdir) -lgcc + $(OBJCOPY) -O srec $(<:.o=) $@ + +eeprom.bin: eeprom.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcek.srec: crcek.o + $(LD) -g -Ttext 0x00000000 \ + -o $(<:.o=) -e $(<:.o=) $^ + $(OBJCOPY) -O srec $(<:.o=) $@ + +crcek.bin: crcek.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcit: crcit.o crc32.o + $(HOSTCC) $(HOST_CFLAGS) -o $@ $^ + +crcit.o: crcit.c + $(HOSTCC) $(HOST_CFLAGS) -c $< + +crc32.o: $(TOPDIR)/tools/crc32.c + $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $< + +clean: + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \ + crcek crcek.srec crcek.bin + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netstar/config.mk b/board/netstar/config.mk new file mode 100644 index 0000000..50d647a --- /dev/null +++ b/board/netstar/config.mk @@ -0,0 +1,14 @@ +# +# Linux-Kernel is expected to be at 1000'8000, +# entry 1000'8000 (mem base + reserved) +# +# We load ourself to internal RAM at 2001'2000 +# Check map file when changing TEXT_BASE. +# Everything has fit into 192kB internal SRAM! +# + +# XXX TEXT_BASE = 0x20012000 +TEXT_BASE = 0x13FC0000 + +# Compile the new NAND code +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S new file mode 100644 index 0000000..6ca4d11 --- /dev/null +++ b/board/netstar/crcek.S @@ -0,0 +1,177 @@ +/** + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2. + * + * Image layout looks like following: + * u32 - size + * u32 - version + * ... - data + * u32 - crc32 + */ + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + mov r0, #0 + ldr r1, \offset + ldr r2, [r1] + cmp r2, r0 @ no data, no problem + beq 2f + tst r2, #3 @ unaligned size + bne 2f + ldr r3, \size + cmp r2, r3 @ bogus size + bhi 2f + add r1, r1, #4 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + b crc2_bad + mov r6, #0 + crcuj _LOADER1_OFFSET, _LOADER_SIZE + bne crc1_bad + orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + b boot_2nd + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h new file mode 100644 index 0000000..30c0860 --- /dev/null +++ b/board/netstar/crcek.h @@ -0,0 +1,3 @@ +#define LOADER_SIZE (448 * 1024) +#define LOADER1_OFFSET (128 * 1024) +#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) diff --git a/board/netstar/crcit b/board/netstar/crcit Binary files differnew file mode 100755 index 0000000..98ae42e --- /dev/null +++ b/board/netstar/crcit diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c new file mode 100644 index 0000000..f6d3066 --- /dev/null +++ b/board/netstar/crcit.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <fcntl.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include "crcek.h" + +extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int); + +uint32_t data[LOADER_SIZE/4 + 3]; + +int doit(char *path, unsigned version) +{ + uint32_t *p; + ssize_t size; + int fd; + + fd = open(path, O_RDONLY); + if (fd == -1) { + perror("Error opening file"); + return EXIT_FAILURE; + } + p = data + 2; + size = read(fd, p, LOADER_SIZE + 4); + if (size == -1) { + perror("Error reading file"); + return EXIT_FAILURE; + } + if (size > LOADER_SIZE) { + fprintf(stderr, "File too large\n"); + return EXIT_FAILURE; + } + size = (((size - 1) >> 2) + 1) << 2; + data[0] = size + 4; /* add size of version field */ + data[1] = version; + data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]); + close(fd); + + if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + perror("Error writing file"); + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} + +int main(int argc, char **argv) +{ + if (argc == 2) { + return doit(argv[1], 0); + } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { + char *endptr, *nptr = argv[2]; + unsigned ver = strtoul(nptr, &endptr, 0); + if (nptr != '\0' && endptr == '\0') + return doit(argv[3], ver); + } + fprintf(stderr, "Usage: crcit [-v version] <image>\n"); + + return EXIT_FAILURE; +} diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c new file mode 100644 index 0000000..fef3822 --- /dev/null +++ b/board/netstar/eeprom.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, michl@2n.cz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some code shamelessly stolen back from Robin Getz. + */ + +#define DEBUG + +#include <common.h> +#include <exports.h> +#include "../drivers/smc91111.h" + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +static u16 read_eeprom_reg(u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + CTL_REG); + timeout = 100; + while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + udelay(100); + if (timeout == 0) { + printf("Timeout Reading EEPROM register %02x\n", reg); + return 0; + } + + return SMC_inw (GP_REG); +} + +static int write_eeprom_reg(u16 value, u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(value, GP_REG); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + timeout = 100; + while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + udelay (100); + if (timeout == 0) { + printf("Timeout Writing EEPROM register %02x\n", reg); + return 0; + } + + return 1; +} + +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + +static int verify_macaddr(char *s) +{ + u16 reg; + int i, err = 0; + + printf("MAC Address: "); + err = i = 0; + for (i = 0; i < 3; i++) { + reg = read_eeprom_reg(0x20 + i); + printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); + if (s) + err |= reg != ((u16 *)s)[i]; + } + + return err ? 0 : 1; +} + +static int set_mac(char *s) +{ + int i; + char *e, eaddr[6]; + + /* turn string into mac value */ + for (i = 0; i < 6; i++) { + eaddr[i] = simple_strtoul(s, &e, 16); + s = (*e) ? e+1 : e; + } + + for (i = 0; i < 3; i++) + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + + return 0; +} + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +extern int crcek(void); + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + return crcek(); + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/netstar/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S new file mode 100644 index 0000000..75d9f05 --- /dev/null +++ b/board/netstar/eeprom_start.S @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + ldr r1, \offset + ldr r2, [r1] + cmp r2, #0 @ no data, no problem + beq 2f + mov r7, #1 + tst r2, #3 @ unaligned size + bne 2f + mov r7, #2 + ldr r0, \size + cmp r2, r0 @ bogus size + bhi 2f + mov r7, #3 + add r1, r1, #4 + mov r0, #0 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + mov r6, #0 +@ crcuj _LOADER1_OFFSET, _LOADER_SIZE +@ bne crc1_bad +@ orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: +@ mov r0, r6 + mov pc, lr + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/flash.c b/board/netstar/flash.c new file mode 100644 index 0000000..692c416 --- /dev/null +++ b/board/netstar/flash.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. <www.2n.cz> + * Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/*#if 0 */ +#if (PHYS_SDRAM_1_SIZE != SZ_32M) + +#include "crcek.h" + +#if (CFG_MAX_FLASH_BANKS > 1) +#error There is always only _one_ flash chip +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x000000f0 +#define CMD_UNLOCK1 0x000000aa +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000a0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i; + + flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); + flash_info[0].size = PHYS_FLASH_1_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < flash_info[0].sector_count; i++) { + switch (i) { + case 0: /* 16kB */ + flash_info[0].start[0] = CFG_FLASH_BASE; + break; + case 1: /* 8kB */ + flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000; + break; + case 2: /* 8kB */ + flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 + + 0x2000; + break; + case 3: /* 32 KB */ + flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000; + break; + case 4: + flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000 + 0x8000; + break; + default: /* 64kB */ + flash_info[0].start[i] = flash_info[0].start[i-1] + + 0x10000; + break; + } + } + + /* U-Boot */ + flash_protect(FLAG_PROTECT_SET, + LOADER1_OFFSET, + LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); + /* Protect crcek, env and r_env as well */ + flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); + + return flash_info[0].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + puts("AMD: "); + break; + default: + puts("Unknown vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV800B & FLASH_TYPEMASK): + puts("AM29LV800BB (8Mb)\n"); + break; + default: + puts("Unknown chip type\n"); + return; + } + + printf(" Size: %ld MB in %d sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector start addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + puts("\n "); + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + puts("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ushort result; + int prot, sect; + int rc = ERR_OK; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + putc('\n'); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + rc = ERR_TIMOUT; + break; + } + + if ((result & 0xfff) & BIT_ERASE_DONE) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + rc = ERR_PROG_ERROR; + break; + } + } + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (rc != ERR_OK) + goto out; + + putc('.'); + } + } +out: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_hword(flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + + /* check if flash is (sufficiently) erased */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + rc = ERR_TIMOUT; + break; + } + + if ((result & 0x80) == (data & 0x80)) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + result = *addr; + + if ((result & 0x80) != (data & 0x80)) + rc = ERR_PROG_ERROR; + } + } + + *addr = CMD_READ_ARRAY; + + if (*addr != data) + rc = ERR_PROG_ERROR; + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + return write_hword(info, wp, data); +} + +#endif diff --git a/board/netstar/nand.c b/board/netstar/nand.c new file mode 100644 index 0000000..f470c1a --- /dev/null +++ b/board/netstar/nand.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_CLE 0x02 +#define MASK_ALE 0x04 + +static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; + case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +/* + * chip R/B detection + */ +/*** +static int netstar_nand_ready(struct mtd_info *mtd) +{ + return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; +} +***/ + +void board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = netstar_nand_hwcontrol; +/* nand->dev_ready = netstar_nand_ready; */ + nand->chip_delay = 18; +} +#endif diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c new file mode 100644 index 0000000..62615e5 --- /dev/null +++ b/board/netstar/netstar.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of NetStar board */ + /* TODO: use define from asm/mach-types.h */ + gd->bd->bi_arch_number = 692; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + /* Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; + udelay(10); /* doesn't work before interrupt_init call */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; + udelay(500); + + return 0; +} + +extern void partition_flash(void); + +int misc_init_r(void) +{ + return 0; +} + +extern void nand_init(void); + +int board_late_init(void) +{ + return 0; +} diff --git a/board/netstar/setup.S b/board/netstar/setup.S new file mode 100644 index 0000000..f67786d --- /dev/null +++ b/board/netstar/setup.S @@ -0,0 +1,287 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 Ales Jindra <jindra@2n.cz> + * (C) Copyright 2005 Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +_TEXT_BASE: + .word TEXT_BASE /* SDRAM load addr from config.mk */ + +OMAP5910_LPG1_BASE: .word 0xfffbd000 +OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 +OMAP5910_MPU_TC_BASE: .word 0xfffecc00 +OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 +OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 +OMAP5910_DPLL1_BASE: .word 0xfffecf00 +OMAP5910_GPIO_BASE: .word 0xfffce000 +OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 +OMAP5910_MPUI_BASE: .word 0xfffec900 + +_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL +_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK + +OMAP5910_MPUI_CTRL: .word 0x0000ff1b + +VAL_EMIFS_CS0_CONFIG: .word 0x00009090 +VAL_EMIFS_CS1_CONFIG: .word 0x00003031 +VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 +VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 +VAL_EMIFS_DYN_WAIT: .word 0x00000000 +/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ + /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ + +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#else +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#endif + +VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 +VAL_EMIFF_MRS: .word 0x00000037 + +/* + * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) + * GPIO07 - LAN91C111 reset + */ +GPIO_DIRECTION: + .word 0x0000ff6f +/* + * Disable everything (green LED is connected via invertor) + */ +GPIO_OUTPUT: + .word 0x00000010 + +MUX_CONFIG_BASE: + .word 0xfffe1000 + +MUX_CONFIG_VALUES: + .align 4 + .word 0x00000000 @ FUNC_MUX_CTRL_0 + .word 0x00000000 @ FUNC_MUX_CTRL_1 + .word 0x00000000 @ FUNC_MUX_CTRL_2 + .word 0x00000000 @ FUNC_MUX_CTRL_3 + .word 0x00000000 @ FUNC_MUX_CTRL_4 + .word 0x02080480 @ FUNC_MUX_CTRL_5 + .word 0x0100001c @ FUNC_MUX_CTRL_6 + .word 0x0004800b @ FUNC_MUX_CTRL_7 + .word 0x10001200 @ FUNC_MUX_CTRL_8 + .word 0x01201012 @ FUNC_MUX_CTRL_9 + .word 0x02082248 @ FUNC_MUX_CTRL_A + .word 0x00000248 @ FUNC_MUX_CTRL_B + .word 0x12240000 @ FUNC_MUX_CTRL_C + .word 0x00002000 @ FUNC_MUX_CTRL_D + .word 0x00000000 @ PULL_DWN_CTRL_0 + .word 0x00000800 @ PULL_DWN_CTRL_1 + .word 0x01801000 @ PULL_DWN_CTRL_2 + .word 0x00000000 @ PULL_DWN_CTRL_3 + .word 0x00000000 @ GATE_INH_CTRL_0 + .word 0x00000000 @ VOLTAGE_CTRL_0 + .word 0x00000000 @ TEST_DBG_CTRL_0 + .word 0x00000006 @ MOD_CONF_CTRL_0 + .word 0x0000eaef @ COMP_MODE_CTRL_0 + +MUX_CONFIG_OFFSETS: + .align 1 + .byte 0x00 @ FUNC_MUX_CTRL_0 + .byte 0x04 @ FUNC_MUX_CTRL_1 + .byte 0x08 @ FUNC_MUX_CTRL_2 + .byte 0x10 @ FUNC_MUX_CTRL_3 + .byte 0x14 @ FUNC_MUX_CTRL_4 + .byte 0x18 @ FUNC_MUX_CTRL_5 + .byte 0x1c @ FUNC_MUX_CTRL_6 + .byte 0x20 @ FUNC_MUX_CTRL_7 + .byte 0x24 @ FUNC_MUX_CTRL_8 + .byte 0x28 @ FUNC_MUX_CTRL_9 + .byte 0x2c @ FUNC_MUX_CTRL_A + .byte 0x30 @ FUNC_MUX_CTRL_B + .byte 0x34 @ FUNC_MUX_CTRL_C + .byte 0x38 @ FUNC_MUX_CTRL_D + .byte 0x40 @ PULL_DWN_CTRL_0 + .byte 0x44 @ PULL_DWN_CTRL_1 + .byte 0x48 @ PULL_DWN_CTRL_2 + .byte 0x4c @ PULL_DWN_CTRL_3 + .byte 0x50 @ GATE_INH_CTRL_0 + .byte 0x60 @ VOLTAGE_CTRL_0 + .byte 0x70 @ TEST_DBG_CTRL_0 + .byte 0x80 @ MOD_CONF_CTRL_0 + .byte 0x0c @ COMP_MODE_CTRL_0 + .byte 0xff + +.globl lowlevel_init +lowlevel_init: + /* Improve performance a bit... */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit + ldrh r1, [r0, #0x18] @ get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 @ set wait counter to 100 clock cycles + +icache_loop: + cmp r2, #0x01 + streqh r1, [r0, #0x18] + add r2, r2, #0x01 + cmp r2, #0x10 + bne icache_loop + nop + + /* Setup clock divisors */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldr r1, _OMAP5910_ARM_CKCTL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0, #0x00] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, _OMAP5910_ARM_EN_CLK + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + @ max delayed ( 32 x CLKIN ) + strh r1, [r0, #0x0c] + + /* Configure 5910 pins functions to match our board. */ + ldr r0, MUX_CONFIG_BASE + adr r1, MUX_CONFIG_VALUES + adr r2, MUX_CONFIG_OFFSETS +next_mux_cfg: + ldrb r3, [r2], #1 + ldr r4, [r1], #4 + cmp r3, #0xff + strne r4, [r0, r3] + bne next_mux_cfg + + /* Configure GPIO pins (also disables Green LED) */ + ldr r0, OMAP5910_GPIO_BASE + ldr r1, GPIO_OUTPUT + strh r1, [r0, #0x04] + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] + + /* EnablePeripherals */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit + mov r1, #0x0001 @ Peripheral enable + strh r1, [r0, #0x14] + + /* Program LED Pulse Generator */ + ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator + mov r1, #0x7F @ Set obscure frequency in + strb r1, [r0, #0x00] @ LCR + mov r1, #0x01 @ Enable clock (CLK_EN) in + strb r1, [r0, #0x04] @ PMR + + /* TIPB Lock UART1 */ + ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches + mov r1, #1 @ ARM allocated + strh r1, [r0,#0x04] @ clear IRQ line and status bits + strh r1, [r0,#0x00] + ldrh r1, [r0,#0x04] + + /* Disable watchdog */ + ldr r0, OMAP5910_MPU_WD_TIMER_BASE + mov r1, #0xf5 + strh r1, [r0, #0x8] + mov r1, #0xa0 + strh r1, [r0, #0x8] + + /* Enable MCLK */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE + mov r1, #0x6 + strh r1, [r0, #0x34] + strh r1, [r0, #0x34] + + /* Setup clock divisors */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register + + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + strh r1, [r0] @ write + +ulocking: + ldrh r1, [r0] @ get DPLL value + tst r1, #1 + beq ulocking @ while LOCK not set + + /* EMIF init */ + ldr r0, OMAP5910_MPU_TC_BASE + ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG + bic r1, r1, #0x0c @ pwr down disabled, flash WP + orr r1, r1, #0x01 + str r1, [r0, #0x0c] + + ldr r1, VAL_EMIFS_CS0_CONFIG + str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG + ldr r1, VAL_EMIFS_CS1_CONFIG + str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG + ldr r1, VAL_EMIFS_CS2_CONFIG + str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG + ldr r1, VAL_EMIFS_CS3_CONFIG + str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG + ldr r1, VAL_EMIFS_DYN_WAIT + str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT + + /* Setup SDRAM */ + ldr r1, VAL_EMIFF_SDRAM_CONFIG + str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG + ldr r1, VAL_EMIFF_SDRAM_CONFIG2 + str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 + ldr r1, VAL_EMIFF_MRS + str r1, [r0, #0x24] @ EMIFF_MRS + /* SDRAM needs 100us to stabilize */ + mov r0, #0x4000 +sdelay: + subs r0, r0, #0x1 + bne sdelay + + /* back to arch calling code */ + mov pc, lr +.end diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds new file mode 100644 index 0000000..8317f72 --- /dev/null +++ b/board/netstar/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netta2/config.mk b/board/netta2/config.mk index 8497ebc..de179c2 100644 --- a/board/netta2/config.mk +++ b/board/netta2/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index c9b4051..3ca7bd3 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -597,7 +597,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netvia/config.mk b/board/netvia/config.mk index 9dddaad..583174a 100644 --- a/board/netvia/config.mk +++ b/board/netvia/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index fb7f770..3e6c616 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -418,7 +418,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 6ae1a49..2387176 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -32,7 +32,7 @@ #include <i2c.h> #include <asm/mach-types.h> #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/pm520/flash.c b/board/pm520/flash.c index ccd0bd1..38f579b 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -242,10 +242,11 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) case (FPW) INTEL_ID_28F256J3A: info->flash_id += FLASH_28F256J3A; - info->sector_count = 256; - info->size = 0x04000000; - info->start[0] = CFG_FLASH_BASE; - break; /* => 64 MB */ + /* In U-Boot we support only 32 MB (no bank-switching) */ + info->sector_count = 256 / 2; + info->size = 0x04000000 / 2; + info->start[0] = CFG_FLASH_BASE + 0x02000000; + break; /* => 32 MB */ case (FPW) INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 13c01d8..475b76b 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -315,7 +315,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk index 0cd8f44..8e73d2f 100644 --- a/board/sixnet/config.mk +++ b/board/sixnet/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xF8000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 867589f..a25dffd 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -34,7 +34,7 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c index a108af7..fd9992d 100644 --- a/board/smdk2400/flash.c +++ b/board/smdk2400/flash.c @@ -353,8 +353,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/stamp/Makefile b/board/stamp/Makefile new file mode 100644 index 0000000..ab97e1b --- /dev/null +++ b/board/stamp/Makefile @@ -0,0 +1,68 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o stamp.o +SOBJS = + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stamp/config.mk b/board/stamp/config.mk new file mode 100644 index 0000000..0d00730 --- /dev/null +++ b/board/stamp/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x07FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c new file mode 100644 index 0000000..3fe0134 --- /dev/null +++ b/board/stamp/stamp.c @@ -0,0 +1,275 @@ +/* + * U-boot - stamp.c STAMP board specific routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mem_init.h> +#include "stamp.h" + +#define STATUS_LED_OFF 0 +#define STATUS_LED_ON 1 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +int checkboard (void) +{ + printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf ("Board: ADI BF533 Stamp board\n"); + printf (" Support: http://blackfin.uclinux.org/\n"); + printf (" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram (int board_type) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG + printf ("SDRAM attributes:\n"); + printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " + "CAS Latency:%d cycles\n", + (SDRAM_tRCD >> 15), + (SDRAM_tRP >> 11), + (SDRAM_tRAS >> 6), + (SDRAM_tWR >> 19), + (SDRAM_CL >> 2)); + printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf ("Bank size = %d MB\n", 128); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return (gd->bd->bi_memsize); +} + +void swap_to (int device_id) +{ + + if (device_id == ETHERNET) { + *pFIO_DIR = PF0; + asm ("ssync;"); + *pFIO_FLAG_S = PF0; + asm ("ssync;"); + } else if (device_id == FLASH) { + *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); + *pFIO_FLAG_S = (PF4 | PF3 | PF2); + *pFIO_MASKA_D = (PF8 | PF6 | PF5); + *pFIO_MASKB_D = (PF7); + *pFIO_POLAR = (PF8 | PF6 | PF5); + *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); + *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); + *pFIO_FLAG_D = (PF4 | PF3 | PF2); + asm ("ssync;"); + } else { + printf ("Unknown bank to switch\n"); + } + + return; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r (void) +{ + int i; + int cf_stat = 0; + + /* Check whether CF card is inserted */ + *pFIO_EDGE = FIO_EDGE_CF_BITS; + *pFIO_POLAR = FIO_POLAR_CF_BITS; + for (i = 0; i < 0x300; i++) + asm ("nop;"); + + if ((*pFIO_FLAG_S) & CF_STAT_BITS) { + cf_stat = 0; + } else { + cf_stat = 1; + } + + *pFIO_EDGE = FIO_EDGE_BITS; + *pFIO_POLAR = FIO_POLAR_BITS; + + + if (cf_stat) { + printf ("Booting from COMPACT flash\n"); + + /* Set cycle time for CF */ + *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL; + + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + + serial_setbrg (); + ide_init (); + + setenv ("bootargs", ""); + setenv ("bootcmd", + "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000"); + } else { + printf ("Booting from FLASH\n"); + } + + return 1; +} +#endif + +#ifdef CONFIG_STAMP_CF + +void cf_outb (unsigned char val, volatile unsigned char *addr) +{ + /* + * Set PF1 PF0 respectively to 0 1 to divert address + * to the expansion memory banks + */ + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + *(addr) = val; + asm ("ssync;"); + + /* Setback PF1 PF0 to 0 0 to address external + * memory banks */ + *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +unsigned char cf_inb (volatile unsigned char *addr) +{ + volatile unsigned char c; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + c = *(addr); + asm ("ssync;"); + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); + + return c; +} + +void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(sect_buf + i) = *(addr); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(addr) = *(sect_buf + i); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} +#endif + +void stamp_led_set (int LED1, int LED2, int LED3) +{ + *pFIO_INEN &= ~(PF2 | PF3 | PF4); + *pFIO_DIR |= (PF2 | PF3 | PF4); + + if (LED1 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF2; + else + *pFIO_FLAG_C = PF2; + if (LED2 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF3; + else + *pFIO_FLAG_C = PF3; + if (LED3 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF4; + else + *pFIO_FLAG_C = PF4; + asm ("ssync;"); +} + +void show_boot_progress (int status) +{ + switch (status) { + case 1: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 2: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 3: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON); + break; + case 4: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF); + break; + case 5: + case 6: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 7: + case 8: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, + STATUS_LED_OFF); + break; + default: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON); + break; + } +} diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h new file mode 100644 index 0000000..7bc33b4 --- /dev/null +++ b/board/stamp/stamp.h @@ -0,0 +1,57 @@ +/* + * U-boot - stamp.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __STAMP_H__ +#define __STAMP_H__ + +extern void init_Flags(void); + +extern volatile unsigned long *ambctl0; +extern volatile unsigned long *ambctl1; +extern volatile unsigned long *amgctl; + +extern unsigned long pll_div_fact; +extern void serial_setbrg(void); +extern void pll_set(int vco, int crystal_frq, int pll_div); + +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + +/* CF Flags used to switch between expansion and external + * memory banks + */ +#define CF_PF0 0x0001 +#define CF_PF1 0x0002 +#define CF_PF1_PF0 0x0003 + +#endif diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds new file mode 100644 index 0000000..9a22e50 --- /dev/null +++ b/board/stamp/u-boot.lds @@ -0,0 +1,147 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index aa3d129..7caf06a 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -576,7 +576,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 13ea6f4..c03b60d 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -296,7 +296,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, 0xffffffff, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ diff --git a/board/trab/Makefile b/board/trab/Makefile index ced9bc5..159404b 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -47,7 +47,7 @@ trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) $(OBJCOPY) -O srec $(<:.o=) $@ trab_fkt.bin: trab_fkt.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/trab/flash.c b/board/trab/flash.c index b4435e3..8cdd824 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -308,8 +308,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index 1076345..5c492eb 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -148,7 +148,7 @@ eth_rx(void) RecvFrameLength = PKTSIZE; Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); if (Result == XST_SUCCESS) { - NetReceive((uchar)etherrxbuff, RecvFrameLength); + NetReceive((uchar *)etherrxbuff, RecvFrameLength); return (1); } else { return (0); diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk index 1072dc7..3e53b2b 100644 --- a/board/zpc1900/config.mk +++ b/board/zpc1900/config.mk @@ -27,4 +27,4 @@ # ZPC.1900 board # -TEXT_BASE = 0xFFE00000 +TEXT_BASE = 0xFE000000 diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 6d16a0d..7db535e 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -2,7 +2,7 @@ * (C) Copyright 2001-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2003 Arabella Software Ltd. + * (C) Copyright 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * See file CREDITS for list of people who contributed to this @@ -27,9 +27,6 @@ #include <common.h> #include <ioports.h> #include <mpc8260.h> -#include <asm/m8260_pci.h> -#include <i2c.h> -#include <spd.h> #include <miiphy.h> /* @@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ @@ -231,11 +228,10 @@ long int initdram(int board_type) vu_char *ramaddr; uchar c = 0xFF; long int msize = CFG_SDRAM_SIZE; - uint psdmr = CFG_PSDMR; int i; if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; @@ -255,10 +251,10 @@ long int initdram(int board_type) */ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; + memctl->memc_or4 = CFG_LSDRAM_OR; + memctl->memc_br4 = CFG_LSDRAM_BR; ramaddr = (vu_char *)CFG_LSDRAM_BASE; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; *ramaddr = c; memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) @@ -271,8 +267,8 @@ long int initdram(int board_type) /* Initialise 60x bus SDRAM */ memctl->memc_psrt = CFG_PSRT; - memctl->memc_or2 = 0xFC0028C0; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + memctl->memc_or2 = CFG_PSDRAM_OR; + memctl->memc_br2 = CFG_PSDRAM_BR; /* * The mode data for Mode Register Write command must appear on * the address lines during a mode-set cycle. It is driven by @@ -283,15 +279,15 @@ long int initdram(int board_type) * length must be 4. */ ramaddr = (vu_char *)(CFG_SDRAM_BASE | - ((psdmr & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; #endif /* CFG_RAMBOOT */ diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile new file mode 100644 index 0000000..999647f --- /dev/null +++ b/board/zylonite/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := zylonite.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk new file mode 100644 index 0000000..09b0f71 --- /dev/null +++ b/board/zylonite/config.mk @@ -0,0 +1,4 @@ +#TEXT_BASE = 0x0 +#TEXT_BASE = 0xa1700000 +#TEXT_BASE = 0xa3080000 +TEXT_BASE = 0xa3008000 diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c new file mode 100644 index 0000000..883c1ba --- /dev/null +++ b/board/zylonite/flash.c @@ -0,0 +1,434 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/byteorder/swab.h> + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#if 0 + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +#endif + return 0; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S new file mode 100644 index 0000000..c3bb4eb --- /dev/null +++ b/board/zylonite/lowlevel_init.S @@ -0,0 +1,371 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm + + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first ----------------------------------------- */ + mov r10, lr + + /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */ + ldr r0, =0x40E10438 @ GPIO41 FFRXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1043C @ GPIO42 FFTXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10440 @ GPIO43 FFCTS + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10444 @ GPIO 44 FFDCD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10448 @ GPIO 45 FFDSR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1044C @ GPIO 46 FFRI + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10450 @ GPIO 47 FFDTR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10454 @ GPIO 48 + ldr r1, =0x802 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + /* mk: replaced with wait macro */ +/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */ +/* mov r2, #0 */ +/* str r2, [r3] */ +/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */ +/* /\* so 0x300 should be plenty *\/ */ +/* 1: */ +/* ldr r2, [r3] */ +/* cmp r4, r2 */ +/* bgt 1b */ + wait #300 + +mem_init: + + /* configure the MEMCLKCFG register */ + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[0] to data flash SRAM mode */ + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[1] to data flash SRAM mode */ + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 0 register for SRAM memory */ + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[2] to data flash SRAM mode */ + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[3] to VLIO mode */ + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 1 register for VLIO memory */ + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + +#if 0 + /* This does not work in Zylonite. -SC */ + ldr r0, =0x15fffff0 + ldr r1, =0xb10b + str r1, [r0] + str r1, [r0, #4] +#endif + + /* Configure ACCR Register */ + ldr r0, =ACCR @ ACCR + ldr r1, =0x0180b108 + str r1, [r0] + ldr r1, [r0] + + /* Configure MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, =0x403 + str r1, [r0] + ldr r1, [r0] + + /* Perform Resistive Compensation by configuring RCOMP register */ + ldr r1, =RCOMP @ RCOMP + ldr r2, =0x000000ff + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS0 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0x60000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS1 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0xa0000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDREFR */ + ldr r1, =MDREFR @ MDREFR + ldr r2, =0x00000006 + str r2, [r1] + ldr r2, [r1] + + /* Configure EMPI */ + ldr r1, =EMPI @ EMPI + ldr r2, =0x80000000 + str r2, [r1] + ldr r2, [r1] + + /* Hardware DDR Read-Strobe Delay Calibration */ + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + + /* Here we assume the hardware calibration alwasy be successful. -SC */ + /* Set DMCEN bit in MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, [r0] + orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access + str r1, [r0] + + /* scrub/init SDRAM if enabled/present */ +/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ +/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ +/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ + ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 32 bytes/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr + +/* +@******************************************************************************** +@ DDR calibration +@ +@ This function is used to calibrate DQS delay lines. +@ Monahans supports three ways to do it. One is software +@ calibration. Two is hardware calibration. Three is hybrid +@ calibration. +@ +@ TBD +@ -SC +ddr_calibration: + + @ Case 1: Write the correct delay value once + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] +*/ +/* @ Case 2: Software Calibration + @ Write test pattern to memory + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] + + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 +ddr_loop1: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 +ddr_loop2: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + +end_loop: + + @ Case 3: Hardware Calibratoin + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr +*/ diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/zylonite/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c new file mode 100644 index 0000000..e618ab9 --- /dev/null +++ b/board/zylonite/zylonite.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} |