diff options
Diffstat (limited to 'board')
47 files changed, 534 insertions, 107 deletions
diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c index 45b8195..371f67f 100644 --- a/board/MAI/AmigaOneG3SE/articiaS_pci.c +++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c @@ -313,7 +313,7 @@ void articiaS_pci_init (void) ARTICIAS_SYS_BUS, ARTICIAS_SYS_PHYS, ARTICIAS_SYS_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(articiaS_hose.regions + 1, diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 0610928..6c40e94 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -31,6 +31,8 @@ #include <i2c.h> #endif +DECLARE_GLOBAL_DATA_PTR; + /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ @@ -38,6 +40,7 @@ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_PATA_EN | \ CLOCK_SCCR1_PCI_EN | \ CLOCK_SCCR1_TPR_EN) @@ -101,6 +104,9 @@ int board_early_init_f (void) */ im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN; +#endif return 0; } @@ -290,17 +296,28 @@ static iopin_t ioregs_init[] = { } }; +static iopin_t rev2_silicon_pci_ioregs_init[] = { + /* FUNC0=PCI Sets next 54 to PCI pads */ + { + IOCTL_PCI_AD31, 54, 0, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) + } +}; + int checkboard (void) { ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0])); + if (SVR_MJREV (im->sysconf.spridr) >= 2) { + iopin_initialize(rev2_silicon_pci_ioregs_init, 1); + } return 0; } @@ -312,3 +329,104 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + debug ("init_ide_reset\n"); + + /* + * Clear the reset bit to reset the interface + * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus + */ + immr->pata.pata_ata_control = 0; + udelay(100); + /* Assert the reset bit to enable the interface */ + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + udelay(100); + +} + +void ide_set_reset (int idereset) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + debug ("ide_set_reset(%d)\n", idereset); + + if (idereset) { + immr->pata.pata_ata_control = 0; + udelay(100); + } else { + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + udelay(100); + } +} + +#define CALC_TIMING(t) (t + period - 1) / period + +int ide_preinit (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + long t; + const struct { + short t0; + short t1; + short t2_8; + short t2_16; + short t2i; + short t4; + short t9; + short tA; + } pio_specs = { + .t0 = 600, + .t1 = 70, + .t2_8 = 290, + .t2_16 = 165, + .t2i = 0, + .t4 = 30, + .t9 = 20, + .tA = 50, + }; + union { + u32 config; + struct { + u8 field1; + u8 field2; + u8 field3; + u8 field4; + }bytes; + }cfg; + + debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n", + (u32)&immr->pata); + + /* Set the reset bit to 1 to enable the interface */ + immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B; + + /* Init timings : we use PIO mode 0 timings */ + t = 1000000000 / gd->ips_clk; /* period in ns */ + cfg.bytes.field1 = 3; + cfg.bytes.field2 = 3; + cfg.bytes.field3 = (pio_specs.t1 + t) / t; + cfg.bytes.field4 = (pio_specs.t2_8 + t) / t; + + immr->pata.pata_time1 = cfg.config; + + cfg.bytes.field1 = (pio_specs.t2_8 + t) / t; + cfg.bytes.field2 = (pio_specs.tA + t) / t + 2; + cfg.bytes.field3 = 1; + cfg.bytes.field4 = (pio_specs.t4 + t) / t; + + immr->pata.pata_time2 = cfg.config; + + cfg.config = immr->pata.pata_time3; + cfg.bytes.field1 = (pio_specs.t9 + t) / t; + + immr->pata.pata_time3 = cfg.config; + debug ("PATA preinit complete.\n"); + + return 0; +} + +#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 4f7dda0..41a1353 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -37,7 +37,11 @@ #include <video_fb.h> #endif +#ifdef CONFIG_FSL_DIU_LOGO_BMP extern unsigned int FSL_Logo_BMP[]; +#else +#define FSL_Logo_BMP NULL +#endif static int xres, yres; @@ -61,16 +65,40 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); } +char *valid_bmp(char *addr) +{ + unsigned long h_addr; + + h_addr = simple_strtoul(addr, NULL, 16); + if (h_addr < CONFIG_SYS_FLASH_BASE || + h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { + printf("bmp addr %lx is not a valid flash address\n", h_addr); + return 0; + } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { + printf("bmp addr is not a bmp\n"); + return 0; + } else + return (char *)h_addr; +} + int ads5121_diu_init(void) { unsigned int pixel_format; + char *bmp = NULL; + char *bmp_env; xres = 1024; yres = 768; pixel_format = 0x88883316; - return fsl_diu_init(xres, pixel_format, 0, - (unsigned char *)FSL_Logo_BMP); + debug("ads5121_diu_init\n"); + bmp_env = getenv("diu_bmp_addr"); + if (bmp_env) { + bmp = valid_bmp(bmp_env); + } + if (!bmp) + bmp = FSL_Logo_BMP; + return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); } int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c index b747e81..806c428 100644 --- a/board/ads5121/pci.c +++ b/board/ads5121/pci.c @@ -153,7 +153,7 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c index 33b4a6e..89c1abd 100644 --- a/board/alaska/alaska.c +++ b/board/alaska/alaska.c @@ -33,9 +33,9 @@ void setupBat (ulong size) /* Flash 0 */ #if defined (CONFIG_SYS_AMD_BOOT) - batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX; #else - batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX; #endif batl = CONFIG_SYS_FLASH0_BASE | 0x22; write_bat (IBAT0, batu, batl); @@ -43,22 +43,22 @@ void setupBat (ulong size) /* Flash 1 */ #if defined (CONFIG_SYS_AMD_BOOT) - batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX; #else - batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX; #endif batl = CONFIG_SYS_FLASH1_BASE | 0x22; write_bat (IBAT1, batu, batl); write_bat (DBAT1, batu, batl); /* CPLD */ - batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX; batl = CONFIG_SYS_CPLD_BASE | 0x22; write_bat (IBAT2, 0, 0); write_bat (DBAT2, batu, batl); /* FPGA */ - batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX; batl = CONFIG_SYS_FPGA_BASE | 0x22; write_bat (IBAT3, 0, 0); write_bat (DBAT3, batu, batl); @@ -80,17 +80,17 @@ void setupBat (ulong size) mtspr (DBAT5U, batu); if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; + blocksize = BATU_BL_8M; else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; + blocksize = BATU_BL_16M; else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; + blocksize = BATU_BL_32M; else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; + blocksize = BATU_BL_64M; else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; + blocksize = BATU_BL_128M; else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; + blocksize = BATU_BL_256M; /* Memory */ batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; @@ -108,17 +108,17 @@ void setupBat (ulong size) } else { size -= 0x10000000; if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; + blocksize = BATU_BL_8M; else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; + blocksize = BATU_BL_16M; else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; + blocksize = BATU_BL_32M; else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; + blocksize = BATU_BL_64M; else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; + blocksize = BATU_BL_128M; else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; + blocksize = BATU_BL_256M; batu = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | blocksize | BPP_RW | BPP_RX; diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index b6c0c11..e078ba4 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -451,5 +451,6 @@ int post_hotkeys_pressed(void) int board_eth_init(bd_t *bis) { + cpu_eth_init(bis); return pci_eth_init(bis); } diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 5224378..669429b 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -195,5 +195,6 @@ int pci_pre_init(struct pci_controller *hose) int board_eth_init(bd_t *bis) { + cpu_eth_init(bis); return pci_eth_init(bis); } diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 28bdab5..53ce88c 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -315,5 +315,6 @@ int post_hotkeys_pressed(void) int board_eth_init(bd_t *bis) { + cpu_eth_init(bis); return pci_eth_init(bis); } diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index c805568..06c7d62 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -956,5 +956,6 @@ int onboard_pci_arbiter_selected(int core_pci) int board_eth_init(bd_t *bis) { + cpu_eth_init(bis); return pci_eth_init(bis); } diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c index a9b3fd8..5fbcd37 100644 --- a/board/amirix/ap1000/pci.c +++ b/board/amirix/ap1000/pci.c @@ -294,7 +294,7 @@ void pci_init_board (void) pci_set_region (hose->regions + 0, AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, AP1000_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI Memory space */ pci_set_region (hose->regions + 1, diff --git a/board/armltd/integratorap/integratorap.c b/board/armltd/integratorap/integratorap.c index ddacabb..9631967 100644 --- a/board/armltd/integratorap/integratorap.c +++ b/board/armltd/integratorap/integratorap.c @@ -428,7 +428,7 @@ void pci_init_board (void) /* System memory space */ pci_set_region (hose->regions + 0, 0x00000000, 0x40000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI Memory - config space */ pci_set_region (hose->regions + 1, diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c index b147ce7..7b764b4 100644 --- a/board/bf537-stamp/spi_flash.c +++ b/board/bf537-stamp/spi_flash.c @@ -180,13 +180,7 @@ static struct manufacturer_info flash_manufacturers[] = { * BF51x, BF533, BF561: SSEL2 */ #ifndef CONFIG_SPI_FLASH_SSEL -# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ - defined(__ADSPBF51x__) -# define CONFIG_SPI_FLASH_SSEL 2 -# else -# define CONFIG_SPI_FLASH_SSEL 1 -# endif +# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL #endif #define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL) diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c index ec0d761..ddfbea9 100644 --- a/board/dave/common/pci.c +++ b/board/dave/common/pci.c @@ -179,7 +179,7 @@ void pci_init(void) /* System memory space */ pci_set_region(hose->regions + 0, 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI Memory space */ pci_set_region(hose->regions + 1, diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index bf36f73..3fe8858 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -124,4 +124,3 @@ void enable_vbus(void) i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1); } #endif - diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c index 46e5a8b..38dd498 100644 --- a/board/eltec/bab7xx/pci.c +++ b/board/eltec/bab7xx/pci.c @@ -50,7 +50,7 @@ void pci_init_board(void) * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1) */ CONFIG_SYS_PCI_MEMORY_SIZE-1, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c index bf133b7..2948531 100644 --- a/board/eltec/elppc/pci.c +++ b/board/eltec/elppc/pci.c @@ -45,7 +45,7 @@ void pci_init_board(void) CONFIG_SYS_PCI_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c index 330978b..8579cfa 100644 --- a/board/emk/common/flash.c +++ b/board/emk/common/flash.c @@ -82,7 +82,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ static ulong flash_get_size(FPWV *addr, flash_info_t *info); static void flash_reset(flash_info_t *info); static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); +flash_info_t *flash_get_info(ulong base); /*----------------------------------------------------------------------- * flash_init() @@ -142,7 +142,7 @@ static void flash_reset(flash_info_t *info) /*----------------------------------------------------------------------- */ -static flash_info_t *flash_get_info(ulong base) +flash_info_t *flash_get_info(ulong base) { int i; flash_info_t * info; diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c index dcb764c..83f8103 100644 --- a/board/esd/common/pci.c +++ b/board/esd/common/pci.c @@ -179,7 +179,7 @@ void pci_init_board(void) /* System memory space */ pci_set_region(hose->regions + 0, 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI Memory space */ pci_set_region(hose->regions + 1, diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c index a3c8138..f9e8619 100644 --- a/board/etin/debris/flash.c +++ b/board/etin/debris/flash.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <asm/pci_io.h> #include <mpc824x.h> +#include <asm/mmu.h> int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); int (*write_dword)(flash_info_t*, ulong, uint64_t); diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c index 8c6afc9..21616f5 100644 --- a/board/etin/kvme080/kvme080.c +++ b/board/etin/kvme080/kvme080.c @@ -27,6 +27,7 @@ #include <i2c.h> #include <netdev.h> #include <asm/processor.h> +#include <asm/mmu.h> int checkboard(void) { diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c index 115e8cd..825bbaf 100644 --- a/board/evb64260/flash.c +++ b/board/evb64260/flash.c @@ -54,7 +54,6 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); static void flash_get_offsets (ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); /*----------------------------------------------------------------------- */ @@ -178,7 +177,7 @@ flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -static flash_info_t *flash_get_info(ulong base) +flash_info_t *flash_get_info(ulong base) { int i; flash_info_t * info; diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c index 5ccd6bc..aeacb91 100644 --- a/board/freescale/common/sgmii_riser.c +++ b/board/freescale/common/sgmii_riser.c @@ -14,6 +14,8 @@ #include <config.h> #include <common.h> +#include <net.h> +#include <libfdt.h> #include <tsec.h> void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) @@ -24,3 +26,66 @@ void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) if (tsec_info[i].flags & TSEC_SGMII) tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; } + +void fsl_sgmii_riser_fdt_fixup(void *fdt) +{ + struct eth_device *dev; + int node; + int i = -1; + int etsec_num = 0; + + node = fdt_path_offset(fdt, "/aliases"); + if (node < 0) + return; + + while ((dev = eth_get_dev_by_index(++i)) != NULL) { + struct tsec_private *priv; + int enet_node; + char enet[16]; + const u32 *phyh; + int phynode; + const char *model; + const char *path; + + printf("Updating PHY address for %s\n", dev->name); + if (!strstr(dev->name, "eTSEC")) + continue; + + sprintf(enet, "ethernet%d", etsec_num++); + path = fdt_getprop(fdt, node, enet, NULL); + if (!path) { + debug("No alias for %s\n", enet); + continue; + } + + enet_node = fdt_path_offset(fdt, path); + if (enet_node < 0) + continue; + + model = fdt_getprop(fdt, enet_node, "model", NULL); + + printf("%s's model is %s\n", enet, model); + /* + * We only want to do this to eTSECs. On some platforms + * there are more than one type of gianfar-style ethernet + * controller, and as we are creating an implicit connection + * between ethernet nodes and eTSEC devices, it is best to + * make the connection use as much explicit information + * as exists. + */ + if (!strstr(model, "TSEC")) + continue; + + phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); + if (!phyh) + continue; + + phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh)); + + priv = dev->priv; + + printf("Device flags are %x\n", priv->flags); + if (priv->flags & TSEC_SGMII) + fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr); + } +} diff --git a/board/freescale/common/sgmii_riser.h b/board/freescale/common/sgmii_riser.h index 8d56a1f..e1fcc85 100644 --- a/board/freescale/common/sgmii_riser.h +++ b/board/freescale/common/sgmii_riser.h @@ -13,3 +13,4 @@ */ void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num); +void fsl_sgmii_riser_fdt_fixup(void *fdt); diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index 2a48dd2..212fb52 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -228,7 +228,7 @@ void pci_init_board(void) CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose[0].region_count = 4; diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index fd2c172..8da7117 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -210,7 +210,7 @@ void pci_init_board(void) pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; @@ -301,7 +301,7 @@ void pci_init_board(void) pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 935aca26..7ac35dc 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -228,7 +228,7 @@ void pci_init_board(void) CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose[0].region_count = 4; diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 156d808..062d762 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -23,6 +23,7 @@ int board_early_init_f(void) { + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ @@ -30,6 +31,18 @@ int board_early_init_f(void) /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; +#ifdef CONFIG_MMC + /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ + bcsr[0xc] |= 0x4c; + + /* Set proper bits in SICR to allow SD signals through */ + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + + clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI), + (SICRH_GPIO2_E_SD | SICRH_SPI_SD)); + +#endif + #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); @@ -38,21 +51,21 @@ int board_early_init_f(void) switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); + "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index eb80500..31c1e15 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -44,6 +44,20 @@ phys_size_t fixed_sdram(void); +int board_early_init_f (void) +{ +#ifdef CONFIG_MMC + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SD_DATA | + MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); + +#endif + return 0; +} + int checkboard (void) { printf ("Board: MPC8536DS, System ID: 0x%02x, " @@ -625,8 +639,10 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_FSL_SGMII_RISER if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) fsl_sgmii_riser_init(tsec_info, num); +#endif tsec_eth_init(bis, tsec_info, num); #endif @@ -653,5 +669,8 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); #endif +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif } #endif diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 7ff5a9b..13760db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -497,5 +497,8 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE3 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); #endif +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif } #endif diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index e57f9ff..33cf0e4 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -42,8 +42,12 @@ long int fixed_sdram(void); int checkboard (void) { - printf ("Board: MPC8572DS, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", + puts ("Board: MPC8572DS "); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) "); +#endif + printf ("Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), in8(PIXIS_BASE + PIXIS_PVER)); return 0; @@ -216,8 +220,10 @@ void pci_init_board(void) pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), PCI_BASE_ADDRESS_1, &temp32); if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - debug(" uli1572 read to %x\n", temp32); - in_be32((unsigned *)temp32); + void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + temp32, 4, 0); + debug(" uli1572 read to %p\n", p); + in_be32(p); } } else { printf (" PCIE3: disabled\n"); @@ -540,7 +546,9 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_init(tsec_info, num); +#endif tsec_eth_init(bis, tsec_info, num); @@ -554,7 +562,8 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, void ft_board_setup(void *blob, bd_t *bd) { - ulong base, size; + phys_addr_t base; + phys_size_t size; ft_cpu_setup(blob, bd); @@ -572,6 +581,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif } #endif diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index a2097a5..b419dcc 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -484,3 +484,11 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +void board_reset(void) +{ + out8(PIXIS_BASE + PIXIS_RST, 0); + + while (1) + ; +} diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index b83ed6c..49718da 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -163,23 +163,23 @@ void pci_init_board(void) } debug("\n"); - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; @@ -195,7 +195,7 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); } else { @@ -212,23 +212,23 @@ void pci_init_board(void) struct pci_controller *hose = &pci2_hose; struct pci_region *r = hose->regions; - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; @@ -363,3 +363,11 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); return pci_eth_init(bis); } + +void board_reset(void) +{ + out8(PIXIS_BASE + PIXIS_RST, 0); + + while (1) + ; +} diff --git a/board/omap3/evm/Makefile b/board/omap3/evm/Makefile index a83ccdc..b951bb4 100644 --- a/board/omap3/evm/Makefile +++ b/board/omap3/evm/Makefile @@ -45,4 +45,3 @@ distclean: clean include $(SRCTREE)/rules.mk sinclude $(obj).depend - diff --git a/board/omap3/overo/Makefile b/board/omap3/overo/Makefile index ed5f451..c165629 100644 --- a/board/omap3/overo/Makefile +++ b/board/omap3/overo/Makefile @@ -45,4 +45,3 @@ distclean: clean include $(SRCTREE)/rules.mk sinclude $(obj).depend - diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c index bed8aea..ccd18e1 100644 --- a/board/pcippc2/cpc710_pci.c +++ b/board/pcippc2/cpc710_pci.c @@ -215,7 +215,7 @@ void cpc710_pci_init (void) PCI_MEMORY_BUS, PCI_MEMORY_PHYS, PCI_MEMORY_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(local_hose.regions + 1, @@ -265,7 +265,7 @@ void cpc710_pci_init (void) PCI_MEMORY_BUS, PCI_MEMORY_PHYS, PCI_MEMORY_MAXSIZE, - PCI_REGION_MEMORY); + PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(cpci_hose.regions + 1, diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c index bf133b7..2948531 100644 --- a/board/ppmc7xx/pci.c +++ b/board/ppmc7xx/pci.c @@ -45,7 +45,7 @@ void pci_init_board(void) CONFIG_SYS_PCI_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index 9022c55..ac5f30b 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -197,7 +197,7 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; @@ -293,7 +293,7 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 519b0f7..a779420 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -470,7 +470,7 @@ pci_init_board(void) CONFIG_SYS_PCI_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* outbound memory */ pci_set_region(r++, diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 508bdc5..52ad2d8 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -384,3 +384,32 @@ unsigned long get_board_sys_clk (ulong dummy) return val; } + +void board_reset(void) +{ +#ifdef CONFIG_SYS_RESET_ADDRESS + ulong addr = CONFIG_SYS_RESET_ADDRESS; + + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); +#endif +} diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c index 4c91923..6ff4293 100644 --- a/board/tb0229/vr4131-pci.c +++ b/board/tb0229/vr4131-pci.c @@ -235,7 +235,7 @@ void init_vr4131_pci (struct pci_controller *hose) pci_set_region (hose->regions + 3, 0x00000000, 0x80000000, - 0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY); + 0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 0eedf4a..cb2cb8d 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -181,7 +181,7 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 3; diff --git a/board/tqc/tqm85xx/config.mk b/board/tqc/tqm85xx/config.mk index 52e84ad..37b7b23 100644 --- a/board/tqc/tqm85xx/config.mk +++ b/board/tqc/tqm85xx/config.mk @@ -23,7 +23,9 @@ # # tqm85xx board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256k # +ifeq ($(CONFIG_TQM8548_BE),y) +TEXT_BASE = 0xfff80000 +else TEXT_BASE = 0xfffc0000 +endif diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index fc92cd8..7e9a2c7 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -66,7 +66,7 @@ #endif struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR), SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c index dea652d..8133fdc 100644 --- a/board/tqc/tqm85xx/nand.c +++ b/board/tqc/tqm85xx/nand.c @@ -395,7 +395,7 @@ static void upmb_write (u_char addr, ulong val) */ static void nand_upm_setup (volatile ccsr_lbc_t *lbc) { - uint i; + uint i, j; uint or3 = CONFIG_SYS_OR3_PRELIM; uint clock = get_lbc_clock (); @@ -429,8 +429,8 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc) /* Assign address of table */ nand_upm_patt = upm_freq_table[i].upm_patt; - for (i = 0; i < 64; i++) { - upmb_write (i, *nand_upm_patt); + for (j = 0; j < 64; j++) { + upmb_write (j, *nand_upm_patt); nand_upm_patt++; } diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 783b280..6d73a88 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -1,3 +1,4 @@ + /* * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. @@ -38,11 +39,20 @@ struct sdram_conf_s { typedef struct sdram_conf_s sdram_conf_t; #ifdef CONFIG_TQM8548 +#ifdef CONFIG_TQM8548_AG +sdram_conf_t ddr_cs_conf[] = { + {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */ + { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ + { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ + { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ +}; +#else /* !CONFIG_TQM8548_AG */ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ }; +#endif /* CONFIG_TQM8548_AG */ #else /* !CONFIG_TQM8548 */ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ @@ -69,6 +79,9 @@ long int sdram_setup (int casl) volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); #ifdef CONFIG_TQM8548 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); +#endif #else /* !CONFIG_TQM8548 */ unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; @@ -81,21 +94,23 @@ long int sdram_setup (int casl) ddr->sdram_cfg = 0; #ifdef CONFIG_TQM8548 + /* Timing and refresh settings for DDR2-533 and below */ + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_3 = 0x00010000; + ddr->timing_cfg_3 = 0x00020000; /* TIMING CFG 1, 533MHz * PRETOACT: 4 Clocks * ACTTOPRE: 12 Clocks * ACTTORW: 4 Clocks * CASLAT: 4 Clocks - * REFREC: 34 Clocks + * REFREC: EXT_REFREC:REFREC 53 Clocks * WRREC: 4 Clocks * ACTTOACT: 3 Clocks * WRTORD: 2 Clocks */ - ddr->timing_cfg_1 = 0x4C47A432; + ddr->timing_cfg_1 = 0x4C47D432; /* TIMING CFG 2, 533MHz * ADD_LAT: 3 Clocks @@ -103,10 +118,10 @@ long int sdram_setup (int casl) * WR_LAT: 3 Clocks * RD_TO_PRE: 2 Clocks * WR_DATA_DELAY: 1/2 Clock - * CKE_PLS: 1 Clock - * FOUR_ACT: 13 Clocks + * CKE_PLS: 3 Clock + * FOUR_ACT: 14 Clocks */ - ddr->timing_cfg_2 = 0x3318484D; + ddr->timing_cfg_2 = 0x331848CE; /* DDR SDRAM Mode, 533MHz * MRS: Extended Mode Register @@ -136,13 +151,12 @@ long int sdram_setup (int casl) ddr->sdram_interval = (1040 << 16) | 0x100; /* - * workaround for erratum DD10 of MPC8458 family below rev. 2.0: - * DDR IO receiver must be set to an acceptable bias point by modifying - * a hidden register. + * Workaround for erratum DDR19 according to MPC8548 Device Errata + * document, Rev. 1: DDR IO receiver must be set to an acceptable + * bias point by modifying a hidden register. */ - if (SVR_REV (get_svr ()) < 0x20) { + if (SVR_REV (get_svr ()) < 0x21) gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ - } /* DDR SDRAM CFG 2 * FRC_SR: normal mode @@ -170,7 +184,104 @@ long int sdram_setup (int casl) /* wait for clock stabilization */ asm ("sync;isync;msync"); - udelay(1000); + udelay (1000); + +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) + /* + * Workaround for erratum DDR20 according to MPC8548 Device Errata + * document, Rev. 1: "CKE signal may not function correctly after + * assertion of HRESET" + */ + + /* 1. Configure DDR register as is done in normal DDR configuration. + * Do not set DDR_SDRAM_CFG[MEM_EN]. + * + * 2. Set reserved bit EEBACR[3] at offset 0x1000 + */ + ecm->eebacr |= 0x10000000; + + /* + * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT] + * + * DDR_SDRAM_CFG_2: + * FRC_SR: normal mode + * SR_IE: no self-refresh interrupt + * DLL_RST_DIS: don't care, leave at reset value + * DQS_CFG: differential DQS signals + * ODT_CFG: assert ODT to internal IOs only during reads to DRAM + * LVWx_CFG: don't care, leave at reset value + * NUM_PR: 1 refresh will be issued at a time + * DM_CFG: don't care, leave at reset value + * D_INIT: enable data initialization + */ + ddr->sdram_cfg_2 |= 0x00000010; + + /* + * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data + * training + */ + ddr->debug_3 |= 0x00000400; + + /* + * 5. Wait 200 micro-seconds + */ + udelay (200); + + /* + * 6. Set DDR_SDRAM_CFG[MEM_EN] + * + * BTW, initialize DDR_SDRAM_CFG: + * MEM_EN: enabled + * SREN: don't care, leave at reset value + * ECC_EN: no error report + * RD_EN: no registered DIMMs + * SDRAM_TYPE: DDR2 + * DYN_PWR: no power management + * 32_BE: don't care, leave at reset value + * 8_BE: 4 beat burst + * NCAP: don't care, leave at reset value + * 2T_EN: 1T Timing + * BA_INTLV_CTL: no interleaving + * x32_EN: x16 organization + * PCHB8: MA[10] for auto-precharge + * HSE: half strength for single and 2-layer stacks + * (full strength for 3- and 4-layer stacks not + * yet considered) + * MEM_HALT: no halt + * BI: automatic initialization + */ + ddr->sdram_cfg = 0x83000008; + + /* + * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware + */ + asm ("sync;isync;msync"); + while (ddr->sdram_cfg_2 & 0x00000010) + asm ("eieio"); + + /* + * 8. Clear D3[21] to re-enable data training + */ + ddr->debug_3 &= ~0x00000400; + + /* + * 9. Set D2(21) to force data training to run + */ + ddr->debug_2 |= 0x00000400; + + /* + * 10. Poll on D2[21] until it is cleared by hardware + */ + asm ("sync;isync;msync"); + while (ddr->debug_2 & 0x00000400) + asm ("eieio"); + + /* + * 11. Clear reserved bit EEBACR[3] at offset 0x1000 + */ + ecm->eebacr &= ~0x10000000; + +#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */ /* DDR SDRAM CLK CNTL * MEM_EN: enabled @@ -192,9 +303,11 @@ long int sdram_setup (int casl) * BI: automatic initialization */ ddr->sdram_cfg = 0x83000008; - asm ("sync; isync; msync"); - udelay(1000); +#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */ + + asm ("sync; isync; msync"); + udelay (1000); #else /* !CONFIG_TQM8548 */ switch (casl) { case 20: diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 16b102d..71fe3ab 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) + /* + * TLB 7+8: 2G DDR, cache enabled + * 0x00000000 2G DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + */ + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#else /* * TLB 7+8: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, @@ -136,7 +149,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - +#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index cda8208..e1e75b8 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -315,8 +315,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, 0xffffffff, &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ @@ -541,9 +540,9 @@ static int first_free_busno; extern int fsl_pci_setup_inbound_windows(struct pci_region *r); extern void fsl_pci_init(struct pci_controller *hose); -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -552,7 +551,7 @@ static struct pci_controller pcie1_hose; static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; @@ -627,9 +626,9 @@ static inline void init_pci1(void) } else { puts ("PCI1: disabled\n"); } -#else /* !(CONFIG_PCI || CONFIG_PCI1) */ +#else /* !CONFIG_PCI1 */ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ -#endif /* CONFIG_PCI || CONFIG_PCI1) */ +#endif /* CONFIG_PCI1 */ } static inline void init_pcie1(void) @@ -708,7 +707,7 @@ void ft_board_setup (void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 |