diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/atc/Makefile | 40 | ||||
| -rw-r--r-- | board/atc/atc.c | 366 | ||||
| -rw-r--r-- | board/atc/config.mk | 43 | ||||
| -rw-r--r-- | board/atc/flash.c | 665 | ||||
| -rw-r--r-- | board/atc/u-boot.lds | 118 | ||||
| -rw-r--r-- | board/gen860t/README | 25 | ||||
| -rw-r--r-- | board/gen860t/gen860t.c | 22 | ||||
| -rw-r--r-- | board/gen860t/ioport.c | 69 | ||||
| -rw-r--r-- | board/gen860t/u-boot-flashenv.lds | 132 | ||||
| -rw-r--r-- | board/gen860t/u-boot.lds | 11 |
10 files changed, 1449 insertions, 42 deletions
diff --git a/board/atc/Makefile b/board/atc/Makefile new file mode 100644 index 0000000..35b8428 --- /dev/null +++ b/board/atc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c new file mode 100644 index 0000000..3547f41 --- /dev/null +++ b/board/atc/atc.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ +#if 1 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#else + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#endif + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ +#if 0 + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ +#else + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ +#endif + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ +#if 0 + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ +#else + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ +#endif + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + printf ("Board: ATC\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + ulong cnt, val; + volatile ulong *addr; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + int i; + ulong save[32]; /* to make test non-destructive */ + ulong maxsize; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + /* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + i = 0; + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *) base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + /* Write the actual size to ORx + */ + *orx_ptr = orx | ~(cnt * sizeof (long) - 1); + return (cnt * sizeof (long)); + } + } + return (maxsize); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + long psize; + + psize = 8 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/atc/config.mk b/board/atc/config.mk new file mode 100644 index 0000000..8fc82f3 --- /dev/null +++ b/board/atc/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ATC boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_atc.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFF800000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFF000000 +endif + +# RAM version +#TEXT_BASE := 0x100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/atc/flash.c b/board/atc/flash.c new file mode 100644 index 0000000..4bcf2ee --- /dev/null +++ b/board/atc/flash.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { +#if 0 + ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; +#else + ulong flashbase = CFG_FLASH_BASE; +#endif + + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", + i, flash_info[i].size); + } + + size += flash_info[i].size; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base < info->start[0] + info->size) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(1000000);//psl + //psl switch (addr[1] & 0xff) { + switch (addr[0] & 0xff) {//psl + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + //psl if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds new file mode 100644 index 0000000..5df4cdb --- /dev/null +++ b/board/atc/u-boot.lds @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/gen860t/README b/board/gen860t/README index 761ceed..7c03f93 100644 --- a/board/gen860t/README +++ b/board/gen860t/README @@ -1,8 +1,7 @@ - This directory contains board specific code for a generic MPC860T based embedded computer, called 'GEN860T'. The design is generic in the sense that common, readily available components are used and that the architecture of the -system is i(relatively) straightforward: +system is relatively straightforward: One eight bit wide boot (FLASH) memory 32 bit main memory using SDRAM @@ -23,14 +22,14 @@ hearing from you, especially if you discover bugs or find ways to improve the quality of this U-Boot port. Here are the salient features of the system: -Clock : 33 Mhz oscillator -Processor core frequency : 66 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33 Mhz +Clock : 33.3 Mhz oscillator +Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 +Bus frequency : 33.3 Mhz Main memory: Type : SDRAM Width : 32 bits - Size : 64 megabytes + Size : 64 mibibytes Chip : Two Micron MT48LC16M16A2TG-7E CS : MPC860T CS1*/UPMA UPMA CONNECTIONS: @@ -42,7 +41,7 @@ Main memory: Boot memory: Type : FLASH Width : 8 bits - Size : 16 megabytes + Size : 16 mibibytes Chip : One Intel 28F128J3A (StrataFlash) CS : MPC860T CS0*/GPCM (this is the "boot" chip select) @@ -56,7 +55,7 @@ EEPROM memory: Filesystem memory: Type : NAND FLASH (Toshiba) Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 megabytes + Size : 32 mibibytes Chip : One DiskOnCHip Millenium Plus (DOC 2000+) CS : MPC860T CS2*/GPCM @@ -92,6 +91,12 @@ Miscellaneous: Mil-Std 1553 databus interface on CS5*/GPCM. Audio sounder (beeper) with digital volume control connected to SPKROUT. +SC variant: + A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. + The 'SC' variant only provides support for the Virtex FPGA, SDRAM main + memory, EEPROM and flash memory. The system clock frequency is reduced + to 24 MHz. + Issues: The DOC 2000+ returns 0x40 as its device ID when probed using the method desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver @@ -105,11 +110,11 @@ Status: in MTD for this device. I wish I had known this sooner :( The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copright and license notices +of others who have contributed to U-Boot. The copyright and license notices of these authors have been retained wherever their code has been reused. All new code to support the GEN860T board is: - (C) Copyright 2001-2002 + (C) Copyright 2001-2003 Keith Outwater (keith_outwater@mvis.com) and the following license applies: diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 16a3262..094eeef 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -271,18 +271,12 @@ misc_init_r (void) int last_stage_init(void) { +#if !defined(CONFIG_SC) unsigned char buf[256]; int i; /* - * Set LEDs here since status LED init code has already run - */ - status_led_set(STATUS_LED_BIT1, STATUS_LED_ON); - status_led_set(STATUS_LED_BIT3, STATUS_LED_ON); - - /* - * Turn the beeper volume all the way down in case this is a warm - * boot. + * Turn the beeper volume all the way down in case this is a warm boot. */ set_beeper_volume(-64); init_beeper(); @@ -294,6 +288,18 @@ last_stage_init(void) if (i > 0) { do_beeper(buf); } +#endif return 0; } + +/* + * Stub to make POST code happy. Can't self-poweroff, so just hang. + */ +void +board_poweroff(void) +{ + puts("### Please power off the board ###\n"); + while (1); +} + /* vim: set ts=4 sw=4 tw=78 : */ diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c index 5d6524d..7b3ebd4 100644 --- a/board/gen860t/ioport.c +++ b/board/gen860t/ioport.c @@ -42,8 +42,9 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High + * Pin Signal Type Active Initial state + * PA7 fpgaProgramLowOut Out Low High + * PA1 fpgaCoreVoltageFailLow In Low N/A */ { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ @@ -62,22 +63,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ +#else /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ }, /* + * Port B configuration * Pin Signal Type Active Initial state * PB14 docBusyLowIn In Low X * PB15 gpio1Sig Out High Low * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low Low + * PB17 swBitOkLowOut Out Low High * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) * PB22 fpgaInitLowBi In Low X * PB23 batteryOkSig In High X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + * PB31 pulseCatcherClr Out High 0 + */ + { /* conf ppar psor pdir podr pdat pint function */ +#if !defined(CONFIG_SC) + /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#else + /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ +#endif /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ @@ -85,19 +96,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ +#else + /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ +#else + /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ +#endif /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 0, 0 }, /* swBitOkLow */ + /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ +#if !defined(CONFIG_SC) /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ - }, +#else + /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ +#endif + }, /* + * Port C configuration * Pin Signal Type Active Initial state * PC4 i2cBus1EnSig Out High High * PC5 i2cBus2EnSig Out High High @@ -108,29 +132,48 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { * PC12 systemBitOkIn In High X * PC15 selfDreqLow In Low X */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ +#else + /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ +#if !defined(CONFIG_SC) /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ +#else + /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ +#else + /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ +#if !defined(CONFIG_SC) /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ +#else + /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ + /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, + }, - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat pint function */ + /* + * Port D configuration + */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ @@ -149,7 +192,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } + } }; /* diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds new file mode 100644 index 0000000..8b1ce1a --- /dev/null +++ b/board/gen860t/u-boot-flashenv.lds @@ -0,0 +1,132 @@ +/* + * Linker command file for the GEN860T board when the environment is + * stored in flash memory. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* + * Read-only sections, merged into text segment: + */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* + * Read-write section, merged into data segment: + */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data: + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); + + .ppcenv: + { + . = env_offset; + common/environment.o + } +} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index 1b53c72..b67faa6 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -56,15 +56,6 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset; - common/environment.o(.text) */ - *(.text) *(.fixup) *(.got1) @@ -128,8 +119,6 @@ SECTIONS *(.bss) *(COMMON) } - _end = . ; PROVIDE (end = .); } - |