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-rw-r--r--board/amcc/bamboo/bamboo.c23
-rw-r--r--board/amcc/ebony/ebony.c8
-rw-r--r--board/amcc/luan/Makefile (renamed from board/tqm8560/Makefile)18
-rw-r--r--board/amcc/luan/config.mk (renamed from board/tqm8560/config.mk)29
-rw-r--r--board/amcc/luan/epld.h85
-rw-r--r--board/amcc/luan/flash.c111
-rw-r--r--board/amcc/luan/init.S132
-rw-r--r--board/amcc/luan/luan.c458
-rw-r--r--board/amcc/luan/u-boot.lds (renamed from board/tqm8560/u-boot.lds)103
-rw-r--r--board/amcc/ocotea/ocotea.c8
-rw-r--r--board/amcc/yellowstone/yellowstone.c24
-rw-r--r--board/amcc/yosemite/yosemite.c24
-rw-r--r--board/prodrive/p3p440/p3p440.c11
-rw-r--r--board/sandburst/karef/karef.c6
-rw-r--r--board/sandburst/metrobox/metrobox.c7
-rw-r--r--board/tqm8540/init.S241
-rw-r--r--board/tqm8540/tqm8540.c284
-rw-r--r--board/tqm85xx/Makefile (renamed from board/tqm8540/Makefile)2
-rw-r--r--board/tqm85xx/config.mk (renamed from board/tqm8540/config.mk)2
-rw-r--r--board/tqm85xx/init.S (renamed from board/tqm8560/init.S)31
-rw-r--r--board/tqm85xx/sdram.c226
-rw-r--r--board/tqm85xx/tqm85xx.c (renamed from board/tqm8560/tqm8560.c)274
-rw-r--r--board/tqm85xx/u-boot.lds (renamed from board/tqm8540/u-boot.lds)4
-rw-r--r--board/xpedite1k/xpedite1k.c8
24 files changed, 1240 insertions, 879 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 53bf735..803995a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -359,10 +359,7 @@ void nand_init(void)
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
@@ -371,12 +368,6 @@ int checkboard(void)
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
return (0);
}
@@ -502,20 +493,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 9191f0f..a2595ee 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -90,11 +90,8 @@ int board_early_init_f(void)
int checkboard(void)
{
- sys_info_t sysinfo;
char *s = getenv("serial#");
- get_sys_info(&sysinfo);
-
printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
@@ -102,11 +99,6 @@ int checkboard(void)
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
diff --git a/board/tqm8560/Makefile b/board/amcc/luan/Makefile
index 403ad2d..5654f91 100644
--- a/board/tqm8560/Makefile
+++ b/board/amcc/luan/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2001
+# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -25,15 +25,15 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o
-SOBJS := init.o
-#SOBJS :=
+OBJS = $(BOARD).o
+OBJS += flash.o
+SOBJS = init.o
-$(LIB): $(OBJS) $(SOBJS)
+$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
- rm -f $(OBJS) $(SOBJS)
+ rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
@@ -41,8 +41,8 @@ distclean: clean
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
--include .depend
+sinclude .depend
#########################################################################
diff --git a/board/tqm8560/config.mk b/board/amcc/luan/config.mk
index 8aab1e2..f52c206 100644
--- a/board/tqm8560/config.mk
+++ b/board/amcc/luan/config.mk
@@ -1,6 +1,6 @@
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -22,8 +22,23 @@
#
#
-# tqm8560 board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
+# esd ADCIOP boards
#
-TEXT_BASE = 0xfffc0000
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
new file mode 100644
index 0000000..05362e0
--- /dev/null
+++ b/board/amcc/luan/epld.h
@@ -0,0 +1,85 @@
+#define EPLD0_FSEL_FB2 0x80
+#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */
+#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */
+#define EPLD0_RAW_CARD_BIT1 0x10
+#define EPLD0_RAW_CARD_BIT2 0x08
+#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */
+#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */
+#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
+
+#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
+#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
+#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
+#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
+#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
+#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
+#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */
+#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */
+
+#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */
+#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */
+#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */
+#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */
+#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */
+#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */
+#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */
+
+#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */
+#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */
+#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
+#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
+
+#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
+#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
+#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
+#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
+
+#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
+#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
+#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
+#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
+
+#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
+#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */
+#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */
+#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */
+#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */
+
+#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */
+#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */
+#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */
+#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */
+#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */
+#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */
+
+
+typedef struct {
+ unsigned char status; /* misc status */
+ unsigned char clock; /* clock status, PCI-X clock control */
+ unsigned char ethuart; /* Ethernet, UART status */
+ unsigned char leds; /* LED register */
+ unsigned char vth01; /* PCI0, PCI1 VTH register */
+ unsigned char pciints; /* PCI0, PCI1 interrupts */
+ unsigned char pci2; /* PCI2 interrupts, clock control */
+ unsigned char vth2; /* PCI2 VTH register */
+ unsigned char filler1[4096-8];
+ unsigned char gpio00; /* GPIO bits 0-7 */
+ unsigned char gpio08; /* GPIO bits 8-15 */
+ unsigned char gpio16; /* GPIO bits 16-23 */
+ unsigned char gpio24; /* GPIO bits 24-31 */
+ unsigned char filler2[4096-4];
+ unsigned char version; /* EPLD version */
+} epld_t;
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
new file mode 100644
index 0000000..d3c3c0d
--- /dev/null
+++ b/board/amcc/luan/flash.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
+ {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
new file mode 100644
index 0000000..7830ebd
--- /dev/null
+++ b/board/amcc/luan/init.S
@@ -0,0 +1,132 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
+ /* large flash */
+ tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+ tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+
+ tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+#else /* else booting from small flash */
+ tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+
+ tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+ tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#endif
+
+ tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
+ tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
+ tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#elif (CFG_SMALL_FLASH == 0xfff00000)
+ tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#else
+ #error DONT KNOW SRAM LOCATION
+#endif
+
+ /* internal ram (l2 cache) */
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /* peripherals at f0000000 */
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* PCI */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
+#endif
+ tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
new file mode 100644
index 0000000..c6b79a9
--- /dev/null
+++ b/board/amcc/luan/luan.c
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2005
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include "epld.h"
+
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*************************************************************************
+ * int board_early_init_f()
+ *
+ ************************************************************************/
+int board_early_init_f(void)
+{
+ volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+
+ mtebc( pb0ap, 0x03800000 ); /* set chip selects */
+ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+ mtebc( pb1ap, 0x03800000 );
+ mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+ mtebc( pb2ap, 0x03800000 );
+ mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+ mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
+ mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
+ mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
+ mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
+ mtdcr( uic1sr, 0xffffffff );
+
+ mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
+ mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
+ mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
+ mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
+ mtdcr( uic0sr, 0xffffffff );
+
+ x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int misc_init_r()
+ *
+ ************************************************************************/
+int misc_init_r(void)
+{
+ volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+ x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int checkboard()
+ *
+ ************************************************************************/
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Luan - AMCC PPC440SP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * long int fixed_sdram()
+ *
+ ************************************************************************/
+static long int fixed_sdram(void)
+{ /* DDR2 init from BDI2000 script */
+ mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
+ mtdcr( 0x11, 0x84000000 );
+ mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
+ mtdcr( 0x11, 0x2D122000 );
+ mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
+ mtdcr( 0x11, 0x00800026 );
+ mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
+ mtdcr( 0x11, 0x82000800 );
+ mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
+ mtdcr( 0x11, 0x80000000 );
+ mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
+ mtdcr( 0x11, 0x00000201 );
+ mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
+ mtdcr( 0x11, 0x00000201 );
+ mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
+ mtdcr( 0x11, 0x08200000 );
+ mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
+ mtdcr( 0x11, 0x80201000 );
+ mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
+ mtdcr( 0x11, 0x42103242 );
+ mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
+ mtdcr( 0x11, 0x0C100D14 );
+ mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
+ mtdcr( 0x11, 0x00000642 );
+ mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
+ mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
+
+ mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
+ mtdcr( 0x11, 0x81b80000 );
+ mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
+ mtdcr( 0x11, 0x82100400 );
+ mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
+ mtdcr( 0x11, 0x80820000 );
+ mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
+ mtdcr( 0x11, 0x80830000 );
+ mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
+ mtdcr( 0x11, 0x80810000 );
+ mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
+ mtdcr( 0x11, 0x80800542 );
+ mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
+ mtdcr( 0x11, 0x82100400 );
+ mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
+ mtdcr( 0x11, 0x99080000 );
+ mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
+ mtdcr( 0x11, 0x80800442 );
+ mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
+ mtdcr( 0x11, 0x80810380 );
+ mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
+ mtdcr( 0x11, 0x80810000 );
+ udelay( 10*1000 );
+
+ mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
+ mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
+ udelay( 100*1000 );
+
+ mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
+ mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
+
+ mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
+ mtdcr( 0x11, 0x00000000 );
+ mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
+ mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
+ mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
+ mtdcr( 0x11, 0x00000200 );
+
+ return 512 << 20;
+}
+
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram( int board_type )
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram (0);
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+ return dram_size;
+}
+
+
+/*************************************************************************
+ * int testdram()
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *) 0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+
+ return 0;
+}
+#endif
+
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init( struct pci_controller *hose )
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The luan board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+ out32r( PCIX0_BAR0, 0 );
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
+
+
+/*************************************************************************
+ * int on_off()
+ *
+ ************************************************************************/
+static int on_off( const char *s )
+{
+ if (strcmp(s, "on") == 0) {
+ return 1;
+ } else if (strcmp(s, "off") == 0) {
+ return 0;
+ }
+ return -1;
+}
+
+
+/*************************************************************************
+ * void l2cache_disable()
+ *
+ ************************************************************************/
+static void l2cache_disable(void)
+{
+ mtdcr( l2_cache_cfg, 0 );
+}
+
+
+/*************************************************************************
+ * void l2cache_enable()
+ *
+ ************************************************************************/
+static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
+{
+ mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
+
+ mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
+
+ mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
+
+ while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
+
+ mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
+
+ mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
+
+ mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
+ mtdcr( l2_cache_snp1, 0 );
+
+ __asm__ volatile ("sync"); /* msync */
+
+ mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
+
+ __asm__ volatile ("sync");
+}
+
+
+/*************************************************************************
+ * int l2cache_status()
+ *
+ ************************************************************************/
+static int l2cache_status(void)
+{
+ return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+}
+
+
+/*************************************************************************
+ * int do_l2cache()
+ *
+ ************************************************************************/
+int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
+{
+ switch (argc) {
+ case 2: /* on / off */
+ switch (on_off(argv[1])) {
+ case 0: l2cache_disable();
+ break;
+ case 1: l2cache_enable();
+ break;
+ }
+ /* FALL TROUGH */
+ case 1: /* get status */
+ printf ("L2 Cache is %s\n",
+ l2cache_status() ? "ON" : "OFF");
+ return 0;
+ default:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ l2cache, 2, 1, do_l2cache,
+ "l2cache - enable or disable L2 cache\n",
+ "[on, off]\n"
+ " - enable or disable L2 cache\n"
+ );
diff --git a/board/tqm8560/u-boot.lds b/board/amcc/luan/u-boot.lds
index 6f9240b..24a0fde 100644
--- a/board/tqm8560/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -1,6 +1,6 @@
/*
- * (C) Copyright 2002,2003, Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -34,61 +34,67 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
- cpu/mpc85xx/start.o (.bootpg)
- board/tqm8560/init.o (.bootpg)
+ cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
.plt : { *(.plt) }
- .text :
+ .text :
{
- cpu/mpc85xx/start.o (.text)
- board/tqm8560/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/luan/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
*(.text)
*(.fixup)
*(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
- .fini : { *(.fini) } =0
+ .fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -104,10 +110,10 @@ SECTIONS
_FIXUP_TABLE_ = .;
*(.fixup)
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
- .data :
+ .data :
{
*(.data)
*(.data1)
@@ -124,6 +130,7 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
@@ -137,7 +144,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
- .bss :
+ .bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 3926109..d1a29c5 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -186,11 +186,8 @@ int board_early_init_f (void)
int checkboard (void)
{
- sys_info_t sysinfo;
char *s = getenv ("serial#");
- get_sys_info (&sysinfo);
-
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
if (s != NULL) {
puts (", serial# ");
@@ -198,11 +195,6 @@ int checkboard (void)
}
putc ('\n');
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 069e28f..585f072 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -188,10 +188,7 @@ int misc_init_r (void)
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
if (s != NULL) {
@@ -200,13 +197,6 @@ int checkboard(void)
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-
return (0);
}
@@ -325,20 +315,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 61a39be..6694517 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -184,10 +184,7 @@ int misc_init_r (void)
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
@@ -196,13 +193,6 @@ int checkboard(void)
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-
return (0);
}
@@ -321,20 +311,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index cc4c9dd..8ba66bf 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -120,11 +120,7 @@ int board_early_init_f(void)
int checkboard(void)
{
- sys_info_t sysinfo;
char *s = getenv("serial#");
- char buf[32];
-
- get_sys_info(&sysinfo);
printf("Board: P3P440");
if (s != NULL) {
@@ -140,13 +136,6 @@ int checkboard(void)
putc('\n');
- printf(" at %s MHz (VCO=%lu, PLB=%lu, OPB=%lu, EBC=%lu MHz)\n",
- strmhz(buf, sysinfo.freqProcessor),
- sysinfo.freqVCOMhz / 1000000,
- sysinfo.freqPLB / 1000000,
- sysinfo.freqOPB / 1000000,
- sysinfo.freqEPB / 1000000);
-
return (0);
}
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index cfbfa47..2d71d3b 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -305,12 +305,6 @@ int checkboard (void)
printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
}
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 869367d..86d259f 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -272,13 +272,6 @@ int checkboard (void)
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
-
/* Fix the ack in the bme 32 */
udelay(5000);
out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
diff --git a/board/tqm8540/init.S b/board/tqm8540/init.S
deleted file mode 100644
index d9f4d8f..0000000
--- a/board/tqm8540/init.S
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0, 1: 32M Non-cacheable, guarded
- * 0xfe000000 32M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 7: 256M DDR
- * 0x00000000 256M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
-#endif
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
- .long 0x05
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4
- entry_end
diff --git a/board/tqm8540/tqm8540.c b/board/tqm8540/tqm8540.c
deleted file mode 100644
index 970c684..0000000
--- a/board/tqm8540/tqm8540.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright 2005 DENX Software Engineering
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <spd.h>
-
-#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-
-extern long int spd_sdram (void);
-
-void local_bus_init (void);
-long int fixed_sdram (void);
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("Board: TQM8540\n");
-
-#ifdef CONFIG_PCI
- printf ("PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf ("PCI1: disabled\n");
-#endif
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur= &immap->im_gur;
- int i,x;
-
- x = 10;
-
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
- x++;
- }
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc (dram_size);
-#endif
-
- return dram_size;
-}
-
-
-/*
- * Initialize Local Bus
- */
-
-void local_bus_init (void)
-{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
- lbc->ltedr = 0xa4c80000; /* DK: !!! */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr ();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
- udelay (200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm ("sync;isync;msync");
- }
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->err_disable = 0x0000000D;
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm ("sync;isync;msync");
- udelay (500);
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
-#endif
- asm ("sync; isync; msync");
- udelay (500);
-#endif
- return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init (struct pci_controller *hose);
-
- pci_mpc85xx_init (&hose);
-#endif /* CONFIG_PCI */
-}
diff --git a/board/tqm8540/Makefile b/board/tqm85xx/Makefile
index 403ad2d..3933d46 100644
--- a/board/tqm8540/Makefile
+++ b/board/tqm85xx/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o
+OBJS := $(BOARD).o sdram.o
SOBJS := init.o
#SOBJS :=
diff --git a/board/tqm8540/config.mk b/board/tqm85xx/config.mk
index b0ba25f..52e84ad 100644
--- a/board/tqm8540/config.mk
+++ b/board/tqm85xx/config.mk
@@ -22,7 +22,7 @@
#
#
-# tqm8540 board
+# tqm85xx board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
diff --git a/board/tqm8560/init.S b/board/tqm85xx/init.S
index d9f4d8f..1f61038 100644
--- a/board/tqm8560/init.S
+++ b/board/tqm85xx/init.S
@@ -108,18 +108,18 @@ tlb1_entry:
/*
- * TLB 0, 1: 32M Non-cacheable, guarded
- * 0xfe000000 32M FLASH
+ * TLB 0, 1: 128M Non-cacheable, guarded
+ * 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
@@ -171,23 +171,21 @@ tlb1_entry:
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-#if !defined(CONFIG_SPD_EEPROM)
/*
- * TLB 7: 256M DDR
- * 0x00000000 256M DDR System memory
+ * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
-#endif
entry_end
@@ -207,19 +205,14 @@ tlb1_entry:
* If flash is 8M at default position (last 8M), no LAW needed.
*/
-#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c
new file mode 100644
index 0000000..9c1f087
--- /dev/null
+++ b/board/tqm85xx/sdram.c
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd.h>
+
+struct sdram_conf_s {
+ unsigned long size;
+ unsigned long reg;
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+sdram_conf_t ddr_cs_conf[] = {
+ {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
+ {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
+ {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
+ {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
+};
+
+#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
+
+int cas_latency(void);
+
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+long int sdram_setup(int casl)
+{
+ int i;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ unsigned long cfg_ddr_timing1;
+ unsigned long cfg_ddr_mode;
+
+ /*
+ * Disable memory controller.
+ */
+ ddr->cs0_config = 0;
+ ddr->sdram_cfg = 0;
+
+ switch (casl) {
+ case 20:
+ cfg_ddr_timing1 = 0x47405331 | (3 << 16);
+ cfg_ddr_mode = 0x40020002 | (2 << 4);
+ break;
+
+ case 25:
+ cfg_ddr_timing1 = 0x47405331 | (4 << 16);
+ cfg_ddr_mode = 0x40020002 | (6 << 4);
+ break;
+
+ case 30:
+ default:
+ cfg_ddr_timing1 = 0x47405331 | (5 << 16);
+ cfg_ddr_mode = 0x40020002 | (3 << 4);
+ break;
+ }
+
+ ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
+ ddr->cs0_config = ddr_cs_conf[0].reg;
+ ddr->timing_cfg_1 = cfg_ddr_timing1;
+ ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
+ ddr->sdram_mode = cfg_ddr_mode;
+ ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
+ ddr->err_disable = 0x0000000D;
+
+ asm ("sync;isync;msync");
+ udelay(1000);
+
+ ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
+ asm ("sync; isync; msync");
+ udelay(1000);
+
+ for (i=0; i<N_DDR_CS_CONF; i++) {
+ ddr->cs0_config = ddr_cs_conf[i].reg;
+
+ if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
+ /*
+ * OK, size detected -> all done
+ */
+ return ddr_cs_conf[i].size;
+ }
+ }
+
+ return 0; /* nothing found ! */
+}
+
+void board_add_ram_info(int use_default)
+{
+ int casl;
+
+ if (use_default)
+ casl = CONFIG_DDR_DEFAULT_CL;
+ else
+ casl = cas_latency();
+
+ puts(" (CL=");
+ switch (casl) {
+ case 20:
+ puts("2)");
+ break;
+
+ case 25:
+ puts("2.5)");
+ break;
+
+ case 30:
+ puts("3)");
+ break;
+ }
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ int casl;
+
+#if defined(CONFIG_DDR_DLL)
+ /*
+ * This DLL-Override only used on TQM8540 and TQM8560
+ */
+ {
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+ int i,x;
+
+ x = 10;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay (200);
+ while (gur->ddrdllcr != 0x81000100) {
+ gur->devdisr = gur->devdisr | 0x00010000;
+ asm("sync;isync;msync");
+ for (i=0; i<x; i++)
+ ;
+ gur->devdisr = gur->devdisr & 0xfff7ffff;
+ asm("sync;isync;msync");
+ x++;
+ }
+ }
+#endif
+
+ casl = cas_latency();
+ dram_size = sdram_setup(casl);
+ if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
+ /*
+ * Try again with default CAS latency
+ */
+ puts("Problem with CAS lantency");
+ board_add_ram_info(1);
+ puts(", using default CL!\n");
+ casl = CONFIG_DDR_DEFAULT_CL;
+ dram_size = sdram_setup(casl);
+ puts(" ");
+ }
+
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf ("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test passed.\n");
+ return 0;
+}
+#endif
diff --git a/board/tqm8560/tqm8560.c b/board/tqm85xx/tqm85xx.c
index 71f5880..13ea6f4 100644
--- a/board/tqm8560/tqm8560.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -1,5 +1,7 @@
/*
- * Copyright 2005 DENX Software Engineering
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@@ -32,16 +34,15 @@
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
+#include <flash.h>
-#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-
-extern long int spd_sdram (void);
+extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
long int fixed_sdram (void);
+ulong flash_get_size (ulong base, int banknum);
+#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
*
@@ -53,24 +54,24 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
@@ -89,20 +90,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
@@ -135,12 +136,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
@@ -195,16 +196,49 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
+#endif /* CONFIG_CPM2 */
+
+#define CASL_STRING1 "casl=xx"
+#define CASL_STRING2 "casl="
+static const int casl_table[] = { 20, 25, 30 };
+#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-int board_early_init_f (void)
+int cas_latency(void)
{
- return 0;
+ char *s = getenv("serial#");
+ int casl;
+ int val;
+ int i;
+
+ casl = CONFIG_DDR_DEFAULT_CL;
+
+ if (s != NULL) {
+ if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
+ strlen(CASL_STRING2)) == 0) {
+ val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
+
+ for (i=0; i<N_CASL; ++i) {
+ if (val == casl_table[i]) {
+ return val;
+ }
+ }
+ }
+ }
+
+ return casl;
}
int checkboard (void)
{
- puts ("Board: TQM8560\n");
+ char *s = getenv("serial#");
+
+ printf("Board: %s", CONFIG_BOARDNAME);
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
@@ -212,6 +246,7 @@ int checkboard (void)
#else
printf ("PCI1: disabled\n");
#endif
+
/*
* Initialize local bus.
*/
@@ -220,59 +255,69 @@ int checkboard (void)
return 0;
}
-
-long int initdram (int board_type)
+int misc_init_r (void)
{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *memctl = &immap->im_lbc;
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur= &immap->im_gur;
- int i,x;
+ /*
+ * Adjust flash start and offset to detected values
+ */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
- x = 10;
+ /*
+ * Check if boot FLASH isn't max size
+ */
+ if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
+ memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
+ memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
- * Work around to stabilize DDR DLL
+ * Re-check to get correct base address
*/
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
- x++;
- }
+ flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC)
/*
- * Initialize and enable DDR ECC.
+ * Check if only one FLASH bank is available
*/
- ddr_enable_ecc (dram_size);
-#endif
+ if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+ memctl->or1 = 0;
+ memctl->br1 = 0;
- return dram_size;
-}
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE, 0xffffffff,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+ &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ }
+ return 0;
+}
/*
* Initialize Local Bus
*/
-
void local_bus_init (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -329,79 +374,6 @@ void local_bus_init (void)
}
}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->err_disable = 0x0000000D;
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm ("sync;isync;msync");
- udelay (500);
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
-#endif
- asm ("sync; isync; msync");
- udelay (500);
-#endif
- return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
diff --git a/board/tqm8540/u-boot.lds b/board/tqm85xx/u-boot.lds
index 4fdf87c..65d0c04 100644
--- a/board/tqm8540/u-boot.lds
+++ b/board/tqm85xx/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/tqm8540/init.o (.bootpg)
+ board/tqm85xx/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/tqm8540/init.o (.text)
+ board/tqm85xx/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index d6b30b9..bb36c96 100644
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -96,15 +96,7 @@ int board_early_init_f(void)
int checkboard (void)
{
- sys_info_t sysinfo;
- get_sys_info (&sysinfo);
-
printf ("Board: XES XPedite1000 440GX\n");
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}