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-rw-r--r--board/cpc45/cpc45.c152
-rw-r--r--board/cpc45/flash.c311
-rw-r--r--board/lpd7a40x/flash.c2
-rw-r--r--board/mx1ads/Makefile48
-rw-r--r--board/mx1ads/config.mk49
-rw-r--r--board/mx1ads/memsetup.S9
-rw-r--r--board/mx1ads/mx1ads.c41
-rw-r--r--board/mx1ads/syncflash.c46
-rw-r--r--board/mx1ads/u-boot.lds2
-rw-r--r--board/pm520/flash.c25
-rw-r--r--board/pm520/mt46v16m16-75.h37
-rw-r--r--board/pm520/mt48lc16m16a2-75.h43
-rw-r--r--board/pm520/pm520.c284
13 files changed, 691 insertions, 358 deletions
diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c
index ad69245..92ccd42 100644
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <asm/processor.h>
#include <pci.h>
+#include <i2c.h>
int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
@@ -58,46 +59,134 @@ int checkboard(void)
return 0;
}
-long int initdram(int board_type)
+long int initdram (int board_type)
{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
+ int m, row, col, bank, i, ref;
+ unsigned long start, end;
+ uint32_t mccr1, mccr2;
+ uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+ uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+ uint8_t mber = 0;
+ unsigned int tmp;
+
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ if (i2c_reg_read (0x50, 2) != 0x04)
+ return 0; /* Memory type */
+
+ m = i2c_reg_read (0x50, 5); /* # of physical banks */
+ row = i2c_reg_read (0x50, 3); /* # of rows */
+ col = i2c_reg_read (0x50, 4); /* # of columns */
+ bank = i2c_reg_read (0x50, 17); /* # of logical banks */
+ ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
+
+ CONFIG_READ_WORD(MCCR1, mccr1);
+ mccr1 &= 0xffff0000;
+
+ CONFIG_READ_WORD(MCCR2, mccr2);
+ mccr2 &= 0xffff0000;
+
+ start = CFG_SDRAM_BASE;
+ end = start + (1 << (col + row + 3) ) * bank - 1;
+
+ for (i = 0; i < m; i++) {
+ mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+ if (i < 4) {
+ msar1 |= ((start >> 20) & 0xff) << i * 8;
+ emsar1 |= ((start >> 28) & 0xff) << i * 8;
+ mear1 |= ((end >> 20) & 0xff) << i * 8;
+ emear1 |= ((end >> 28) & 0xff) << i * 8;
+ } else {
+ msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
+ emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+ mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
+ emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+ }
+ mber |= 1 << i;
+ start += (1 << (col + row + 3) ) * bank;
+ end += (1 << (col + row + 3) ) * bank;
+ }
+ for (; i < 8; i++) {
+ if (i < 4) {
+ msar1 |= 0xff << i * 8;
+ emsar1 |= 0x30 << i * 8;
+ mear1 |= 0xff << i * 8;
+ emear1 |= 0x30 << i * 8;
+ } else {
+ msar2 |= 0xff << (i-4) * 8;
+ emsar2 |= 0x30 << (i-4) * 8;
+ mear2 |= 0xff << (i-4) * 8;
+ emear2 |= 0x30 << (i-4) * 8;
+ }
+ }
+
+ switch(ref) {
+ case 0x00:
+ case 0x80:
+ tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+ break;
+ case 0x01:
+ case 0x81:
+ tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+ break;
+ case 0x02:
+ case 0x82:
+ tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+ break;
+ case 0x03:
+ case 0x83:
+ tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+ break;
+ case 0x04:
+ case 0x84:
+ tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+ break;
+ case 0x05:
+ case 0x85:
+ tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+ break;
+ default:
+ tmp = 0x512;
+ break;
+ }
+
+ CONFIG_WRITE_WORD(MCCR1, mccr1);
+ CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+ CONFIG_WRITE_WORD(MSAR1, msar1);
+ CONFIG_WRITE_WORD(EMSAR1, emsar1);
+ CONFIG_WRITE_WORD(MEAR1, mear1);
+ CONFIG_WRITE_WORD(EMEAR1, emear1);
+ CONFIG_WRITE_WORD(MSAR2, msar2);
+ CONFIG_WRITE_WORD(EMSAR2, emsar2);
+ CONFIG_WRITE_WORD(MEAR2, mear2);
+ CONFIG_WRITE_WORD(EMEAR2, emear2);
+ CONFIG_WRITE_BYTE(MBER, mber);
+
+ return (1 << (col + row + 3) ) * bank * m;
}
+
/*
* Initialize PCI Devices, report devices found.
*/
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_sandpoint_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+ PCI_PLX9030_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
{ }
};
-#endif
-
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
- config_table: pci_sandpoint_config_table,
+ config_table: pci_cpc45_config_table,
#endif
};
@@ -108,6 +197,9 @@ void pci_init_board(void)
/* init PCI_to_LOCAL Bus BRIDGE */
Plx9030Init();
+ /* Clear Display */
+ DISP_CWORD = 0x0;
+
sysControlDisplay(0,' ');
sysControlDisplay(1,'C');
sysControlDisplay(2,'P');
@@ -130,16 +222,14 @@ void pci_init_board(void)
* RETURNS: NA
*/
-int sysControlDisplay
- (
- int digit, /* number of digit 0..7 */
- uchar ascii_code /* ASCII code */
- )
+int sysControlDisplay (int digit, /* number of digit 0..7 */
+ uchar ascii_code /* ASCII code */
+ )
{
if ((digit < 0) || (digit > 7))
return (-1);
- *((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
+ *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
return (0);
}
diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c
index 9049235..37dd182 100644
--- a/board/cpc45/flash.c
+++ b/board/cpc45/flash.c
@@ -41,12 +41,12 @@
#define MAIN_SECT_SIZE 0x40000
#define PARAM_SECT_SIZE 0x8000
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-static int write_data (flash_info_t *info, ulong dest, ulong *data);
-static void write_via_fpu(vu_long *addr, ulong *data);
-static __inline__ unsigned long get_msr(void);
-static __inline__ void set_msr(unsigned long msr);
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
@@ -62,102 +62,132 @@ static __inline__ void set_msr(unsigned long msr);
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init(void)
+unsigned long flash_init (void)
{
- int i, j;
- ulong size = 0;
- uchar tempChar;
+ int i, j;
+ ulong size = 0;
+ uchar tempChar;
+ vu_long *tmpaddr;
- /* Enable flash writes on CPC45 */
+ /* Enable flash writes on CPC45 */
- tempChar = BOARD_CTRL;
+ tempChar = BOARD_CTRL;
- tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+ tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
- tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+ tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
- BOARD_CTRL = tempChar;
+ BOARD_CTRL = tempChar;
+ __asm__ volatile ("sync\n eieio");
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
- vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
- addr[0] = 0x00900090;
+ addr[0] = 0x00900090;
- DEBUGF ("Flash bank # %d:\n"
- "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
- "\tDevice ID @ 0x%08lX: 0x%08lX\n",
- i,
- (ulong)(&addr[0]), addr[0],
- (ulong)(&addr[2]), addr[2]);
+ __asm__ volatile ("sync\n eieio");
+ udelay (100);
- if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
- (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
- {
+ DEBUGF ("Flash bank # %d:\n"
+ "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+ "\tDevice ID @ 0x%08lX: 0x%08lX\n",
+ i,
+ (ulong) (&addr[0]), addr[0],
+ (ulong) (&addr[2]), addr[2]);
- flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
- (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
- } else {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- addr[0] = 0xFFFFFFFF;
- goto Done;
- }
+ if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+ (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
- DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+ flash_info[i].flash_id =
+ (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+ (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
- addr[0] = 0xFFFFFFFF;
+ } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+ && (addr[2] == addr[3])
+ && (addr[2] == INTEL_ID_28F160C3T)) {
+
+ flash_info[i].flash_id =
+ (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+ (INTEL_ID_28F160C3T & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
- for (j = 0; j < flash_info[i].sector_count; j++) {
- if (j > 30) {
- flash_info[i].start[j] = CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
} else {
- flash_info[i].start[j] = CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- j * MAIN_SECT_SIZE;
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ addr[0] = 0xFFFFFFFF;
+ goto Done;
+ }
+
+ DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+ addr[0] = 0xFFFFFFFF;
+
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ if (j > 30) {
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
+ (MAIN_SECT_SIZE * 31) + (j -
+ 31) *
+ PARAM_SECT_SIZE;
+ } else {
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
+ j * MAIN_SECT_SIZE;
+ }
+ }
+
+ /* unlock sectors, if 160C3T */
+
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ tmpaddr = (vu_long *) flash_info[i].start[j];
+
+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+ (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+ tmpaddr[0] = 0x00600060;
+ tmpaddr[0] = 0x00D000D0;
+ tmpaddr[1] = 0x00600060;
+ tmpaddr[1] = 0x00D000D0;
+ }
}
+
+ size += flash_info[i].size;
+
+ addr[0] = 0x00FF00FF;
+ addr[1] = 0x00FF00FF;
}
- size += flash_info[i].size;
- }
- /* Protect monitor and environment sectors
- */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* Protect monitor and environment sectors
+ */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[1]);
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[1]);
#else
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- &flash_info[1]);
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
#else
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- &flash_info[0]);
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
#endif
Done:
- return size;
+ return size;
}
/*-----------------------------------------------------------------------
@@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
printf ("28F160F3T (16Mbit)\n");
break;
+
+ case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+ printf ("28F160C3T (16Mbit)\n");
+ break;
+
default:
printf ("Unknown Chip Type 0x%04x\n", i);
goto Done;
@@ -186,7 +221,7 @@ void flash_print_info (flash_info_t * info)
}
printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
+ info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
@@ -194,7 +229,7 @@ void flash_print_info (flash_info_t * info)
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
+ info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
@@ -205,7 +240,7 @@ Done:
/*-----------------------------------------------------------------------
*/
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong start, now, last;
@@ -229,33 +264,32 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
+ for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
start = get_timer (0);
- last = start;
+ last = start;
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
+ vu_long *addr = (vu_long *) (info->start[sect]);
DEBUGF ("Erase sect %d @ 0x%08lX\n",
- sect, (ulong)addr);
+ sect, (ulong) addr);
/* Disable interrupts which might cause a timeout
* here.
*/
- flag = disable_interrupts();
+ flag = disable_interrupts ();
addr[0] = 0x00500050; /* clear status register */
addr[0] = 0x00200020; /* erase setup */
@@ -267,23 +301,23 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
- enable_interrupts();
+ enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080) ) {
- if ((now=get_timer(start)) >
- CFG_FLASH_ERASE_TOUT) {
+ ((addr[1] & 0x00800080) != 0x00800080)) {
+ if ((now = get_timer (start)) >
+ CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
- addr[0] = 0x00B000B0; /* suspend erase */
- addr[0] = 0x00FF00FF; /* to read mode */
+ addr[0] = 0x00B000B0; /* suspend erase */
+ addr[0] = 0x00FF00FF; /* to read mode */
return 1;
}
/* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
+ if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
@@ -306,7 +340,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
#define FLASH_WIDTH 8 /* flash bus width in bytes */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, cp, msr;
int l, rc, i;
@@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
ulong *datal = &data[1];
DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
- addr, (ulong)src, cnt);
+ addr, (ulong) src, cnt);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
- msr = get_msr();
- set_msr(msr | MSR_FP);
+ msr = get_msr ();
+ set_msr (msr | MSR_FP);
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
+ wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */
/*
* handle unaligned start bytes
@@ -335,39 +369,35 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
for (i = 0, cp = wp; i < l; i++, cp++) {
if (i >= 4) {
*datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
+ ((*datal & 0xFF000000) >> 24);
}
- *datal = (*datal << 8) | (*(uchar *)cp);
+ *datal = (*datal << 8) | (*(uchar *) cp);
}
for (; i < FLASH_WIDTH && cnt > 0; ++i) {
- char tmp;
-
- tmp = *src;
-
- src++;
+ char tmp = *src++;
if (i >= 4) {
*datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
+ ((*datal & 0xFF000000) >> 24);
}
*datal = (*datal << 8) | tmp;
-
- --cnt; ++cp;
+ --cnt;
+ ++cp;
}
for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
*datah = (*datah << 8) |
- ((*datal & 0xFF000000) >> 24);
+ ((*datal & 0xFF000000) >> 24);
}
- *datal = (*datah << 8) | (*(uchar *)cp);
+ *datal = (*datah << 8) | (*(uchar *) cp);
}
- if ((rc = write_data(info, wp, data)) != 0) {
- set_msr(msr);
+ if ((rc = write_data (info, wp, data)) != 0) {
+ set_msr (msr);
return (rc);
}
@@ -378,19 +408,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
- *datah = *(ulong *)src;
- *datal = *(ulong *)(src + 4);
- if ((rc = write_data(info, wp, data)) != 0) {
- set_msr(msr);
+ *datah = *(ulong *) src;
+ *datal = *(ulong *) (src + 4);
+ if ((rc = write_data (info, wp, data)) != 0) {
+ set_msr (msr);
return (rc);
}
- wp += FLASH_WIDTH;
+ wp += FLASH_WIDTH;
cnt -= FLASH_WIDTH;
src += FLASH_WIDTH;
}
if (cnt == 0) {
- set_msr(msr);
+ set_msr (msr);
return (0);
}
@@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
*datah = *datal = 0;
for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
- char tmp;
-
- tmp = *src;
-
- src++;
+ char tmp = *src++;
if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+ *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+ 24);
}
*datal = (*datal << 8) | tmp;
-
--cnt;
}
for (; i < FLASH_WIDTH; ++i, ++cp) {
if (i >= 4) {
- *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+ *datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+ 24);
}
- *datal = (*datal << 8) | (*(uchar *)cp);
+ *datal = (*datal << 8) | (*(uchar *) cp);
}
- rc = write_data(info, wp, data);
- set_msr(msr);
+ rc = write_data (info, wp, data);
+ set_msr (msr);
return (rc);
}
@@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_data (flash_info_t *info, ulong dest, ulong *data)
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
{
- vu_long *addr = (vu_long *)dest;
+ vu_long *addr = (vu_long *) dest;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if (((addr[0] & data[0]) != data[0]) ||
- ((addr[1] & data[1]) != data[1]) ) {
+ ((addr[1] & data[1]) != data[1])) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
+ flag = disable_interrupts ();
- addr[0] = 0x00400040; /* write setup */
- write_via_fpu(addr, data);
+ addr[0] = 0x00400040; /* write setup */
+ write_via_fpu (addr, data);
/* re-enable interrupts if necessary */
if (flag)
- enable_interrupts();
+ enable_interrupts ();
start = get_timer (0);
while (((addr[0] & 0x00800080) != 0x00800080) ||
- ((addr[1] & 0x00800080) != 0x00800080) ) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ ((addr[1] & 0x00800080) != 0x00800080)) {
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
addr[0] = 0x00FF00FF; /* restore read mode */
return (1);
}
@@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)
/*-----------------------------------------------------------------------
*/
-static void write_via_fpu(vu_long *addr, ulong *data)
+static void write_via_fpu (vu_long * addr, ulong * data)
{
- __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
- __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+ __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
+ __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
}
+
/*-----------------------------------------------------------------------
*/
-static __inline__ unsigned long get_msr(void)
+static __inline__ unsigned long get_msr (void)
{
- unsigned long msr;
+ unsigned long msr;
+
+ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
- __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
- return msr;
+ return msr;
}
-static __inline__ void set_msr(unsigned long msr)
+static __inline__ void set_msr (unsigned long msr)
{
- __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+ __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
}
diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
index 26a9ce4..7b8e014 100644
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -300,7 +300,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
do {
ulong now;
/* check timeout */
- //if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ /*if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { */
if ((now = get_timer(tstart)) > CFG_FLASH_ERASE_TOUT) {
printf("tstart = 0x%08lx, now = 0x%08lx\n", tstart, now);
*addr = CMD_STATUS_RESET;
diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile
index 8a17702..72f850d 100644
--- a/board/mx1ads/Makefile
+++ b/board/mx1ads/Makefile
@@ -1,28 +1,26 @@
-#/*
-#* board/mx1ads/Makefile
-#*
-#* (c) Copyright 2004
-#* Techware Information Technology, Inc.
-#* http://www.techware.com.tw/
-#*
-#* Ming-Len Wu <minglen_wu@techware.com.tw>
-#*
-#* This program is free software; you can redistribute it and/or
-#* modify it under the terms of the GNU General Public License as
-#* published by the Free Software Foundation; either version 2 of
-#* the License, or (at your option) any later version.
-#*
-#* This program is distributed in the hope that it will be useful,
-#* but WITHOUT ANY WARRANTY; without even the implied warranty of
-#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-#* GNU General Public License for more details.
-#*
-#* You should have received a copy of the GNU General Public License
-#* along with this program; if not, write to the Free Software
-#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-#* MA 02111-1307 USA
-#*/
-
+#
+# board/mx1ads/Makefile
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
include $(TOPDIR)/config.mk
diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk
index 16a0b84..f6ac40d 100644
--- a/board/mx1ads/config.mk
+++ b/board/mx1ads/config.mk
@@ -1,28 +1,25 @@
-#/*
-#* board/mx1ads/config.mk
-#*
-#* (c) Copyright 2004
-#* Techware Information Technology, Inc.
-#* http://www.techware.com.tw/
-#*
-#* Ming-Len Wu <minglen_wu@techware.com.tw>
-#*
-#* This program is free software; you can redistribute it and/or
-#* modify it under the terms of the GNU General Public License as
-#* published by the Free Software Foundation; either version 2 of
-#* the License, or (at your option) any later version.
-#*
-#* This program is distributed in the hope that it will be useful,
-#* but WITHOUT ANY WARRANTY; without even the implied warranty of
-#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-#* GNU General Public License for more details.
-#*
-#* You should have received a copy of the GNU General Public License
-#* along with this program; if not, write to the Free Software
-#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-#* MA 02111-1307 USA
-#*/
-
+#
+# board/mx1ads/config.mk
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
TEXT_BASE = 0x08400000
-
diff --git a/board/mx1ads/memsetup.S b/board/mx1ads/memsetup.S
index 39b71fe..1b06fa3 100644
--- a/board/mx1ads/memsetup.S
+++ b/board/mx1ads/memsetup.S
@@ -1,6 +1,6 @@
/*
* board/mx1ads/memsetup.S
- *
+ *
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -49,7 +49,7 @@ memsetup:
/* Issue Precharge All Commad */
ldr r3, =0x8200000
ldr r2, [r3]
-
+
/* Set AutoRefresh Command */
ldr r3, =0xA2120200
str r3, [r1]
@@ -64,11 +64,11 @@ memsetup:
ldr r2, [r3]
ldr r2, [r3]
ldr r2, [r3]
-
+
/* Set Mode Register */
ldr r3, =0xB2120200
str r3, [r1]
-
+
/* Issue Mode Register Command */
ldr r3, =0x08111800 /* Mode Register Value */
ldr r2, [r3]
@@ -79,4 +79,3 @@ memsetup:
/* everything is fine now */
mov pc, lr
-
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 567f88a..453e4bb 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -1,6 +1,6 @@
/*
* board/mx1ads/mx1ads.c
- *
+ *
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -61,7 +61,7 @@ static inline void delay (unsigned long loops) {
"bne 1b":"=r" (loops):"0" (loops));
}
-#endif
+#endif
/*
* Miscellaneous platform dependent initialisations
@@ -76,7 +76,7 @@ void SetAsynchMode(void) {
"mcr p15,0,r0,c1,c0,0 \n"
);
}
-
+
static u32 mc9328sid;
int board_init (void) {
@@ -88,16 +88,13 @@ int board_init (void) {
mc9328sid = MX1_SIDR;
MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
-
+
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
-
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
-/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
-
-
+/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
@@ -108,13 +105,13 @@ int board_init (void) {
MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
-
+
MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
MX1_CS4L = 0x00001501;
-
+
MX1_GIUS_A &= 0xFF3FFFFF;
MX1_GPR_A &= 0xFF3FFFFF;
-
+
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
@@ -135,9 +132,9 @@ int board_init (void) {
/* set PERCLKs */
MX1_PCDR = 0x00000055; /* set PERCLKS */
-
-/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
- * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
MX1_INTTYPEH = 0;
@@ -154,24 +151,24 @@ int board_late_init(void) {
switch (mc9328sid) {
case 0x0005901d :
- printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
+ printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x04d4c01d :
- printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x00d4c01d :
- printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
default :
- printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
+ printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
-
+
}
-
+
return 0;
-}
-
+}
+
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index fc1d7f6..09fc0f8 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -1,6 +1,6 @@
/*
* board/mx1ads/syncflash.c
- *
+ *
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -61,7 +61,7 @@ u32 SF_SR(void) {
reg_SFCTL = CMD_PROGRAM;
tmp = __REG(CFG_FLASH_BASE);
-
+
reg_SFCTL = CMD_NORMAL;
reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
@@ -97,7 +97,7 @@ void SF_PrechargeAll(void) {
u32 tmp;
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
- tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+ tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
}
@@ -105,7 +105,7 @@ void SF_PrechargeAll(void) {
void SF_Normal(void) {
SF_PrechargeAll();
-
+
reg_SFCTL = CMD_NORMAL;
}
@@ -118,10 +118,10 @@ void SF_Erase(u32 RowAddress) {
reg_SFCTL = CMD_PREC;
tmp = __REG(RowAddress);
-
+
reg_SFCTL = CMD_LCR; /* Set LCR mode */
__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
-
+
reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
@@ -134,7 +134,7 @@ void SF_NvmodeErase(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
-
+
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
@@ -146,7 +146,7 @@ void SF_NvmodeWrite(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
-
+
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
@@ -168,11 +168,11 @@ ulong flash_init(void) {
tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
SF_Normal();
-
+
i = 0;
flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
-
+
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
@@ -181,7 +181,7 @@ ulong flash_init(void) {
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
}
-
+
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1,
@@ -208,8 +208,8 @@ void flash_print_info (flash_info_t *info) {
printf("Unknown Vendor ");
break;
}
-
-
+
+
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
@@ -226,13 +226,13 @@ void flash_print_info (flash_info_t *info) {
printf(" Sector Start Addresses: ");
for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0)
+ if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
-
+
printf ("\n");
}
@@ -248,19 +248,19 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
- if ((s_first < 0) || (s_first > s_last))
+ if ((s_first < 0) || (s_first > s_last))
return ERR_INVAL;
- if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+ if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
+ if (info->protect[sect])
prot++;
}
-
+
if (prot) {
printf("protected!\n");
return ERR_PROTECTED;
@@ -279,7 +279,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
-
+
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
@@ -307,8 +307,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
return rc;
}
-
-
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
@@ -316,7 +314,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
int i;
- for(i = 0; i < cnt; i += 4) {
+ for(i = 0; i < cnt; i += 4) {
SF_PrechargeAll();
@@ -327,6 +325,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
}
SF_Normal();
-
+
return ERR_OK;
}
diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds
index 946994d..53743cd 100644
--- a/board/mx1ads/u-boot.lds
+++ b/board/mx1ads/u-boot.lds
@@ -1,6 +1,6 @@
/*
* board/mx1ads/u-boot.lds
- *
+ *
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
index 4ea8b36..572cc9b 100644
--- a/board/pm520/flash.c
+++ b/board/pm520/flash.c
@@ -83,12 +83,18 @@ unsigned long flash_init (void)
{
int i;
ulong size = 0;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(ulong, ulong);
+ ulong flashbase = CFG_FLASH_BASE;
+
+ flash_preinit();
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
- flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+ flash_get_size ((FPW *) flashbase, &flash_info[i]);
+ flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
@@ -99,14 +105,22 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#ifndef CONFIG_BOOT_ROM
flash_protect ( FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0] );
+#endif
+#endif
+#ifdef CFG_ENV_IS_IN_FLASH
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+#endif
+
+ flash_afterinit(flash_info[0].start[0], flash_info[0].size);
return size;
}
@@ -195,6 +209,8 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
addr[0x5555] = (FPW) 0x00900090;
mb ();
+ udelay(100);
+
value = addr[0];
switch (value) {
@@ -220,18 +236,21 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
+ info->start[0] = CFG_FLASH_BASE;
break; /* => 32 MB */
case (FPW) INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x01000000;
+ info->start[0] = CFG_FLASH_BASE + 0x01000000;
break; /* => 16 MB */
case (FPW) INTEL_ID_28F320J3A:
info->flash_id += FLASH_28F320J3A;
info->sector_count = 32;
- info->size = 0x00800000;
+ info->size = 0x800000;
+ info->start[0] = CFG_FLASH_BASE + 0x01800000;
break; /* => 8 MB */
default:
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
new file mode 100644
index 0000000..f650faa
--- /dev/null
+++ b/board/pm520/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..ffdf039
--- /dev/null
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xC2222600
+#define SDRAM_CONFIG2 0x88B70004
+#define SDRAM_ADDRSEL 0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
index bb0268f..54f59f5 100644
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -2,6 +2,9 @@
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,127 +28,209 @@
#include <mpc5xxx.h>
#include <pci.h>
-#ifndef CFG_RAMBOOT
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
- /* set mode register */
-#if defined(CONFIG_MPC5200)
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
-#elif defined(CONFIG_MGT5100)
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
#endif
+
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
/* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
/* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
/* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
}
#endif
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
ulong dramsize = 0;
+ ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
- /* configure SDRAM start/end */
-#if defined(CONFIG_MPC5200)
+ /* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
/* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CFG_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CFG_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+ ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
+ /* setup and enable SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+ __asm__ volatile ("sync");
/* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
/* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
-#endif
+ *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+ __asm__ volatile ("sync");
+
+ /* find RAM size */
sdram_start(0);
- test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
-#if defined(CONFIG_MPC5200)
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
- (0x13 + __builtin_ffs(dramsize >> 20) - 1);
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#elif defined(CONFIG_MGT5100)
+
+ /* set SDRAM end address according to size */
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-#endif
-#else
-#ifdef CONFIG_MGT5100
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+#else /* CFG_RAMBOOT */
+
+ /* Retrieve amount of SDRAM available */
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-#else
- dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
-#endif
+
#endif /* CFG_RAMBOOT */
- /* return total ram size */
+
return dramsize;
}
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
int checkboard (void)
{
#if defined(CONFIG_MPC5200)
@@ -171,14 +256,32 @@ void flash_preinit(void)
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
-void flash_afterinit(ulong size)
+void flash_afterinit(ulong start, ulong size)
{
- if (size == 0x800000) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
- }
+#if defined(CONFIG_BOOT_ROM)
+ /* adjust mapping */
+ *(vu_long *)MPC5XXX_CS1_START =
+ START_REG(start);
+ *(vu_long *)MPC5XXX_CS1_STOP =
+ STOP_REG(start, size);
+#else
+ /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(start);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(start, size);
+#endif
+}
+
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+int misc_init_r (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ /* adjust flash start */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ return (0);
}
#ifdef CONFIG_PCI
@@ -191,3 +294,26 @@ void pci_init_board(void)
pci_mpc5xxx_init(&hose);
}
#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+ doc_probe (CFG_DOC_BASE);
+}
+#endif
generated by cgit v1.1 at 2024-11-16 20:00:35 +0000