diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx50_arm2/Makefile | 49 | ||||
| -rw-r--r-- | board/freescale/mx50_arm2/config.mk | 7 | ||||
| -rw-r--r-- | board/freescale/mx50_arm2/flash_header.S | 346 | ||||
| -rw-r--r-- | board/freescale/mx50_arm2/lowlevel_init.S | 207 | ||||
| -rw-r--r-- | board/freescale/mx50_arm2/mx50_arm2.c | 680 | ||||
| -rw-r--r-- | board/freescale/mx50_arm2/u-boot.lds | 73 |
6 files changed, 1362 insertions, 0 deletions
diff --git a/board/freescale/mx50_arm2/Makefile b/board/freescale/mx50_arm2/Makefile new file mode 100644 index 0000000..2bbcde3 --- /dev/null +++ b/board/freescale/mx50_arm2/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx50_arm2.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx50_arm2/config.mk b/board/freescale/mx50_arm2/config.mk new file mode 100644 index 0000000..fcb4c00 --- /dev/null +++ b/board/freescale/mx50_arm2/config.mk @@ -0,0 +1,7 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp + +ifndef TEXT_BASE + TEXT_BASE = 0x77800000 +endif diff --git a/board/freescale/mx50_arm2/flash_header.S b/board/freescale/mx50_arm2/flash_header.S new file mode 100644 index 0000000..aa246df --- /dev/null +++ b/board/freescale/mx50_arm2/flash_header.S @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx50.h> + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +#define CPU_2_BE_32(l) \ + ((((l) & 0x000000FF) << 24) | \ + (((l) & 0x0000FF00) << 8) | \ + (((l) & 0x00FF0000) >> 8) | \ + (((l) & 0xFF000000) >> 24)) + +#define MXC_DCD_ITEM(i, addr, val) \ +dcd_node_##i: \ + .word CPU_2_BE_32(addr) ; \ + .word CPU_2_BE_32(val) ; \ + +#define DCDGEN_CHECKDATA(i,addr,mask,count) \ +dcd_chkdata_##i: ; \ + .word CPU_2_BE_32(addr) ;\ + .word CPU_2_BE_32(mask) ;\ + .word CPU_2_BE_32(count) ;\ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .word _start +reserv1: .word 0x0 +dcd_ptr: .word dcd_hdr +boot_data_ptr: .word boot_data +self_ptr: .word ivt_header +app_code_csf: .word 0x0 +reserv2: .word 0x0 + +boot_data: .word TEXT_BASE +image_len: .word _end - TEXT_BASE +plugin: .word 0x0 + +#if defined(CONFIG_LPDDR2) + +/* DCD for LPDDR2 board */ + +/* Tag=0xD2, Len=4 + 76 + 16 + 844 + 26 = 966 (0x03c6), Ver=0x40. */ +dcd_hdr: .word 0x40c603D2 + +/* Tag = 0xCC, Len = 9*8 + 4 = 76(0x4C), Param = 4 */ +write_ccm_dcd_cmd: .word 0x044C00CC + +MXC_DCD_ITEM(01, 0x53fd4068 , 0xffffffff) +MXC_DCD_ITEM(02, 0x53fd406c , 0xffffffff) +MXC_DCD_ITEM(03, 0x53fd4070 , 0xffffffff) +MXC_DCD_ITEM(04, 0x53fd4074 , 0xffffffff) +MXC_DCD_ITEM(05, 0x53fd4078 , 0xffffffff) +MXC_DCD_ITEM(06, 0x53fd407c , 0xffffffff) +MXC_DCD_ITEM(07, 0x53fd4080 , 0xffffffff) +MXC_DCD_ITEM(08, 0x53fd4084 , 0xffffffff) +MXC_DCD_ITEM(09, 0x53FD4098 , 0x80000003) + +/* poll for completion of CCM_CSR2 for update: use dummy write to wait */ +/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4(Mast & Set bit are zero) */ +check_data_dcd_cmd: .word 0x241000CF +/* loop 0x1FFFFFFF times to make sure bit 2(ddr_clk_ref_pll_bsy) is cleared */ +DCDGEN_CHECKDATA(1, CCM_BASE_ADDR + 0x8c, 0x04, 0x1FFFFFFF) + +/* Tag=0xCC, Len=105*8 + 4 = 844(0x034C), Param=4 */ +write_dcd_cmd: .word 0x044C03CC + +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x6ac, 0x04000000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x6a4, 0x00380000) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x668, 0x00380000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x698, 0x00380000) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x6a0, 0x00380000) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x6a8, 0x00380000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x6b4, 0x00380000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x498, 0x00380000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x49c, 0x00380000) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4f0, 0x00380000) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x500, 0x00380000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4c8, 0x00380000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x528, 0x00380000) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4f4, 0x00380000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4fc, 0x00380000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4cc, 0x00380000) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x524, 0x00380000) + +MXC_DCD_ITEM(18, DATABAHN_BASE_ADDR + 0x000, 0x00000500) +MXC_DCD_ITEM(19, DATABAHN_BASE_ADDR + 0x004, 0x00000000) +MXC_DCD_ITEM(20, DATABAHN_BASE_ADDR + 0x008, 0x0000001b) +MXC_DCD_ITEM(21, DATABAHN_BASE_ADDR + 0x00c, 0x0000d056) +MXC_DCD_ITEM(22, DATABAHN_BASE_ADDR + 0x010, 0x0000010b) +MXC_DCD_ITEM(23, DATABAHN_BASE_ADDR + 0x014, 0x00000a6b) +MXC_DCD_ITEM(24, DATABAHN_BASE_ADDR + 0x018, 0x02020d0c) +MXC_DCD_ITEM(25, DATABAHN_BASE_ADDR + 0x01c, 0x0c110302) +MXC_DCD_ITEM(26, DATABAHN_BASE_ADDR + 0x020, 0x05020503) +MXC_DCD_ITEM(27, DATABAHN_BASE_ADDR + 0x024, 0x00000105) +MXC_DCD_ITEM(28, DATABAHN_BASE_ADDR + 0x028, 0x01000403) +MXC_DCD_ITEM(29, DATABAHN_BASE_ADDR + 0x02c, 0x09040501) +MXC_DCD_ITEM(30, DATABAHN_BASE_ADDR + 0x030, 0x02000000) +MXC_DCD_ITEM(31, DATABAHN_BASE_ADDR + 0x034, 0x00000e02) +MXC_DCD_ITEM(32, DATABAHN_BASE_ADDR + 0x038, 0x00000006) +MXC_DCD_ITEM(33, DATABAHN_BASE_ADDR + 0x03c, 0x00002301) +MXC_DCD_ITEM(34, DATABAHN_BASE_ADDR + 0x040, 0x00050408) +MXC_DCD_ITEM(35, DATABAHN_BASE_ADDR + 0x044, 0x00000300) +MXC_DCD_ITEM(36, DATABAHN_BASE_ADDR + 0x048, 0x00260026) +MXC_DCD_ITEM(37, DATABAHN_BASE_ADDR + 0x04c, 0x00010000) + +MXC_DCD_ITEM(38, DATABAHN_BASE_ADDR + 0x05c, 0x02000000) +MXC_DCD_ITEM(39, DATABAHN_BASE_ADDR + 0x060, 0x00000002) +MXC_DCD_ITEM(40, DATABAHN_BASE_ADDR + 0x064, 0x00000000) +MXC_DCD_ITEM(41, DATABAHN_BASE_ADDR + 0x068, 0x00000000) +MXC_DCD_ITEM(42, DATABAHN_BASE_ADDR + 0x06c, 0x00040042) +MXC_DCD_ITEM(43, DATABAHN_BASE_ADDR + 0x070, 0x00000001) +MXC_DCD_ITEM(44, DATABAHN_BASE_ADDR + 0x074, 0x00000000) +MXC_DCD_ITEM(45, DATABAHN_BASE_ADDR + 0x078, 0x00040042) +MXC_DCD_ITEM(46, DATABAHN_BASE_ADDR + 0x07c, 0x00000001) +MXC_DCD_ITEM(47, DATABAHN_BASE_ADDR + 0x080, 0x010b0000) +MXC_DCD_ITEM(48, DATABAHN_BASE_ADDR + 0x084, 0x00000060) +MXC_DCD_ITEM(49, DATABAHN_BASE_ADDR + 0x088, 0x02400018) +MXC_DCD_ITEM(50, DATABAHN_BASE_ADDR + 0x08c, 0x01000e00) +MXC_DCD_ITEM(51, DATABAHN_BASE_ADDR + 0x090, 0x0a010101) +MXC_DCD_ITEM(52, DATABAHN_BASE_ADDR + 0x094, 0x01011f1f) +MXC_DCD_ITEM(53, DATABAHN_BASE_ADDR + 0x098, 0x01010101) +MXC_DCD_ITEM(54, DATABAHN_BASE_ADDR + 0x09c, 0x00030101) +MXC_DCD_ITEM(55, DATABAHN_BASE_ADDR + 0x0a0, 0x00010000) +MXC_DCD_ITEM(56, DATABAHN_BASE_ADDR + 0x0a4, 0x00010000) +MXC_DCD_ITEM(57, DATABAHN_BASE_ADDR + 0x0a8, 0x00000000) +MXC_DCD_ITEM(58, DATABAHN_BASE_ADDR + 0x0ac, 0x0000ffff) +MXC_DCD_ITEM(59, DATABAHN_BASE_ADDR + 0x0c8, 0x02020101) +MXC_DCD_ITEM(60, DATABAHN_BASE_ADDR + 0x0cc, 0x01000000) +MXC_DCD_ITEM(61, DATABAHN_BASE_ADDR + 0x0d0, 0x01000201) +MXC_DCD_ITEM(62, DATABAHN_BASE_ADDR + 0x0d4, 0x00000200) +MXC_DCD_ITEM(63, DATABAHN_BASE_ADDR + 0x0d8, 0x00000102) +MXC_DCD_ITEM(64, DATABAHN_BASE_ADDR + 0x0dc, 0x0000ffff) +MXC_DCD_ITEM(65, DATABAHN_BASE_ADDR + 0x0e0, 0x0000ffff) +MXC_DCD_ITEM(66, DATABAHN_BASE_ADDR + 0x0e4, 0x02020000) +MXC_DCD_ITEM(67, DATABAHN_BASE_ADDR + 0x0e8, 0x02020202) +MXC_DCD_ITEM(68, DATABAHN_BASE_ADDR + 0x0ec, 0x00000202) +MXC_DCD_ITEM(69, DATABAHN_BASE_ADDR + 0x0f0, 0x01010064) +MXC_DCD_ITEM(70, DATABAHN_BASE_ADDR + 0x0f4, 0x01010101) +MXC_DCD_ITEM(71, DATABAHN_BASE_ADDR + 0x0f8, 0x00010101) +MXC_DCD_ITEM(72, DATABAHN_BASE_ADDR + 0x0fc, 0x00000064) +MXC_DCD_ITEM(73, DATABAHN_BASE_ADDR + 0x100, 0x00000000) +MXC_DCD_ITEM(74, DATABAHN_BASE_ADDR + 0x104, 0x02000802) +MXC_DCD_ITEM(75, DATABAHN_BASE_ADDR + 0x108, 0x04080000) +MXC_DCD_ITEM(76, DATABAHN_BASE_ADDR + 0x10c, 0x04080408) +MXC_DCD_ITEM(77, DATABAHN_BASE_ADDR + 0x110, 0x04080408) +MXC_DCD_ITEM(78, DATABAHN_BASE_ADDR + 0x114, 0x03060408) +MXC_DCD_ITEM(79, DATABAHN_BASE_ADDR + 0x118, 0x01010002) +MXC_DCD_ITEM(80, DATABAHN_BASE_ADDR + 0x11c, 0x00000000) + +MXC_DCD_ITEM(81, DATABAHN_BASE_ADDR + 0x200, 0x00000000) +MXC_DCD_ITEM(82, DATABAHN_BASE_ADDR + 0x204, 0x00000000) +MXC_DCD_ITEM(83, DATABAHN_BASE_ADDR + 0x208, 0xf5003a27) +MXC_DCD_ITEM(84, DATABAHN_BASE_ADDR + 0x20c, 0x074002e1) +MXC_DCD_ITEM(85, DATABAHN_BASE_ADDR + 0x210, 0xf5003a27) +MXC_DCD_ITEM(86, DATABAHN_BASE_ADDR + 0x214, 0x074002e1) +MXC_DCD_ITEM(87, DATABAHN_BASE_ADDR + 0x218, 0xf5003a27) +MXC_DCD_ITEM(88, DATABAHN_BASE_ADDR + 0x21c, 0x074002e1) +MXC_DCD_ITEM(89, DATABAHN_BASE_ADDR + 0x220, 0xf5003a27) +MXC_DCD_ITEM(90, DATABAHN_BASE_ADDR + 0x224, 0x074002e1) +MXC_DCD_ITEM(91, DATABAHN_BASE_ADDR + 0x228, 0xf5003a27) +MXC_DCD_ITEM(92, DATABAHN_BASE_ADDR + 0x22c, 0x074002e1) +MXC_DCD_ITEM(93, DATABAHN_BASE_ADDR + 0x230, 0x00000000) +MXC_DCD_ITEM(94, DATABAHN_BASE_ADDR + 0x234, 0x00810006) +MXC_DCD_ITEM(95, DATABAHN_BASE_ADDR + 0x238, 0x20099414) +MXC_DCD_ITEM(96, DATABAHN_BASE_ADDR + 0x23c, 0x000a1401) +MXC_DCD_ITEM(97, DATABAHN_BASE_ADDR + 0x240, 0x20099414) +MXC_DCD_ITEM(98, DATABAHN_BASE_ADDR + 0x244, 0x000a1401) +MXC_DCD_ITEM(99, DATABAHN_BASE_ADDR + 0x248, 0x20099414) +MXC_DCD_ITEM(100, DATABAHN_BASE_ADDR + 0x24c, 0x000a1401) +MXC_DCD_ITEM(101, DATABAHN_BASE_ADDR + 0x250, 0x20099414) +MXC_DCD_ITEM(102, DATABAHN_BASE_ADDR + 0x254, 0x000a1401) +MXC_DCD_ITEM(103, DATABAHN_BASE_ADDR + 0x258, 0x20099414) +MXC_DCD_ITEM(104, DATABAHN_BASE_ADDR + 0x25c, 0x000a1401) +MXC_DCD_ITEM(105, DATABAHN_BASE_ADDR + 0x000, 0x00000501) + + +/* poll for completion of HW_DRAM_CTL42 for DDR inti completion */ +/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4 (Mast & Set bit are zero) */ +check_ddr_init_dcd_cmd: .word 0x341000CF +/* loop 0x1FFFFFFF times to make sure bit 4 (int_status) is set */ +DCDGEN_CHECKDATA(2, DATABAHN_BASE_ADDR + 0xa8, 0x10, 0x1FFFFFFF) + +#else + +/* DCD for mDDR board */ + +/* Tag=0xD2, Len=4 + 76 + 16 + 796 + 26 = 908 (03A4), Ver=0x40. */ +dcd_hdr: .word 0x408C03D2 + +/* Tag = 0xCC, Len = 9*8 + 4 = 76(0x4C), Param = 4 */ +write_ccm_dcd_cmd: .word 0x044C00CC + +MXC_DCD_ITEM(01, 0x53fd4068 , 0xffffffff) +MXC_DCD_ITEM(02, 0x53fd406c , 0xffffffff) +MXC_DCD_ITEM(03, 0x53fd4070 , 0xffffffff) +MXC_DCD_ITEM(04, 0x53fd4074 , 0xffffffff) +MXC_DCD_ITEM(05, 0x53fd4078 , 0xffffffff) +MXC_DCD_ITEM(06, 0x53fd407c , 0xffffffff) +MXC_DCD_ITEM(07, 0x53fd4080 , 0xffffffff) +MXC_DCD_ITEM(08, 0x53fd4084 , 0xffffffff) +MXC_DCD_ITEM(09, 0x53FD4098 , 0x80000004) + +/* poll for completion of CCM_CSR2 for update: use dummy write to wait */ +/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4(Mast & Set bit are zero) */ +check_data_dcd_cmd: .word 0x241000CF +/* loop 0x1FFFFFFF times to make sure bit 2(ddr_clk_ref_pll_bsy) is cleared */ +DCDGEN_CHECKDATA(1, CCM_BASE_ADDR + 0x8c, 0x04, 0x1FFFFFFF) + +write_dcd_cmd: .word 0x041C03CC /* Tag=0xCC, Len=99*8 + 4, Param=4 */ + +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x6ac, 0x02000000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x668, 0x00200000) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x66c, 0x00000000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x670, 0x00000000) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x68c, 0x00000000) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x698, 0x00200000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x6a0, 0x00200000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x6a4, 0x00200000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x6a8, 0x00200000) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x6b4, 0x00200000) + +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x498, 0x00200000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x49c, 0x00200000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4c8, 0x00200000) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4cc, 0x00200000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4f0, 0x00200000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4f4, 0x00200000) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4fc, 0x00200000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x500, 0x00200000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x524, 0x00200000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x528, 0x00200000) + +MXC_DCD_ITEM(21, DATABAHN_BASE_ADDR + 0x000, 0x00000100) +MXC_DCD_ITEM(22, DATABAHN_BASE_ADDR + 0x008, 0x00009c40) +MXC_DCD_ITEM(23, DATABAHN_BASE_ADDR + 0x014, 0x02000000) +MXC_DCD_ITEM(24, DATABAHN_BASE_ADDR + 0x018, 0x01010706) +MXC_DCD_ITEM(25, DATABAHN_BASE_ADDR + 0x01c, 0x080b0201) +MXC_DCD_ITEM(26, DATABAHN_BASE_ADDR + 0x020, 0x02000303) +MXC_DCD_ITEM(27, DATABAHN_BASE_ADDR + 0x024, 0x0136b002) +MXC_DCD_ITEM(28, DATABAHN_BASE_ADDR + 0x028, 0x01000101) +MXC_DCD_ITEM(29, DATABAHN_BASE_ADDR + 0x02c, 0x06030301) +MXC_DCD_ITEM(30, DATABAHN_BASE_ADDR + 0x030, 0x00000000) +MXC_DCD_ITEM(31, DATABAHN_BASE_ADDR + 0x034, 0x00000a02) +MXC_DCD_ITEM(32, DATABAHN_BASE_ADDR + 0x038, 0x00000003) +MXC_DCD_ITEM(33, DATABAHN_BASE_ADDR + 0x03c, 0x00001401) +MXC_DCD_ITEM(34, DATABAHN_BASE_ADDR + 0x040, 0x0005030f) +MXC_DCD_ITEM(35, DATABAHN_BASE_ADDR + 0x044, 0x00000200) +MXC_DCD_ITEM(36, DATABAHN_BASE_ADDR + 0x048, 0x00180018) +MXC_DCD_ITEM(37, DATABAHN_BASE_ADDR + 0x04c, 0x00010000) +MXC_DCD_ITEM(38, DATABAHN_BASE_ADDR + 0x05c, 0x01000000) +MXC_DCD_ITEM(39, DATABAHN_BASE_ADDR + 0x060, 0x00000001) +MXC_DCD_ITEM(40, DATABAHN_BASE_ADDR + 0x064, 0x00000000) +MXC_DCD_ITEM(41, DATABAHN_BASE_ADDR + 0x068, 0x00320000) +MXC_DCD_ITEM(42, DATABAHN_BASE_ADDR + 0x06c, 0x00000000) +MXC_DCD_ITEM(43, DATABAHN_BASE_ADDR + 0x070, 0x00000000) +MXC_DCD_ITEM(44, DATABAHN_BASE_ADDR + 0x074, 0x00320000) +MXC_DCD_ITEM(45, DATABAHN_BASE_ADDR + 0x080, 0x02000000) +MXC_DCD_ITEM(46, DATABAHN_BASE_ADDR + 0x084, 0x00000100) +MXC_DCD_ITEM(47, DATABAHN_BASE_ADDR + 0x088, 0x02400040) +MXC_DCD_ITEM(48, DATABAHN_BASE_ADDR + 0x08c, 0x01000000) +MXC_DCD_ITEM(49, DATABAHN_BASE_ADDR + 0x090, 0x0a000100) +MXC_DCD_ITEM(50, DATABAHN_BASE_ADDR + 0x094, 0x01011f1f) +MXC_DCD_ITEM(51, DATABAHN_BASE_ADDR + 0x098, 0x01010101) +MXC_DCD_ITEM(52, DATABAHN_BASE_ADDR + 0x09c, 0x00030101) +MXC_DCD_ITEM(53, DATABAHN_BASE_ADDR + 0x0a4, 0x00010000) +MXC_DCD_ITEM(54, DATABAHN_BASE_ADDR + 0x0ac, 0x0000ffff) +MXC_DCD_ITEM(55, DATABAHN_BASE_ADDR + 0x0c8, 0x02020101) +MXC_DCD_ITEM(56, DATABAHN_BASE_ADDR + 0x0cc, 0x00000000) +MXC_DCD_ITEM(57, DATABAHN_BASE_ADDR + 0x0d0, 0x01000202) +MXC_DCD_ITEM(58, DATABAHN_BASE_ADDR + 0x0d4, 0x02030302) +MXC_DCD_ITEM(59, DATABAHN_BASE_ADDR + 0x0d8, 0x00000001) +MXC_DCD_ITEM(60, DATABAHN_BASE_ADDR + 0x0dc, 0x0000ffff) /* sync mode */ +MXC_DCD_ITEM(61, DATABAHN_BASE_ADDR + 0x0e0, 0x0000ffff) +MXC_DCD_ITEM(62, DATABAHN_BASE_ADDR + 0x0e4, 0x02020000) +MXC_DCD_ITEM(63, DATABAHN_BASE_ADDR + 0x0e8, 0x02020202) +MXC_DCD_ITEM(64, DATABAHN_BASE_ADDR + 0x0ec, 0x00000202) +MXC_DCD_ITEM(65, DATABAHN_BASE_ADDR + 0x0f0, 0x01010064) +MXC_DCD_ITEM(66, DATABAHN_BASE_ADDR + 0x0f4, 0x01010101) +MXC_DCD_ITEM(67, DATABAHN_BASE_ADDR + 0x0f8, 0x00010101) +MXC_DCD_ITEM(68, DATABAHN_BASE_ADDR + 0x0fc, 0x00000064) +MXC_DCD_ITEM(69, DATABAHN_BASE_ADDR + 0x104, 0x02000602) +MXC_DCD_ITEM(70, DATABAHN_BASE_ADDR + 0x108, 0x06120000) +MXC_DCD_ITEM(71, DATABAHN_BASE_ADDR + 0x10c, 0x06120612) +MXC_DCD_ITEM(72, DATABAHN_BASE_ADDR + 0x110, 0x06120612) +MXC_DCD_ITEM(73, DATABAHN_BASE_ADDR + 0x114, 0x01030612) +MXC_DCD_ITEM(74, DATABAHN_BASE_ADDR + 0x118, 0x01010002) + +MXC_DCD_ITEM(75, DATABAHN_BASE_ADDR + 0x200, 0x00000000) +MXC_DCD_ITEM(76, DATABAHN_BASE_ADDR + 0x204, 0x00000000) +MXC_DCD_ITEM(77, DATABAHN_BASE_ADDR + 0x208, 0xf5002725) +MXC_DCD_ITEM(78, DATABAHN_BASE_ADDR + 0x20c, 0x070002d0) +MXC_DCD_ITEM(79, DATABAHN_BASE_ADDR + 0x210, 0xf5002725) +MXC_DCD_ITEM(80, DATABAHN_BASE_ADDR + 0x214, 0x074002d0) +MXC_DCD_ITEM(81, DATABAHN_BASE_ADDR + 0x218, 0xf5002725) +MXC_DCD_ITEM(82, DATABAHN_BASE_ADDR + 0x21c, 0x074002d0) +MXC_DCD_ITEM(83, DATABAHN_BASE_ADDR + 0x220, 0xf5002725) +MXC_DCD_ITEM(84, DATABAHN_BASE_ADDR + 0x224, 0x074002d0) +MXC_DCD_ITEM(85, DATABAHN_BASE_ADDR + 0x228, 0xf5002725) +MXC_DCD_ITEM(86, DATABAHN_BASE_ADDR + 0x22c, 0x074002d0) +MXC_DCD_ITEM(87, DATABAHN_BASE_ADDR + 0x230, 0x00000000) +MXC_DCD_ITEM(88, DATABAHN_BASE_ADDR + 0x234, 0x00800006) +MXC_DCD_ITEM(89, DATABAHN_BASE_ADDR + 0x238, 0x200e1014) +MXC_DCD_ITEM(90, DATABAHN_BASE_ADDR + 0x23c, 0x000d9f01) +MXC_DCD_ITEM(91, DATABAHN_BASE_ADDR + 0x240, 0x200e1014) +MXC_DCD_ITEM(92, DATABAHN_BASE_ADDR + 0x244, 0x000d9f01) +MXC_DCD_ITEM(93, DATABAHN_BASE_ADDR + 0x248, 0x200e1014) +MXC_DCD_ITEM(94, DATABAHN_BASE_ADDR + 0x24c, 0x000d9f01) +MXC_DCD_ITEM(95, DATABAHN_BASE_ADDR + 0x250, 0x200e1014) +MXC_DCD_ITEM(96, DATABAHN_BASE_ADDR + 0x254, 0x000d9f01) +MXC_DCD_ITEM(97, DATABAHN_BASE_ADDR + 0x258, 0x200e1014) +MXC_DCD_ITEM(98, DATABAHN_BASE_ADDR + 0x25c, 0x000d9f01) +MXC_DCD_ITEM(99, DATABAHN_BASE_ADDR + 0x000, 0x00000101) + + +/* poll for completion of HW_DRAM_CTL42 for DDR inti completion */ +/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4 (Mast & Set bit are zero) */ +check_ddr_init_dcd_cmd: .word 0x341000CF +/* loop 0x1FFFFFFF times to make sure bit 4 (int_status) is set */ +DCDGEN_CHECKDATA(2, DATABAHN_BASE_ADDR + 0xa8, 0x10, 0x1FFFFFFF) + +#endif + +#endif diff --git a/board/freescale/mx50_arm2/lowlevel_init.S b/board/freescale/mx50_arm2/lowlevel_init.S new file mode 100644 index 0000000..4e031c7 --- /dev/null +++ b/board/freescale/mx50_arm2/lowlevel_init.S @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx50.h> + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] +.endm /* init_aips */ + +.macro setup_pll pll, freq + ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + /* Set periph_clk_sel[1:0]=0b10 to PLL3 */ + + ldr r0, CCM_BASE_ADDR_W + ldr r1, [r0, #CLKCTL_CBCDR] + orr r1, r1, #(3 << 25) + eor r1, r1, #(3 << 25) + orr r1, r1, #(2 << 25) + str r1, [r0, #CLKCTL_CBCDR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ + + /* Switch peripheral to PLL2 */ + /* Set periph_clk_sel[1:0]=0b01 to PLL2 */ + + ldr r0, CCM_BASE_ADDR_W + ldr r1, [r0, #CLKCTL_CBCDR] + orr r1, r1, #(3 << 25) + eor r1, r1, #(3 << 25) + orr r1, r1, #(1 << 25) + + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) + str r1, [r0, #CLKCTL_CBCDR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #PLATFORM_ICGC] + + /* ARM2 run at full speed */ + ldr r0, CCM_BASE_ADDR_W + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_clock /* not finished */ + + mov pc, lr + +/* Board level setting value */ +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx50_arm2/mx50_arm2.c b/board/freescale/mx50_arm2/mx50_arm2.c new file mode 100644 index 0000000..d606dfc --- /dev/null +++ b/board/freescale/mx50_arm2/mx50_arm2.c @@ -0,0 +1,680 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx50.h> +#include <asm/arch/mx50_pins.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> + +#ifdef CONFIG_IMX_CSPI +#include <imx_spi.h> +#include <asm/arch/imx_spi_pmic.h> +#endif + +#if CONFIG_I2C_MXC +#include <i2c.h> +#endif + +#ifdef CONFIG_CMD_MMC +#include <mmc.h> +#include <fsl_esdhc.h> +#endif + +#ifdef CONFIG_ARCH_MMU +#include <asm/mmu.h> +#include <asm/arch/mmu.h> +#endif + +#ifdef CONFIG_CMD_CLOCK +#include <asm/clock.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; +u32 mx51_io_base_addr; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + if (bt_mem_type) + boot_dev = SATA_BOOT; + else + boot_dev = PATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + system_rev = 0x50000 | CHIP_REV_1_0; +} + +static inline void setup_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x070, 0x070, 0x010, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SATA */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ + X_ARM_MMU_SECTION(0x200, 0x200, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x700, 0x700, 0x400, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0x700, 0xB00, 0x400, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRam */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + + /* UART1 RXD */ + mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + + /* UART1 TXD */ + mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4); +} + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + switch (module_base) { + case I2C1_BASE_ADDR: + /* i2c1 SDA */ + mxc_request_iomux(MX50_PIN_I2C1_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX50_PIN_I2C1_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_request_iomux(MX50_PIN_I2C2_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C2_SDA, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX50_PIN_I2C2_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C2_SCL, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C3_BASE_ADDR: + /* i2c3 SDA */ + mxc_request_iomux(MX50_PIN_I2C3_SDA, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C3_SDA, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c3 SCL */ + mxc_request_iomux(MX50_PIN_I2C3_SCL, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX50_PIN_I2C3_SCL, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +#endif + +#ifdef CONFIG_IMX_CSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* PMIC */ + dev->base = CSPI3_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_HIGH; + dev->ss = 0; + dev->fifo_sz = 32; + dev->us_delay = 0; + break; + case 1: + /* SPI-NOR */ + dev->base = CSPI3_BASE_ADDR; + dev->freq = 25000000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 32; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID! \n"); + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI3_BASE_ADDR: + mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4); + + mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4); + + if (dev->ss == 0) { + /* de-select SS1 of instance: cspi */ + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, + IOMUX_CONFIG_ALT1); + + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4); + } else if (dev->ss == 1) { + /* de-select SS0 of instance: cspi */ + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1); + + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, + IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4); + mxc_iomux_set_input( + MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1); + } + + mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4); + break; + case CSPI2_BASE_ADDR: + case CSPI1_BASE_ADDR: + /* ecspi1-2 fall through */ + break; + default: + break; + } +} +#endif + +#ifdef CONFIG_MXC_FEC +static void setup_fec(void) +{ + volatile unsigned int reg; + + /*FEC_MDIO*/ + mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC); + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004); + + /* FEC RXD1 */ + mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0); + + /* FEC RXD0 */ + mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0); + + /* FEC TXD1 */ + mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004); + + /* FEC TXD0 */ + mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004); + + /* FEC TX_EN */ + mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0); + + /* FEC RX_ER */ + mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0); + + /* FEC CRS */ + mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0); + + /* phy reset: gpio4-6 */ + mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg &= ~0x40; + writel(reg, GPIO4_BASE_ADDR + 0x0); + + reg = readl(GPIO4_BASE_ADDR + 0x4); + reg |= 0x40; + writel(reg, GPIO4_BASE_ADDR + 0x4); + + udelay(500); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= 0x40; + writel(reg, GPIO4_BASE_ADDR + 0x0); +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[3] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; + + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int mmc_devno = 0; + + switch (soc_sbmr & 0x00300000) { + default: + case 0: + mmc_devno = 0; + break; + case 1: + mmc_devno = 1; + break; + case 2: + mmc_devno = 2; + break; + } + + return mmc_devno; +} +#endif + + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX50_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD1_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD1_D3, 0x1D4); + + break; + case 1: + mxc_request_iomux(MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD2_CMD, 0x1E4); + mxc_iomux_set_pad(MX50_PIN_SD2_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD2_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D3, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D4, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D5, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D6, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD2_D7, 0x1D4); + + break; + case 2: + mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX50_PIN_SD3_CMD, 0x1E4); + mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0xD4); + mxc_iomux_set_pad(MX50_PIN_SD3_D0, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D1, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D2, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D3, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D4, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D5, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D6, 0x1D4); + mxc_iomux_set_pad(MX50_PIN_SD3_D7, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#ifdef CONFIG_IMX_CSPI +static void setup_power(void) +{ + struct spi_slave *slave; + unsigned int val; + unsigned int reg; + + puts("PMIC Mode: SPI\n"); + + /* Enable VGEN1 to enable ethernet */ + slave = spi_pmic_probe(); + + val = pmic_reg(slave, 30, 0, 0); + val |= 0x3; + pmic_reg(slave, 30, val, 1); + + val = pmic_reg(slave, 32, 0, 0); + val |= 0x1; + pmic_reg(slave, 32, val, 1); + + /* Enable VCAM */ + val = pmic_reg(slave, 33, 0, 0); + val |= 0x40; + pmic_reg(slave, 33, val, 1); + + spi_pmic_free(slave); +} + +void setup_voltage_cpu(void) +{ + /* Currently VDDGP 1.05v + * no one tell me we need increase the core + * voltage to let CPU run at 800Mhz, not do it + */ + + /* Raise the core frequency to 800MHz */ + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); + +} +#endif + +int board_init(void) +{ + /* boot device */ + setup_boot_device(); + + /* soc rev */ + setup_soc_rev(); + + /* arch id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2; + + /* boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* iomux for uart */ + setup_uart(); + +#ifdef CONFIG_MXC_FEC + /* iomux for fec */ + setup_fec(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_IMX_CSPI + setup_power(); +#endif + return 0; +} + +int checkboard(void) +{ + printf("Board: MX50 ARM2 board\n"); + + printf("Boot Reason: ["); + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + + return 0; +} diff --git a/board/freescale/mx50_arm2/u-boot.lds b/board/freescale/mx50_arm2/u-boot.lds new file mode 100644 index 0000000..07478dd --- /dev/null +++ b/board/freescale/mx50_arm2/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx50_arm2/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx50_arm2/libmx50_arm2.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |