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-rw-r--r--board/a3m071/a3m071.c3
-rw-r--r--board/logicpd/zoom1/config.mk1
-rw-r--r--board/logicpd/zoom1/zoom1.c38
-rw-r--r--board/logicpd/zoom1/zoom1.h19
-rw-r--r--board/silica/pengwyn/Makefile2
-rw-r--r--board/ti/am335x/Makefile2
-rw-r--r--board/ti/am335x/board.c15
-rw-r--r--board/ti/beagle/beagle.c11
-rw-r--r--board/ti/dra7xx/evm.c19
-rw-r--r--board/ti/k2hk_evm/Makefile9
-rw-r--r--board/ti/k2hk_evm/README122
-rw-r--r--board/ti/k2hk_evm/board.c301
-rw-r--r--board/ti/k2hk_evm/ddr3.c268
-rw-r--r--board/ti/omap5_uevm/evm.c25
-rw-r--r--board/ti/panda/panda.c23
15 files changed, 811 insertions, 47 deletions
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index 7aeefb2..b96ba81 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -412,7 +412,8 @@ int spl_start_uboot(void)
env_init();
getenv_f("boot_os", s, sizeof(s));
- if ((s != NULL) && (strcmp(s, "yes") == 0))
+ if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
+ *s == 't' || *s == 'T'))
return 0;
return 1;
diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk
index f5a19ed..c7ebfd9 100644
--- a/board/logicpd/zoom1/config.mk
+++ b/board/logicpd/zoom1/config.mk
@@ -14,4 +14,3 @@
# (mem base + reserved)
# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 9846f24..461a852 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -18,6 +18,7 @@
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
@@ -26,6 +27,20 @@
DECLARE_GLOBAL_DATA_PTR;
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/* GPMC definitions for Ethenet Controller LAN9211 */
+static const u32 gpmc_lab_enet[] = {
+ ZOOM1_ENET_GPMC_CONF1,
+ ZOOM1_ENET_GPMC_CONF2,
+ ZOOM1_ENET_GPMC_CONF3,
+ ZOOM1_ENET_GPMC_CONF4,
+ ZOOM1_ENET_GPMC_CONF5,
+ ZOOM1_ENET_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -33,6 +48,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* CS1 is Ethernet LAN9211 */
+ enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
+ DEBUG_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
/* boot param addr */
@@ -84,9 +102,25 @@ int board_mmc_init(bd_t *bis)
int board_eth_init(bd_t *bis)
{
int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("zoom1: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
#endif
+
return rc;
}
#endif
diff --git a/board/logicpd/zoom1/zoom1.h b/board/logicpd/zoom1/zoom1.h
index 62ef94f..3a943df 100644
--- a/board/logicpd/zoom1/zoom1.h
+++ b/board/logicpd/zoom1/zoom1.h
@@ -17,6 +17,13 @@ const omap3_sysinfo sysinfo = {
"NAND",
};
+#define ZOOM1_ENET_GPMC_CONF1 0x00611000
+#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
+#define ZOOM1_ENET_GPMC_CONF3 0x00080803
+#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
+#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
+#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
+
/*
* IEN - Input Enable
* IDIS - Input Disable
@@ -94,13 +101,13 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
index c8b4f9a..804ac37 100644
--- a/board/silica/pengwyn/Makefile
+++ b/board/silica/pengwyn/Makefile
@@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index c8b4f9a..804ac37 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 554398f..da780ed 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -30,6 +30,7 @@
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
+#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -81,7 +82,7 @@ static int read_eeprom(struct am335x_baseboard_id *header)
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
@@ -219,7 +220,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
}
#endif
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 9669a32..0674afd 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -316,6 +316,7 @@ int misc_init_r(void)
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+ bool generate_fake_mac = false;
/* Enable i2c2 pullup resisters */
writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
@@ -349,6 +350,7 @@ int misc_init_r(void)
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
case REVISION_XM_C:
printf("Beagle xM Rev C\n");
@@ -359,6 +361,7 @@ int misc_init_r(void)
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
@@ -368,6 +371,7 @@ int misc_init_r(void)
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
}
switch (get_expansion_id()) {
@@ -486,6 +490,13 @@ int misc_init_r(void)
musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
#endif
+ if (generate_fake_mac) {
+ u32 id[4];
+
+ get_dieid(id);
+ usb_fake_mac_from_die_id(id);
+ }
+
return 0;
}
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index c6c4fd1..073d151 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
+#include <environment.h>
#include "mux_data.h"
@@ -124,6 +125,24 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
/* Delay value to add to calibrated value */
diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile
new file mode 100644
index 0000000..3645f2f
--- /dev/null
+++ b/board/ti/k2hk_evm/Makefile
@@ -0,0 +1,9 @@
+#
+# K2HK-EVM: board Makefile
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3.o
diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README
new file mode 100644
index 0000000..bfeb05b
--- /dev/null
+++ b/board/ti/k2hk_evm/README
@@ -0,0 +1,122 @@
+U-Boot port for Texas Instruments XTCIEVMK2X
+============================================
+
+Author: Murali Karicheri <m-karicheri2@ti.com>
+
+This README has information on the u-boot port for XTCIEVMK2X EVM board.
+Documentation for this board can be found at
+ http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
+
+The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K.
+More details on these SoCs are available at company websites
+ K2K: http://www.ti.com/product/tci6638k2k
+ K2H: http://www.ti.com/product/tci6638k2h
+
+Board configuration:
+====================
+
+Some of the peripherals that are configured by u-boot are:-
+
+1. 2GB DDR3 (can support 8GB SO DIMM as well)
+2. 512M NAND (over ti emif16 bus)
+3. 6MB MSM SRAM (part of the SoC)
+4. two 1GBit Ethernet ports (SoC supports upto 4)
+5. two UART ports
+6. three i2c interfaces
+7. three spi interfaces (only 1 interface supported in driver)
+
+There are seperate PLLs to drive clocks to Tetris ARM and Peripherals.
+To bring up SMP Linux on this board, there is a boot monitor
+code that will be installed in MSMC SRAM. There is command available
+to install this image from u-boot.
+
+The port related files can be found at following folders
+ keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
+ K2HK evm board files: board/ti/k2hk_evm/
+
+board configuration file: include/configs/k2hk_evm.h
+
+Supported boot modes:
+ - SPI NOR boot
+
+Supported image formats:-
+ - u-boot.bin: for loading and running u-boot.bin through Texas instruments
+ code composure studio (CCS)
+ - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+
+Build instructions:
+===================
+
+To build u-boot.bin
+ >make k2hk_evm_config
+ >make u-boot-spi.gph
+
+To build u-boot-spi.gph
+ >make k2hk_evm_config
+ >make u-boot-spi.gph
+
+Load and Run U-Boot on K2HK EVM using CCS
+=========================================
+
+Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
+on EVM. See instructions at below link for installing CCS on a Windows PC.
+http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
+Installing_Code_Composer_Studio
+Use u-boot.bin from the build folder for loading annd running u-boot binary
+on EVM. Follow instructions at
+http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
+to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
+and Power ON the EVM. Follow instructions to connect serial port of EVM to
+PC and start TeraTerm or Hyper Terminal.
+
+Start CCS on a Windows machine and Launch Target
+configuration as instructed at http://processors.wiki.ti.com/index.php/
+MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
+The instructions provided in the above link uses a script for
+loading the u-boot binary on the target EVM. Instead do the following:-
+
+1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
+ isconnected: Unknown)" at the debug window (This is created once Target
+ configuration is launched) and select "Connect Target".
+2. Once target connect is successful, choose Tools->Load Memory option from the
+ top level menu. At the Load Memory window, choose the file u-boot.bin
+ through "Browse" button and click "next >" button. In the next window, enter
+ Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
+ button.
+3. Click View -> Registers from the top level menu to view registers window.
+4. From Registers, window expand "Core Registers" to view PC. Edit PC value
+ to be 0xc001000. From the "Run" top level menu, select "Free Run"
+5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
+ below and type any key to stop autoboot as instructed :=
+
+U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
+
+I2C: ready
+Detected SO-DIMM [SQR-SD3T-2G1333SED]
+DRAM: 1.1 GiB
+NAND: 512 MiB
+Net: K2HK_EMAC
+Warning: K2HK_EMAC using MAC address from net device
+, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
+Hit any key to stop autoboot: 0
+
+SPI NOR Flash programming instructions
+======================================
+U-Boot image can be flashed to first 512KB of the NOR flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+ using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv addr_uboot 0x87000000
+ setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
+ run burn_uboot
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "SPI Little Endian Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
new file mode 100644
index 0000000..dc39139
--- /dev/null
+++ b/board/ti/k2hk_evm/board.c
@@ -0,0 +1,301 @@
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/psc_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 device_big_endian;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 125000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 125000000,
+ [ddr3a_clk] = 100000000,
+ [ddr3b_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_srio_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+ [rp1_clk] = 123456789 /* TODO: cannot find
+ what is that */
+};
+
+static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+ { /* CS0 */
+ .mode = ASYNC_EMIF_MODE_NAND,
+ .wr_setup = 0xf,
+ .wr_strobe = 0x3f,
+ .wr_hold = 7,
+ .rd_setup = 0xf,
+ .rd_strobe = 0x3f,
+ .rd_hold = 7,
+ .turn_around = 3,
+ .width = ASYNC_EMIF_8,
+ },
+
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1228,
+ PASS_PLL_983,
+ TETRIS_PLL_1200,
+};
+
+int dram_init(void)
+{
+ init_ddr3();
+
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2HK_EMAC",
+ .rx_flow = 22,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC1",
+ .rx_flow = 23,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC2",
+ .rx_flow = 24,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2HK_EMAC3",
+ .rx_flow = 25,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_eth_env_param(char *env_name)
+{
+ char *env;
+ int res = -1;
+
+ env = getenv(env_name);
+ if (env)
+ res = simple_strtol(env, NULL, 0);
+
+ return res;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int j;
+ int res;
+ char link_type_name[32];
+
+ for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
+ j++) {
+ sprintf(link_type_name, "sgmii%d_link_type", j);
+ res = get_eth_env_param(link_type_name);
+ if (res >= 0)
+ eth_priv_cfg[j].sgmii_link_type = res;
+
+ keystone2_emac_initialize(&eth_priv_cfg[j]);
+ }
+
+ return 0;
+}
+#endif
+
+/* Byte swap the 32-bit data if the device is BE */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+ u32 i;
+
+ if (device_big_endian)
+ for (i = 0; i < length; i++, ptr++)
+ *ptr = __swab32(*ptr);
+
+ return 0;
+}
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#define K2_DDR3_START_ADDR 0x80000000
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 start[2];
+ u64 size[2];
+ char name[32], *env, *endp;
+ int lpae, nodeoffset;
+ u32 ddr3a_size;
+ int nbanks;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ ddr3a_size = 0;
+ if (lpae) {
+ env = getenv("ddr3a_size");
+ if (env)
+ ddr3a_size = simple_strtol(env, NULL, 10);
+ if ((ddr3a_size != 8) && (ddr3a_size != 4))
+ ddr3a_size = 0;
+ }
+
+ nbanks = 1;
+ start[0] = bd->bi_dram[0].start;
+ size[0] = bd->bi_dram[0].size;
+
+ /* adjust memory start address for LPAE */
+ if (lpae) {
+ start[0] -= K2_DDR3_START_ADDR;
+ start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ }
+
+ if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
+ size[1] = ((u64)ddr3a_size - 2) << 30;
+ start[1] = 0x880000000;
+ nbanks++;
+ }
+
+ /* reserve memory at start of bank */
+ sprintf(name, "mem_reserve_head");
+ env = getenv(name);
+ if (env) {
+ start[0] += ustrtoul(env, &endp, 0);
+ size[0] -= ustrtoul(env, &endp, 0);
+ }
+
+ sprintf(name, "mem_reserve");
+ env = getenv(name);
+ if (env)
+ size[0] -= ustrtoul(env, &endp, 0);
+
+ fdt_fixup_memory_banks(blob, start, size, nbanks);
+
+ /* Fix up the initrd */
+ if (lpae) {
+ u64 initrd_start, initrd_end;
+ u32 *prop1, *prop2;
+ int err;
+ nodeoffset = fdt_path_offset(blob, "/chosen");
+ if (nodeoffset >= 0) {
+ prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-start", NULL);
+ prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-end", NULL);
+ if (prop1 && prop2) {
+ initrd_start = __be32_to_cpu(*prop1);
+ initrd_start -= K2_DDR3_START_ADDR;
+ initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start = __cpu_to_be64(initrd_start);
+ initrd_end = __be32_to_cpu(*prop2);
+ initrd_end -= K2_DDR3_START_ADDR;
+ initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end = __cpu_to_be64(initrd_end);
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-start");
+ if (err < 0)
+ puts("error deleting initrd-start\n");
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-end");
+ if (err < 0)
+ puts("error deleting initrd-end\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-start",
+ &initrd_start,
+ sizeof(initrd_start));
+ if (err < 0)
+ puts("error adding initrd-start\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-end",
+ &initrd_end,
+ sizeof(initrd_end));
+ if (err < 0)
+ puts("error adding linux,initrd-end\n");
+ }
+ }
+ }
+}
+
+void ft_board_setup_ex(void *blob, bd_t *bd)
+{
+ int lpae;
+ char *env;
+ u64 *reserve_start, size;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ if (lpae) {
+ /*
+ * the initrd and other reserved memory areas are
+ * embedded in in the DTB itslef. fix up these addresses
+ * to 36 bit format
+ */
+ reserve_start = (u64 *)((char *)blob +
+ fdt_off_mem_rsvmap(blob));
+ while (1) {
+ *reserve_start = __cpu_to_be64(*reserve_start);
+ size = __cpu_to_be64(*(reserve_start + 1));
+ if (size) {
+ *reserve_start -= K2_DDR3_START_ADDR;
+ *reserve_start +=
+ CONFIG_SYS_LPAE_SDRAM_BASE;
+ *reserve_start =
+ __cpu_to_be64(*reserve_start);
+ } else {
+ break;
+ }
+ reserve_start += 2;
+ }
+ }
+}
+#endif
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
new file mode 100644
index 0000000..6092eb8
--- /dev/null
+++ b/board/ti/k2hk_evm/ddr3.c
@@ -0,0 +1,268 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1600_64A = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1600_64 = {
+ .sdcfg = 0x6200CE6aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1600_32 = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1600_32 = {
+ .sdcfg = 0x6200DE6aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1333_64A = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
+ NOSRA_MASK | UDIMM_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1333_64 = {
+ .sdcfg = 0x62008C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001457ul,
+};
+
+static struct ddr3_phy_config ddr3phy_1333_32 = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
+ NOSRA_MASK | UDIMM_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+static struct ddr3_emif_config ddr3_1333_32 = {
+ .sdcfg = 0x62009C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0xf0073200ul,
+ .sdrfc = 0x00001457ul,
+};
+
+/************************* *****************************/
+static struct ddr3_phy_config ddr3phy_1333_64 = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
+ .dcr_val = ((1 << 10) | (1 << 27)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x12857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+/******************************************************/
+int get_dimm_params(char *dimm_name)
+{
+ u8 spd_params[256];
+ int ret;
+ int old_bus;
+
+ i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+ i2c_set_bus_num(old_bus);
+
+ dimm_name[0] = '\0';
+
+ if (ret) {
+ puts("Cannot read DIMM params\n");
+ return 1;
+ }
+
+ /*
+ * We need to convert spd data to dimm parameters
+ * and to DDR3 EMIF and PHY regirsters values.
+ * For now we just return DIMM type string value.
+ * Caller may use this value to choose appropriate
+ * a pre-set DDR3 configuration
+ */
+
+ strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+ dimm_name[18] = '\0';
+
+ return 0;
+}
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
+
+void init_ddr3(void)
+{
+ char dimm_name[32];
+
+ get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ init_pll(&ddr3a_400);
+ if (cpu_revision() > 0) {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
+ printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ } else {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
+ printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ }
+ } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+ init_pll(&ddr3a_333);
+ if (cpu_revision() > 0) {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
+ } else {
+ init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
+ init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
+ }
+ } else {
+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+ while (1)
+ ;
+ }
+
+ init_pll(&ddr3b_333);
+ init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
+ init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
+}
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 3eaa5ac..4666b38 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -119,28 +119,19 @@ static void enable_host_clocks(void)
int misc_init_r(void)
{
int reg;
- uint8_t device_mac[6];
+ u32 id[4];
#ifdef CONFIG_PALMAS_POWER
palmas_init_settings();
#endif
- if (!getenv("usbethaddr")) {
- reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(reg + 0x10) & 0xff;
- device_mac[2] = readl(reg + 0xC) & 0xff;
- device_mac[3] = readl(reg + 0x8) & 0xff;
- device_mac[4] = readl(reg) & 0xff;
- device_mac[5] = (readl(reg) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ id[0] = readl(reg);
+ id[1] = readl(reg + 0x8);
+ id[2] = readl(reg + 0xC);
+ id[3] = readl(reg + 0x10);
+ usb_fake_mac_from_die_id(id);
return 0;
}
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 5ab6db9..16368cb 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -193,7 +193,7 @@ int misc_init_r(void)
{
int phy_type;
u32 auxclk, altclksrc;
- uint8_t device_mac[6];
+ u32 id[4];
/* EHCI is not supported on ES1.0 */
if (omap_revision() == OMAP4430_ES1_0)
@@ -247,20 +247,11 @@ int misc_init_r(void)
writel(altclksrc, &scrm->altclksrc);
- if (!getenv("usbethaddr")) {
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(STD_FUSE_DIE_ID_3) & 0xff;
- device_mac[2] = readl(STD_FUSE_DIE_ID_2) & 0xff;
- device_mac[3] = readl(STD_FUSE_DIE_ID_1) & 0xff;
- device_mac[4] = readl(STD_FUSE_DIE_ID_0) & 0xff;
- device_mac[5] = (readl(STD_FUSE_DIE_ID_0) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
+ id[0] = readl(STD_FUSE_DIE_ID_0);
+ id[1] = readl(STD_FUSE_DIE_ID_1);
+ id[2] = readl(STD_FUSE_DIE_ID_2);
+ id[3] = readl(STD_FUSE_DIE_ID_3);
+ usb_fake_mac_from_die_id(id);
return 0;
}
@@ -308,7 +299,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
- sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
+ setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
generated by cgit v1.1 at 2024-11-15 13:31:09 +0000