summaryrefslogtreecommitdiff
path: root/board
diff options
context:
space:
mode:
Diffstat (limited to 'board')
-rw-r--r--board/compal/paz00/paz00.c5
-rw-r--r--board/compulab/dts/tegra20-trimslice.dts3
-rw-r--r--board/compulab/trimslice/trimslice.c8
-rw-r--r--board/nvidia/common/board.c24
-rw-r--r--board/nvidia/dts/tegra20-seaboard.dts33
-rw-r--r--board/nvidia/harmony/harmony.c5
-rw-r--r--board/nvidia/seaboard/seaboard.c5
-rw-r--r--board/samsung/smdk5250/Makefile2
-rw-r--r--board/samsung/smdk5250/smdk5250.c8
-rw-r--r--board/samsung/smdk5250/spl_boot.c (renamed from board/samsung/smdk5250/mmc_boot.c)31
-rw-r--r--board/samsung/trats/trats.c80
-rw-r--r--board/samsung/universal_c210/Makefile1
-rw-r--r--board/samsung/universal_c210/lowlevel_init.S395
-rw-r--r--board/samsung/universal_c210/universal.c335
14 files changed, 392 insertions, 543 deletions
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 0725989..6492d41 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -61,9 +61,8 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
- /* init dev 0, eMMC chip, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, -1, -1);
+ /* init dev 0, eMMC chip, with 8-bit bus */
+ tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
index db79e77..4450674 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -8,6 +8,7 @@
aliases {
usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5000000";
};
memory {
@@ -48,7 +49,7 @@
};
usb@c5000000 {
- status = "disabled";
+ nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
};
usb@c5004000 {
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 9ef66fd..8f4dd09 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -34,6 +34,14 @@
#include <mmc.h>
#endif
+void pin_mux_usb(void)
+{
+ /*
+ * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+ * in the current device tree.
+ */
+ pinmux_tristate_disable(PINGRP_UAC);
+}
void pin_mux_spi(void)
{
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 2c7cd0d..76ec687 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -26,10 +26,12 @@
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
#include <asm/arch/emc.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
#include <asm/arch-tegra/board.h>
@@ -119,6 +121,13 @@ int board_init(void)
pin_mux_spi();
spi_init();
#endif
+#ifdef CONFIG_PWM_TEGRA
+ if (pwm_init(gd->fdt_blob))
+ debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -144,6 +153,9 @@ int board_init(void)
pin_mux_usb();
board_usb_init(gd->fdt_blob);
#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
#ifdef CONFIG_TEGRA_NAND
pin_mux_nand();
@@ -174,7 +186,19 @@ int board_early_init_f(void)
/* Initialize periph GPIOs */
gpio_early_init();
gpio_early_init_uart();
+#ifdef CONFIG_LCD
+ tegra_lcd_early_init(gd->fdt_blob);
+#endif
return 0;
}
#endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+ /* Make sure we finish initing the LCD */
+ tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+ return 0;
+}
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 25a63a0..dd98ca4 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -163,4 +163,37 @@
compatible = "hynix,hy27uf4g2b", "nand-flash";
};
};
+
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+ };
+
+ lcd_panel: panel {
+ /* Seaboard has 1366x768 */
+ clock = <70600000>;
+ xres = <1366>;
+ yres = <768>;
+ left-margin = <58>;
+ right-margin = <58>;
+ hsync-len = <58>;
+ lower-margin = <4>;
+ upper-margin = <4>;
+ vsync-len = <4>;
+ hsync-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 2 0>;
+ nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,panel-timings = <400 4 203 17 15>;
+ };
+
};
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index c7590ac..93430ed 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -64,9 +64,8 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
debug("board_mmc_init: init SD slot J26\n");
- /* init dev 0, SD slot J26, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ /* init dev 0, SD slot J26, with 8-bit bus */
+ tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index c412c07..3e33da0 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -71,9 +71,8 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
- /* init dev 0, eMMC chip, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, -1, -1);
+ /* init dev 0, eMMC chip, with 8-bit bus */
+ tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 1474fa8..47c6a5a 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -36,7 +36,7 @@ COBJS += smdk5250.o
endif
ifdef CONFIG_SPL_BUILD
-COBJS += mmc_boot.o
+COBJS += spl_boot.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index a5816e4..4c50342 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -24,11 +24,13 @@
#include <asm/io.h>
#include <i2c.h>
#include <netdev.h>
+#include <spi.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
+#include <pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -63,6 +65,12 @@ static int smc9115_pre_init(void)
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined(CONFIG_PMIC)
+ pmic_init();
+#endif
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
return 0;
}
diff --git a/board/samsung/smdk5250/mmc_boot.c b/board/samsung/smdk5250/spl_boot.c
index 449a919..d8f3c1e 100644
--- a/board/samsung/smdk5250/mmc_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -23,6 +23,16 @@
#include<common.h>
#include<config.h>
+enum boot_mode {
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+ typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -30,9 +40,26 @@
*/
void copy_uboot_to_ram(void)
{
- u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+ spi_copy_func_t spi_copy;
+ enum boot_mode bootmode;
+ u32 (*copy_bl2)(u32, u32, u32);
+
+ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
- copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+ switch (bootmode) {
+ case BOOT_MODE_SERIAL:
+ spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+ spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
+ CONFIG_SYS_TEXT_BASE);
+ break;
+ case BOOT_MODE_MMC:
+ copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+ copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
+ CONFIG_SYS_TEXT_BASE);
+ break;
+ default:
+ break;
+ }
}
void board_init_f(unsigned long bootflag)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index e11a892..d5c681c 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -29,6 +29,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
@@ -93,7 +94,9 @@ void i2c_init_board(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
@@ -104,6 +107,10 @@ void dram_init_banksize(void)
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
}
static unsigned int get_hw_revision(void)
@@ -151,54 +158,22 @@ int board_mmc_init(bd_t *bis)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int i, err;
+ int err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
/*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
- }
-
- /*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
- err = s5p_mmc_init(0, 8);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
@@ -209,24 +184,11 @@ int board_mmc_init(bd_t *bis)
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
@@ -359,6 +321,10 @@ static void board_power_init(void)
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+ /* It is necessary to power down core 1 */
+ /* to successfully boot CPU1 in kernel */
+ writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
static void board_uart_init(void)
diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile
index bfec08f..587cc1b 100644
--- a/board/samsung/universal_c210/Makefile
+++ b/board/samsung/universal_c210/Makefile
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := universal.o onenand.o
-SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
deleted file mode 100644
index dc7f69e..0000000
--- a/board/samsung/universal_c210/lowlevel_init.S
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Lowlevel setup for universal board based on EXYNOS4210
- *
- * Copyright (C) 2010 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
- .globl lowlevel_init
-lowlevel_init:
- mov r11, lr
-
- /* r5 has always zero */
- mov r5, #0
-
- ldr r7, =EXYNOS4_GPIO_PART1_BASE
- ldr r6, =EXYNOS4_GPIO_PART2_BASE
-
- /* System Timer */
- ldr r0, =EXYNOS4_SYSTIMER_BASE
- ldr r1, =0x5000
- str r1, [r0, #0x0]
- ldr r1, =0xffffffff
- str r1, [r0, #0x8]
- ldr r1, =0x49
- str r1, [r0, #0x4]
-
- /* PMIC manual reset */
- /* nPOWER: XEINT_23: GPX2[7] */
- add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
- ldr r1, [r0, #0x0]
- bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
- orr r1, r1, #(0x1 << 28) @ Output
- str r1, [r0, #0x0]
-
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
- str r1, [r0, #0x4]
-
- /* init system clock */
- bl system_clock_init
-
- /* Disable Watchdog */
- ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
- str r5, [r0]
-
- /* UART */
- bl uart_asm_init
-
- /* PMU init */
- bl system_power_init
-
- bl tzpc_init
-
- mov lr, r11
- mov pc, lr
- nop
- nop
- nop
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
- /*
- * setup UART0-UART4 GPIOs (part1)
- * GPA1CON[3] = I2C_3_SCL (3)
- * GPA1CON[2] = I2C_3_SDA (3)
- */
- mov r0, r7
- ldr r1, =0x22222222
- str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
- ldr r1, =0x00223322
- str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
-
- /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
- add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
- ldr r1, [r0, #0x0]
- bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
- orr r1, r1, #(0x1 << 28)
- str r1, [r0, #0x0]
-
- ldr r1, [r0, #0x8]
- bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
- orr r1, r1, #(0x3 << 14) @ Pull-up enabled
- str r1, [r0, #0x8]
-
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
- str r1, [r0, #0x4]
-
- mov pc, lr
- nop
- nop
- nop
-
-system_clock_init:
- ldr r0, =EXYNOS4_CLOCK_BASE
-
- /* APLL(1), MPLL(1), CORE(0), HPM(0) */
- ldr r1, =0x0101
- ldr r2, =0x14200 @ CLK_SRC_CPU
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-1: subs r1, r1, #1
- bne 1b
-
- /*
- * CLK_SRC_TOP0
- * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
- * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
- * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
- */
- ldr r1, =0x10000110
- ldr r2, =0x0C210 @ CLK_SRC_TOP
- str r1, [r0, r2]
-
- /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
- ldr r1, =0x0066666
- ldr r2, =0x0C240 @ CLK_SRC_FSYS
- str r1, [r0, r2]
- /* UART[0:5], PWM: SCLKMPLL(6) */
- ldr r1, =0x6666666
- ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
- ldr r1, =0x0133730
- ldr r2, =0x14500 @ CLK_DIV_CPU0
- str r1, [r0, r2]
- /* CPU1: COPY, HPM */
- ldr r1, =0x03
- ldr r2, =0x14504 @ CLK_DIV_CPU1
- str r1, [r0, r2]
- /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
- ldr r1, =0x13111113
- ldr r2, =0x10500 @ CLK_DIV_DMC0
- str r1, [r0, r2]
- /* DMC1: PWI, DVSEM, DPM */
- ldr r1, =0x01010100
- ldr r2, =0x10504 @ CLK_DIV_DMC1
- str r1, [r0, r2]
- /* LEFTBUS: GDL, GPL */
- ldr r1, =0x13
- ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
- str r1, [r0, r2]
- /* RIGHHTBUS: GDR, GPR */
- ldr r1, =0x13
- ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
- str r1, [r0, r2]
- /*
- * CLK_DIV_TOP
- * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
- * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
- */
- ldr r1, =0x00005473
- ldr r2, =0x0C510 @ CLK_DIV_TOP
- str r1, [r0, r2]
- /* MMC[0:1] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C544 @ CLK_DIV_FSYS1
- str r1, [r0, r2]
- /* MMC[2:3] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C548 @ CLK_DIV_FSYS2
- str r1, [r0, r2]
- /* MMC4 */
- ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C54C @ CLK_DIV_FSYS3
- str r1, [r0, r2]
- /* UART[0:5] */
- ldr r1, =0x774777
- ldr r2, =0x0C550 @ CLK_DIV_PERIL0
- str r1, [r0, r2]
- /* SLIMBUS: ???, PWM */
- ldr r1, =0x8
- ldr r2, =0x0C55C @ CLK_DIV_PERIL3
- str r1, [r0, r2]
-
- /* PLL Setting */
- ldr r1, =0x1C20
- ldr r2, =0x14000 @ APLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x14008 @ MPLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x0C010 @ EPLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x0C020 @ VPLL_LOCK
- str r1, [r0, r2]
-
- /* APLL */
- ldr r1, =0x8000001c
- ldr r2, =0x14104 @ APLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80c80601 @ 800MHz
- ldr r2, =0x14100 @ APLL_CON0
- str r1, [r0, r2]
- /* MPLL */
- ldr r1, =0x8000001C
- ldr r2, =0x1410C @ MPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80c80601 @ 800MHz
- ldr r2, =0x14108 @ MPLL_CON0
- str r1, [r0, r2]
- /* EPLL */
- ldr r1, =0x0
- ldr r2, =0x0C114 @ EPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80300302 @ 96MHz
- ldr r2, =0x0C110 @ EPLL_CON0
- str r1, [r0, r2]
- /* VPLL */
- ldr r1, =0x11000400
- ldr r2, =0x0C124 @ VPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80350302 @ 108MHz
- ldr r2, =0x0C120 @ VPLL_CON0
- str r1, [r0, r2]
-
- /*
- * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
- * Turn off all
- */
- ldr r1, =0xFFF80000
- ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFC0
- ldr r2, =0x0C924 @ CLK_GATE_IP_VP
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFE0
- ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFFC
- ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFC00
- ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
- str r1, [r0, r2]
-
- /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
- ldr r1, =0xFFFFFFF1
- ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFC0
- ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
- str r1, [r0, r2]
-
- /*
- * SMMUPCIE[18], NFCON[16] : 1111 1010
- * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
- * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
- */
- ldr r1, =0xFFFAB8A3
- ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFFC
- ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
- str r1, [r0, r2]
-
- /*
- * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
- * I2C2[8] : 1111 1110
- */
- ldr r1, =0xF1FFFEFF
- ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
- str r1, [r0, r2]
-
- /*
- * KEYIF[16] : 1111 1110
- */
- ldr r1, =0xFFFEFFFF
- ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
- str r1, [r0, r2]
-
- /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
- ldr r1, =0xFFFFFFD1
- ldr r2, =0x0C970 @ CLK_GATE_BLOCK
- str r1, [r0, r2]
- mov pc, lr
- nop
- nop
- nop
-
-system_power_init:
- ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
-
- ldr r2, =0x330C @ PS_HOLD_CONTROL
- ldr r1, [r0, r2]
- orr r1, r1, #(0x3 << 8) @ Data High, Output En
- str r1, [r0, r2]
-
- /* Power Down */
- add r2, r0, #0x3000
- str r5, [r2, #0xC20] @ TV_CONFIGURATION
- str r5, [r2, #0xC40] @ MFC_CONFIGURATION
- str r5, [r2, #0xC60] @ G3D_CONFIGURATION
- str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
- str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
-
- mov pc, lr
- nop
- nop
- nop
-
-tzpc_init:
- ldr r0, =0x10110000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10120000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10130000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10140000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10150000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- mov pc, lr
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 90fff5c..afe3bb0 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -23,14 +23,21 @@
*/
#include <common.h>
+#include <spi.h>
+#include <lcd.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <max8998_pmic.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,24 +57,6 @@ static int get_hwrev(void)
static void check_hw_revision(void);
-int board_init(void)
-{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
- gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-#if defined(CONFIG_PMIC)
- pmic_init();
-#endif
-
- check_hw_revision();
- printf("HW Revision:\t0x%x\n", board_rev);
-
- return 0;
-}
-
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
@@ -177,7 +166,7 @@ int checkboard(void)
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i, err;
+ int err;
switch (get_hwrev()) {
case 0:
@@ -200,75 +189,30 @@ int board_mmc_init(bd_t *bis)
}
/*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
*/
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
- }
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
/*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = s5p_mmc_init(0, 8);
-
- /*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
@@ -320,3 +264,240 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_flags = PHY0_SLEEP,
};
#endif
+
+int board_early_init_f(void)
+{
+ wdt_stop();
+
+ return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+ CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+ gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+ SPI_SCL(1);
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+ return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+ unsigned char val;
+ int ret = 0;
+
+ struct pmic *p = get_pmic();
+
+ if (pmic_probe(p))
+ return;
+
+ /* LDO7 1.8V */
+ val = 0x02; /* (1800 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
+
+ /* LDO17 3.0V */
+ val = 0xe; /* (3000 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
+
+ /* Disable unneeded regulators */
+ /*
+ * ONOFF1
+ * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+ * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+ */
+ val = 0xB9;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
+
+ /* ONOFF2
+ * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+ * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+ */
+ val = 0x50;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
+
+ /* ONOFF3
+ * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+ * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+ */
+ val = 0x00;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
+
+ if (ret)
+ puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+ unsigned int i, f3_end = 4;
+
+ for (i = 0; i < 8; i++) {
+ /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ }
+
+ for (i = 0; i < f3_end; i++) {
+ /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+ }
+
+ /* gpio pad configuration for LCD reset. */
+ s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+ spi_init();
+}
+
+static void reset_lcd(void)
+{
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 0);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+ struct pmic *p = get_pmic();
+
+ if (pmic_probe(p))
+ return;
+
+ pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+ pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 480,
+ .vl_row = 800,
+ .vl_width = 480,
+ .vl_height = 800,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+
+ .vl_bpix = 5, /* Bits per pixel */
+
+ /* LD9040 LCD Panel */
+ .vl_hspw = 2,
+ .vl_hbpd = 16,
+ .vl_hfpd = 16,
+
+ .vl_vspw = 2,
+ .vl_vbpd = 8,
+ .vl_vfpd = 8,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 0,
+ .cfg_gpio = lcd_cfg_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = lcd_power_on,
+ .reset_lcd = reset_lcd,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 10000,
+ .reset_delay = 10000,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .mipi_enabled = 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->logo_on = 1;
+ vid->resolution = HD_RESOLUTION;
+ vid->rgb_mode = MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ vid->cfg_ldo = ld9040_cfg_ldo;
+ vid->enable_ldo = ld9040_enable_ldo;
+
+ setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#if defined(CONFIG_PMIC)
+ pmic_init();
+ init_pmic_lcd();
+#endif
+#ifdef CONFIG_SOFT_SPI
+ soft_spi_init();
+#endif
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
generated by cgit v1.1 at 2024-11-11 08:24:51 +0000