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-rw-r--r--board/atmel/atngw100/atngw100.c19
-rw-r--r--board/atmel/atstk1000/atstk1000.c19
-rw-r--r--board/earthlcd/favr-32-ezkit/favr-32-ezkit.c19
-rw-r--r--board/esd/meesc/meesc.c116
-rw-r--r--board/eukrea/cpuat91/cpuat91.c53
-rw-r--r--board/mimc/mimc200/mimc200.c24
-rw-r--r--board/miromico/hammerhead/hammerhead.c19
-rw-r--r--board/samsung/goni/goni.c8
-rw-r--r--board/samsung/goni/lowlevel_init.S6
-rw-r--r--board/samsung/smdkc100/lowlevel_init.S2
-rw-r--r--board/samsung/smdkc100/onenand.c3
-rw-r--r--board/samsung/smdkc100/smdkc100.c4
-rw-r--r--board/syteco/jadecpu/Makefile55
-rw-r--r--board/syteco/jadecpu/config.mk1
-rw-r--r--board/syteco/jadecpu/jadecpu.c170
-rw-r--r--board/syteco/jadecpu/lowlevel_init.S265
16 files changed, 672 insertions, 111 deletions
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index 004d8da..49bc03e 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -26,11 +26,26 @@
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_16BIT,
.row_bits = 13,
@@ -75,13 +90,11 @@ phys_size_t initdram(int board_type)
unsigned long actual_size;
void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+ sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
index c36cb57..8b1e1b5 100644
--- a/board/atmel/atstk1000/atstk1000.c
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -25,11 +25,26 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
static const struct sdram_config sdram_config = {
#if defined(CONFIG_ATSTK1006)
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
@@ -97,13 +112,11 @@ phys_size_t initdram(int board_type)
unsigned long actual_size;
void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+ sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
index 8af680f..b0eca93 100644
--- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
+++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
@@ -24,10 +24,25 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
static const struct sdram_config sdram_config = {
/* MT48LC4M32B2P-6 (16 MB) */
.data_bits = SDRAM_DATA_32BIT,
@@ -68,13 +83,11 @@ phys_size_t initdram(int board_type)
unsigned long actual_size;
void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+ sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 694bd74..41fa3e1 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -3,7 +3,7 @@
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
- * (C) Copyright 2009
+ * (C) Copyright 2009-2010
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
@@ -28,13 +28,13 @@
#include <common.h>
#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <netdev.h>
@@ -52,10 +52,10 @@ int get_hw_rev(void)
if (hw_rev >= 0)
return hw_rev;
- hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
- hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
- hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
- hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+ hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
if (hw_rev == 15)
hw_rev = 0;
@@ -67,44 +67,44 @@ int get_hw_rev(void)
static void meesc_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA,
- csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
-#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
-#endif
- AT91_SMC_TDF_(2));
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
#ifdef CONFIG_MACB
static void meesc_macb_hw_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
at91_macb_hw_init();
}
#endif
@@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void)
*/
static void meesc_ethercat_hw_init(void)
{
+ at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE;
+
/* Configure SMC EBI1_CS0 for EtherCAT */
- at91_sys_write(AT91_SMC1_SETUP(0),
- AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC1_PULSE(0),
- AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
- AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
- at91_sys_write(AT91_SMC1_CYCLE(0),
- AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
+ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc1->cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+ AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+ &smc1->cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+ &smc1->cs[0].cycle);
/*
* Configure behavior at external wait signal, byte-select mode, 16 bit
* data bus width, none data float wait states and TDF optimization
*/
- at91_sys_write(AT91_SMC1_MODE(0),
- AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
- AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
- AT91_SMC_TDFMODE);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+ AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+ AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
/* Configure RDY/BSY */
- at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
+ at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
}
int dram_init(void)
@@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+ rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
#endif
return rc;
}
@@ -175,7 +176,7 @@ int checkboard(void)
gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
puts("Board: EtherCAN/2 Gateway");
/* switch on LED1D */
- at91_set_gpio_output(AT91_PIN_PB12, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
break;
default:
/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
@@ -222,8 +223,9 @@ u32 get_board_rev(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- char *str;
- char buf[32];
+ char *str;
+ char buf[32];
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/*
* Normally the processor clock has a divisor of 2.
@@ -231,10 +233,9 @@ int misc_init_r(void)
* Check the user has set environment mdiv to 4 to change the divisor.
*/
if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
- at91_sys_write(AT91_PMC_MCKR,
- (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
- AT91SAM9_PMC_MDIV_4);
- at91_clock_init(0);
+ writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+ AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+ at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
serial_setbrg();
/* Notify the user that the clock is not default */
printf("Setting master clock to %s MHz\n",
@@ -247,10 +248,14 @@ int misc_init_r(void)
int board_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Peripheral Clock Enable Register */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
- 1 << AT91SAM9263_ID_PIOB |
- 1 << AT91SAM9263_ID_PIOCDE);
+ writel(1 << AT91SAM9263_ID_PIOA |
+ 1 << AT91SAM9263_ID_PIOB |
+ 1 << AT91SAM9263_ID_PIOCDE |
+ 1 << AT91SAM9263_ID_UHP,
+ &pmc->pcer);
/* initialize ET1100 Controller */
meesc_ethercat_hw_init();
@@ -271,5 +276,8 @@ int board_init(void)
#ifdef CONFIG_AT91_CAN
at91_can_hw_init();
#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
return 0;
}
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
index 0017962..cd4d42c 100644
--- a/board/eukrea/cpuat91/cpuat91.c
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006 Eukrea Electromatique <www.eukrea.com>
+ * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
* Eric Benard <eric@eukrea.com>
* based on at91rm9200dk.c which is :
* (C) Copyright 2002
@@ -27,13 +27,11 @@
#include <common.h>
#include <netdev.h>
-#include <asm/arch/AT91RM9200.h>
-#include <asm/io.h>
-#if defined(CONFIG_DRIVER_ETHER)
-#include <at91rm9200_net.h>
-#include <ks8721.h>
-#endif
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -61,31 +59,7 @@ int dram_init(void)
return 0;
}
-#if defined(CONFIG_DRIVER_ETHER)
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- * at91rm9200_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = ks8721_initphy;
- p_phyops->IsPhyConnected = ks8721_isphyconnected;
- p_phyops->GetLinkSpeed = ks8721_getlinkspeed;
- p_phyops->AutoNegotiate = ks8721_autonegotiate;
-}
-
-#endif /* CONFIG_CMD_NET */
-#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
-
int board_eth_init(bd_t *bis)
{
int rc = 0;
@@ -93,3 +67,20 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
+
+#ifdef CONFIG_SOFT_I2C
+void i2c_init_board(void)
+{
+ u32 pin;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+ writel(1 << AT91_ID_PIOA, &pmc->pcer);
+ pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+}
+#endif
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
index cc0f137..470adba 100644
--- a/board/mimc/mimc200/mimc200.c
+++ b/board/mimc/mimc200/mimc200.c
@@ -27,12 +27,32 @@
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <atmel_lcdc.h>
#include <lcd.h>
#include "../../../arch/avr32/cpu/hsmc3.h"
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
#if defined(CONFIG_LCD)
/* 480x272x16 @ 72 Hz */
vidinfo_t panel_info = {
@@ -153,13 +173,11 @@ phys_size_t initdram(int board_type)
unsigned long actual_size;
void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+ sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
index 8b3e22c..78f4fd4 100644
--- a/board/miromico/hammerhead/hammerhead.c
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -30,10 +30,25 @@
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/memory-map.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
@@ -80,13 +95,11 @@ phys_size_t initdram(int board_type)
unsigned long actual_size;
void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+ sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
-
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 060d5d1..4336729 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -67,7 +67,7 @@ int board_mmc_init(bd_t *bis)
int i;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
- gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1);
+ gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
/*
* MMC0 GPIO
@@ -80,11 +80,11 @@ int board_mmc_init(bd_t *bis)
if (i == 2)
continue;
/* GPG0[0:6] special function 2 */
- gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2);
+ gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
/* GPG0[0:6] pull disable */
- gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE);
+ gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
- gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X);
+ gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
}
return s5p_mmc_init(0);
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
index 4b72992..62737ab 100644
--- a/board/samsung/goni/lowlevel_init.S
+++ b/board/samsung/goni/lowlevel_init.S
@@ -51,7 +51,7 @@ lowlevel_init:
ldr r7, =S5PC100_GPIO_BASE
ldr r8, =S5PC100_GPIO_BASE
/* Read CPU ID */
- ldr r2, =S5PC1XX_PRO_ID
+ ldr r2, =S5PC110_PRO_ID
ldr r0, [r2]
mov r1, #0x00010000
and r0, r0, r1
@@ -377,7 +377,7 @@ lockloop:
* void system_clock_init(void)
*/
system_clock_init:
- ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
+ ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Check S5PC100 */
cmp r7, r8
@@ -437,7 +437,7 @@ system_clock_init:
ldr r1, =0x3ff03ff
str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
- ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
+ ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
index 32572c5..30d0d06 100644
--- a/board/samsung/smdkc100/lowlevel_init.S
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -131,7 +131,7 @@ wakeup_reset:
* void system_clock_init(void)
*/
system_clock_init:
- ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000
+ ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x00011110
diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
index c25869e..501855e 100644
--- a/board/samsung/smdkc100/onenand.c
+++ b/board/samsung/smdkc100/onenand.c
@@ -35,7 +35,8 @@
void onenand_board_init(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
- struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
struct samsung_onenand *onenand;
int value;
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index fb466c6..31e8d9e 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -38,10 +38,10 @@ static void smc9115_pre_init(void)
u32 smc_bw_conf, smc_bc_conf;
struct s5pc100_gpio *const gpio =
- (struct s5pc100_gpio *)S5PC100_GPIO_BASE;
+ (struct s5pc100_gpio *)samsung_get_base_gpio();
/* gpio configuration GPK0CON */
- gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+ gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
new file mode 100644
index 0000000..87d2234
--- /dev/null
+++ b/board/syteco/jadecpu/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += jadecpu.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk
new file mode 100644
index 0000000..c661f0b
--- /dev/null
+++ b/board/syteco/jadecpu/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x46000000
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
new file mode 100644
index 0000000..04d2f9d
--- /dev/null
+++ b/board/syteco/jadecpu/jadecpu.c
@@ -0,0 +1,170 @@
+/*
+ * (c) 2010 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mb86r0x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
+ MB86R0x_CCNT_BASE;
+
+ /* We select mode 0 for group 2 and mode 1 for group 4 */
+ writel(0x00000010, &ccnt->cmux_md);
+
+ gd->flags = 0;
+ gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
+ gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
+
+ icache_enable();
+
+ return 0;
+}
+
+static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
+ unsigned long pwm_base)
+{
+ struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+ MB86R0x_GPIO_BASE;
+ struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
+ const char *e;
+
+ writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
+
+ e = getenv(pwm_opts);
+ if (e != NULL) {
+ const char *s;
+ uint32_t freq, init;
+
+ freq = 0;
+ init = 0;
+
+ s = strchr(e, 'f');
+ if (s != NULL)
+ freq = simple_strtol(s + 2, NULL, 0);
+
+ s = strchr(e, 'i');
+ if (s != NULL)
+ init = simple_strtol(s + 2, NULL, 0);
+
+ if (freq > 0) {
+ writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
+ &pwm->bcr);
+ writel(1002, &pwm->tpr);
+ writel(1, &pwm->pr);
+ writel(init * 10 + 1, &pwm->dr);
+ writel(1, &pwm->cr);
+ writel(1, &pwm->sr);
+ }
+ }
+}
+
+int board_late_init(void)
+{
+ struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+ MB86R0x_GPIO_BASE;
+ uint32_t in_word;
+
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+ /* Check if we have valid display settings and turn on power if so */
+ /* Display 0 */
+ if (getenv("gs_dsp_0_param") || getenv("videomode"))
+ setup_display_power((1 << 3), "gs_dsp_0_pwm",
+ MB86R0x_PWM0_BASE);
+
+ /* The corresponding GPIO is always an output */
+ writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
+
+ /* Display 1 */
+ if (getenv("gs_dsp_1_param") || getenv("videomode1"))
+ setup_display_power((1 << 4), "gs_dsp_1_pwm",
+ MB86R0x_PWM1_BASE);
+
+ /* The corresponding GPIO is always an output */
+ writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
+#endif /* CONFIG_VIDEO_MB86R0xGDC */
+
+ /* 5V enable */
+ writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
+ writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
+
+ /* We have special boot options if told by GPIOs */
+ in_word = readl(&gpio->gpdr1);
+
+ if ((in_word & 0xC0) == 0xC0) {
+ setenv("stdin", "serial");
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ setenv("preboot", "run gs_slow_boot");
+ } else if ((in_word & 0xC0) != 0) {
+ setenv("stdout", "vga");
+ setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;"
+ "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
+ "bootelf 0x40000000; bootelf 0x10080000");
+ setenv("preboot", "run gs_slow_boot");
+ } else {
+ setenv("stdin", "serial");
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ if (getenv("gs_devel")) {
+ setenv("preboot", "run gs_slow_boot");
+ } else {
+ setenv("gs_bootcmd", "bootelf 0x10080000");
+ setenv("preboot", "run gs_fast_boot");
+ }
+ }
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S
new file mode 100644
index 0000000..5ad4dce
--- /dev/null
+++ b/board/syteco/jadecpu/lowlevel_init.S
@@ -0,0 +1,265 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/mb86r0x.h>
+#include <asm/arch/asm-offsets.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+/*
+ * Initialize Clock Reset Generator (CRG)
+ */
+
+ ldr r0, =MB86R0x_CRG_BASE
+
+ /* Not change the initial value that is set by external pin.*/
+WAIT_PLL:
+ ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
+ tst r2, #MB86R0x_CRG_CRPR_PLLRDY
+ beq WAIT_PLL
+
+ /* Set clock gate control */
+ ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
+ str r1, [r0, #CRG_CRHA]
+ ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
+ str r1, [r0, #CRG_CRPA]
+ ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
+ str r1, [r0, #CRG_CRPB]
+ ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
+ str r1, [r0, #CRG_CRHB]
+ ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
+ str r1, [r0, #CRG_CRAM]
+
+/*
+ * Initialize External Bus Interface
+ */
+ ldr r0, =MB86R0x_MEMC_BASE
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
+ str r1, [r0, #MEMC_MCFMODE0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
+ str r1, [r0, #MEMC_MCFMODE2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
+ str r1, [r0, #MEMC_MCFMODE4]
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
+ str r1, [r0, #MEMC_MCFTIM0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
+ str r1, [r0, #MEMC_MCFTIM2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
+ str r1, [r0, #MEMC_MCFTIM4]
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
+ str r1, [r0, #MEMC_MCFAREA0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
+ str r1, [r0, #MEMC_MCFAREA2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
+ str r1, [r0, #MEMC_MCFAREA4]
+
+/*
+ * Initialize DDR2 Controller
+ */
+
+ /* Wait for PLL LOCK up time or more */
+ wait_timer 20
+
+ /*
+ * (2) Initialize DDRIF
+ */
+ ldr r0, =MB86R0x_DDR2_BASE
+ ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
+ strh r1, [r0, #DDR2_DRIMS]
+
+ /*
+ * (3) Wait for 20MCKPs(120nsec) or more
+ */
+ wait_timer 20
+
+ /*
+ * (4) IRESET/IUSRRST release
+ */
+ ldr r0, =MB86R0x_CCNT_BASE
+ ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
+ str r1, [r0, #CCNT_CDCRC]
+
+ /*
+ * (5) Wait for 20MCKPs(120nsec) or more
+ */
+ wait_timer 20
+
+ /*
+ * (6) IDLLRST release
+ */
+ ldr r0, =MB86R0x_CCNT_BASE
+ ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
+ str r1, [r0, #CCNT_CDCRC]
+
+ /*
+ * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
+ */
+ wait_timer 33536
+
+ /*
+ * (9) MCKE ON
+ */
+ ldr r0, =MB86R0x_DDR2_BASE
+ ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
+ strh r1, [r0, #DDR2_DRCA]
+ ldr r1, =MB86R0x_DDR2_DRCI_INIT
+ strh r1, [r0, #DDR2_DRIC]
+
+ /*
+ * (10) Initialize SDRAM
+ */
+
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 67 /* 400ns wait */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 200
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 18 /* 105ns wait */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 200 /* MRS to OCD: 200clock */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
+ strh r1, [r0, #DDR2_DRCM]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
+ strh r1, [r0, #DDR2_DRCST1]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
+ strh r1, [r0, #DDR2_DRCST2]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
+ strh r1, [r0, #DDR2_DRCR]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
+ strh r1, [r0, #DDR2_DRCF]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
+ strh r1, [r0, #DDR2_DRASR]
+
+ /*
+ * (11) ODT setting
+ */
+ ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
+ strh r1, [r0, #DDR2_DROBS]
+ ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
+ strh r1, [r0, #DDR2_DROABA]
+ ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
+ strh r1, [r0, #DDR2_DRIBSODT1]
+
+ /*
+ * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
+ */
+ ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
+ strh r1, [r0, #DDR2_DROS]
+ ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
+ strh r1, [r0, #DDR2_DRIC]
+
+ mov pc, lr
generated by cgit v1.1 at 2024-12-13 13:26:53 +0000