diff options
Diffstat (limited to 'board')
185 files changed, 3886 insertions, 1542 deletions
diff --git a/board/8dtech/eco5pk/Kconfig b/board/8dtech/eco5pk/Kconfig index fb1b308..0af1b30 100644 --- a/board/8dtech/eco5pk/Kconfig +++ b/board/8dtech/eco5pk/Kconfig @@ -1,9 +1,5 @@ if TARGET_ECO5PK -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "eco5pk" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "8dtech" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "eco5pk" diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig index a8134479..588ee73 100644 --- a/board/Barix/ipam390/Kconfig +++ b/board/Barix/ipam390/Kconfig @@ -1,9 +1,5 @@ if TARGET_IPAM390 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "ipam390" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Barix" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "ipam390" diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds index 8604696..5f290ec 100644 --- a/board/Barix/ipam390/u-boot-spl-ipam390.lds +++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig index f1151d1..9675a9e 100644 --- a/board/LaCie/edminiv2/Kconfig +++ b/board/LaCie/edminiv2/Kconfig @@ -1,9 +1,5 @@ if TARGET_EDMINIV2 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "edminiv2" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "LaCie" -config SYS_SOC - string - default "orion5x" - config SYS_CONFIG_NAME string default "edminiv2" diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig index 867d0d3..e8eb9ad 100644 --- a/board/LaCie/net2big_v2/Kconfig +++ b/board/LaCie/net2big_v2/Kconfig @@ -1,9 +1,5 @@ if TARGET_NET2BIG_V2 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "net2big_v2" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "LaCie" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "lacie_kw" diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig index fb6fbef..6242a42 100644 --- a/board/LaCie/netspace_v2/Kconfig +++ b/board/LaCie/netspace_v2/Kconfig @@ -1,9 +1,5 @@ if TARGET_NETSPACE_V2 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "netspace_v2" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "LaCie" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "lacie_kw" diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig index 4815cde..ea6850f 100644 --- a/board/LaCie/wireless_space/Kconfig +++ b/board/LaCie/wireless_space/Kconfig @@ -1,9 +1,5 @@ if TARGET_WIRELESS_SPACE -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "wireless_space" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "LaCie" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "wireless_space" diff --git a/board/Marvell/dreamplug/Kconfig b/board/Marvell/dreamplug/Kconfig index e067318..afaddf4 100644 --- a/board/Marvell/dreamplug/Kconfig +++ b/board/Marvell/dreamplug/Kconfig @@ -1,9 +1,5 @@ if TARGET_DREAMPLUG -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dreamplug" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "dreamplug" diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig index fce8562..0b10e9f 100644 --- a/board/Marvell/guruplug/Kconfig +++ b/board/Marvell/guruplug/Kconfig @@ -1,9 +1,5 @@ if TARGET_GURUPLUG -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "guruplug" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "guruplug" diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig index 17adab0..49654fe 100644 --- a/board/Marvell/mv88f6281gtw_ge/Kconfig +++ b/board/Marvell/mv88f6281gtw_ge/Kconfig @@ -1,9 +1,5 @@ if TARGET_MV88F6281GTW_GE -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "mv88f6281gtw_ge" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "mv88f6281gtw_ge" diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig index 2dfed34..7032ba5 100644 --- a/board/Marvell/openrd/Kconfig +++ b/board/Marvell/openrd/Kconfig @@ -1,9 +1,5 @@ if TARGET_OPENRD -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "openrd" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "openrd" diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig index ae753b0..e8702a7 100644 --- a/board/Marvell/rd6281a/Kconfig +++ b/board/Marvell/rd6281a/Kconfig @@ -1,9 +1,5 @@ if TARGET_RD6281A -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "rd6281a" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "rd6281a" diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig index 6f3eb38..1c24d24 100644 --- a/board/Marvell/sheevaplug/Kconfig +++ b/board/Marvell/sheevaplug/Kconfig @@ -1,9 +1,5 @@ if TARGET_SHEEVAPLUG -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "sheevaplug" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Marvell" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "sheevaplug" diff --git a/board/Seagate/dockstar/Kconfig b/board/Seagate/dockstar/Kconfig index 4696ac6..13ea620 100644 --- a/board/Seagate/dockstar/Kconfig +++ b/board/Seagate/dockstar/Kconfig @@ -1,9 +1,5 @@ if TARGET_DOCKSTAR -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dockstar" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Seagate" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "dockstar" diff --git a/board/Seagate/goflexhome/Kconfig b/board/Seagate/goflexhome/Kconfig index 0f918cb..2fb14ef 100644 --- a/board/Seagate/goflexhome/Kconfig +++ b/board/Seagate/goflexhome/Kconfig @@ -1,9 +1,5 @@ if TARGET_GOFLEXHOME -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "goflexhome" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "Seagate" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "goflexhome" diff --git a/board/ait/cam_enc_4xx/Kconfig b/board/ait/cam_enc_4xx/Kconfig index d1f89df..2b88692 100644 --- a/board/ait/cam_enc_4xx/Kconfig +++ b/board/ait/cam_enc_4xx/Kconfig @@ -1,9 +1,5 @@ if TARGET_CAM_ENC_4XX -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "cam_enc_4xx" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ait" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "cam_enc_4xx" diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index c0d09ad..f5c19df 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c deleted file mode 100644 index 580d590..0000000 --- a/board/altera/common/epled.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <nios2-io.h> -#include <status_led.h> - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - val ^= mask; - writel (val, &pio->data); -} diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index aa362b3..5e4192c 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -8,5 +8,3 @@ obj-y := nios2-generic.o obj-$(CONFIG_CMD_IDE) += ../common/cfide.o -obj-$(CONFIG_EPLED) += ../common/epled.o -obj-y += text_base.o diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index fd3ec9a..cf75d35 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -1,78 +1,89 @@ /* - * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * This header is generated by sopc2dts + * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> + * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file is generated by sopc-create-config-files. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CUSTOM_FPGA_H_ #define _CUSTOM_FPGA_H_ -/* generated from std_1c20.sopc */ - -/* cpu.data_master is a altera_nios2 */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SYS_RESET_ADDR 0x00000000 -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_ICACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_SIZE 2048 -#define CONFIG_SYS_DCACHELINE_SIZE 4 - -/* sdram.s1 is a altera_avalon_new_sdram_controller */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 - -/* uart1.s1 is a altera_avalon_uart */ -#define CONFIG_SYS_UART_BASE 0x82120840 -#define CONFIG_SYS_UART_FREQ 50000000 -#define CONFIG_SYS_UART_BAUD 115200 - -/* lan91c111.s1 is a altera_avalon_lan91c111 */ -#define CONFIG_SMC91111_BASE 0x82110300 -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT - -/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ -#define EPCS_CONTROLLER_REG_BASE 0x82100200 -#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } -#define CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO +/* generated from qsys_ghrd_3c120.sopcinfo */ + +/* Dumping slaves of cpu.data_master */ + +/* cpu.jtag_debug_module is a altera_nios2_qsys */ +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_DCACHELINE_SIZE 32 +#define CONFIG_SYS_ICACHELINE_SIZE 32 +#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 +#define CONFIG_SYS_ICACHE_SIZE 32768 +#define CONFIG_SYS_RESET_ADDR 0xc2800000 +#define IO_REGION_BASE 0xE0000000 + +/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ + +/* ddr2_bot.s1 is a altmemddr2 */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_io.m0 */ + +/* timer_1ms.s1 is a altera_avalon_timer */ +#define CONFIG_SYS_TIMER_IRQ 11 +#define CONFIG_SYS_TIMER_FREQ 125000000 +#define CONFIG_SYS_TIMER_BASE 0xE8400000 + +/* sysid.control_slave is a altera_avalon_sysid_qsys */ +#define CONFIG_SYS_SYSID_BASE 0xE8004D40 /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ -#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 +#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 + +/* tse_mac.control_port is a triple_speed_ethernet */ +#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 +#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 +#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 +#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 +#define CONFIG_ALTERA_TSE +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 +#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 + +/* uart.s1 is a altera_avalon_uart */ +#define CONFIG_SYS_UART_BAUD 115200 +#define CONFIG_SYS_UART_BASE 0xE8004C80 +#define CONFIG_SYS_UART_FREQ 62500000 + +/* user_led_pio_8out.s1 is a altera_avalon_pio */ +#define USER_LED_PIO_8OUT_BASE 0xE8004CC0 -/* led_pio.s1 is a altera_avalon_pio */ -#define LED_PIO_BASE 0x82120870 -#define LED_PIO_WIDTH 8 -#define LED_PIO_RSTVAL 0x0 +/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ +#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 +#define USER_DIPSW_PIO_8IN_IRQ 8 -/* high_res_timer.s1 is a altera_avalon_timer */ -#define CONFIG_SYS_TIMER_BASE 0x82120820 -#define CONFIG_SYS_TIMER_IRQ 3 -#define CONFIG_SYS_TIMER_FREQ 50000000 +/* user_pb_pio_4in.s1 is a altera_avalon_pio */ +#define USER_PB_PIO_4IN_BASE 0xE8004D00 +#define USER_PB_PIO_4IN_IRQ 9 + +/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ +#define CFI_FLASH_64M_BASE 0xE0000000 /* ext_flash.s1 is a altera_avalon_cfi_flash */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 +#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 -#define CONFIG_SYS_SRAM_SIZE 0x00100000 - -/* sysid.control_slave is a altera_avalon_sysid */ -#define CONFIG_SYS_SYSID_BASE 0x821208b8 +#define CONFIG_SYS_MAX_FLASH_SECT 512 #endif /* _CUSTOM_FPGA_H_ */ diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 5ab9471..834cbeb 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -14,8 +14,6 @@ #include <asm/io.h> #include <asm/gpio.h> -void text_base_hook(void); /* nop hook for text_base.S */ - #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ defined(CONFIG_CFI_FLASH_MTD) static void __early_flash_cmd_reset(void) @@ -30,7 +28,6 @@ void early_flash_cmd_reset(void) int board_early_init_f(void) { - text_base_hook(); #ifdef CONFIG_ALTERA_PIO #ifdef LED_PIO_BASE altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o', diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S deleted file mode 100644 index f236db1..0000000 --- a/board/altera/nios2-generic/text_base.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * text_base - * - * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <config.h> - -#ifdef CONFIG_SYS_MONITOR_BASE - .text - /* text base used in link script u-boot.lds */ - .global text_base - .equ text_base,CONFIG_SYS_MONITOR_BASE - /* dummy func to let linker include this file */ - .global text_base_hook -text_base_hook: - ret -#endif diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds deleted file mode 100644 index e35fae5..0000000 --- a/board/altera/nios2-generic/u-boot.lds +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -OUTPUT_FORMAT("elf32-littlenios2") -OUTPUT_ARCH(nios2) -ENTRY(_start) - -SECTIONS -{ - . = text_base; - .text : - { - arch/nios2/cpu/start.o (.text) - *(.text) - *(.text.*) - *(.gnu.linkonce.t*) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.gnu.linkonce.r*) - } - . = ALIGN (4); - _etext = .; - PROVIDE (etext = .); - - /* CMD TABLE - sandwich this in between text and data so - * the initialization code relocates the command table as - * well -- admittedly, this is just pure laziness ;-) - */ - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - /* INIT DATA sections - "Small" data (see the gcc -G option) - * is always gp-relative. Here we make all init data sections - * adjacent to simplify the startup code -- and provide - * the global pointer for gp-relative access. - */ - _data = .; - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - } - - . = ALIGN(16); - _gp = .; /* Global pointer addr */ - PROVIDE (gp = .); - - .sdata : - { - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - } - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* UNINIT DATA - Small uninitialized data is first so it's - * adjacent to sdata and can be referenced via gp. The normal - * bss follows. We keep it adjacent to simplify init code. - */ - __bss_start = .; - .sbss (NOLOAD) : - { - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } - . = ALIGN(4); - .bss (NOLOAD) : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - *(.scommon) - } - . = ALIGN(4); - __bss_end = .; - PROVIDE (end = .); - - /* DEBUG -- symbol table, string table, etc. etc. - */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile index de339ec..44baa00 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/socfpga/Makefile @@ -7,4 +7,4 @@ # obj-y := socfpga_cyclone5.o -obj-$(CONFIG_SPL_BUILD) += pinmux_config.o +obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index f366565..fb92852 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -37,12 +37,3 @@ int board_init(void) icache_enable(); return 0; } - -/* - * DesignWare Ethernet initialization - */ -/* We know all the init functions have been run now */ -int board_eth_init(bd_t *bis) -{ - return 0; -} diff --git a/board/highbank/Kconfig b/board/aristainetos/Kconfig index 1c32490..58078ea 100644 --- a/board/highbank/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,4 +1,4 @@ -if TARGET_HIGHBANK +if TARGET_ARISTAINETOS config SYS_CPU string @@ -6,14 +6,14 @@ config SYS_CPU config SYS_BOARD string - default "highbank" + default "aristainetos" config SYS_SOC string - default "highbank" + default "mx6" config SYS_CONFIG_NAME string - default "highbank" + default "aristainetos" endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS new file mode 100644 index 0000000..d45d423 --- /dev/null +++ b/board/aristainetos/MAINTAINERS @@ -0,0 +1,6 @@ +ARISTAINETOS BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/aristainetos/ +F: include/configs/aristainetos.h +F: configs/aristainetos_defconfig diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile new file mode 100644 index 0000000..5de48bc --- /dev/null +++ b/board/aristainetos/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := aristainetos.o diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c new file mode 100644 index 0000000..3bfcf5b --- /dev/null +++ b/board/aristainetos/aristainetos.c @@ -0,0 +1,519 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <pwm.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define DISP_PAD_CTRL (0x10) + +#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const gpio_pads[] = { + /* LED enable */ + MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi flash WP protect */ + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* backlight enable */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED yellow */ + MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED red */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED green */ + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED blue */ + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* i2c4 scl */ + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* i2c4 sda */ + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi CS 1 */ + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const misc_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG Power enable */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); +} + +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const display_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN4__GPIO4_IO20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + int i; + + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); + for (i = 0; i < 3; i++) + enable_spi_clk(true, i); + + /* set cs1 to high */ + gpio_direction_output(ECSPI4_CS1, 1); +} + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); +} +#endif + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *iomuxc_regs = + (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + setup_iomux_enet(); + /* clear gpr1[14], gpr1[18:17] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); + + ret = enable_fec_anatop_clock(ENET_50MHz); + if (ret) + return ret; + + return cpu_eth_init(bis); +} +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_lvds(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + display_pads, + ARRAY_SIZE(display_pads)); + imx_iomux_v3_setup_multiple_pads( + backlight_pads, + ARRAY_SIZE(backlight_pads)); + + /* enable backlight PWM 3 */ + if (pwm_init(2, 0, 0)) + goto error; + /* duty cycle 200ns, period: 3000ns */ + if (pwm_config(2, 200, 3000)) + goto error; + if (pwm_enable(2)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); + return; +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "lb07wv8", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33246, + .left_margin = 88, + .right_margin = 88, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 25, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + + reg = readl(&mxc_ccm->cs2cdr); + /* select pll 5 clock */ + reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; + reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cs2cdr); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); +} + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_gpio(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int board_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_spi(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info3); + + /* i2c4 not used, set it to gpio input */ + gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl"); + gpio_direction_input(IMX_GPIO_NR(1, 7)); + gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda"); + gpio_direction_input(IMX_GPIO_NR(1, 8)); + + /* SPI NOR Flash read only */ + gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); + gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); + gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); + + /* enable LED */ + gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); + gpio_direction_output(IMX_GPIO_NR(2, 13), 0); + + gpio_request(IMX_GPIO_NR(1, 3), "LED yellow"); + gpio_direction_output(IMX_GPIO_NR(1, 3), 1); + gpio_request(IMX_GPIO_NR(1, 4), "LED red"); + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + gpio_request(IMX_GPIO_NR(1, 5), "LED green"); + gpio_direction_output(IMX_GPIO_NR(1, 5), 1); + gpio_request(IMX_GPIO_NR(1, 6), "LED blue"); + gpio_direction_output(IMX_GPIO_NR(1, 6), 1); + + setup_gpmi_nand(); + + /* GPIO_1 for USB_OTG_ID */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK); + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + + return 0; +} + +int checkboard(void) +{ + puts("Board: aristaitenos\n"); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + int ret; + + ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); + ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); + else + gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); + return 0; +} +#endif diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg new file mode 100644 index 0000000..2290180 --- /dev/null +++ b/board/aristainetos/aristainetos.cfg @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd + */ +BOOT_FROM spi + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "mt41j128M.cfg" +#include "clocks.cfg" diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg new file mode 100644 index 0000000..651449e --- /dev/null +++ b/board/aristainetos/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00c03f3f +DATA 4, CCM_CCGR1, 0x0030fcff +DATA 4, CCM_CCGR2, 0x0fffcfc0 +DATA 4, CCM_CCGR3, 0x3ff0300f +DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0f0000c3 +DATA 4, CCM_CCGR6, 0x000003ff diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg new file mode 100644 index 0000000..c72a3ef --- /dev/null +++ b/board/aristainetos/ddr-setup.cfg @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* Data Strobe */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg new file mode 100644 index 0000000..3561655 --- /dev/null +++ b/board/aristainetos/mt41j128M.cfg @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* ZQ Calibration */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* + * DQS gating, read delay, write delay calibration values + * based on calibration compare of 0x00ffff00 + */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +/* MR2 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a +/* MR3 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +/* MR1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +/* MR0 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +/* final ddr setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d +DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/armltd/versatile/Kconfig b/board/armltd/versatile/Kconfig deleted file mode 100644 index f96d0b2..0000000 --- a/board/armltd/versatile/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -if TARGET_VERSATILEAB - -config SYS_CPU - string - default "arm926ejs" - -config SYS_BOARD - string - default "versatile" - -config SYS_VENDOR - string - default "armltd" - -config SYS_SOC - string - default "versatile" - -config SYS_CONFIG_NAME - string - default "versatile" - -endif - -if TARGET_VERSATILEPB - -config SYS_CPU - string - default "arm926ejs" - -config SYS_BOARD - string - default "versatile" - -config SYS_VENDOR - string - default "armltd" - -config SYS_SOC - string - default "versatile" - -config SYS_CONFIG_NAME - string - default "versatile" - -endif - -if TARGET_VERSATILEQEMU - -config SYS_CPU - string - default "arm926ejs" - -config SYS_BOARD - string - default "versatile" - -config SYS_VENDOR - string - default "armltd" - -config SYS_SOC - string - default "versatile" - -config SYS_CONFIG_NAME - string - default "versatile" - -endif diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS index cfde7f2..e730f4f 100644 --- a/board/armltd/vexpress/MAINTAINERS +++ b/board/armltd/vexpress/MAINTAINERS @@ -7,7 +7,7 @@ F: configs/vexpress_ca15_tc2_defconfig VEXPRESS_CA5X2 BOARD M: Matt Waddel <matt.waddel@linaro.org> -S: Maintained +S: Orphan (since 2014-08) F: include/configs/vexpress_ca5x2.h F: configs/vexpress_ca5x2_defconfig F: include/configs/vexpress_ca9x4.h diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig index c8f89fe..3365c7b 100644 --- a/board/atmark-techno/armadillo-800eva/Kconfig +++ b/board/atmark-techno/armadillo-800eva/Kconfig @@ -1,9 +1,5 @@ if TARGET_ARMADILLO_800EVA -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "armadillo-800eva" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "atmark-techno" -config SYS_SOC - string - default "rmobile" - config SYS_CONFIG_NAME string default "armadillo-800eva" diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig index 2472fe2..16001e4 100644 --- a/board/avionic-design/medcom-wide/Kconfig +++ b/board/avionic-design/medcom-wide/Kconfig @@ -1,10 +1,5 @@ if TARGET_MEDCOM_WIDE -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "medcom-wide" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "avionic-design" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "medcom-wide" diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig index a697a54..c9a90247 100644 --- a/board/avionic-design/plutux/Kconfig +++ b/board/avionic-design/plutux/Kconfig @@ -1,10 +1,5 @@ if TARGET_PLUTUX -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "plutux" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "avionic-design" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "plutux" diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig index f52edda..e6b69e8 100644 --- a/board/avionic-design/tec-ng/Kconfig +++ b/board/avionic-design/tec-ng/Kconfig @@ -1,10 +1,5 @@ if TARGET_TEC_NG -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "tec-ng" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "avionic-design" -config SYS_SOC - string - default "tegra30" - config SYS_CONFIG_NAME string default "tec-ng" diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig index d19e3f4..fbf7f46 100644 --- a/board/avionic-design/tec/Kconfig +++ b/board/avionic-design/tec/Kconfig @@ -1,10 +1,5 @@ if TARGET_TEC -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "tec" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "avionic-design" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "tec" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 84294db..60a09f4 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -644,8 +644,7 @@ int overwrite_console(void) int board_init(void) { - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, diff --git a/board/broadcom/bcm28155_w1d/MAINTAINERS b/board/broadcom/bcm28155_w1d/MAINTAINERS new file mode 100644 index 0000000..a436490 --- /dev/null +++ b/board/broadcom/bcm28155_w1d/MAINTAINERS @@ -0,0 +1,6 @@ +BCM28155_W1D BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm28155_ap.h +F: configs/bcm28155_w1d_defconfig diff --git a/board/broadcom/bcm958300k/Kconfig b/board/broadcom/bcm958300k/Kconfig new file mode 100644 index 0000000..165cee7 --- /dev/null +++ b/board/broadcom/bcm958300k/Kconfig @@ -0,0 +1,23 @@ +if TARGET_BCM958300K + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "bcm_ep" + +config SYS_VENDOR + string + default "broadcom" + +config SYS_SOC + string + default "bcmcygnus" + +config SYS_CONFIG_NAME + string + default "bcm_ep_board" + +endif diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS new file mode 100644 index 0000000..f75ee6e --- /dev/null +++ b/board/broadcom/bcm958300k/MAINTAINERS @@ -0,0 +1,6 @@ +Broadcom: Cygnus +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm958300k/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958300k_defconfig diff --git a/board/broadcom/bcm958622hr/Kconfig b/board/broadcom/bcm958622hr/Kconfig new file mode 100644 index 0000000..6d09592 --- /dev/null +++ b/board/broadcom/bcm958622hr/Kconfig @@ -0,0 +1,23 @@ +if TARGET_BCM958622HR + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "bcm_ep" + +config SYS_VENDOR + string + default "broadcom" + +config SYS_SOC + string + default "bcmnsp" + +config SYS_CONFIG_NAME + string + default "bcm_ep_board" + +endif diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS new file mode 100644 index 0000000..c34272f --- /dev/null +++ b/board/broadcom/bcm958622hr/MAINTAINERS @@ -0,0 +1,6 @@ +Broadcom: Northstar Plus +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm958622hr/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958622hr_defconfig diff --git a/board/broadcom/bcm_ep/Makefile b/board/broadcom/bcm_ep/Makefile new file mode 100644 index 0000000..8914e54 --- /dev/null +++ b/board/broadcom/bcm_ep/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c new file mode 100644 index 0000000..e48cd3f --- /dev/null +++ b/board/broadcom/bcm_ep/board.c @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <config.h> +#include <asm/system.h> +#include <asm/iproc-common/armpll.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + /* + * Address of boot parameters passed to kernel + * Use default offset 0x100 + */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * dram_init - sets u-boot's idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +int board_early_init_f(void) +{ + uint32_t status = 0; + + /* Setup PLL if required */ +#if defined(CONFIG_ARMCLK) + armpll_config(CONFIG_ARMCLK); +#endif + + return status; +} diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig index 99f7b7c..50a620e 100644 --- a/board/buffalo/lsxl/Kconfig +++ b/board/buffalo/lsxl/Kconfig @@ -1,9 +1,5 @@ if TARGET_LSXL -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "lsxl" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "buffalo" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "lsxl" diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds index b0d892a..4aa7891 100644 --- a/board/cirrus/edb93xx/u-boot.lds +++ b/board/cirrus/edb93xx/u-boot.lds @@ -21,6 +21,7 @@ SECTIONS . = ALIGN(4); .text : { *(.__image_copy_start) + *(.vectors) arch/arm/cpu/arm920t/start.o (.text*) . = 0x1000; diff --git a/board/cloudengines/pogo_e02/Kconfig b/board/cloudengines/pogo_e02/Kconfig index 149a1a2..fe36314 100644 --- a/board/cloudengines/pogo_e02/Kconfig +++ b/board/cloudengines/pogo_e02/Kconfig @@ -1,9 +1,5 @@ if TARGET_POGO_E02 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "pogo_e02" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "cloudengines" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "pogo_e02" diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig index d7a2bf2..4c5ea09 100644 --- a/board/comelit/dig297/Kconfig +++ b/board/comelit/dig297/Kconfig @@ -1,9 +1,5 @@ if TARGET_DIG297 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "dig297" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "comelit" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "dig297" diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig index 4f0f09f..690d7a7 100644 --- a/board/compal/paz00/Kconfig +++ b/board/compal/paz00/Kconfig @@ -1,10 +1,5 @@ if TARGET_PAZ00 -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "paz00" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "compal" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "paz00" diff --git a/board/compulab/cm_t35/Kconfig b/board/compulab/cm_t35/Kconfig index fd960bc..06de692 100644 --- a/board/compulab/cm_t35/Kconfig +++ b/board/compulab/cm_t35/Kconfig @@ -1,9 +1,5 @@ if TARGET_CM_T35 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "cm_t35" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "compulab" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "cm_t35" diff --git a/board/compulab/cm_t54/Kconfig b/board/compulab/cm_t54/Kconfig index 0fe3692..0edab5c 100644 --- a/board/compulab/cm_t54/Kconfig +++ b/board/compulab/cm_t54/Kconfig @@ -1,9 +1,5 @@ if TARGET_CM_T54 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "cm_t54" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "compulab" -config SYS_SOC - string - default "omap5" - config SYS_CONFIG_NAME string default "cm_t54" diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index fadfddc..944b723 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -43,7 +43,7 @@ const struct omap_sysinfo sysinfo = { */ int board_init(void) { - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); /* boot param addr */ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); return 0; } @@ -89,7 +89,7 @@ uint mmc_get_env_part(struct mmc *mmc) * If booted from eMMC boot partition then force eMMC * FIRST boot partition to be env storage */ - if (bootmode == BOOT_DEVICE_MMC2_2) + if (bootmode == BOOT_DEVICE_MMC2) bootpart = 1; return bootpart; @@ -169,7 +169,7 @@ static int handle_mac_address(void) return 0; ret = cl_eeprom_read_mac_addr(enetaddr); - if (!ret || !is_valid_ether_addr(enetaddr)) + if (ret || !is_valid_ether_addr(enetaddr)) generate_mac_addr(enetaddr); if (!is_valid_ether_addr(enetaddr)) diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig index e545f0c..6ae030c 100644 --- a/board/compulab/trimslice/Kconfig +++ b/board/compulab/trimslice/Kconfig @@ -1,10 +1,5 @@ if TARGET_TRIMSLICE -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "trimslice" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "compulab" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "trimslice" diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig index a1e06e7..5147fd7 100644 --- a/board/corscience/tricorder/Kconfig +++ b/board/corscience/tricorder/Kconfig @@ -1,9 +1,5 @@ if TARGET_TRICORDER -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "tricorder" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "corscience" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "tricorder" diff --git a/board/d-link/dns325/Kconfig b/board/d-link/dns325/Kconfig index dea6071..763f93c 100644 --- a/board/d-link/dns325/Kconfig +++ b/board/d-link/dns325/Kconfig @@ -1,9 +1,5 @@ if TARGET_DNS325 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dns325" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "d-link" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "dns325" diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index 89f78d7..b123703 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -1,9 +1,5 @@ if TARGET_DA830EVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "da8xxevm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "da830evm" @@ -24,10 +16,6 @@ endif if TARGET_DA850EVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "da8xxevm" @@ -36,10 +24,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "da850evm" @@ -48,10 +32,6 @@ endif if TARGET_HAWKBOARD -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "da8xxevm" @@ -60,10 +40,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "hawkboard" diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index de21a13..ab4f50c 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index 299226b..682f268 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -18,6 +18,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*) drivers/mtd/nand/built-in.o (.text*) diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig index 2dbb509..7490bc0 100644 --- a/board/davinci/dm355evm/Kconfig +++ b/board/davinci/dm355evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_DM355EVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dm355evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_dm355evm" diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig index 345704f..73a53ff 100644 --- a/board/davinci/dm355leopard/Kconfig +++ b/board/davinci/dm355leopard/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_DM355LEOPARD -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dm355leopard" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_dm355leopard" diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig index d5f7ea2..266c6ee 100644 --- a/board/davinci/dm365evm/Kconfig +++ b/board/davinci/dm365evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_DM365EVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dm365evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_dm365evm" diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig index f7b225d..1c4d0f0 100644 --- a/board/davinci/dm6467evm/Kconfig +++ b/board/davinci/dm6467evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_DM6467EVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dm6467evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_dm6467evm" diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig index 7a2d86b..e020f8d 100644 --- a/board/davinci/dvevm/Kconfig +++ b/board/davinci/dvevm/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_DVEVM -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "dvevm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_dvevm" diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig index afab821..93950fd 100644 --- a/board/davinci/ea20/Kconfig +++ b/board/davinci/ea20/Kconfig @@ -1,9 +1,5 @@ if TARGET_EA20 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "ea20" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "ea20" diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig index 45401e4..7aa459d 100644 --- a/board/davinci/schmoogie/Kconfig +++ b/board/davinci/schmoogie/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_SCHMOOGIE -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "schmoogie" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_schmoogie" diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig index aeb7ef2..95461fc 100644 --- a/board/davinci/sffsdr/Kconfig +++ b/board/davinci/sffsdr/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_SFFSDR -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "sffsdr" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_sffsdr" diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig index 2cf5035..a21fb8e 100644 --- a/board/davinci/sonata/Kconfig +++ b/board/davinci/sonata/Kconfig @@ -1,9 +1,5 @@ if TARGET_DAVINCI_SONATA -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "sonata" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "davinci" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "davinci_sonata" diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index d06b57d..530ea4f 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -246,6 +246,7 @@ int board_mmc_init(bd_t *bis) riotboard_usdhc3_pads, ARRAY_SIZE(riotboard_usdhc3_pads)); gpio_direction_input(USDHC3_CD_GPIO); + } else { gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); udelay(250); gpio_set_value(IMX_GPIO_NR(7, 8), 1); diff --git a/board/enbw/enbw_cmc/Kconfig b/board/enbw/enbw_cmc/Kconfig index e061e7e..183334b 100644 --- a/board/enbw/enbw_cmc/Kconfig +++ b/board/enbw/enbw_cmc/Kconfig @@ -1,9 +1,5 @@ if TARGET_ENBW_CMC -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "enbw_cmc" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "enbw" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "enbw_cmc" diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS index 2e057db..ec2a320 100644 --- a/board/freescale/mx31pdk/MAINTAINERS +++ b/board/freescale/mx31pdk/MAINTAINERS @@ -1,5 +1,5 @@ MX31PDK BOARD -M: Fabio Estevam <fabio.estevam@freescale.com> +M: Magnus Lilja <lilja.magnus@gmail.com> S: Maintained F: board/freescale/mx31pdk/ F: include/configs/mx31pdk.h diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d7c4b4f..80c8ebd 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -466,7 +466,7 @@ static int pfuze_init(void) if (ret) return ret; - p = pmic_get("PFUZE100_PMIC"); + p = pmic_get("PFUZE100"); ret = pmic_probe(p); if (ret) return ret; diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index d2b64cc..a990b4c 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis) static int setup_fec(void) { - struct iomuxc_base_regs *iomuxc_regs = - (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig new file mode 100644 index 0000000..ee8f4a6 --- /dev/null +++ b/board/freescale/mx6sxsabresd/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SXSABRESD + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "mx6sxsabresd" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "mx6" + +config SYS_CONFIG_NAME + string + default "mx6sxsabresd" + +endif diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS new file mode 100644 index 0000000..f52f300 --- /dev/null +++ b/board/freescale/mx6sxsabresd/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABRESD BOARD +M: Fabio Estevam <fabio.estevam@freescale.com> +S: Maintained +F: board/freescale/mx6sxsabresd/ +F: include/configs/mx6sxsabresd.h +F: configs/mx6sxsabresd_defconfig diff --git a/board/freescale/mx6sxsabresd/Makefile b/board/freescale/mx6sxsabresd/Makefile new file mode 100644 index 0000000..97dbfda --- /dev/null +++ b/board/freescale/mx6sxsabresd/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sxsabresd.o diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg new file mode 100644 index 0000000..c862617 --- /dev/null +++ b/board/freescale/mx6sxsabresd/imximage.cfg @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000020 +DATA 4 0x020e02fc 0x00000020 +DATA 4 0x020e05f4 0x00000020 + +/* Control */ +DATA 4 0x020e0340 0x00000020 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000020 +DATA 4 0x020e0314 0x00000020 +DATA 4 0x020e0614 0x00000020 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000028 +DATA 4 0x020e0334 0x00000028 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e033c 0x00000028 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x00290025 +DATA 4 0x021b0810 0x00220022 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x41480144 +DATA 4 0x021b0840 0x01340130 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x3C3E4244 +DATA 4 0x021b0850 0x34363638 + +/* Read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c new file mode 100644 index 0000000..5eaec1b --- /dev/null +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const phy_control_pads[] = { + /* 25MHz Ethernet PHY Clock */ + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + /* ENET PHY Power */ + MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* AR8031 PHY Reset */ + MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int ret; + int reg; + + /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + imx_iomux_v3_setup_multiple_pads(phy_control_pads, + ARRAY_SIZE(phy_control_pads)); + + /* Enable the ENET power, active low */ + gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); + + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + + reg = readl(&anatop->pll_enet); + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; + writel(reg, &anatop->pll_enet); + + ret = enable_fec_anatop_clock(ENET_125MHz); + if (ret) + return ret; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + setup_fec(); + + return cpu_eth_init(bis); +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +static int pfuze_init(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + pfuze_init(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SX SABRE SDB\n"); + + return 0; +} diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index e90186e..3edc915 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -6,7 +6,10 @@ */ #include <common.h> +#include <errno.h> #include <i2c.h> +#include <malloc.h> +#include <asm/bitops.h> #include "gsc.h" #include "ventana_eeprom.h" @@ -38,14 +41,12 @@ read_eeprom(int bus, struct ventana_board_info *info) /* read eeprom config section */ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { puts("EEPROM: Failed to read EEPROM\n"); - info->model[0] = 0; return GW_UNKNOWN; } /* sanity checks */ if (info->model[0] != 'G' || info->model[1] != 'W') { puts("EEPROM: Invalid Model in EEPROM\n"); - info->model[0] = 0; return GW_UNKNOWN; } @@ -55,7 +56,6 @@ read_eeprom(int bus, struct ventana_board_info *info) if ((info->chksum[0] != chksum>>8) || (info->chksum[1] != (chksum&0xff))) { puts("EEPROM: Failed EEPROM checksum\n"); - info->model[0] = 0; return GW_UNKNOWN; } @@ -87,3 +87,165 @@ read_eeprom(int bus, struct ventana_board_info *info) } return type; } + +/* list of config bits that the bootloader will remove from dtb if not set */ +struct ventana_eeprom_config econfig[] = { + { "eth0", "ethernet0", EECONFIG_ETH0 }, + { "eth1", "ethernet1", EECONFIG_ETH1 }, + { "sata", "ahci0", EECONFIG_SATA }, + { "pcie", NULL, EECONFIG_PCIE}, + { "lvds0", NULL, EECONFIG_LVDS0 }, + { "lvds1", NULL, EECONFIG_LVDS1 }, + { "usb0", NULL, EECONFIG_USB0 }, + { "usb1", NULL, EECONFIG_USB1 }, + { "mmc0", NULL, EECONFIG_SD0 }, + { "mmc1", NULL, EECONFIG_SD1 }, + { "mmc2", NULL, EECONFIG_SD2 }, + { "mmc3", NULL, EECONFIG_SD3 }, + { "uart0", NULL, EECONFIG_UART0 }, + { "uart1", NULL, EECONFIG_UART1 }, + { "uart2", NULL, EECONFIG_UART2 }, + { "uart3", NULL, EECONFIG_UART3 }, + { "uart4", NULL, EECONFIG_UART4 }, + { "ipu0", NULL, EECONFIG_IPU0 }, + { "ipu1", NULL, EECONFIG_IPU1 }, + { "can0", NULL, EECONFIG_FLEXCAN }, + { "i2c0", NULL, EECONFIG_I2C0 }, + { "i2c1", NULL, EECONFIG_I2C1 }, + { "i2c2", NULL, EECONFIG_I2C2 }, + { "vpu", NULL, EECONFIG_VPU }, + { "csi0", NULL, EECONFIG_CSI0 }, + { "csi1", NULL, EECONFIG_CSI1 }, + { "spi0", NULL, EECONFIG_ESPCI0 }, + { "spi1", NULL, EECONFIG_ESPCI1 }, + { "spi2", NULL, EECONFIG_ESPCI2 }, + { "spi3", NULL, EECONFIG_ESPCI3 }, + { "spi4", NULL, EECONFIG_ESPCI4 }, + { "spi5", NULL, EECONFIG_ESPCI5 }, + { "gps", "pps", EECONFIG_GPS }, + { "hdmi_in", NULL, EECONFIG_HDMI_IN }, + { "hdmi_out", NULL, EECONFIG_HDMI_OUT }, + { "cvbs_in", NULL, EECONFIG_VID_IN }, + { "cvbs_out", NULL, EECONFIG_VID_OUT }, + { "nand", NULL, EECONFIG_NAND }, + { /* Sentinel */ } +}; + +#ifdef CONFIG_CMD_EECONFIG +static struct ventana_eeprom_config *get_config(const char *name) +{ + struct ventana_eeprom_config *cfg = econfig; + + while (cfg->name) { + if (0 == strcmp(name, cfg->name)) + return cfg; + cfg++; + } + return NULL; +} + +static u8 econfig_bytes[sizeof(ventana_info.config)]; +static int econfig_init = -1; + +int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct ventana_eeprom_config *cfg; + struct ventana_board_info *info = &ventana_info; + int i; + + if (argc < 2) + return CMD_RET_USAGE; + + /* initialize */ + if (econfig_init != 1) { + memcpy(econfig_bytes, info->config, sizeof(econfig_bytes)); + econfig_init = 1; + } + + /* list configs */ + if ((strncmp(argv[1], "list", 4) == 0)) { + cfg = econfig; + while (cfg->name) { + printf("%s: %d\n", cfg->name, + test_bit(cfg->bit, econfig_bytes) ? 1 : 0); + cfg++; + } + } + + /* save */ + else if ((strncmp(argv[1], "save", 4) == 0)) { + unsigned char *buf = (unsigned char *)info; + int chksum; + + /* calculate new checksum */ + memcpy(info->config, econfig_bytes, sizeof(econfig_bytes)); + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + debug("old chksum:0x%04x\n", + (info->chksum[0] << 8) | info->chksum[1]); + debug("new chksum:0x%04x\n", chksum); + info->chksum[0] = chksum >> 8; + info->chksum[1] = chksum & 0xff; + + /* write new config data */ + if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info, + 1, econfig_bytes, sizeof(econfig_bytes))) { + printf("EEPROM: Failed updating config\n"); + return CMD_RET_FAILURE; + } + + /* write new config data */ + if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info, + 1, info->chksum, 2)) { + printf("EEPROM: Failed updating checksum\n"); + return CMD_RET_FAILURE; + } + + printf("Config saved to EEPROM\n"); + } + + /* get config */ + else if (argc == 2) { + cfg = get_config(argv[1]); + if (cfg) { + printf("%s: %d\n", cfg->name, + test_bit(cfg->bit, econfig_bytes) ? 1 : 0); + } else { + printf("invalid config: %s\n", argv[1]); + return CMD_RET_FAILURE; + } + } + + /* set config */ + else if (argc == 3) { + cfg = get_config(argv[1]); + if (cfg) { + if (simple_strtol(argv[2], NULL, 10)) { + test_and_set_bit(cfg->bit, econfig_bytes); + printf("Enabled %s\n", cfg->name); + } else { + test_and_clear_bit(cfg->bit, econfig_bytes); + printf("Disabled %s\n", cfg->name); + } + } else { + printf("invalid config: %s\n", argv[1]); + return CMD_RET_FAILURE; + } + } + + else + return CMD_RET_USAGE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + econfig, 3, 0, do_econfig, + "EEPROM configuration", + "list - list config\n" + "save - save config to EEPROM\n" + "<name> - get config 'name'\n" + "<name> [0|1] - set config 'name' to value\n" +); + +#endif /* CONFIG_CMD_EECONFIG */ diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 37966ab..1cf38d4 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -57,7 +57,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) break; mdelay(10); } - mdelay(1); + mdelay(100); return ret; } diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9d2651f..a222921 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -50,10 +50,6 @@ DECLARE_GLOBAL_DATA_PTR; #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) -/* I2C bus numbers */ -#define I2C_GSC 0 -#define I2C_PMIC 1 - #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -78,11 +74,18 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) + + /* * EEPROM board info struct populated by read_eeprom so that we only have to * read it once. */ -static struct ventana_board_info ventana_info; +struct ventana_board_info ventana_info; int board_type; @@ -187,7 +190,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* CD */ - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), }; /* ENET */ @@ -211,7 +214,7 @@ iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* PHY nRST */ - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), }; /* NAND */ @@ -281,10 +284,10 @@ static void setup_iomux_uart(void) #ifdef CONFIG_USB_EHCI_MX6 iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), + IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), /* OTG PWR */ - IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), }; int board_ehci_hcd_init(int port) @@ -296,15 +299,13 @@ int board_ehci_hcd_init(int port) /* Reset USB HUB (present on GW54xx/GW53xx) */ switch (info->model[3]) { case '3': /* GW53xx */ - SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | - MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 9), 0); mdelay(2); gpio_set_value(IMX_GPIO_NR(1, 9), 1); break; case '4': /* GW54xx */ - SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | - MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 16), 0); mdelay(2); gpio_set_value(IMX_GPIO_NR(1, 16), 1); @@ -426,7 +427,7 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[2]); /* Enable Backlight */ - SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 18), 1); } @@ -523,7 +524,7 @@ static void setup_display(void) writel(reg, &iomux->gpr[3]); /* Backlight CABEN on LVDS connector */ - SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 10), 0); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -535,118 +536,128 @@ static void setup_display(void) /* common to add baseboards */ static iomux_v3_cfg_t const gw_gpio_pads[] = { /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), }; /* prototype */ static iomux_v3_cfg_t const gwproto_gpio_pads[] = { /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* GPS_SHDN */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), /* USBOTG_SEL */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* VID_PWR */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* MIPI_DIO */ - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), /* RS485_EN */ - IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; /* @@ -677,6 +688,7 @@ struct ventana { int dioi2c_en; int pcie_sson; int usb_sel; + int wdis; }; struct ventana gpio_cfg[] = { @@ -762,6 +774,7 @@ struct ventana gpio_cfg[] = { .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 2), .vidin_en = IMX_GPIO_NR(5, 20), + .wdis = IMX_GPIO_NR(7, 12), }, /* GW52xx */ @@ -805,6 +818,7 @@ struct ventana gpio_cfg[] = { .gps_shdn = IMX_GPIO_NR(1, 27), .vidin_en = IMX_GPIO_NR(3, 31), .usb_sel = IMX_GPIO_NR(1, 2), + .wdis = IMX_GPIO_NR(7, 12), }, /* GW53xx */ @@ -847,6 +861,7 @@ struct ventana gpio_cfg[] = { .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 27), .vidin_en = IMX_GPIO_NR(3, 31), + .wdis = IMX_GPIO_NR(7, 12), }, /* GW54xx */ @@ -891,6 +906,7 @@ struct ventana gpio_cfg[] = { .vidin_en = IMX_GPIO_NR(3, 31), .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), + .wdis = IMX_GPIO_NR(5, 17), }, }; @@ -902,8 +918,8 @@ int power_init_board(void) /* configure PFUZE100 PMIC */ if (board_type == GW54xx || board_type == GW54proto) { - power_pfuze100_init(I2C_PMIC); - p = pmic_get("PFUZE100_PMIC"); + power_pfuze100_init(CONFIG_I2C_PMIC); + p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { pmic_reg_read(p, PFUZE100_DEVICEID, ®); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); @@ -924,7 +940,7 @@ int power_init_board(void) /* configure LTC3676 PMIC */ else { - power_ltc3676_init(I2C_PMIC); + power_ltc3676_init(CONFIG_I2C_PMIC); p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { puts("PMIC: LTC3676\n"); @@ -975,12 +991,10 @@ static void setup_board_gpio(int board) gpio_direction_output(GP_MSATA_SEL, 0); } - /* - * assert PCI_RST# (released by OS when clock is valid) - * TODO: figure out why leaving this de-asserted from PCI scan on boot - * causes linux pcie driver to hang during enumeration - */ +#if !defined(CONFIG_CMD_PCI) + /* assert PCI_RST# (released by OS when clock is valid) */ gpio_direction_output(gpio_cfg[board].pcie_rst, 0); +#endif /* turn off (active-high) user LED's */ for (i = 0; i < 4; i++) { @@ -1016,21 +1030,27 @@ static void setup_board_gpio(int board) if (gpio_cfg[board].usb_sel) gpio_direction_output(gpio_cfg[board].usb_sel, 0); + /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ + if (gpio_cfg[board].wdis) + gpio_direction_output(gpio_cfg[board].wdis, 1); + /* * Configure DIO pinmux/padctl registers * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions */ for (i = 0; i < 4; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; - unsigned ctrl = DIO_PAD_CTRL; + iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; sprintf(arg, "dio%d", i); if (!hwconfig(arg)) continue; s = hwconfig_subarg(arg, "padctrl", &len); - if (s) - ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; + if (s) { + ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) + & 0x1ffff) | MUX_MODE_SION; + } if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { if (!quiet) { printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, @@ -1039,7 +1059,7 @@ static void setup_board_gpio(int board) cfg->gpio_param); } imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | - MUX_PAD_CTRL(ctrl)); + ctrl); gpio_direction_input(cfg->gpio_param); } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && cfg->pwm_padmux) { @@ -1122,8 +1142,7 @@ int dram_init(void) int board_init(void) { - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, @@ -1152,7 +1171,7 @@ int board_init(void) setup_sata(); #endif /* read Gateworks EEPROM into global struct (used later) */ - board_type = read_eeprom(I2C_GSC, &ventana_info); + board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); /* board-specifc GPIO iomux */ SETUP_IOMUX_PADS(gw_gpio_pads); @@ -1200,7 +1219,7 @@ int checkboard(void) return 0; /* Display GSC firmware revision/CRC/status */ - i2c_set_bus_num(I2C_GSC); + i2c_set_bus_num(CONFIG_I2C_GSC); if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { printf("GSC: v%d", buf[0]); if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { @@ -1264,6 +1283,10 @@ int misc_init_r(void) else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) cputype = "imx6dl"; + if (8 << (ventana_info.nand_flash_size-1) >= 2048) + setenv("flash_layout", "large"); + else + setenv("flash_layout", "normal"); memset(str, 0, sizeof(str)); for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) str[i] = tolower(info->model[i]); @@ -1326,7 +1349,7 @@ int misc_init_r(void) * * Disable the boot watchdog and display/clear the timeout flag if set */ - i2c_set_bus_num(I2C_GSC); + i2c_set_bus_num(CONFIG_I2C_GSC); if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { reg |= (1 << GSC_SC_CTRL1_WDDIS); if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) @@ -1336,7 +1359,7 @@ int misc_init_r(void) } if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ - puts("GSC boot watchdog timeout detected"); + puts("GSC boot watchdog timeout detected\n"); reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); } @@ -1347,74 +1370,6 @@ int misc_init_r(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -/* FDT aliases associated with EEPROM config bits */ -const char *fdt_aliases[] = { - "ethernet0", - "ethernet1", - "hdmi_out", - "ahci0", - "pcie", - "ssi0", - "ssi1", - "lcd0", - "lvds0", - "lvds1", - "usb0", - "usb1", - "mmc0", - "mmc1", - "mmc2", - "mmc3", - "uart0", - "uart1", - "uart2", - "uart3", - "uart4", - "ipu0", - "ipu1", - "can0", - "mipi_dsi", - "mipi_csi", - "tzasc0", - "tzasc1", - "i2c0", - "i2c1", - "i2c2", - "vpu", - "csi0", - "csi1", - "caam", - NULL, - NULL, - NULL, - NULL, - NULL, - "spi0", - "spi1", - "spi2", - "spi3", - "spi4", - "spi5", - NULL, - NULL, - "pps", - NULL, - NULL, - NULL, - "hdmi_in", - "cvbs_out", - "cvbs_in", - "nand", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, -}; - /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -1426,8 +1381,8 @@ const char *fdt_aliases[] = { */ void ft_board_setup(void *blob, bd_t *bd) { - int bit; struct ventana_board_info *info = &ventana_info; + struct ventana_eeprom_config *cfg; struct node_info nodes[] = { { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ @@ -1462,9 +1417,17 @@ void ft_board_setup(void *blob, bd_t *bd) * remove nodes by alias path if EEPROM config tells us the * peripheral is not loaded on the board. */ - for (bit = 0; bit < 64; bit++) { - if (!test_bit(bit, info->config)) - fdt_del_node_and_alias(blob, fdt_aliases[bit]); + if (getenv("fdt_noconfig")) { + puts(" Skiping periperhal config (fdt_noconfig defined)\n"); + return; + } + cfg = econfig; + while (cfg->name) { + if (!test_bit(cfg->bit, info->config)) { + fdt_del_node_and_alias(blob, cfg->dtalias ? + cfg->dtalias : cfg->name); + } + cfg++; } } #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index 5b065be..d64b910 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -110,8 +110,19 @@ enum { GW53xx, GW54xx, GW_UNKNOWN, + GW_BADCRC, }; +/* config items */ +struct ventana_eeprom_config { + const char *name; /* name of item */ + const char *dtalias; /* name of dt node to remove if not set */ + int bit; /* bit within config */ +}; + +extern struct ventana_eeprom_config econfig[]; +extern struct ventana_board_info ventana_info; + int read_eeprom(int bus, struct ventana_board_info *); #endif diff --git a/board/gumstix/duovero/Kconfig b/board/gumstix/duovero/Kconfig index d1b5c66..f662798 100644 --- a/board/gumstix/duovero/Kconfig +++ b/board/gumstix/duovero/Kconfig @@ -1,9 +1,5 @@ if TARGET_DUOVERO -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "duovero" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "gumstix" -config SYS_SOC - string - default "omap4" - config SYS_CONFIG_NAME string default "duovero" diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig index 1e2c679..343ff4d 100644 --- a/board/htkw/mcx/Kconfig +++ b/board/htkw/mcx/Kconfig @@ -1,9 +1,5 @@ if TARGET_MCX -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "mcx" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "htkw" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "mcx" diff --git a/board/iomega/iconnect/Kconfig b/board/iomega/iconnect/Kconfig index 8ac21d2..f75c06b 100644 --- a/board/iomega/iconnect/Kconfig +++ b/board/iomega/iconnect/Kconfig @@ -1,9 +1,5 @@ if TARGET_ICONNECT -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "iconnect" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "iomega" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "iconnect" diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig index c9f2969..c9352fd 100644 --- a/board/isee/igep00x0/Kconfig +++ b/board/isee/igep00x0/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_IGEP00X0 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "igep00x0" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "isee" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_igep00x0" diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig index 546491b..24071f6 100644 --- a/board/karo/tk71/Kconfig +++ b/board/karo/tk71/Kconfig @@ -1,9 +1,5 @@ if TARGET_TK71 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "tk71" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "karo" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "tk71" diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig index dec4626..3e9cddb 100644 --- a/board/keymile/km_arm/Kconfig +++ b/board/keymile/km_arm/Kconfig @@ -1,9 +1,5 @@ if TARGET_KM_KIRKWOOD -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "km_arm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "keymile" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "km_kirkwood" diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig index 2d40173..ab4812f 100644 --- a/board/kmc/kzm9g/Kconfig +++ b/board/kmc/kzm9g/Kconfig @@ -1,9 +1,5 @@ if TARGET_KZM9G -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "kzm9g" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "kmc" -config SYS_SOC - string - default "rmobile" - config SYS_CONFIG_NAME string default "kzm9g" diff --git a/board/logicpd/am3517evm/Kconfig b/board/logicpd/am3517evm/Kconfig index 9bc5ae5..1012d3d 100644 --- a/board/logicpd/am3517evm/Kconfig +++ b/board/logicpd/am3517evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_AM3517_EVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "am3517evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "logicpd" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "am3517_evm" diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig index daaefa6..adeaf4d 100644 --- a/board/logicpd/omap3som/Kconfig +++ b/board/logicpd/omap3som/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_LOGIC -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "omap3som" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "logicpd" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_logic" diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig index 3199130..e9a5623 100644 --- a/board/logicpd/zoom1/Kconfig +++ b/board/logicpd/zoom1/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_ZOOM1 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "zoom1" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "logicpd" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_zoom1" diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig index d89c1e3..69f0566 100644 --- a/board/matrix_vision/mvblx/Kconfig +++ b/board/matrix_vision/mvblx/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_MVBLX -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "mvblx" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "matrix_vision" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_mvblx" diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig index 41d0daa..faa90d2 100644 --- a/board/nokia/rx51/Kconfig +++ b/board/nokia/rx51/Kconfig @@ -1,9 +1,5 @@ if TARGET_NOKIA_RX51 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "rx51" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "nokia" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "nokia_rx51" diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig index f052676..e487b66 100644 --- a/board/nvidia/beaver/Kconfig +++ b/board/nvidia/beaver/Kconfig @@ -1,10 +1,5 @@ if TARGET_BEAVER -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "beaver" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra30" - config SYS_CONFIG_NAME string default "beaver" diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig index 9853114..150815f 100644 --- a/board/nvidia/cardhu/Kconfig +++ b/board/nvidia/cardhu/Kconfig @@ -1,10 +1,5 @@ if TARGET_CARDHU -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "cardhu" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra30" - config SYS_CONFIG_NAME string default "cardhu" diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig index 33b78db..9eed19c 100644 --- a/board/nvidia/dalmore/Kconfig +++ b/board/nvidia/dalmore/Kconfig @@ -1,10 +1,5 @@ if TARGET_DALMORE -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "dalmore" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra114" - config SYS_CONFIG_NAME string default "dalmore" diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig index 2a3bde4..7d75f2d 100644 --- a/board/nvidia/harmony/Kconfig +++ b/board/nvidia/harmony/Kconfig @@ -1,10 +1,5 @@ if TARGET_HARMONY -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "harmony" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "harmony" diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig index 22b4c69..02b46b7 100644 --- a/board/nvidia/jetson-tk1/Kconfig +++ b/board/nvidia/jetson-tk1/Kconfig @@ -1,10 +1,5 @@ if TARGET_JETSON_TK1 -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "jetson-tk1" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra124" - config SYS_CONFIG_NAME string default "jetson-tk1" diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig index 39c65b5..7863702 100644 --- a/board/nvidia/seaboard/Kconfig +++ b/board/nvidia/seaboard/Kconfig @@ -1,10 +1,5 @@ if TARGET_SEABOARD -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "seaboard" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "seaboard" diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig index 84a7160..993da79 100644 --- a/board/nvidia/venice2/Kconfig +++ b/board/nvidia/venice2/Kconfig @@ -1,10 +1,5 @@ if TARGET_VENICE2 -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "venice2" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra124" - config SYS_CONFIG_NAME string default "venice2" diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h index a7b2403..06c366e 100644 --- a/board/nvidia/venice2/as3722_init.h +++ b/board/nvidia/venice2/as3722_init.h @@ -18,7 +18,7 @@ #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ #define AS3722_LDCONTROL_REG 0x4E -#ifdef CONFIG_BOARD_JETSON_TK1 +#ifdef CONFIG_TARGET_JETSON_TK1 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) #else #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig index 59e85c4..95840a8 100644 --- a/board/nvidia/ventana/Kconfig +++ b/board/nvidia/ventana/Kconfig @@ -1,10 +1,5 @@ if TARGET_VENTANA -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "ventana" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "ventana" diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig index f025413..113e2ef 100644 --- a/board/nvidia/whistler/Kconfig +++ b/board/nvidia/whistler/Kconfig @@ -1,10 +1,5 @@ if TARGET_WHISTLER -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "whistler" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "nvidia" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "whistler" diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig index 923af8a..46e95d8 100644 --- a/board/omicron/calimain/Kconfig +++ b/board/omicron/calimain/Kconfig @@ -1,9 +1,5 @@ if TARGET_CALIMAIN -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "calimain" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "omicron" -config SYS_SOC - string - default "davinci" - config SYS_CONFIG_NAME string default "calimain" diff --git a/board/overo/Kconfig b/board/overo/Kconfig index 1d4a261..d1ea236 100644 --- a/board/overo/Kconfig +++ b/board/overo/Kconfig @@ -1,17 +1,9 @@ if TARGET_OMAP3_OVERO -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "overo" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_overo" diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig index a36c0c8..6f41005 100644 --- a/board/pandora/Kconfig +++ b/board/pandora/Kconfig @@ -1,17 +1,9 @@ if TARGET_OMAP3_PANDORA -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "pandora" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_pandora" diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 50e8d82..5427de5 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -93,6 +93,7 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; @@ -103,6 +104,7 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len return 0; } +#endif static int alpr_nand_dev_ready(struct mtd_info *mtd) { @@ -128,7 +130,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_byte = alpr_nand_read_byte; nand->write_buf = alpr_nand_write_buf; nand->read_buf = alpr_nand_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = alpr_nand_verify_buf; +#endif nand->dev_ready = alpr_nand_dev_ready; return 0; diff --git a/board/raidsonic/ib62x0/Kconfig b/board/raidsonic/ib62x0/Kconfig index 1e667c4..c0c3a93 100644 --- a/board/raidsonic/ib62x0/Kconfig +++ b/board/raidsonic/ib62x0/Kconfig @@ -1,9 +1,5 @@ if TARGET_IB62X0 -config SYS_CPU - string - default "arm926ejs" - config SYS_BOARD string default "ib62x0" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "raidsonic" -config SYS_SOC - string - default "kirkwood" - config SYS_CONFIG_NAME string default "ib62x0" diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig index d317025..dc01a38 100644 --- a/board/renesas/alt/Kconfig +++ b/board/renesas/alt/Kconfig @@ -1,9 +1,5 @@ if TARGET_ALT -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "alt" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "renesas" -config SYS_SOC - string - default "rmobile" - config SYS_CONFIG_NAME string default "alt" diff --git a/board/renesas/koelsch/Kconfig b/board/renesas/koelsch/Kconfig index 0def847..e7c6437 100644 --- a/board/renesas/koelsch/Kconfig +++ b/board/renesas/koelsch/Kconfig @@ -1,9 +1,5 @@ if TARGET_KOELSCH -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "koelsch" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "renesas" -config SYS_SOC - string - default "rmobile" - config SYS_CONFIG_NAME string default "koelsch" diff --git a/board/renesas/lager/Kconfig b/board/renesas/lager/Kconfig index e88f4f6..07dc98c 100644 --- a/board/renesas/lager/Kconfig +++ b/board/renesas/lager/Kconfig @@ -1,9 +1,5 @@ if TARGET_LAGER -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "lager" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "renesas" -config SYS_SOC - string - default "rmobile" - config SYS_CONFIG_NAME string default "lager" diff --git a/board/samsung/arndale/Kconfig b/board/samsung/arndale/Kconfig index c3af0ec..5fdbacb 100644 --- a/board/samsung/arndale/Kconfig +++ b/board/samsung/arndale/Kconfig @@ -1,9 +1,5 @@ if TARGET_ARNDALE -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "arndale" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "arndale" diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index ef88314..83fd3bd 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -117,3 +117,13 @@ int checkboard(void) return 0; } #endif + +#ifdef CONFIG_S5P_PA_SYSRAM +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + writel(addr, CONFIG_S5P_PA_SYSRAM); + + /* make sure this write is really executed */ + __asm__ volatile ("dsb\n"); +} +#endif diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index b22f9e0..4a933c8 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -21,6 +21,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram diff --git a/board/samsung/origen/Kconfig b/board/samsung/origen/Kconfig index f52de83..3eda350 100644 --- a/board/samsung/origen/Kconfig +++ b/board/samsung/origen/Kconfig @@ -1,9 +1,5 @@ if TARGET_ORIGEN -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "origen" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "origen" diff --git a/board/samsung/smdk5250/Kconfig b/board/samsung/smdk5250/Kconfig index edebbde..e7036f5 100644 --- a/board/samsung/smdk5250/Kconfig +++ b/board/samsung/smdk5250/Kconfig @@ -1,9 +1,5 @@ if TARGET_SMDK5250 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "smdk5250" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "smdk5250" @@ -24,10 +16,6 @@ endif if TARGET_SNOW -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "smdk5250" @@ -36,10 +24,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "snow" diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index 052c275..fb9bedd 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,9 +1,5 @@ if TARGET_PEACH_PIT -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "smdk5420" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "peach-pit" @@ -24,10 +16,6 @@ endif if TARGET_SMDK5420 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "smdk5420" @@ -36,10 +24,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "smdk5420" diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig index e467092..785fae2 100644 --- a/board/samsung/smdkv310/Kconfig +++ b/board/samsung/smdkv310/Kconfig @@ -1,9 +1,5 @@ if TARGET_SMDKV310 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "smdkv310" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "smdkv310" diff --git a/board/samsung/trats/Kconfig b/board/samsung/trats/Kconfig index 040413e..8bfb12d 100644 --- a/board/samsung/trats/Kconfig +++ b/board/samsung/trats/Kconfig @@ -1,9 +1,5 @@ if TARGET_TRATS -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "trats" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "trats" diff --git a/board/samsung/trats2/Kconfig b/board/samsung/trats2/Kconfig index a82fdfb..f359c03 100644 --- a/board/samsung/trats2/Kconfig +++ b/board/samsung/trats2/Kconfig @@ -1,9 +1,5 @@ if TARGET_TRATS2 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "trats2" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "trats2" diff --git a/board/samsung/universal_c210/Kconfig b/board/samsung/universal_c210/Kconfig index 082168f..72b879a 100644 --- a/board/samsung/universal_c210/Kconfig +++ b/board/samsung/universal_c210/Kconfig @@ -1,9 +1,5 @@ if TARGET_S5PC210_UNIVERSAL -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "universal_c210" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "samsung" -config SYS_SOC - string - default "exynos" - config SYS_CONFIG_NAME string default "s5pc210_universal" diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 3802c7e..7394478 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -18,7 +18,9 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); static u_char sc_nand_read_byte(struct mtd_info *mtd); static u16 sc_nand_read_word(struct mtd_info *mtd); static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); +#endif static int sc_nand_device_ready(struct mtd_info *mtdinfo); #define FPGA_NAND_CMD_MASK (0x7 << 28) @@ -100,6 +102,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /** * sc_nand_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -116,6 +119,7 @@ static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) } return 0; } +#endif /** * sc_nand_device_ready - Check the NAND device is ready for next command. @@ -174,7 +178,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_word = sc_nand_read_word; nand->write_buf = sc_nand_write_buf; nand->read_buf = sc_nand_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = sc_nand_verify_buf; +#endif return 0; } diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c index 2e2fb2a..6d204b3 100644 --- a/board/solidrun/hummingboard/hummingboard.c +++ b/board/solidrun/hummingboard/hummingboard.c @@ -144,8 +144,7 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { - struct iomuxc_base_regs *const iomuxc_regs = - (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret = enable_fec_anatop_clock(ENET_25MHz); if (ret) diff --git a/board/st/nhk8815/Kconfig b/board/st/nhk8815/Kconfig index ec3f880..ba2e7c2 100644 --- a/board/st/nhk8815/Kconfig +++ b/board/st/nhk8815/Kconfig @@ -1,8 +1,4 @@ -if TARGET_NHK8815 - -config SYS_CPU - string - default "arm926ejs" +if NOMADIK_NHK8815 config SYS_BOARD string @@ -12,10 +8,6 @@ config SYS_VENDOR string default "st" -config SYS_SOC - string - default "nomadik" - config SYS_CONFIG_NAME string default "nhk8815" diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b06b5e0..c61c650 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -1,17 +1,5 @@ if TARGET_SUN4I -config SYS_CPU - string - default "armv7" - -config SYS_BOARD - string - default "sunxi" - -config SYS_SOC - string - default "sunxi" - config SYS_CONFIG_NAME string default "sun4i" @@ -20,25 +8,21 @@ endif if TARGET_SUN5I -config SYS_CPU +config SYS_CONFIG_NAME string - default "armv7" + default "sun5i" -config SYS_BOARD - string - default "sunxi" +endif -config SYS_SOC - string - default "sunxi" +if TARGET_SUN7I config SYS_CONFIG_NAME string - default "sun5i" + default "sun7i" endif -if TARGET_SUN7I +if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I config SYS_CPU string @@ -52,8 +36,7 @@ config SYS_SOC string default "sunxi" -config SYS_CONFIG_NAME - string - default "sun7i" +config FTDFILE + string "Default ftdfile env setting for this board" endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1a56608..b0b1804 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -2,11 +2,26 @@ SUNXI BOARD M: Hans de Goede <hdegoede@redhat.com> S: Maintained F: board/sunxi/ -F: include/configs/sun5i.h -F: configs/A13-OLinuXinoM_defconfig F: include/configs/sun4i.h +F: configs/A10-OLinuXino-Lime_defconfig +F: configs/ba10_tv_box_defconfig F: configs/Cubieboard_defconfig +F: configs/Mele_A1000_defconfig +F: configs/Mele_A1000G_defconfig +F: configs/Mini-X_defconfig +F: configs/Mini-X-1Gb_defconfig +F: include/configs/sun5i.h +F: configs/A10s-OLinuXino-M_defconfig +F: configs/A13-OLinuXino_defconfig +F: configs/A13-OLinuXinoM_defconfig +F: configs/Auxtek-T004_defconfig F: configs/r7-tv-dongle_defconfig +F: include/configs/sun7i.h +F: configs/A20-OLinuXino_MICRO_defconfig +F: configs/Bananapi_defconfig +F: configs/i12-tvbox_defconfig +F: configs/Linksprite_pcDuino3_defconfig +F: configs/qt840a_defconfig CUBIEBOARD2 BOARD M: Ian Campbell <ijc@hellion.org.uk> diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 62acb8f..cf001e7 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,8 +10,24 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_SUNXI_AHCI) += ahci.o +obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o +obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o +obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o +obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o +# This is not a typo, uses the same mem settings as the a10s-olinuxino-m +obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o +obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o +obj-$(CONFIG_BANANAPI) += dram_bananapi.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o +obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o +obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o +obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o +obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o +obj-$(CONFIG_QT840A) += dram_sun7i_384_512_busw16_iow16.o obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c new file mode 100644 index 0000000..0c262ea --- /dev/null +++ b/board/sunxi/ahci.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <ahci.h> +#include <scsi.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#define AHCI_PHYCS0R 0x00c0 +#define AHCI_PHYCS1R 0x00c4 +#define AHCI_PHYCS2R 0x00c8 +#define AHCI_RWCR 0x00fc + +/* This magic PHY initialisation was taken from the Allwinner releases + * and Linux driver, but is completely undocumented. + */ +static int sunxi_ahci_phy_init(u32 base) +{ + u8 *reg_base = (u8 *)base; + u32 reg_val; + int timeout; + + writel(0, reg_base + AHCI_RWCR); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, + (0x7 << 24), + (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); + clrsetbits_le32(reg_base + AHCI_PHYCS1R, + (0x3 << 16) | (0x1f << 8) | (0x3 << 6), + (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); + setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); + clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); + clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + + timeout = 250; /* Power up takes approx 50 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); + if (reg_val == (0x2 << 28)) + break; + if (--timeout == 0) { + printf("AHCI PHY power up failed.\n"); + return -EIO; + } + udelay(1); + }; + + setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + + timeout = 100; /* Calibration takes approx 10 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); + if (reg_val == 0x0) + break; + if (--timeout == 0) { + printf("AHCI PHY calibration failed.\n"); + return -EIO; + } + udelay(1); + } + + mdelay(15); + + writel(0x7, reg_base + AHCI_RWCR); + + return 0; +} + +void scsi_init(void) +{ + printf("SUNXI SCSI INIT\n"); +#ifdef CONFIG_SATAPWR + gpio_direction_output(CONFIG_SATAPWR, 1); +#endif + + if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) + return; + + ahci_init(SUNXI_SATA_BASE); +} diff --git a/board/sunxi/dram_a10_olinuxino_l.c b/board/sunxi/dram_a10_olinuxino_l.c new file mode 100644 index 0000000..24a1bd9 --- /dev/null +++ b/board/sunxi/dram_a10_olinuxino_l.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 16, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 512, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_a10s_olinuxino_m.c b/board/sunxi/dram_a10s_olinuxino_m.c new file mode 100644 index 0000000..8900539 --- /dev/null +++ b/board/sunxi/dram_a10s_olinuxino_m.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 432, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 16, + .cas = 9, + .zq = 123, + .odt_en = 0, + .size = 512, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_a13_olinuxino.c b/board/sunxi/dram_a13_olinuxino.c new file mode 100644 index 0000000..ca96260 --- /dev/null +++ b/board/sunxi/dram_a13_olinuxino.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 408, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 8, + .bus_width = 16, + .cas = 9, + .zq = 123, + .odt_en = 0, + .size = 512, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_bananapi.c b/board/sunxi/dram_bananapi.c new file mode 100644 index 0000000..0ed7943 --- /dev/null +++ b/board/sunxi/dram_bananapi.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 432, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0x0, + .tpr4 = 0x1, + .tpr5 = 0x0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_linksprite_pcduino3.c b/board/sunxi/dram_linksprite_pcduino3.c new file mode 100644 index 0000000..9cc6e19 --- /dev/null +++ b/board/sunxi/dram_linksprite_pcduino3.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7a, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun4i_360_1024_iow16.c b/board/sunxi/dram_sun4i_360_1024_iow16.c new file mode 100644 index 0000000..3763713 --- /dev/null +++ b/board/sunxi/dram_sun4i_360_1024_iow16.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 360, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun4i_360_1024_iow8.c b/board/sunxi/dram_sun4i_360_1024_iow8.c new file mode 100644 index 0000000..2a5c9ed --- /dev/null +++ b/board/sunxi/dram_sun4i_360_1024_iow8.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 360, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 8, + .bus_width = 32, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun4i_360_512.c b/board/sunxi/dram_sun4i_360_512.c new file mode 100644 index 0000000..48aa6e2 --- /dev/null +++ b/board/sunxi/dram_sun4i_360_512.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 360, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 16, + .bus_width = 32, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 512, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun4i_384_1024_iow8.c b/board/sunxi/dram_sun4i_384_1024_iow8.c new file mode 100644 index 0000000..b0fcc55 --- /dev/null +++ b/board/sunxi/dram_sun4i_384_1024_iow8.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 384, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 8, + .bus_width = 32, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun7i_384_1024_iow16.c b/board/sunxi/dram_sun7i_384_1024_iow16.c new file mode 100644 index 0000000..04e4b1e --- /dev/null +++ b/board/sunxi/dram_sun7i_384_1024_iow16.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include "common.h" +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 384, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun7i_384_512_busw16_iow16.c b/board/sunxi/dram_sun7i_384_512_busw16_iow16.c new file mode 100644 index 0000000..2e36011 --- /dev/null +++ b/board/sunxi/dram_sun7i_384_512_busw16_iow16.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include "common.h" +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 384, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 16, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 512, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/technexion/tao3530/Kconfig b/board/technexion/tao3530/Kconfig index 06e56a4..910a9cd 100644 --- a/board/technexion/tao3530/Kconfig +++ b/board/technexion/tao3530/Kconfig @@ -1,9 +1,5 @@ if TARGET_TAO3530 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "tao3530" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "technexion" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "tao3530" diff --git a/board/technexion/twister/Kconfig b/board/technexion/twister/Kconfig index 1790f6d..e6f811a 100644 --- a/board/technexion/twister/Kconfig +++ b/board/technexion/twister/Kconfig @@ -1,9 +1,5 @@ if TARGET_TWISTER -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "twister" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "technexion" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "twister" diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig index 96cf7c0..a567204 100644 --- a/board/teejet/mt_ventoux/Kconfig +++ b/board/teejet/mt_ventoux/Kconfig @@ -1,9 +1,5 @@ if TARGET_MT_VENTOUX -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "mt_ventoux" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "teejet" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "mt_ventoux" diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index c3b61af..0e5149c 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -20,4 +20,13 @@ config SYS_CONFIG_NAME string default "am335x_evm" +config CONS_INDEX + int "UART used for console" + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index d81eec9..0739e60 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -383,24 +383,19 @@ const struct dpll_params *get_dpll_ddr_params(void) void set_uart_mux_conf(void) { -#ifdef CONFIG_SERIAL1 +#if CONFIG_CONS_INDEX == 1 enable_uart0_pin_mux(); -#endif /* CONFIG_SERIAL1 */ -#ifdef CONFIG_SERIAL2 +#elif CONFIG_CONS_INDEX == 2 enable_uart1_pin_mux(); -#endif /* CONFIG_SERIAL2 */ -#ifdef CONFIG_SERIAL3 +#elif CONFIG_CONS_INDEX == 3 enable_uart2_pin_mux(); -#endif /* CONFIG_SERIAL3 */ -#ifdef CONFIG_SERIAL4 +#elif CONFIG_CONS_INDEX == 4 enable_uart3_pin_mux(); -#endif /* CONFIG_SERIAL4 */ -#ifdef CONFIG_SERIAL5 +#elif CONFIG_CONS_INDEX == 5 enable_uart4_pin_mux(); -#endif /* CONFIG_SERIAL5 */ -#ifdef CONFIG_SERIAL6 +#elif CONFIG_CONS_INDEX == 6 enable_uart5_pin_mux(); -#endif /* CONFIG_SERIAL6 */ +#endif } void set_mux_conf_regs(void) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index b2bfda5..f4bb9f8 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,91 +171,75 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +#ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; - -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#elif defined(CONFIG_NOR) static struct module_pin_mux bone_norcape_pin_mux[] = { - {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ - {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ - {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ - {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ - {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ - {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ - {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ - {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ - {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ - {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ - {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ - {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ - {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ - {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ - {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ - {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ - {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ - {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ - {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ - {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ - {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ - {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ - {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ - {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ - {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ - {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ - {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ - {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ - {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ - {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ - {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ - {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ - {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ - {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ - {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ - {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ - - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ + {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ + {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ + {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ + {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ + {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ + {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ + {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ + {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ + {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ + {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ + {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ + {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ + {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ + {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ {-1}, }; #endif #if defined(CONFIG_NOR_BOOT) -static struct module_pin_mux norboot_pin_mux[] = { - {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, - {-1}, -}; - void enable_norboot_pin_mux(void) { - configure_module_pin_mux(norboot_pin_mux); + configure_module_pin_mux(bone_norcape_pin_mux); } #endif @@ -336,11 +320,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); -#ifndef CONFIG_NOR - configure_module_pin_mux(mmc1_pin_mux); -#endif -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); +#else + configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ @@ -351,19 +336,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) configure_module_pin_mux(nand_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } } else if (board_is_idk(header)) { - /* - * Industrial Motor Control (IDK) - * note: IDK console is on UART3 by default. - * So u-boot mus be build with CONFIG_SERIAL4 and - * CONFIG_CONS_INDEX=4 - */ + /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); } else if (board_is_evm_sk(header)) { @@ -377,7 +359,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); +#endif } else { puts("Unknown board, cannot configure pinmux."); hang(); diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig index fdb20ab..c44dab5 100644 --- a/board/ti/am3517crane/Kconfig +++ b/board/ti/am3517crane/Kconfig @@ -1,9 +1,5 @@ if TARGET_AM3517_CRANE -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "am3517crane" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "am3517_crane" diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51fa9e0..a1c3c17 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -626,6 +626,7 @@ int board_init(void) modena_init0_bw_integer, modena_init0_watermark_0; gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); /* Clear all important bits for DSS errata that may need to be tweaked*/ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 50967e1..a670b0b 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -73,7 +73,38 @@ static struct module_pin_mux gpio5_7_pin_mux[] = { {-1}, }; -static struct module_pin_mux qspi_pin_mux[] = { +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */ + {-1}, +}; +#endif + +static __maybe_unused struct module_pin_mux qspi_pin_mux[] = { {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ @@ -97,12 +128,22 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif } else if (board_is_sk()) { configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + printf("Error: NAND flash not present on this board\n"); +#endif configure_module_pin_mux(qspi_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#else configure_module_pin_mux(qspi_pin_mux); +#endif } } diff --git a/board/ti/beagle/Kconfig b/board/ti/beagle/Kconfig index 15dccdf..10c81c2 100644 --- a/board/ti/beagle/Kconfig +++ b/board/ti/beagle/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_BEAGLE -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "beagle" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_beagle" diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig index 4b13ef4..9ee13c5 100644 --- a/board/ti/dra7xx/Kconfig +++ b/board/ti/dra7xx/Kconfig @@ -1,9 +1,5 @@ if TARGET_DRA7XX_EVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "dra7xx" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap5" - config SYS_CONFIG_NAME string default "dra7xx_evm" diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index ae50d88..5592fc5 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -13,6 +13,8 @@ #include <common.h> #include <palmas.h> #include <sata.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -26,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; +/* GPIO 7_11 */ +#define GPIO_DDR_VTT_EN 203 + const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; @@ -272,3 +277,29 @@ int board_eth_init(bd_t *bis) return ret; } #endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +/* VTT regulator enable */ +static inline void vtt_regulator_enable(void) +{ + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + /* Do not enable VTT for DRA722 */ + if (omap_revision() == DRA722_ES1_0) + return; + + /* + * EVM Rev G and later use gpio7_11 for DDR3 termination. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); +} + +int board_early_init_f(void) +{ + vtt_regulator_enable(); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7db7032..7276014 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ +#if defined(CONFIG_NOR) + /* NOR only pin-mux */ + {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ + {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ + {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ + {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ + {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ + {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ + {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ + {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ + {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ + {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ + {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ + {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ + {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ + {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ + {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ + {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ + {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ + {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ + {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ + {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ + {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ + {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ + {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ + {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ + {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ + {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ + {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ +#else + /* eMMC pinmux */ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ @@ -31,6 +62,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ +#endif #if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ @@ -68,6 +100,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {VIN2A_D21, (IEN | M3)}, {VIN2A_D22, (IEN | M3)}, {VIN2A_D23, (IEN | M3)}, +#if defined(CONFIG_NAND) || defined(CONFIG_NOR) + /* NAND / NOR pin-mux */ + {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ + {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ + {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ + {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ + {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ + {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ + {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ + {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ + {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ + {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ + {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ + {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ + {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ + {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ + {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ + {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ + {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ + {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ + {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ + {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ + {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ + {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ + /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ +#else + /* QSPI pin-mux */ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ @@ -78,6 +137,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ +#endif /* CONFIG_NAND || CONFIG_NOR */ {USB2_DRVVBUS, (M0 | IEN | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig index e342942..c54ce33 100644 --- a/board/ti/evm/Kconfig +++ b/board/ti/evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_EVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_evm" @@ -24,10 +16,6 @@ endif if TARGET_OMAP3_EVM_QUICK_MMC -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "evm" @@ -36,10 +24,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_evm_quick_mmc" @@ -48,10 +32,6 @@ endif if TARGET_OMAP3_EVM_QUICK_NAND -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "evm" @@ -60,10 +40,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_evm_quick_nand" diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 7890b30..3108782 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -1,9 +1,5 @@ if TARGET_K2E_EVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "ks2_evm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "keystone" - config SYS_CONFIG_NAME string default "k2e_evm" @@ -24,10 +16,6 @@ endif if TARGET_K2HK_EVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "ks2_evm" @@ -36,10 +24,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "keystone" - config SYS_CONFIG_NAME string default "k2hk_evm" diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index d2499b7..5472a43 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = { [usb_clk] = 100000000, }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1200, - PASS_PLL_1000, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_800, + CORE_PLL_850, + CORE_PLL_1000, + CORE_PLL_1250, + CORE_PLL_1350, + CORE_PLL_1400, + CORE_PLL_1500, }; + +static struct pll_init_data pa_pll_config = + PASS_PLL_1000; + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + return 0; } #endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index a369d6b..6fb3d21 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/emac_defs.h> @@ -28,12 +29,23 @@ unsigned int external_clk[ext_clk_count] = { [rp1_clk] = 123456789 }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1228, - PASS_PLL_983, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_999, + CORE_PLL_1200, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_800, + TETRIS_PLL_1000, TETRIS_PLL_1200, + TETRIS_PLL_1350, + TETRIS_PLL_1400, }; +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -75,7 +87,16 @@ int get_num_eth_ports(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + return 0; } #endif diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig index 7c7d5dc..3592e7b 100644 --- a/board/ti/omap5_uevm/Kconfig +++ b/board/ti/omap5_uevm/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP5_UEVM -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "omap5_uevm" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap5" - config SYS_CONFIG_NAME string default "omap5_uevm" diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig index be1307d..b69218b 100644 --- a/board/ti/panda/Kconfig +++ b/board/ti/panda/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP4_PANDA -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "panda" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap4" - config SYS_CONFIG_NAME string default "omap4_panda" diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig index 81989b7..fcf7329 100644 --- a/board/ti/sdp3430/Kconfig +++ b/board/ti/sdp3430/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP3_SDP3430 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "sdp3430" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "omap3_sdp3430" diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig index 140e1f1..9c1d8fe 100644 --- a/board/ti/sdp4430/Kconfig +++ b/board/ti/sdp4430/Kconfig @@ -1,9 +1,5 @@ if TARGET_OMAP4_SDP4430 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "sdp4430" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "ti" -config SYS_SOC - string - default "omap4" - config SYS_CONFIG_NAME string default "omap4_sdp4430" diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig index d9c920c..d1603f4 100644 --- a/board/timll/devkit8000/Kconfig +++ b/board/timll/devkit8000/Kconfig @@ -1,9 +1,5 @@ if TARGET_DEVKIT8000 -config SYS_CPU - string - default "armv7" - config SYS_BOARD string default "devkit8000" @@ -12,10 +8,6 @@ config SYS_VENDOR string default "timll" -config SYS_SOC - string - default "omap3" - config SYS_CONFIG_NAME string default "devkit8000" diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20_iris/Kconfig index 334b7e0..cccdd58 100644 --- a/board/toradex/colibri_t20_iris/Kconfig +++ b/board/toradex/colibri_t20_iris/Kconfig @@ -1,10 +1,5 @@ if TARGET_COLIBRI_T20_IRIS -config SYS_CPU - string - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - config SYS_BOARD string default "colibri_t20_iris" @@ -13,10 +8,6 @@ config SYS_VENDOR string default "toradex" -config SYS_SOC - string - default "tegra20" - config SYS_CONFIG_NAME string default "colibri_t20_iris" diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig new file mode 100644 index 0000000..ea6c08a --- /dev/null +++ b/board/toradex/colibri_t30/Kconfig @@ -0,0 +1,15 @@ +if TARGET_COLIBRI_T30 + +config SYS_BOARD + string + default "colibri_t30" + +config SYS_VENDOR + string + default "toradex" + +config SYS_CONFIG_NAME + string + default "colibri_t30" + +endif diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS new file mode 100644 index 0000000..73b8e5d --- /dev/null +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -0,0 +1,7 @@ +Colibri T30 +M: Stefan Agner <stefan.agner@toradex.com> +S: Maintained +F: board/toradex/colibri_t30/ +F: include/configs/colibri_t30.h +F: configs/colibri_t30_defconfig +F: arch/arm/dts/tegra30-colibri.dtb diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile new file mode 100644 index 0000000..3d58a4b --- /dev/null +++ b/board/toradex/colibri_t30/Makefile @@ -0,0 +1,6 @@ +# Copyright (c) 2013-2014 Stefan Agner +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += colibri_t30.o diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c new file mode 100644 index 0000000..ed043f4 --- /dev/null +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2014 + * Stefan Agner <stefan@agner.ch> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include "pinmux-config-colibri_t30.h" +#include <i2c.h> +#include <asm/gpio.h> + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_pinmux_common, + ARRAY_SIZE(tegra3_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(colibri_t30_padctrl, + ARRAY_SIZE(colibri_t30_padctrl)); +} + +/* + * Enable AX88772B USB to LAN controller + */ +void pin_mux_usb(void) +{ + /* Reset ASIX using LAN_RESET */ + gpio_request(GPIO_PDD0, NULL); + gpio_direction_output(GPIO_PDD0, 0); + udelay(5); + gpio_set_value(GPIO_PDD0, 1); +} diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h new file mode 100644 index 0000000..4e73c07 --- /dev/null +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2013-2014, Stefan Agner + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_ +#define _PINMUX_CONFIG_COLIBRI_T30_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra3_pinmux_common[] = { + /* SDMMC1 disabled */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux (eMMC) */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + DEFAULT_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT), + + /* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + /* UARTA RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT), + + + /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */ + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, TRISTATE, INPUT), + + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), + + /* SDMMC2 pinmux */ + DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + /* LAN_RESET */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + + /* LAN_VBUS */ + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* GPIOs */ + /* SDMMC1 CD gpio */ + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + /* SDMMC1 WP gpio */ + LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* Touch panel GPIO */ + /* Touch IRQ */ + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), + + /* Touch RESET */ + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), + + /* Power rails GPIO */ + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config colibri_t30_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_COLIBRI_T30_H_ */ diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c index 4925b8d..7fb2dfa 100644 --- a/board/tqc/tqm8272/nand.c +++ b/board/tqc/tqm8272/nand.c @@ -188,6 +188,7 @@ static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int *base = buf[i]; } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; @@ -199,6 +200,7 @@ static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int return -1; return 0; } +#endif #endif /* #ifndef CONFIG_NAND_SPL */ void board_nand_select_device(struct nand_chip *nand, int chip) @@ -247,8 +249,10 @@ int board_nand_init(struct nand_chip *nand) #ifndef CONFIG_NAND_SPL nand->write_buf = tqm8272_write_buf; nand->read_buf = tqm8272_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = tqm8272_verify_buf; #endif +#endif /* * Select required NAND chip diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig new file mode 100644 index 0000000..44b4142 --- /dev/null +++ b/board/tqc/tqma6/Kconfig @@ -0,0 +1,23 @@ +if TARGET_TQMA6 + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "tqma6" + +config SYS_VENDOR + string + default "tqc" + +config SYS_SOC + string + default "mx6" + +config SYS_CONFIG_NAME + string + default "tqma6" + +endif diff --git a/board/tqc/tqma6/MAINTAINERS b/board/tqc/tqma6/MAINTAINERS new file mode 100644 index 0000000..91cd244 --- /dev/null +++ b/board/tqc/tqma6/MAINTAINERS @@ -0,0 +1,6 @@ +TQ SYSTEMS TQMA6 BOARD +M: Markus Niebel <Markus.Niebel@tq-group.com> +S: Maintained +F: board/tqc/tqma6/ +F: include/configs/tqma6.h +F: configs/tqma6*_defconfig diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile new file mode 100644 index 0000000..9ee6920 --- /dev/null +++ b/board/tqc/tqma6/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tqma6.o + +obj-$(CONFIG_MBA6) += tqma6_mba6.o diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README new file mode 100644 index 0000000..2c012e7 --- /dev/null +++ b/board/tqc/tqma6/README @@ -0,0 +1,35 @@ +U-Boot for the TQ Systems TQMa6 modules + +This file contains information for the port of +U-Boot to the TQ Systems TQMa6 modules. + +1. Boot source +-------------- + +The following boot source is supported: + +- SD/eMMC +- SPI NOR + +2. Building +------------ + +To build U-Boot for the TQ Systems TQMa6 modules: + + make tqma6<x>_<baseboard>_<boot>_config + make + +x is a placeholder for the CPU variant +q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +s - means i.MX6S: TQMa6S (i.MX6S) + +baseboard is a placeholder for the boot device +mmc - means eMMC +spi - mean SPI NOR + +This gives the following configurations: + +tqma6q_mba6_mmc_config +tqma6q_mba6_spi_config +tqma6s_mba6_mmc_config +tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg new file mode 100644 index 0000000..d9dd273 --- /dev/null +++ b/board/tqc/tqma6/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c new file mode 100644 index 0000000..b552bb8 --- /dev/null +++ b/board/tqc/tqma6/tqma6.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel <markus.niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <libfdt.h> +#include <i2c.h> +#include <mmc.h> +#include <power/pfuze100_pmic.h> +#include <power/pmic.h> + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static const uint16_t tqma6_emmc_dsr = 0x0100; + +/* eMMC on USDHCI3 always present */ +static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), + /* eMMC reset */ + NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), +}; + +/* + * According to board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 eMMC (SD3) on TQMa6 + * mmc1 .. n optional slots used on baseboard + */ +struct fsl_esdhc_cfg tqma6_usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tqma6_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 0; + else + ret = tqma6_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, + ARRAY_SIZE(tqma6_usdhc3_pads)); + tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { + puts("Warning: failed to initialize eMMC dev\n"); + } else { + struct mmc *mmc = find_mmc_device(0); + if (mmc) + mmc_set_dsr(mmc, tqma6_emmc_dsr); + } + + tqma6_bb_board_mmc_init(bis); + + return 0; +} + +static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { + /* SS1 */ + NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), +}; + +static unsigned const tqma6_ecspi1_cs[] = { + IMX_GPIO_NR(3, 19), +}; + +static void tqma6_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) + gpio_direction_output(tqma6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, + ARRAY_SIZE(tqma6_ecspi1_pads)); +} + +static struct i2c_pads_info tqma6_i2c3_pads = { + /* I2C3: on board LM75, M24C64, */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +static void tqma6_setup_i2c(void) +{ + /* use logical index for bus, e.g. I2C1 -> 0 */ + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); +} + +int board_early_init_f(void) +{ + return tqma6_bb_board_early_init_f(); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + tqma6_iomuxc_spi(); + tqma6_setup_i2c(); + + tqma6_bb_board_init(); + + return 0; +} + +static const char *tqma6_get_boardname(void) +{ + u32 cpurev = get_cpu_rev(); + + switch ((cpurev & 0xFF000) >> 12) { + case MXC_CPU_MX6SOLO: + return "TQMa6S"; + break; + case MXC_CPU_MX6DL: + return "TQMa6DL"; + break; + case MXC_CPU_MX6D: + return "TQMa6D"; + break; + case MXC_CPU_MX6Q: + return "TQMa6Q"; + break; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + struct pmic *p; + u32 reg; + + setenv("board_name", tqma6_get_boardname()); + + /* + * configure PFUZE100 PMIC: + * TODO: should go to power_init_board if bus switching is + * fixed in generic power code + */ + power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + } + + tqma6_bb_board_late_init(); + + return 0; +} + +int checkboard(void) +{ + printf("Board: %s on a %s\n", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + return 0; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + /* bring in eMMC dsr settings */ + do_fixup_by_path_u32(blob, + "/soc/aips-bus@02100000/usdhc@02198000", + "dsr", tqma6_emmc_dsr, 2); + tqma6_bb_ft_board_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h new file mode 100644 index 0000000..9d072d2 --- /dev/null +++ b/board/tqc/tqma6/tqma6_bb.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013, 2014 TQ Systems + * Author: Markus Niebel <markus.niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TQMA6_BB__ +#define __TQMA6_BB + +#include <common.h> + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc); +int tqma6_bb_board_mmc_getcd(struct mmc *mmc); +int tqma6_bb_board_mmc_init(bd_t *bis); + +int tqma6_bb_board_early_init_f(void); +int tqma6_bb_board_init(void); +int tqma6_bb_board_late_init(void); +int tqma6_bb_checkboard(void); + +const char *tqma6_bb_get_boardname(void); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd); +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c new file mode 100644 index 0000000..fd59287 --- /dev/null +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel <markus.niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> + +#include <common.h> +#include <fsl_esdhc.h> +#include <libfdt.h> +#include <malloc.h> +#include <i2c.h> +#include <micrel.h> +#include <miiphy.h> +#include <mmc.h> +#include <netdev.h> + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#if defined(CONFIG_MX6Q) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac + +#elif defined(CONFIG_MX6S) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 + +#else + +#error "need to define target CPU" + +#endif + +#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm) +#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_34ohm) +#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_60ohm) + +/* disable on die termination for RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 +/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 +/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25) + +static iomux_v3_cfg_t const mba6_enet_pads[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, + ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL), + /* + * these pins are also used for config strapping by phy + */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, + ENET_RX_PAD_CTRL), + /* KSZ9031 PHY Reset */ + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_enet(void) +{ + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + + imx_iomux_v3_setup_multiple_pads(mba6_enet_pads, + ARRAY_SIZE(mba6_enet_pads)); + + /* Reset PHY */ + gpio_direction_output(ENET_PHY_RESET_GPIO , 0); + /* Need delay 10ms after power on according to KSZ9031 spec */ + udelay(1000 * 10); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); + /* + * KSZ9031 manual: 100 usec wait time after reset before communication + * over MDIO + * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on + * reset before the phy sees a high level + */ + udelay(200); +} + +static iomux_v3_cfg_t const mba6_uart2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, + ARRAY_SIZE(mba6_uart2_pads)); +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) + +int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_CD_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = gpio_get_value(USDHC2_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba6_usdhc_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, +}; + +static iomux_v3_cfg_t const mba6_usdhc2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL), +}; + +int tqma6_bb_board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads, + ARRAY_SIZE(mba6_usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_input(USDHC2_WP_GPIO); + + mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg)) + puts("Warning: failed to initialize SD\n"); + + return 0; +} + +static struct i2c_pads_info mba6_i2c1_pads = { +/* I2C1: MBa6x */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static void mba6_setup_i2c(void) +{ + /* use logical index for bus, e.g. I2C1 -> 0 */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); +} + + +static iomux_v3_cfg_t const mba6_ecspi1_pads[] = { + NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL), +}; + +static unsigned const mba6_ecspi1_cs[] = { + IMX_GPIO_NR(3, 24), + IMX_GPIO_NR(3, 25), +}; + +static void mba6_setup_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i) + gpio_direction_output(mba6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads, + ARRAY_SIZE(mba6_ecspi1_pads)); +} + +int board_phy_config(struct phy_device *phydev) +{ +/* + * optimized pad skew values depends on CPU variant on the TQMa6x module: + * i.MX6Q/D or i.MX6DL/S + */ +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0032 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2036 +#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0030 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2052 +#else +#error +#endif + /* min rx/tx ctrl delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CTRL_SKEW); + /* min rx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_RX_SKEW); + /* max tx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_TX_SKEW); + /* rx/tx clk skew */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CLK_SKEW); + + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy */ + phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), + PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + puts("No phy found\n"); + return 0; + } + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + puts("FEC MXC: probe failed\n"); + free(phydev); + free(bus); + } + + return 0; +} + +int tqma6_bb_board_early_init_f(void) +{ + mba6_setup_iomuxc_uart(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + mba6_setup_i2c(); + mba6_setup_iomuxc_spi(); + /* do it here - to have reset completed */ + mba6_setup_iomuxc_enet(); + + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "MBa6x"; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg new file mode 100644 index 0000000..f54dff7 --- /dev/null +++ b/board/tqc/tqma6/tqma6q.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include <config.h> + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6Q/D DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg new file mode 100644 index 0000000..24d4e2f --- /dev/null +++ b/board/tqc/tqma6/tqma6s.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include <config.h> + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6S DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 5dbf94e..a10ea71 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -19,6 +19,7 @@ SECTIONS . = CONFIG_SPL_TEXT_BASE; .text.0 : { + *(.vectors) arch/arm/cpu/pxa/start.o (.text*) arch/arm/lib/built-in.o (.text*) board/vpac270/built-in.o (.text*) diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig deleted file mode 100644 index 3b72a5f..0000000 --- a/board/xilinx/zynq/Kconfig +++ /dev/null @@ -1,95 +0,0 @@ -if TARGET_ZYNQ_MICROZED - -config SYS_CPU - string - default "armv7" - -config SYS_BOARD - string - default "zynq" - -config SYS_VENDOR - string - default "xilinx" - -config SYS_SOC - string - default "zynq" - -config SYS_CONFIG_NAME - string - default "zynq_microzed" - -endif - -if TARGET_ZYNQ_ZC70X - -config SYS_CPU - string - default "armv7" - -config SYS_BOARD - string - default "zynq" - -config SYS_VENDOR - string - default "xilinx" - -config SYS_SOC - string - default "zynq" - -config SYS_CONFIG_NAME - string - default "zynq_zc70x" - -endif - -if TARGET_ZYNQ_ZC770 - -config SYS_CPU - string - default "armv7" - -config SYS_BOARD - string - default "zynq" - -config SYS_VENDOR - string - default "xilinx" - -config SYS_SOC - string - default "zynq" - -config SYS_CONFIG_NAME - string - default "zynq_zc770" - -endif - -if TARGET_ZYNQ_ZED - -config SYS_CPU - string - default "armv7" - -config SYS_BOARD - string - default "zynq" - -config SYS_VENDOR - string - default "xilinx" - -config SYS_SOC - string - default "zynq" - -config SYS_CONFIG_NAME - string - default "zynq_zed" - -endif diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS index e167816..382e921 100644 --- a/board/xilinx/zynq/MAINTAINERS +++ b/board/xilinx/zynq/MAINTAINERS @@ -3,13 +3,5 @@ M: Michal Simek <monstr@monstr.eu> M: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> S: Maintained F: board/xilinx/zynq/ -F: include/configs/zynq_microzed.h -F: configs/zynq_microzed_defconfig -F: include/configs/zynq_zc70x.h -F: configs/zynq_zc70x_defconfig -F: include/configs/zynq_zc770.h -F: configs/zynq_zc770_xm010_defconfig -F: configs/zynq_zc770_xm012_defconfig -F: configs/zynq_zc770_xm013_defconfig -F: include/configs/zynq_zed.h -F: configs/zynq_zed_defconfig +F: include/configs/zynq*.h +F: configs/zynq_*_defconfig |