diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/coreboot/coreboot/coreboot.c | 6 | ||||
| -rw-r--r-- | board/google/chromebook_link/link.c | 40 |
2 files changed, 46 insertions, 0 deletions
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 0240c34..b260f9a 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -6,6 +6,7 @@ #include <common.h> #include <cros_ec.h> +#include <asm/gpio.h> int arch_early_init_r(void) { @@ -14,3 +15,8 @@ int arch_early_init_r(void) return 0; } + +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1822237..4d95c1c 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -7,6 +7,9 @@ #include <common.h> #include <cros_ec.h> #include <asm/gpio.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> int arch_early_init_r(void) { @@ -121,3 +124,40 @@ int board_early_init_f(void) return 0; } + +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +{ + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} |