diff options
Diffstat (limited to 'board')
41 files changed, 842 insertions, 646 deletions
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 064d143..383b064 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -440,7 +440,8 @@ void muxSetupTouchScreen(void) void muxSetupGPMC(void) { /* gpmc_io_dir, MCR */ - writel(0x4800008C, 0x19000000); + volatile unsigned int *MCR = (unsigned int *) 0x4800008C; + *MCR = 0x19000000; /* NOR FLASH CS0 */ /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ diff --git a/board/atmel/at91cap9adk/Makefile b/board/atmel/at91cap9adk/Makefile new file mode 100644 index 0000000..359fdab --- /dev/null +++ b/board/atmel/at91cap9adk/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := at91cap9adk.o led.o nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c new file mode 100644 index 0000000..bde6aa9 --- /dev/null +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/AT91CAP9.h> + +#define MP_BLOCK_3_BASE 0xFDF00000 + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void at91cap9_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; +#endif + +#ifdef CONFIG_USART1 + AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1; +#endif + +#ifdef CONFIG_USART2 + AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2; +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; +#endif + + +} + +static void at91cap9_nor_hw_init(void) +{ + /* Ensure EBI supply is 3.3V */ + AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3; + + /* Configure SMC CS0 for parallel flash */ + AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP | + AT91C_FLASH_NCS_WR_SETUP | + AT91C_FLASH_NRD_SETUP | + AT91C_FLASH_NCS_RD_SETUP; + + AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE | + AT91C_FLASH_NCS_WR_PULSE | + AT91C_FLASH_NRD_PULSE | + AT91C_FLASH_NCS_RD_PULSE; + + AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE | + AT91C_FLASH_NRD_CYCLE; + + AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE | + AT91C_SMC_WRITEMODE | + AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_BAT_BYTE_WRITE | + AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | + (AT91C_SMC_TDF & (1 << 16)); +} + +#ifdef CONFIG_CMD_NAND +static void at91cap9_nand_hw_init(void) +{ + /* Enable CS3 */ + AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3; + + /* Configure SMC CS3 for NAND/SmartMedia */ + AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP | + AT91C_SM_NCS_WR_SETUP | + AT91C_SM_NRD_SETUP | + AT91C_SM_NCS_RD_SETUP; + + AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE | + AT91C_SM_NCS_WR_PULSE | + AT91C_SM_NRD_PULSE | + AT91C_SM_NCS_RD_PULSE; + + AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE | + AT91C_SM_NRD_CYCLE; + + AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE | + AT91C_SMC_WRITEMODE | + AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_EIGTH_BITS | + AT91C_SM_TDF; + + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; + + /* RDY/BSY is not connected */ + + /* Enable NandFlash */ + AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15; + AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15; +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void at91cap9_spi_hw_init(void) +{ + AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D | + AT91C_PD1_SPI0_NPCS3D; + AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D | + AT91C_PD1_SPI0_NPCS3D; + + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A; + AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A | + AT91C_PA1_SPI0_MOSI | + AT91C_PA0_SPI0_MISO | + AT91C_PA3_SPI0_NPCS1 | + AT91C_PA5_SPI0_NPCS0 | + AT91C_PA2_SPI0_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A | + AT91C_PA4_SPI0_NPCS2A | + AT91C_PA1_SPI0_MOSI | + AT91C_PA0_SPI0_MISO | + AT91C_PA3_SPI0_NPCS1 | + AT91C_PA5_SPI0_NPCS0 | + AT91C_PA2_SPI0_SPCK; + + /* Enable Clock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0; +} +#endif + +#ifdef CONFIG_MACB +static void at91cap9_macb_hw_init(void) +{ + unsigned int gpio; + + /* Enable clock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; + + /* + * Disable pull-up on: + * RXDV (PB22) => PHY normal mode (not Test mode) + * ERX0 (PB25) => PHY ADDR0 + * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV | + AT91C_PB25_E_RX0 | + AT91C_PB26_E_RX1; + + /* Need to reset PHY -> 500ms reset */ + AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) | + (AT91C_RSTC_ERSTL & (0x0D << 8)) | + AT91C_RSTC_URSTEN; + AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) | + AT91C_RSTC_EXTRST; + + /* Wait for end hardware reset */ + while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); + + /* Re-enable pull-up */ + AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV | + AT91C_PB25_E_RX0 | + AT91C_PB26_E_RX1; + +#ifdef CONFIG_RMII + gpio = AT91C_PB30_E_MDIO | + AT91C_PB29_E_MDC | + AT91C_PB21_E_TXCK | + AT91C_PB27_E_RXER | + AT91C_PB25_E_RX0 | + AT91C_PB22_E_RXDV | + AT91C_PB26_E_RX1 | + AT91C_PB28_E_TXEN | + AT91C_PB23_E_TX0 | + AT91C_PB24_E_TX1; + AT91C_BASE_PIOB->PIO_ASR = gpio; + AT91C_BASE_PIOB->PIO_BSR = 0; + AT91C_BASE_PIOB->PIO_PDR = gpio; +#else +#error AT91CAP9A-DK works only in RMII mode +#endif + + /* Unlock EMAC, 3 0 2 1 sequence */ +#define MP_MAC_KEY0 0x5969cb2a +#define MP_MAC_KEY1 0xb4a1872e +#define MP_MAC_KEY2 0x05683fbc +#define MP_MAC_KEY3 0x3634fba4 +#define UNLOCK_MAC 0x00000008 + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC; +} +#endif + +#ifdef CONFIG_USB_OHCI_NEW +static void at91cap9_uhp_hw_init(void) +{ + /* Unlock USB OHCI, 3 2 0 1 sequence */ +#define MP_OHCI_KEY0 0x896c11ca +#define MP_OHCI_KEY1 0x68ebca21 +#define MP_OHCI_KEY2 0x4823efbc +#define MP_OHCI_KEY3 0x8651aae4 +#define UNLOCK_OHCI 0x00000010 + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1; + *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI; +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91CAP9ADK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91cap9_serial_hw_init(); + at91cap9_nor_hw_init(); +#ifdef CONFIG_CMD_NAND + at91cap9_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91cap9_spi_hw_init(); +#endif +#ifdef CONFIG_MACB + at91cap9_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91cap9_uhp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif diff --git a/board/atmel/at91cap9adk/config.mk b/board/atmel/at91cap9adk/config.mk new file mode 100644 index 0000000..e241aee --- /dev/null +++ b/board/atmel/at91cap9adk/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x73000000 diff --git a/board/atmel/at91cap9adk/led.c b/board/atmel/at91cap9adk/led.c new file mode 100644 index 0000000..8588a91 --- /dev/null +++ b/board/atmel/at91cap9adk/led.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/AT91CAP9.h> + +#define RED_LED AT91C_PIO_PC29 /* this is the power led */ +#define GREEN_LED AT91C_PIO_PA10 /* this is the user1 led */ +#define YELLOW_LED AT91C_PIO_PA11 /* this is the user1 led */ + +void red_LED_on(void) +{ + AT91C_BASE_PIOC->PIO_SODR = RED_LED; +} + +void red_LED_off(void) +{ + AT91C_BASE_PIOC->PIO_CODR = RED_LED; +} + +void green_LED_on(void) +{ + AT91C_BASE_PIOA->PIO_CODR = GREEN_LED; +} + +void green_LED_off(void) +{ + AT91C_BASE_PIOA->PIO_SODR = GREEN_LED; +} + +void yellow_LED_on(void) +{ + AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED; +} + +void yellow_LED_off(void) +{ + AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED; +} + +void coloured_LED_init(void) +{ + /* Enable clock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; + + /* Disable peripherals on LEDs */ + AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED; + /* Enable pins as outputs */ + AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED; + /* Turn all LEDs OFF */ + AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED; + + /* Disable peripherals on LEDs */ + AT91C_BASE_PIOC->PIO_PER = RED_LED; + /* Enable pins as outputs */ + AT91C_BASE_PIOC->PIO_OER = RED_LED; + /* Turn all LEDs OFF */ + AT91C_BASE_PIOC->PIO_CODR = RED_LED; +} diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c new file mode 100644 index 0000000..2f02126 --- /dev/null +++ b/board/atmel/at91cap9adk/nand.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#ifdef CONFIG_CMD_NAND + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + case NAND_CTL_CLRNCE: + AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15; + break; + case NAND_CTL_SETNCE: + AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15; + break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = at91cap9adk_nand_hwcontrol; + nand->chip_delay = 20; + + return 0; +} +#endif diff --git a/board/atmel/at91cap9adk/u-boot.lds b/board/atmel/at91cap9adk/u-boot.lds new file mode 100644 index 0000000..05a6d83 --- /dev/null +++ b/board/atmel/at91cap9adk/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index bd4b6b4..1ccbe2c 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -23,6 +23,7 @@ #include <asm/io.h> #include <asm/sdram.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/hmatrix2.h> @@ -40,6 +41,8 @@ static const struct sdram_info sdram = { .trcd = 2, .tras = 5, .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, }; int board_early_init_f(void) diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 6618963..28f64c4 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -23,6 +23,7 @@ #include <asm/io.h> #include <asm/sdram.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/hmatrix2.h> @@ -40,6 +41,8 @@ static const struct sdram_info sdram = { .trcd = 2, .tras = 5, .txsr = 5, + /* 15.6 us */ + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, }; int board_early_init_f(void) diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 93d790f..4047825 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -159,7 +159,7 @@ int __flashprog write_buff(flash_info_t *info, uchar *src, { unsigned long flags; uint16_t *base, *p, *s, *end; - uint16_t word, status; + uint16_t word, status, status1; int ret = ERR_OK; if (addr < info->start[0] @@ -194,20 +194,33 @@ int __flashprog write_buff(flash_info_t *info, uchar *src, sync_write_buffer(); /* Wait for completion */ + status1 = readw(p); do { /* TODO: Timeout */ - status = readw(p); - } while ((status != word) && !(status & 0x28)); + status = status1; + status1 = readw(p); + } while (((status ^ status1) & 0x40) /* toggled */ + && !(status1 & 0x28)); /* error bits */ - writew(0xf0, base); - readw(base); - - if (status != word) { - printf("Flash write error at address 0x%p: 0x%02x\n", - p, status); + /* + * We'll need to check once again for toggle bit + * because the toggle bit may stop toggling as I/O5 + * changes to "1" (ref at49bv642.pdf p9) + */ + status1 = readw(p); + status = readw(p); + if ((status ^ status1) & 0x40) { + printf("Flash write error at address 0x%p: " + "0x%02x != 0x%02x\n", + p, status,word); ret = ERR_PROG_ERROR; + writew(0xf0, base); + readw(base); break; } + + writew(0xf0, base); + readw(base); } if (flags) diff --git a/board/bf533-ezkit/.gitignore b/board/bf533-ezkit/.gitignore new file mode 100644 index 0000000..945f324 --- /dev/null +++ b/board/bf533-ezkit/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index 299cdba..cdf4dc6 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -286,9 +286,9 @@ int write_flash(long nOffset, int nValue) long addr; addr = (CFG_FLASH_BASE + nOffset); - sync(); + SSYNC(); *(unsigned volatile short *)addr = nValue; - sync(); + SSYNC(); if (poll_toggle_bit(nOffset) < 0) return FLASH_FAIL; return FLASH_SUCCESS; @@ -301,9 +301,9 @@ int read_flash(long nOffset, int *pnValue) if (nOffset != 0x2) reset_flash(); - sync(); + SSYNC(); nValue = *(volatile unsigned short *)addr; - sync(); + SSYNC(); *pnValue = nValue; return TRUE; } diff --git a/board/bf533-stamp/.gitignore b/board/bf533-stamp/.gitignore new file mode 100644 index 0000000..945f324 --- /dev/null +++ b/board/bf533-stamp/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 69e425b..af03597 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -76,9 +76,9 @@ void swap_to(int device_id) if (device_id == ETHERNET) { *pFIO_DIR = PF0; - sync(); + SSYNC(); *pFIO_FLAG_S = PF0; - sync(); + SSYNC(); } else if (device_id == FLASH) { *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); *pFIO_FLAG_S = (PF4 | PF3 | PF2); @@ -88,7 +88,7 @@ void swap_to(int device_id) *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); *pFIO_FLAG_D = (PF4 | PF3 | PF2); - sync(); + SSYNC(); } else { printf("Unknown bank to switch\n"); } @@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr) */ *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); *(addr) = val; - sync(); + SSYNC(); /* Setback PF1 PF0 to 0 0 to address external * memory banks */ *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } unsigned char cf_inb(volatile unsigned char *addr) @@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); c = *(addr); - sync(); + SSYNC(); *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); return c; } @@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); for (i = 0; i < words; i++) { *(sect_buf + i) = *(addr); - sync(); + SSYNC(); } *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) @@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) *pFIO_FLAG_S = CF_PF0; *pFIO_FLAG_C = CF_PF1; - sync(); + SSYNC(); for (i = 0; i < words; i++) { *(addr) = *(sect_buf + i); - sync(); + SSYNC(); } *pFIO_FLAG_C = CF_PF1_PF0; - sync(); + SSYNC(); } #endif @@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3) *pFIO_FLAG_S = PF4; else *pFIO_FLAG_C = PF4; - sync(); + SSYNC(); } void show_boot_progress(int status) diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c index d30750f..15141cf 100644 --- a/board/bf533-stamp/spi.c +++ b/board/bf533-stamp/spi.c @@ -4,6 +4,7 @@ #include <common.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/mach-common/bits/spi.h> #if defined(CONFIG_SPI) @@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand) /*sends the actual command to the SPI TX register */ *pSPI_TDBR = iCommand; - sync(); + SSYNC(); /*The SPI status register will be polled to check the SPIF bit */ Wait_For_SPIF(); @@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting) *pSPI_FLG = 0xFB04; *pSPI_BAUD = CONFIG_SPI_BAUD; *pSPI_CTL = spi_setting; - sync(); + SSYNC(); } void SPI_OFF(void) @@ -183,7 +184,7 @@ void SPI_OFF(void) *pSPI_CTL = 0x0400; /* disable SPI */ *pSPI_FLG = 0; *pSPI_BAUD = 0; - sync(); + SSYNC(); udelay(CONFIG_CCLK_HZ / 50000000); } @@ -241,10 +242,10 @@ char ReadStatusRegister(void) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ *pSPI_TDBR = 0; /*send dummy to receive the status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the data has been sent */ status_register = *pSPI_RDBR; /*read the status register */ @@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock) /* Send the erase block command to the flash followed by the 24 address */ /* to point to the start of a sector. */ *pSPI_TDBR = SPI_SE; - sync(); + SSYNC(); Wait_For_SPIF(); ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ *pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ /*Turns off the SPI */ @@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); *pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */ *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */ *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ *pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */ - sync(); + SSYNC(); Wait_For_SPIF(); /* Wait until the instruction has been sent */ /* After the SPI device address has been placed on the MOSI pin the data can be */ /* received on the MISO pin. */ for (i = 0; i < lCount; i++) { *pSPI_TDBR = 0; /*send dummy */ - sync(); + SSYNC(); while (!(*pSPI_STAT & RXS)) ; *cnData++ = *pSPI_RDBR; /*read */ @@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, /* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */ *pSPI_TDBR = SPI_PP; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = (ulStartAddr >> 16); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = (ulStartAddr >> 8); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ ulWAddr = ulStartAddr; *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ /* Fourth, maximum number of 256 bytes will be taken from the Buffer */ /* and sent to the SPI device. */ for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) { iData = *temp; *pSPI_TDBR = iData; - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ temp++; } diff --git a/board/bf537-stamp/.gitignore b/board/bf537-stamp/.gitignore new file mode 100644 index 0000000..945f324 --- /dev/null +++ b/board/bf537-stamp/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 6954b30..d279817 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <net.h> #include "ether_bf537.h" +#include <asm/mach-common/bits/bootrom.h> /** * is_valid_ether_addr - Determine if the given Ethernet address is valid @@ -117,7 +118,7 @@ int checkboard(void) void cf_outb(unsigned char val, volatile unsigned char *addr) { *(addr) = val; - sync(); + SSYNC(); } unsigned char cf_inb(volatile unsigned char *addr) @@ -125,7 +126,7 @@ unsigned char cf_inb(volatile unsigned char *addr) volatile unsigned char c; c = *(addr); - sync(); + SSYNC(); return c; } @@ -136,7 +137,7 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) for (i = 0; i < words; i++) *(sect_buf + i) = *(addr); - sync(); + SSYNC(); } void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) @@ -145,7 +146,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) for (i = 0; i < words; i++) *(addr) = *(sect_buf + i); - sync(); + SSYNC(); } #endif /* CONFIG_BFIN_IDE */ diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c index 36c1536..6c514c6 100644 --- a/board/bf537-stamp/ether_bf537.c +++ b/board/bf537-stamp/ether_bf537.c @@ -30,6 +30,10 @@ #include <malloc.h> #include "ether_bf537.h" +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/emac.h> +#include <asm/mach-common/bits/pll.h> + #ifdef CONFIG_POST #include <post.h> #endif @@ -364,7 +368,7 @@ int SetupSystemRegs(int *opmode) u16 sysctl, phydat; int count = 0; /* Enable PHY output */ - *pVR_CTL |= PHYCLKOE; + *pVR_CTL |= CLKBUFOE; /* MDC = 2.5 MHz */ sysctl = SET_MDCDIV(24); /* Odd word alignment for Receive Frame DMA word */ diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c index ed85841..8252c42 100644 --- a/board/bf537-stamp/flash.c +++ b/board/bf537-stamp/flash.c @@ -255,7 +255,7 @@ int write_flash(long nOffset, int nValue) addr = (CFG_FLASH_BASE + nOffset); *(unsigned volatile short *)addr = nValue; - sync(); + SSYNC(); #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) if (icache_status()) udelay(CONFIG_CCLK_HZ / 1000000); diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index f95b584..6ff0f4f 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -64,13 +64,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd) this->IO_ADDR_R = this->IO_ADDR_W; /* Drain the writebuffer */ - sync(); + SSYNC(); } int bfin_device_ready(struct mtd_info *mtd) { int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0; - sync(); + SSYNC(); return ret; } diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 6039350..fa11991 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -104,15 +104,15 @@ void post_init_uart(int sclk) *pUART_GCTL = 0x00; *pUART_LCR = 0x83; - sync(); + SSYNC(); *pUART_DLL = (divisor & 0xFF); - sync(); + SSYNC(); *pUART_DLH = ((divisor >> 8) & 0xFF); - sync(); + SSYNC(); *pUART_LCR = 0x03; - sync(); + SSYNC(); *pUART_GCTL = 0x01; - sync(); + SSYNC(); } void post_out_buff(char *buff) @@ -124,7 +124,7 @@ void post_out_buff(char *buff) while ((buff[i] != '\0') && (i != 100)) { while (!(*pUART_LSR & 0x20)) ; *pUART_THR = buff[i]; - sync(); + SSYNC(); i++; } for (i = 0; i < 0x80000; i++) ; @@ -141,7 +141,7 @@ int post_key_pressed(void) *pPORTF_FER &= ~PF5; *pPORTFIO_DIR &= ~PF5; *pPORTFIO_INEN |= PF5; - sync(); + SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { @@ -303,7 +303,7 @@ int post_init_sdram(int sclk) (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS); - sync(); + SSYNC(); *pEBIU_SDGCTL |= 0x1000000; /* Set the SDRAM Refresh Rate control register based on SSCLK value */ @@ -314,7 +314,7 @@ int post_init_sdram(int sclk) /* SDRAM Memory Global Control Register */ *pEBIU_SDGCTL = mem_SDGCTL; - sync(); + SSYNC(); return mem_SDRRC; } diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c index d9c08ee..c48c3c7 100644 --- a/board/bf537-stamp/stm_m25p64.c +++ b/board/bf537-stamp/stm_m25p64.c @@ -4,6 +4,7 @@ #include <common.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/mach-common/bits/spi.h> #if defined(CONFIG_SPI) @@ -142,7 +143,7 @@ void SendSingleCommand(const int iCommand) /* sends the actual command to the SPI TX register */ *pSPI_TDBR = iCommand; - sync(); + SSYNC(); /* The SPI status register will be polled to check the SPIF bit */ Wait_For_SPIF(); @@ -164,10 +165,10 @@ void SetupSPI(const int spi_setting) *pSPI_FLG = 0xFF02; *pSPI_BAUD = CONFIG_SPI_BAUD; *pSPI_CTL = spi_setting; - sync(); + SSYNC(); *pSPI_FLG = 0xFD02; - sync(); + SSYNC(); } void SPI_OFF(void) @@ -176,7 +177,7 @@ void SPI_OFF(void) *pSPI_CTL = 0x0400; /* disable SPI */ *pSPI_FLG = 0; *pSPI_BAUD = 0; - sync(); + SSYNC(); udelay(CONFIG_CCLK_HZ / 50000000); } @@ -234,10 +235,10 @@ char ReadStatusRegister(void) SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the instruction has been sent */ *pSPI_TDBR = 0; /*send dummy to receive the status register */ - sync(); + SSYNC(); Wait_For_SPIF(); /*wait until the data has been sent */ status_register = *pSPI_RDBR; /*read the status register */ @@ -300,23 +301,23 @@ ERROR_CODE EraseBlock(int nBlock) * to point to the start of a sector */ *pSPI_TDBR = SPI_SE; - sync(); + SSYNC(); Wait_For_SPIF(); /* Send the highest byte of the 24 bit address at first */ ShiftValue = (ulSectorOff >> 16); *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the middle byte of the 24 bit address at second */ ShiftValue = (ulSectorOff >> 8); *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the lowest byte of the 24 bit address finally */ *pSPI_TDBR = ulSectorOff; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); @@ -357,33 +358,33 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) /* Send the read command to SPI device */ *pSPI_TDBR = SPI_READ; #endif - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the highest byte of the 24 bit address at first */ ShiftValue = (ulStart >> 16); /* Send the byte to the SPI device */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the middle byte of the 24 bit address at second */ ShiftValue = (ulStart >> 8); /* Send the byte to the SPI device */ *pSPI_TDBR = ShiftValue; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); /* Send the lowest byte of the 24 bit address finally */ *pSPI_TDBR = ulStart; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); #ifdef CONFIG_SPI_FLASH_FAST_READ /* Send dummy for FAST_READ */ *pSPI_TDBR = 0; - sync(); + SSYNC(); /* Wait until the instruction has been sent */ Wait_For_SPIF(); #endif @@ -392,7 +393,7 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) /* received on the MISO pin. */ for (i = 0; i < lCount; i++) { *pSPI_TDBR = 0; - sync(); + SSYNC(); while (!(*pSPI_STAT & RXS)) ; *cnData++ = *pSPI_RDBR; @@ -435,22 +436,22 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, */ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); *pSPI_TDBR = SPI_PP; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = (ulStartAddr >> 16); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = (ulStartAddr >> 8); *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); ulWAddr = ulStartAddr; *pSPI_TDBR = ulWAddr; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); /* @@ -460,7 +461,7 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) { iData = *temp; *pSPI_TDBR = iData; - sync(); + SSYNC(); /*wait until the instruction has been sent */ Wait_For_SPIF(); temp++; diff --git a/board/bf561-ezkit/.gitignore b/board/bf561-ezkit/.gitignore new file mode 100644 index 0000000..945f324 --- /dev/null +++ b/board/bf561-ezkit/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 2ff44a7..d504217 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -65,9 +65,9 @@ int misc_init_r(void) /* Keep PF12 low to be able to drive the USB-LAN Extender */ *pFIO0_DIR = 0x0000; *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */ - sync(); + SSYNC(); *pFIO0_POLAR = 0x0000; - sync(); + SSYNC(); return 0; } diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 44c0978..c8e17d0 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -79,7 +79,7 @@ int mac_show(void) /* Show Build Date, * BCD date values, as YYMMDDhhmmss. */ - printf("Date 20%02x\/%02x\/%02x %02x:%02x:%02x\n", + printf("Date 20%02x/%02x/%02x %02x:%02x:%02x\n", mac_data.date[0], mac_data.date[1], mac_data.date[2], diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 12a92ae..489689e 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -27,9 +27,7 @@ endif LIB = $(obj)lib$(BOARD).a -SOBJS := init.o - -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S deleted file mode 100644 index 4d811e1..0000000 --- a/board/freescale/mpc8610hpcd/init.S +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <config.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <mpc86xx.h> - -#define LAWAR_TRGT_PCI1 0x00000000 -#define LAWAR_TRGT_PCIE1 0x00200000 -#define LAWAR_TRGT_PCIE2 0x00100000 -#define LAWAR_TRGT_LBC 0x00400000 -#define LAWAR_TRGT_DDR 0x00f00000 - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#else -#define LAWBAR1 0 -#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) - -#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) -#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - - addi r4,r7,0 - addi r5,r7,0 - - /* Skip LAWAR0, start at LAWAR1 */ - lis r6,LAWBAR1@h - ori r6,r6,LAWBAR1@l - stwu r6, 0xc28(r4) - - lis r6,LAWAR1@h - ori r6,r6,LAWAR1@l - stwu r6, 0xc30(r5) - - /* LAWBAR2, LAWAR2 */ - lis r6,LAWBAR2@h - ori r6,r6,LAWBAR2@l - stwu r6, 0x20(r4) - - lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) - - /* LAWBAR3, LAWAR3 */ - lis r6,LAWBAR3@h - ori r6,r6,LAWBAR3@l - stwu r6, 0x20(r4) - - lis r6,LAWAR3@h - ori r6,r6,LAWAR3@l - stwu r6, 0x20(r5) - - /* LAWBAR4, LAWAR4 */ - lis r6,LAWBAR4@h - ori r6,r6,LAWBAR4@l - stwu r6, 0x20(r4) - - lis r6,LAWAR4@h - ori r6,r6,LAWAR4@l - stwu r6, 0x20(r5) - /* LAWBAR5, LAWAR5 */ - lis r6,LAWBAR5@h - ori r6,r6,LAWBAR5@l - stwu r6, 0x20(r4) - - lis r6,LAWAR5@h - ori r6,r6,LAWAR5@l - stwu r6, 0x20(r5) - - /* LAWBAR6, LAWAR6 */ - lis r6,LAWBAR6@h - ori r6,r6,LAWBAR6@l - stwu r6, 0x20(r4) - - lis r6,LAWAR6@h - ori r6,r6,LAWAR6@l - stwu r6, 0x20(r5) - - /* LAWBAR7, LAWAR7 */ - lis r6,LAWBAR7@h - ori r6,r6,LAWBAR7@l - stwu r6, 0x20(r4) - - lis r6,LAWAR7@h - ori r6,r6,LAWAR7@l - stwu r6, 0x20(r5) - - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) - - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) - - /* LAWBAR9, LAWAR9 */ - lis r6,LAWBAR9@h - ori r6,r6,LAWBAR9@l - stwu r6, 0x20(r4) - - lis r6,LAWAR9@h - ori r6,r6,LAWAR9@l - stwu r6, 0x20(r5) - - blr diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c new file mode 100644 index 0000000..b4d222d --- /dev/null +++ b/board/freescale/mpc8610hpcd/law.c @@ -0,0 +1,44 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#if !defined(CONFIG_SPD_EEPROM) + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), +#endif + SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), + SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds index 37838ec..b88138e 100644 --- a/board/freescale/mpc8610hpcd/u-boot.lds +++ b/board/freescale/mpc8610hpcd/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/freescale/mpc8610hpcd/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 201da3e..115df05 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o - -SOBJS := init.o +COBJS := $(BOARD).o law.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8641hpcn/init.S b/board/freescale/mpc8641hpcn/init.S deleted file mode 100644 index cb21ba6..0000000 --- a/board/freescale/mpc8641hpcn/init.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc86xx.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf800_0000 0xf80f_ffff CCSRBAR 1M - * 0xf810_0000 0xf81f_ffff PIXIS 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR1 0 -#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) - -#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR8 0 -#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff) -#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - .section .bootpg, "ax" - .globl law_entry -law_entry: - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - - addi r4,r7,0 - addi r5,r7,0 - - /* Skip LAWAR0, start at LAWAR1 */ - lis r6,LAWBAR1@h - ori r6,r6,LAWBAR1@l - stwu r6, 0xc28(r4) - - lis r6,LAWAR1@h - ori r6,r6,LAWAR1@l - stwu r6, 0xc30(r5) - - /* LAWBAR2, LAWAR2 */ - lis r6,LAWBAR2@h - ori r6,r6,LAWBAR2@l - stwu r6, 0x20(r4) - - lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) - - /* LAWBAR3, LAWAR3 */ - lis r6,LAWBAR3@h - ori r6,r6,LAWBAR3@l - stwu r6, 0x20(r4) - - lis r6,LAWAR3@h - ori r6,r6,LAWAR3@l - stwu r6, 0x20(r5) - - /* LAWBAR4, LAWAR4 */ - lis r6,LAWBAR4@h - ori r6,r6,LAWBAR4@l - stwu r6, 0x20(r4) - - lis r6,LAWAR4@h - ori r6,r6,LAWAR4@l - stwu r6, 0x20(r5) - /* LAWBAR5, LAWAR5 */ - lis r6,LAWBAR5@h - ori r6,r6,LAWBAR5@l - stwu r6, 0x20(r4) - - lis r6,LAWAR5@h - ori r6,r6,LAWAR5@l - stwu r6, 0x20(r5) - - /* LAWBAR6, LAWAR6 */ - lis r6,LAWBAR6@h - ori r6,r6,LAWBAR6@l - stwu r6, 0x20(r4) - - lis r6,LAWAR6@h - ori r6,r6,LAWAR6@l - stwu r6, 0x20(r5) - - /* LAWBAR7, LAWAR7 */ - lis r6,LAWBAR7@h - ori r6,r6,LAWBAR7@l - stwu r6, 0x20(r4) - - lis r6,LAWAR7@h - ori r6,r6,LAWAR7@l - stwu r6, 0x20(r5) - - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) - - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) - - /* LAWBAR9, LAWAR9 */ - lis r6,LAWBAR9@h - ori r6,r6,LAWBAR9@l - stwu r6, 0x20(r4) - - lis r6,LAWAR9@h - ori r6,r6,LAWAR9@l - stwu r6, 0x20(r5) - - blr diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c new file mode 100644 index 0000000..245f420 --- /dev/null +++ b/board/freescale/mpc8641hpcn/law.c @@ -0,0 +1,64 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#if !defined(CONFIG_SPD_EEPROM) + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), +#if !defined(CONFIG_SPD_EEPROM) + SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), +#endif + SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds index 9900670..06d491b 100644 --- a/board/freescale/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/freescale/mpc8641hpcn/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index b13d9d4..3d1d65d 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2007 Netstal Maschinen AG +# (C) Copyright 2007-2008 Netstal Maschinen AG # Niklaus Giger (ng@netstal.com) # # This program is free software; you can redistribute it and/or @@ -22,18 +22,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath fixed_sdram.c ../common -vpath hcu_flash.c ../common -vpath nm_bsp.c ../common - # NOBJS : Netstal common objects -NOBJS = ../common/fixed_sdram.o ../common/hcu_flash.o ../common/nm_bsp.o +NOBJS = fixed_sdram.o hcu_flash.o nm_bsp.o COBJS = $(BOARD).o SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) OBJS := $(addprefix $(obj),$(COBJS)) -NOBJS := $(addprefix $(obj),$(NOBJS)) +NOBJS := $(addprefix $(obj)../common/,$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) $(NOBJS) diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 9f248a4..349c653 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2007 Netstal Maschinen AG +# (C) Copyright 2007-2008 Netstal Maschinen AG # Niklaus Giger (ng@netstal.com) # # This program is free software; you can redistribute it and/or @@ -22,17 +22,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath hcu_flash.c ../common -vpath nm_bsp.c ../common # NOBJS : Netstal common objects -NOBJS = ../common/hcu_flash.o ../common/nm_bsp.o +NOBJS = hcu_flash.o nm_bsp.o COBJS = $(BOARD).o sdram.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) OBJS := $(addprefix $(obj),$(COBJS)) -NOBJS := $(addprefix $(obj),$(NOBJS)) +NOBJS := $(addprefix $(obj)../common/,$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) $(NOBJS) diff --git a/board/netstar/nand.c b/board/netstar/nand.c index d47e1d8..b76d2a3 100644 --- a/board/netstar/nand.c +++ b/board/netstar/nand.c @@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) this->IO_ADDR_W = (void *) IO_ADDR_W; } -/* - * chip R/B detection - */ -/*** -static int netstar_nand_ready(struct mtd_info *mtd) -{ - return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; -} -***/ - int board_nand_init(struct nand_chip *nand) { nand->options = NAND_SAMSUNG_LP_OPTIONS; nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = netstar_nand_hwcontrol; -/* nand->dev_ready = netstar_nand_ready; */ - nand->chip_delay = 18; + nand->chip_delay = 400; return 0; } #endif diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 90e99d3..96adbc9 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -175,7 +175,7 @@ int board_early_init_f(void) *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ + mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile index a90b725..115df05 100644 --- a/board/sbc8641d/Makefile +++ b/board/sbc8641d/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o -SOBJS := init.o +COBJS := $(BOARD).o law.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8641d/init.S b/board/sbc8641d/init.S deleted file mode 100644 index c151d7e..0000000 --- a/board/sbc8641d/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> - * Copyright 2007 Embedded Specialties, Inc. - * Joe Hamman joe.hamman@embeddedspecialties.com - * - * Copyright 2004 Freescale Semiconductor. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include <config.h> -#include <mpc86xx.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x0fff_ffff DDR1 256M - * 0x1000_0000 0x1fff_ffff DDR2 256M - * 0xe000_0000 0xffff_ffff LBC 512M - * - * Notes: - * CCSRBAR doesn't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -# DDR Bank 1 -# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -# DDR Bank 2 -# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) -# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -# LBC -# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff) -# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))) - -/* - * LAW (Local Access Window) configuration: - * - * 0x0000_0000 DDR 256M - * 0x1000_0000 DDR2 256M - * 0x8000_0000 PCI1 MEM 512M - * 0xa000_0000 PCI2 MEM 512M - * 0xc000_0000 RapidIO 512M - * 0xe200_0000 PCI1 IO 16M - * 0xe300_0000 PCI2 IO 16M - * 0xf800_0000 CCSRBAR 2M - * 0xfe00_0000 FLASH (boot bank) 32M - * - */ - -#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) - -#define LAWBAR4 ((0xf8000000>>12) & 0xffffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) - -#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) -#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) - -#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) - -#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - .section .bootpg, "ax" - .globl law_entry -law_entry: - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - - addi r4,r7,0 - addi r5,r7,0 - - /* Skip LAWAR0, start at LAWAR1 */ - lis r6,LAWBAR1@h - ori r6,r6,LAWBAR1@l - stwu r6, 0xc28(r4) - - lis r6,LAWAR1@h - ori r6,r6,LAWAR1@l - stwu r6, 0xc30(r5) - - /* LAWBAR2, LAWAR2 */ - lis r6,LAWBAR2@h - ori r6,r6,LAWBAR2@l - stwu r6, 0x20(r4) - - lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) - - /* LAWBAR3, LAWAR3 */ - lis r6,LAWBAR3@h - ori r6,r6,LAWBAR3@l - stwu r6, 0x20(r4) - - lis r6,LAWAR3@h - ori r6,r6,LAWAR3@l - stwu r6, 0x20(r5) - - /* LAWBAR4, LAWAR4 */ - lis r6,LAWBAR4@h - ori r6,r6,LAWBAR4@l - stwu r6, 0x20(r4) - - lis r6,LAWAR4@h - ori r6,r6,LAWAR4@l - stwu r6, 0x20(r5) - - /* LAWBAR5, LAWAR5 */ - lis r6,LAWBAR5@h - ori r6,r6,LAWBAR5@l - stwu r6, 0x20(r4) - - lis r6,LAWAR5@h - ori r6,r6,LAWAR5@l - stwu r6, 0x20(r5) - - /* LAWBAR6, LAWAR6 */ - lis r6,LAWBAR6@h - ori r6,r6,LAWBAR6@l - stwu r6, 0x20(r4) - - lis r6,LAWAR6@h - ori r6,r6,LAWAR6@l - stwu r6, 0x20(r5) - - /* LAWBAR7, LAWAR7 */ - lis r6,LAWBAR7@h - ori r6,r6,LAWBAR7@l - stwu r6, 0x20(r4) - - lis r6,LAWAR7@h - ori r6,r6,LAWAR7@l - stwu r6, 0x20(r5) - - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) - - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) - - /* LAWBAR9, LAWAR9 */ - lis r6,LAWBAR9@h - ori r6,r6,LAWBAR9@l - stwu r6, 0x20(r4) - - lis r6,LAWAR9@h - ori r6,r6,LAWAR9@l - stwu r6, 0x20(r5) - - blr diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c new file mode 100644 index 0000000..d403873 --- /dev/null +++ b/board/sbc8641d/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW (Local Access Window) configuration: + * + * 0x0000_0000 DDR 256M + * 0x1000_0000 DDR2 256M + * 0x8000_0000 PCI1 MEM 512M + * 0xa000_0000 PCI2 MEM 512M + * 0xc000_0000 RapidIO 512M + * 0xe200_0000 PCI1 IO 16M + * 0xe300_0000 PCI2 IO 16M + * 0xf800_0000 CCSRBAR 2M + * 0xfe00_0000 FLASH (boot bank) 32M + * + */ + + +struct law_entry law_table[] = { + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds index 5de9b78..be362ee 100644 --- a/board/sbc8641d/u-boot.lds +++ b/board/sbc8641d/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/sbc8641d/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) |