diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6q_sabresd/flash_header.S | 79 |
1 files changed, 41 insertions, 38 deletions
diff --git a/board/freescale/mx6q_sabresd/flash_header.S b/board/freescale/mx6q_sabresd/flash_header.S index 13678b0..4a803fd 100644 --- a/board/freescale/mx6q_sabresd/flash_header.S +++ b/board/freescale/mx6q_sabresd/flash_header.S @@ -59,51 +59,54 @@ write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */ # IOMUXC_BASE_ADDR = 0x20e0000 # DDR IO TYPE -MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000c0000) -MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000) +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000) # Clock -MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030) -MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030) # Address -MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030) -MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030) MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030) # Control -MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030) -MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000) -MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000) -MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000) -MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030) -MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030) -MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030) # Data Strobe MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000) -MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030) -MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030) -MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030) -MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030) -MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030) -MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030) -MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030) -MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030) + +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030) # DATA -MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000) -MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030) -MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030) -MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030) -MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030) -MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030) -MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030) -MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000) + +MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030) +MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030) +MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030) +MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030) +MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030) +MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030) +MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030) MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030) -MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030) -MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030) -MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030) -MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030) -MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030) -MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030) -MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030) -MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030) + +MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030) +MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030) +MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030) +MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030) +MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030) +MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030) +MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030) +MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x00000030) # MMDC_P0_BASE_ADDR = 0x021b0000 # MMDC_P1_BASE_ADDR = 0x021b4000 @@ -175,7 +178,7 @@ MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00022227) MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00022227) MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) -MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x004, 0x00011006) +MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x404, 0x00011006) MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ |